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1/* pci.c: UltraSparc PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
9 */
10
11#include <linux/export.h>
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/sched.h>
15#include <linux/capability.h>
16#include <linux/errno.h>
17#include <linux/pci.h>
18#include <linux/msi.h>
19#include <linux/irq.h>
20#include <linux/init.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23
24#include <asm/uaccess.h>
25#include <asm/pgtable.h>
26#include <asm/irq.h>
27#include <asm/prom.h>
28#include <asm/apb.h>
29
30#include "pci_impl.h"
31
32/* List of all PCI controllers found in the system. */
33struct pci_pbm_info *pci_pbm_root = NULL;
34
35/* Each PBM found gets a unique index. */
36int pci_num_pbms = 0;
37
38volatile int pci_poke_in_progress;
39volatile int pci_poke_cpu = -1;
40volatile int pci_poke_faulted;
41
42static DEFINE_SPINLOCK(pci_poke_lock);
43
44void pci_config_read8(u8 *addr, u8 *ret)
45{
46 unsigned long flags;
47 u8 byte;
48
49 spin_lock_irqsave(&pci_poke_lock, flags);
50 pci_poke_cpu = smp_processor_id();
51 pci_poke_in_progress = 1;
52 pci_poke_faulted = 0;
53 __asm__ __volatile__("membar #Sync\n\t"
54 "lduba [%1] %2, %0\n\t"
55 "membar #Sync"
56 : "=r" (byte)
57 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
58 : "memory");
59 pci_poke_in_progress = 0;
60 pci_poke_cpu = -1;
61 if (!pci_poke_faulted)
62 *ret = byte;
63 spin_unlock_irqrestore(&pci_poke_lock, flags);
64}
65
66void pci_config_read16(u16 *addr, u16 *ret)
67{
68 unsigned long flags;
69 u16 word;
70
71 spin_lock_irqsave(&pci_poke_lock, flags);
72 pci_poke_cpu = smp_processor_id();
73 pci_poke_in_progress = 1;
74 pci_poke_faulted = 0;
75 __asm__ __volatile__("membar #Sync\n\t"
76 "lduha [%1] %2, %0\n\t"
77 "membar #Sync"
78 : "=r" (word)
79 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
80 : "memory");
81 pci_poke_in_progress = 0;
82 pci_poke_cpu = -1;
83 if (!pci_poke_faulted)
84 *ret = word;
85 spin_unlock_irqrestore(&pci_poke_lock, flags);
86}
87
88void pci_config_read32(u32 *addr, u32 *ret)
89{
90 unsigned long flags;
91 u32 dword;
92
93 spin_lock_irqsave(&pci_poke_lock, flags);
94 pci_poke_cpu = smp_processor_id();
95 pci_poke_in_progress = 1;
96 pci_poke_faulted = 0;
97 __asm__ __volatile__("membar #Sync\n\t"
98 "lduwa [%1] %2, %0\n\t"
99 "membar #Sync"
100 : "=r" (dword)
101 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
102 : "memory");
103 pci_poke_in_progress = 0;
104 pci_poke_cpu = -1;
105 if (!pci_poke_faulted)
106 *ret = dword;
107 spin_unlock_irqrestore(&pci_poke_lock, flags);
108}
109
110void pci_config_write8(u8 *addr, u8 val)
111{
112 unsigned long flags;
113
114 spin_lock_irqsave(&pci_poke_lock, flags);
115 pci_poke_cpu = smp_processor_id();
116 pci_poke_in_progress = 1;
117 pci_poke_faulted = 0;
118 __asm__ __volatile__("membar #Sync\n\t"
119 "stba %0, [%1] %2\n\t"
120 "membar #Sync"
121 : /* no outputs */
122 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
123 : "memory");
124 pci_poke_in_progress = 0;
125 pci_poke_cpu = -1;
126 spin_unlock_irqrestore(&pci_poke_lock, flags);
127}
128
129void pci_config_write16(u16 *addr, u16 val)
130{
131 unsigned long flags;
132
133 spin_lock_irqsave(&pci_poke_lock, flags);
134 pci_poke_cpu = smp_processor_id();
135 pci_poke_in_progress = 1;
136 pci_poke_faulted = 0;
137 __asm__ __volatile__("membar #Sync\n\t"
138 "stha %0, [%1] %2\n\t"
139 "membar #Sync"
140 : /* no outputs */
141 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
142 : "memory");
143 pci_poke_in_progress = 0;
144 pci_poke_cpu = -1;
145 spin_unlock_irqrestore(&pci_poke_lock, flags);
146}
147
148void pci_config_write32(u32 *addr, u32 val)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&pci_poke_lock, flags);
153 pci_poke_cpu = smp_processor_id();
154 pci_poke_in_progress = 1;
155 pci_poke_faulted = 0;
156 __asm__ __volatile__("membar #Sync\n\t"
157 "stwa %0, [%1] %2\n\t"
158 "membar #Sync"
159 : /* no outputs */
160 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 : "memory");
162 pci_poke_in_progress = 0;
163 pci_poke_cpu = -1;
164 spin_unlock_irqrestore(&pci_poke_lock, flags);
165}
166
167static int ofpci_verbose;
168
169static int __init ofpci_debug(char *str)
170{
171 int val = 0;
172
173 get_option(&str, &val);
174 if (val)
175 ofpci_verbose = 1;
176 return 1;
177}
178
179__setup("ofpci_debug=", ofpci_debug);
180
181static unsigned long pci_parse_of_flags(u32 addr0)
182{
183 unsigned long flags = 0;
184
185 if (addr0 & 0x02000000) {
186 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
187 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
188 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
189 if (addr0 & 0x40000000)
190 flags |= IORESOURCE_PREFETCH
191 | PCI_BASE_ADDRESS_MEM_PREFETCH;
192 } else if (addr0 & 0x01000000)
193 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
194 return flags;
195}
196
197/* The of_device layer has translated all of the assigned-address properties
198 * into physical address resources, we only have to figure out the register
199 * mapping.
200 */
201static void pci_parse_of_addrs(struct platform_device *op,
202 struct device_node *node,
203 struct pci_dev *dev)
204{
205 struct resource *op_res;
206 const u32 *addrs;
207 int proplen;
208
209 addrs = of_get_property(node, "assigned-addresses", &proplen);
210 if (!addrs)
211 return;
212 if (ofpci_verbose)
213 printk(" parse addresses (%d bytes) @ %p\n",
214 proplen, addrs);
215 op_res = &op->resource[0];
216 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
217 struct resource *res;
218 unsigned long flags;
219 int i;
220
221 flags = pci_parse_of_flags(addrs[0]);
222 if (!flags)
223 continue;
224 i = addrs[0] & 0xff;
225 if (ofpci_verbose)
226 printk(" start: %llx, end: %llx, i: %x\n",
227 op_res->start, op_res->end, i);
228
229 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
230 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
231 } else if (i == dev->rom_base_reg) {
232 res = &dev->resource[PCI_ROM_RESOURCE];
233 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE
234 | IORESOURCE_SIZEALIGN;
235 } else {
236 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
237 continue;
238 }
239 res->start = op_res->start;
240 res->end = op_res->end;
241 res->flags = flags;
242 res->name = pci_name(dev);
243 }
244}
245
246static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
247 struct device_node *node,
248 struct pci_bus *bus, int devfn)
249{
250 struct dev_archdata *sd;
251 struct pci_slot *slot;
252 struct platform_device *op;
253 struct pci_dev *dev;
254 const char *type;
255 u32 class;
256
257 dev = alloc_pci_dev();
258 if (!dev)
259 return NULL;
260
261 sd = &dev->dev.archdata;
262 sd->iommu = pbm->iommu;
263 sd->stc = &pbm->stc;
264 sd->host_controller = pbm;
265 sd->op = op = of_find_device_by_node(node);
266 sd->numa_node = pbm->numa_node;
267
268 sd = &op->dev.archdata;
269 sd->iommu = pbm->iommu;
270 sd->stc = &pbm->stc;
271 sd->numa_node = pbm->numa_node;
272
273 if (!strcmp(node->name, "ebus"))
274 of_propagate_archdata(op);
275
276 type = of_get_property(node, "device_type", NULL);
277 if (type == NULL)
278 type = "";
279
280 if (ofpci_verbose)
281 printk(" create device, devfn: %x, type: %s\n",
282 devfn, type);
283
284 dev->bus = bus;
285 dev->sysdata = node;
286 dev->dev.parent = bus->bridge;
287 dev->dev.bus = &pci_bus_type;
288 dev->dev.of_node = of_node_get(node);
289 dev->devfn = devfn;
290 dev->multifunction = 0; /* maybe a lie? */
291 set_pcie_port_type(dev);
292
293 list_for_each_entry(slot, &dev->bus->slots, list)
294 if (PCI_SLOT(dev->devfn) == slot->number)
295 dev->slot = slot;
296
297 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
298 dev->device = of_getintprop_default(node, "device-id", 0xffff);
299 dev->subsystem_vendor =
300 of_getintprop_default(node, "subsystem-vendor-id", 0);
301 dev->subsystem_device =
302 of_getintprop_default(node, "subsystem-id", 0);
303
304 dev->cfg_size = pci_cfg_space_size(dev);
305
306 /* We can't actually use the firmware value, we have
307 * to read what is in the register right now. One
308 * reason is that in the case of IDE interfaces the
309 * firmware can sample the value before the the IDE
310 * interface is programmed into native mode.
311 */
312 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
313 dev->class = class >> 8;
314 dev->revision = class & 0xff;
315
316 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
317 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
318
319 if (ofpci_verbose)
320 printk(" class: 0x%x device name: %s\n",
321 dev->class, pci_name(dev));
322
323 /* I have seen IDE devices which will not respond to
324 * the bmdma simplex check reads if bus mastering is
325 * disabled.
326 */
327 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
328 pci_set_master(dev);
329
330 dev->current_state = 4; /* unknown power state */
331 dev->error_state = pci_channel_io_normal;
332 dev->dma_mask = 0xffffffff;
333
334 if (!strcmp(node->name, "pci")) {
335 /* a PCI-PCI bridge */
336 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
337 dev->rom_base_reg = PCI_ROM_ADDRESS1;
338 } else if (!strcmp(type, "cardbus")) {
339 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
340 } else {
341 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
342 dev->rom_base_reg = PCI_ROM_ADDRESS;
343
344 dev->irq = sd->op->archdata.irqs[0];
345 if (dev->irq == 0xffffffff)
346 dev->irq = PCI_IRQ_NONE;
347 }
348
349 pci_parse_of_addrs(sd->op, node, dev);
350
351 if (ofpci_verbose)
352 printk(" adding to system ...\n");
353
354 pci_device_add(dev, bus);
355
356 return dev;
357}
358
359static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
360{
361 u32 idx, first, last;
362
363 first = 8;
364 last = 0;
365 for (idx = 0; idx < 8; idx++) {
366 if ((map & (1 << idx)) != 0) {
367 if (first > idx)
368 first = idx;
369 if (last < idx)
370 last = idx;
371 }
372 }
373
374 *first_p = first;
375 *last_p = last;
376}
377
378/* For PCI bus devices which lack a 'ranges' property we interrogate
379 * the config space values to set the resources, just like the generic
380 * Linux PCI probing code does.
381 */
382static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
383 struct pci_bus *bus,
384 struct pci_pbm_info *pbm)
385{
386 struct pci_bus_region region;
387 struct resource *res, res2;
388 u8 io_base_lo, io_limit_lo;
389 u16 mem_base_lo, mem_limit_lo;
390 unsigned long base, limit;
391
392 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
393 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
394 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
395 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
396
397 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
398 u16 io_base_hi, io_limit_hi;
399
400 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
401 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
402 base |= (io_base_hi << 16);
403 limit |= (io_limit_hi << 16);
404 }
405
406 res = bus->resource[0];
407 if (base <= limit) {
408 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
409 res2.flags = res->flags;
410 region.start = base;
411 region.end = limit + 0xfff;
412 pcibios_bus_to_resource(dev, &res2, ®ion);
413 if (!res->start)
414 res->start = res2.start;
415 if (!res->end)
416 res->end = res2.end;
417 }
418
419 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
420 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
421 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
422 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
423
424 res = bus->resource[1];
425 if (base <= limit) {
426 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
427 IORESOURCE_MEM);
428 region.start = base;
429 region.end = limit + 0xfffff;
430 pcibios_bus_to_resource(dev, res, ®ion);
431 }
432
433 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
434 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
435 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
436 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
437
438 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
439 u32 mem_base_hi, mem_limit_hi;
440
441 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
442 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
443
444 /*
445 * Some bridges set the base > limit by default, and some
446 * (broken) BIOSes do not initialize them. If we find
447 * this, just assume they are not being used.
448 */
449 if (mem_base_hi <= mem_limit_hi) {
450 base |= ((long) mem_base_hi) << 32;
451 limit |= ((long) mem_limit_hi) << 32;
452 }
453 }
454
455 res = bus->resource[2];
456 if (base <= limit) {
457 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
458 IORESOURCE_MEM | IORESOURCE_PREFETCH);
459 region.start = base;
460 region.end = limit + 0xfffff;
461 pcibios_bus_to_resource(dev, res, ®ion);
462 }
463}
464
465/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
466 * a proper 'ranges' property.
467 */
468static void __devinit apb_fake_ranges(struct pci_dev *dev,
469 struct pci_bus *bus,
470 struct pci_pbm_info *pbm)
471{
472 struct pci_bus_region region;
473 struct resource *res;
474 u32 first, last;
475 u8 map;
476
477 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
478 apb_calc_first_last(map, &first, &last);
479 res = bus->resource[0];
480 res->flags = IORESOURCE_IO;
481 region.start = (first << 21);
482 region.end = (last << 21) + ((1 << 21) - 1);
483 pcibios_bus_to_resource(dev, res, ®ion);
484
485 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
486 apb_calc_first_last(map, &first, &last);
487 res = bus->resource[1];
488 res->flags = IORESOURCE_MEM;
489 region.start = (first << 21);
490 region.end = (last << 21) + ((1 << 21) - 1);
491 pcibios_bus_to_resource(dev, res, ®ion);
492}
493
494static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
495 struct device_node *node,
496 struct pci_bus *bus);
497
498#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
499
500static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
501 struct device_node *node,
502 struct pci_dev *dev)
503{
504 struct pci_bus *bus;
505 const u32 *busrange, *ranges;
506 int len, i, simba;
507 struct pci_bus_region region;
508 struct resource *res;
509 unsigned int flags;
510 u64 size;
511
512 if (ofpci_verbose)
513 printk("of_scan_pci_bridge(%s)\n", node->full_name);
514
515 /* parse bus-range property */
516 busrange = of_get_property(node, "bus-range", &len);
517 if (busrange == NULL || len != 8) {
518 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
519 node->full_name);
520 return;
521 }
522 ranges = of_get_property(node, "ranges", &len);
523 simba = 0;
524 if (ranges == NULL) {
525 const char *model = of_get_property(node, "model", NULL);
526 if (model && !strcmp(model, "SUNW,simba"))
527 simba = 1;
528 }
529
530 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
531 if (!bus) {
532 printk(KERN_ERR "Failed to create pci bus for %s\n",
533 node->full_name);
534 return;
535 }
536
537 bus->primary = dev->bus->number;
538 bus->subordinate = busrange[1];
539 bus->bridge_ctl = 0;
540
541 /* parse ranges property, or cook one up by hand for Simba */
542 /* PCI #address-cells == 3 and #size-cells == 2 always */
543 res = &dev->resource[PCI_BRIDGE_RESOURCES];
544 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
545 res->flags = 0;
546 bus->resource[i] = res;
547 ++res;
548 }
549 if (simba) {
550 apb_fake_ranges(dev, bus, pbm);
551 goto after_ranges;
552 } else if (ranges == NULL) {
553 pci_cfg_fake_ranges(dev, bus, pbm);
554 goto after_ranges;
555 }
556 i = 1;
557 for (; len >= 32; len -= 32, ranges += 8) {
558 flags = pci_parse_of_flags(ranges[0]);
559 size = GET_64BIT(ranges, 6);
560 if (flags == 0 || size == 0)
561 continue;
562 if (flags & IORESOURCE_IO) {
563 res = bus->resource[0];
564 if (res->flags) {
565 printk(KERN_ERR "PCI: ignoring extra I/O range"
566 " for bridge %s\n", node->full_name);
567 continue;
568 }
569 } else {
570 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
571 printk(KERN_ERR "PCI: too many memory ranges"
572 " for bridge %s\n", node->full_name);
573 continue;
574 }
575 res = bus->resource[i];
576 ++i;
577 }
578
579 res->flags = flags;
580 region.start = GET_64BIT(ranges, 1);
581 region.end = region.start + size - 1;
582 pcibios_bus_to_resource(dev, res, ®ion);
583 }
584after_ranges:
585 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
586 bus->number);
587 if (ofpci_verbose)
588 printk(" bus name: %s\n", bus->name);
589
590 pci_of_scan_bus(pbm, node, bus);
591}
592
593static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
594 struct device_node *node,
595 struct pci_bus *bus)
596{
597 struct device_node *child;
598 const u32 *reg;
599 int reglen, devfn, prev_devfn;
600 struct pci_dev *dev;
601
602 if (ofpci_verbose)
603 printk("PCI: scan_bus[%s] bus no %d\n",
604 node->full_name, bus->number);
605
606 child = NULL;
607 prev_devfn = -1;
608 while ((child = of_get_next_child(node, child)) != NULL) {
609 if (ofpci_verbose)
610 printk(" * %s\n", child->full_name);
611 reg = of_get_property(child, "reg", ®len);
612 if (reg == NULL || reglen < 20)
613 continue;
614
615 devfn = (reg[0] >> 8) & 0xff;
616
617 /* This is a workaround for some device trees
618 * which list PCI devices twice. On the V100
619 * for example, device number 3 is listed twice.
620 * Once as "pm" and once again as "lomp".
621 */
622 if (devfn == prev_devfn)
623 continue;
624 prev_devfn = devfn;
625
626 /* create a new pci_dev for this device */
627 dev = of_create_pci_dev(pbm, child, bus, devfn);
628 if (!dev)
629 continue;
630 if (ofpci_verbose)
631 printk("PCI: dev header type: %x\n",
632 dev->hdr_type);
633
634 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
635 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
636 of_scan_pci_bridge(pbm, child, dev);
637 }
638}
639
640static ssize_t
641show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
642{
643 struct pci_dev *pdev;
644 struct device_node *dp;
645
646 pdev = to_pci_dev(dev);
647 dp = pdev->dev.of_node;
648
649 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
650}
651
652static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
653
654static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
655{
656 struct pci_dev *dev;
657 struct pci_bus *child_bus;
658 int err;
659
660 list_for_each_entry(dev, &bus->devices, bus_list) {
661 /* we don't really care if we can create this file or
662 * not, but we need to assign the result of the call
663 * or the world will fall under alien invasion and
664 * everybody will be frozen on a spaceship ready to be
665 * eaten on alpha centauri by some green and jelly
666 * humanoid.
667 */
668 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
669 (void) err;
670 }
671 list_for_each_entry(child_bus, &bus->children, node)
672 pci_bus_register_of_sysfs(child_bus);
673}
674
675struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
676 struct device *parent)
677{
678 LIST_HEAD(resources);
679 struct device_node *node = pbm->op->dev.of_node;
680 struct pci_bus *bus;
681
682 printk("PCI: Scanning PBM %s\n", node->full_name);
683
684 pci_add_resource_offset(&resources, &pbm->io_space,
685 pbm->io_space.start);
686 pci_add_resource_offset(&resources, &pbm->mem_space,
687 pbm->mem_space.start);
688 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
689 pbm, &resources);
690 if (!bus) {
691 printk(KERN_ERR "Failed to create bus for %s\n",
692 node->full_name);
693 pci_free_resource_list(&resources);
694 return NULL;
695 }
696 bus->secondary = pbm->pci_first_busno;
697 bus->subordinate = pbm->pci_last_busno;
698
699 pci_of_scan_bus(pbm, node, bus);
700 pci_bus_add_devices(bus);
701 pci_bus_register_of_sysfs(bus);
702
703 return bus;
704}
705
706void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
707{
708}
709
710void pcibios_update_irq(struct pci_dev *pdev, int irq)
711{
712}
713
714resource_size_t pcibios_align_resource(void *data, const struct resource *res,
715 resource_size_t size, resource_size_t align)
716{
717 return res->start;
718}
719
720int pcibios_enable_device(struct pci_dev *dev, int mask)
721{
722 u16 cmd, oldcmd;
723 int i;
724
725 pci_read_config_word(dev, PCI_COMMAND, &cmd);
726 oldcmd = cmd;
727
728 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
729 struct resource *res = &dev->resource[i];
730
731 /* Only set up the requested stuff */
732 if (!(mask & (1<<i)))
733 continue;
734
735 if (res->flags & IORESOURCE_IO)
736 cmd |= PCI_COMMAND_IO;
737 if (res->flags & IORESOURCE_MEM)
738 cmd |= PCI_COMMAND_MEMORY;
739 }
740
741 if (cmd != oldcmd) {
742 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
743 pci_name(dev), cmd);
744 /* Enable the appropriate bits in the PCI command register. */
745 pci_write_config_word(dev, PCI_COMMAND, cmd);
746 }
747 return 0;
748}
749
750char * __devinit pcibios_setup(char *str)
751{
752 return str;
753}
754
755/* Platform support for /proc/bus/pci/X/Y mmap()s. */
756
757/* If the user uses a host-bridge as the PCI device, he may use
758 * this to perform a raw mmap() of the I/O or MEM space behind
759 * that controller.
760 *
761 * This can be useful for execution of x86 PCI bios initialization code
762 * on a PCI card, like the xfree86 int10 stuff does.
763 */
764static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
765 enum pci_mmap_state mmap_state)
766{
767 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
768 unsigned long space_size, user_offset, user_size;
769
770 if (mmap_state == pci_mmap_io) {
771 space_size = resource_size(&pbm->io_space);
772 } else {
773 space_size = resource_size(&pbm->mem_space);
774 }
775
776 /* Make sure the request is in range. */
777 user_offset = vma->vm_pgoff << PAGE_SHIFT;
778 user_size = vma->vm_end - vma->vm_start;
779
780 if (user_offset >= space_size ||
781 (user_offset + user_size) > space_size)
782 return -EINVAL;
783
784 if (mmap_state == pci_mmap_io) {
785 vma->vm_pgoff = (pbm->io_space.start +
786 user_offset) >> PAGE_SHIFT;
787 } else {
788 vma->vm_pgoff = (pbm->mem_space.start +
789 user_offset) >> PAGE_SHIFT;
790 }
791
792 return 0;
793}
794
795/* Adjust vm_pgoff of VMA such that it is the physical page offset
796 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
797 *
798 * Basically, the user finds the base address for his device which he wishes
799 * to mmap. They read the 32-bit value from the config space base register,
800 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
801 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
802 *
803 * Returns negative error code on failure, zero on success.
804 */
805static int __pci_mmap_make_offset(struct pci_dev *pdev,
806 struct vm_area_struct *vma,
807 enum pci_mmap_state mmap_state)
808{
809 unsigned long user_paddr, user_size;
810 int i, err;
811
812 /* First compute the physical address in vma->vm_pgoff,
813 * making sure the user offset is within range in the
814 * appropriate PCI space.
815 */
816 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
817 if (err)
818 return err;
819
820 /* If this is a mapping on a host bridge, any address
821 * is OK.
822 */
823 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
824 return err;
825
826 /* Otherwise make sure it's in the range for one of the
827 * device's resources.
828 */
829 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
830 user_size = vma->vm_end - vma->vm_start;
831
832 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
833 struct resource *rp = &pdev->resource[i];
834 resource_size_t aligned_end;
835
836 /* Active? */
837 if (!rp->flags)
838 continue;
839
840 /* Same type? */
841 if (i == PCI_ROM_RESOURCE) {
842 if (mmap_state != pci_mmap_mem)
843 continue;
844 } else {
845 if ((mmap_state == pci_mmap_io &&
846 (rp->flags & IORESOURCE_IO) == 0) ||
847 (mmap_state == pci_mmap_mem &&
848 (rp->flags & IORESOURCE_MEM) == 0))
849 continue;
850 }
851
852 /* Align the resource end to the next page address.
853 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
854 * because actually we need the address of the next byte
855 * after rp->end.
856 */
857 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
858
859 if ((rp->start <= user_paddr) &&
860 (user_paddr + user_size) <= aligned_end)
861 break;
862 }
863
864 if (i > PCI_ROM_RESOURCE)
865 return -EINVAL;
866
867 return 0;
868}
869
870/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
871 * mapping.
872 */
873static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
874 enum pci_mmap_state mmap_state)
875{
876 vma->vm_flags |= (VM_IO | VM_RESERVED);
877}
878
879/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
880 * device mapping.
881 */
882static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
883 enum pci_mmap_state mmap_state)
884{
885 /* Our io_remap_pfn_range takes care of this, do nothing. */
886}
887
888/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
889 * for this architecture. The region in the process to map is described by vm_start
890 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
891 * The pci device structure is provided so that architectures may make mapping
892 * decisions on a per-device or per-bus basis.
893 *
894 * Returns a negative error code on failure, zero on success.
895 */
896int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
897 enum pci_mmap_state mmap_state,
898 int write_combine)
899{
900 int ret;
901
902 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
903 if (ret < 0)
904 return ret;
905
906 __pci_mmap_set_flags(dev, vma, mmap_state);
907 __pci_mmap_set_pgprot(dev, vma, mmap_state);
908
909 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
910 ret = io_remap_pfn_range(vma, vma->vm_start,
911 vma->vm_pgoff,
912 vma->vm_end - vma->vm_start,
913 vma->vm_page_prot);
914 if (ret)
915 return ret;
916
917 return 0;
918}
919
920#ifdef CONFIG_NUMA
921int pcibus_to_node(struct pci_bus *pbus)
922{
923 struct pci_pbm_info *pbm = pbus->sysdata;
924
925 return pbm->numa_node;
926}
927EXPORT_SYMBOL(pcibus_to_node);
928#endif
929
930/* Return the domain number for this pci bus */
931
932int pci_domain_nr(struct pci_bus *pbus)
933{
934 struct pci_pbm_info *pbm = pbus->sysdata;
935 int ret;
936
937 if (!pbm) {
938 ret = -ENXIO;
939 } else {
940 ret = pbm->index;
941 }
942
943 return ret;
944}
945EXPORT_SYMBOL(pci_domain_nr);
946
947#ifdef CONFIG_PCI_MSI
948int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
949{
950 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
951 unsigned int irq;
952
953 if (!pbm->setup_msi_irq)
954 return -EINVAL;
955
956 return pbm->setup_msi_irq(&irq, pdev, desc);
957}
958
959void arch_teardown_msi_irq(unsigned int irq)
960{
961 struct msi_desc *entry = irq_get_msi_desc(irq);
962 struct pci_dev *pdev = entry->dev;
963 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
964
965 if (pbm->teardown_msi_irq)
966 pbm->teardown_msi_irq(irq, pdev);
967}
968#endif /* !(CONFIG_PCI_MSI) */
969
970static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
971{
972 struct pci_dev *ali_isa_bridge;
973 u8 val;
974
975 /* ALI sound chips generate 31-bits of DMA, a special register
976 * determines what bit 31 is emitted as.
977 */
978 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
979 PCI_DEVICE_ID_AL_M1533,
980 NULL);
981
982 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
983 if (set_bit)
984 val |= 0x01;
985 else
986 val &= ~0x01;
987 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
988 pci_dev_put(ali_isa_bridge);
989}
990
991int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
992{
993 u64 dma_addr_mask;
994
995 if (pdev == NULL) {
996 dma_addr_mask = 0xffffffff;
997 } else {
998 struct iommu *iommu = pdev->dev.archdata.iommu;
999
1000 dma_addr_mask = iommu->dma_addr_mask;
1001
1002 if (pdev->vendor == PCI_VENDOR_ID_AL &&
1003 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
1004 device_mask == 0x7fffffff) {
1005 ali_sound_dma_hack(pdev,
1006 (dma_addr_mask & 0x80000000) != 0);
1007 return 1;
1008 }
1009 }
1010
1011 if (device_mask >= (1UL << 32UL))
1012 return 0;
1013
1014 return (device_mask & dma_addr_mask) == dma_addr_mask;
1015}
1016
1017void pci_resource_to_user(const struct pci_dev *pdev, int bar,
1018 const struct resource *rp, resource_size_t *start,
1019 resource_size_t *end)
1020{
1021 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1022 unsigned long offset;
1023
1024 if (rp->flags & IORESOURCE_IO)
1025 offset = pbm->io_space.start;
1026 else
1027 offset = pbm->mem_space.start;
1028
1029 *start = rp->start - offset;
1030 *end = rp->end - offset;
1031}
1032
1033void pcibios_set_master(struct pci_dev *dev)
1034{
1035 /* No special bus mastering setup handling */
1036}
1037
1038static int __init pcibios_init(void)
1039{
1040 pci_dfl_cache_line_size = 64 >> 2;
1041 return 0;
1042}
1043subsys_initcall(pcibios_init);
1044
1045#ifdef CONFIG_SYSFS
1046static void __devinit pci_bus_slot_names(struct device_node *node,
1047 struct pci_bus *bus)
1048{
1049 const struct pci_slot_names {
1050 u32 slot_mask;
1051 char names[0];
1052 } *prop;
1053 const char *sp;
1054 int len, i;
1055 u32 mask;
1056
1057 prop = of_get_property(node, "slot-names", &len);
1058 if (!prop)
1059 return;
1060
1061 mask = prop->slot_mask;
1062 sp = prop->names;
1063
1064 if (ofpci_verbose)
1065 printk("PCI: Making slots for [%s] mask[0x%02x]\n",
1066 node->full_name, mask);
1067
1068 i = 0;
1069 while (mask) {
1070 struct pci_slot *pci_slot;
1071 u32 this_bit = 1 << i;
1072
1073 if (!(mask & this_bit)) {
1074 i++;
1075 continue;
1076 }
1077
1078 if (ofpci_verbose)
1079 printk("PCI: Making slot [%s]\n", sp);
1080
1081 pci_slot = pci_create_slot(bus, i, sp, NULL);
1082 if (IS_ERR(pci_slot))
1083 printk(KERN_ERR "PCI: pci_create_slot returned %ld\n",
1084 PTR_ERR(pci_slot));
1085
1086 sp += strlen(sp) + 1;
1087 mask &= ~this_bit;
1088 i++;
1089 }
1090}
1091
1092static int __init of_pci_slot_init(void)
1093{
1094 struct pci_bus *pbus = NULL;
1095
1096 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
1097 struct device_node *node;
1098
1099 if (pbus->self) {
1100 /* PCI->PCI bridge */
1101 node = pbus->self->dev.of_node;
1102 } else {
1103 struct pci_pbm_info *pbm = pbus->sysdata;
1104
1105 /* Host PCI controller */
1106 node = pbm->op->dev.of_node;
1107 }
1108
1109 pci_bus_slot_names(node, pbus);
1110 }
1111
1112 return 0;
1113}
1114
1115module_init(of_pci_slot_init);
1116#endif
1/* pci.c: UltraSparc PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
9 */
10
11#include <linux/export.h>
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/sched.h>
15#include <linux/capability.h>
16#include <linux/errno.h>
17#include <linux/pci.h>
18#include <linux/msi.h>
19#include <linux/irq.h>
20#include <linux/init.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23
24#include <asm/uaccess.h>
25#include <asm/pgtable.h>
26#include <asm/irq.h>
27#include <asm/prom.h>
28#include <asm/apb.h>
29
30#include "pci_impl.h"
31
32/* List of all PCI controllers found in the system. */
33struct pci_pbm_info *pci_pbm_root = NULL;
34
35/* Each PBM found gets a unique index. */
36int pci_num_pbms = 0;
37
38volatile int pci_poke_in_progress;
39volatile int pci_poke_cpu = -1;
40volatile int pci_poke_faulted;
41
42static DEFINE_SPINLOCK(pci_poke_lock);
43
44void pci_config_read8(u8 *addr, u8 *ret)
45{
46 unsigned long flags;
47 u8 byte;
48
49 spin_lock_irqsave(&pci_poke_lock, flags);
50 pci_poke_cpu = smp_processor_id();
51 pci_poke_in_progress = 1;
52 pci_poke_faulted = 0;
53 __asm__ __volatile__("membar #Sync\n\t"
54 "lduba [%1] %2, %0\n\t"
55 "membar #Sync"
56 : "=r" (byte)
57 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
58 : "memory");
59 pci_poke_in_progress = 0;
60 pci_poke_cpu = -1;
61 if (!pci_poke_faulted)
62 *ret = byte;
63 spin_unlock_irqrestore(&pci_poke_lock, flags);
64}
65
66void pci_config_read16(u16 *addr, u16 *ret)
67{
68 unsigned long flags;
69 u16 word;
70
71 spin_lock_irqsave(&pci_poke_lock, flags);
72 pci_poke_cpu = smp_processor_id();
73 pci_poke_in_progress = 1;
74 pci_poke_faulted = 0;
75 __asm__ __volatile__("membar #Sync\n\t"
76 "lduha [%1] %2, %0\n\t"
77 "membar #Sync"
78 : "=r" (word)
79 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
80 : "memory");
81 pci_poke_in_progress = 0;
82 pci_poke_cpu = -1;
83 if (!pci_poke_faulted)
84 *ret = word;
85 spin_unlock_irqrestore(&pci_poke_lock, flags);
86}
87
88void pci_config_read32(u32 *addr, u32 *ret)
89{
90 unsigned long flags;
91 u32 dword;
92
93 spin_lock_irqsave(&pci_poke_lock, flags);
94 pci_poke_cpu = smp_processor_id();
95 pci_poke_in_progress = 1;
96 pci_poke_faulted = 0;
97 __asm__ __volatile__("membar #Sync\n\t"
98 "lduwa [%1] %2, %0\n\t"
99 "membar #Sync"
100 : "=r" (dword)
101 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
102 : "memory");
103 pci_poke_in_progress = 0;
104 pci_poke_cpu = -1;
105 if (!pci_poke_faulted)
106 *ret = dword;
107 spin_unlock_irqrestore(&pci_poke_lock, flags);
108}
109
110void pci_config_write8(u8 *addr, u8 val)
111{
112 unsigned long flags;
113
114 spin_lock_irqsave(&pci_poke_lock, flags);
115 pci_poke_cpu = smp_processor_id();
116 pci_poke_in_progress = 1;
117 pci_poke_faulted = 0;
118 __asm__ __volatile__("membar #Sync\n\t"
119 "stba %0, [%1] %2\n\t"
120 "membar #Sync"
121 : /* no outputs */
122 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
123 : "memory");
124 pci_poke_in_progress = 0;
125 pci_poke_cpu = -1;
126 spin_unlock_irqrestore(&pci_poke_lock, flags);
127}
128
129void pci_config_write16(u16 *addr, u16 val)
130{
131 unsigned long flags;
132
133 spin_lock_irqsave(&pci_poke_lock, flags);
134 pci_poke_cpu = smp_processor_id();
135 pci_poke_in_progress = 1;
136 pci_poke_faulted = 0;
137 __asm__ __volatile__("membar #Sync\n\t"
138 "stha %0, [%1] %2\n\t"
139 "membar #Sync"
140 : /* no outputs */
141 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
142 : "memory");
143 pci_poke_in_progress = 0;
144 pci_poke_cpu = -1;
145 spin_unlock_irqrestore(&pci_poke_lock, flags);
146}
147
148void pci_config_write32(u32 *addr, u32 val)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&pci_poke_lock, flags);
153 pci_poke_cpu = smp_processor_id();
154 pci_poke_in_progress = 1;
155 pci_poke_faulted = 0;
156 __asm__ __volatile__("membar #Sync\n\t"
157 "stwa %0, [%1] %2\n\t"
158 "membar #Sync"
159 : /* no outputs */
160 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 : "memory");
162 pci_poke_in_progress = 0;
163 pci_poke_cpu = -1;
164 spin_unlock_irqrestore(&pci_poke_lock, flags);
165}
166
167static int ofpci_verbose;
168
169static int __init ofpci_debug(char *str)
170{
171 int val = 0;
172
173 get_option(&str, &val);
174 if (val)
175 ofpci_verbose = 1;
176 return 1;
177}
178
179__setup("ofpci_debug=", ofpci_debug);
180
181static unsigned long pci_parse_of_flags(u32 addr0)
182{
183 unsigned long flags = 0;
184
185 if (addr0 & 0x02000000) {
186 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
187 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
188 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
189 if (addr0 & 0x40000000)
190 flags |= IORESOURCE_PREFETCH
191 | PCI_BASE_ADDRESS_MEM_PREFETCH;
192 } else if (addr0 & 0x01000000)
193 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
194 return flags;
195}
196
197/* The of_device layer has translated all of the assigned-address properties
198 * into physical address resources, we only have to figure out the register
199 * mapping.
200 */
201static void pci_parse_of_addrs(struct platform_device *op,
202 struct device_node *node,
203 struct pci_dev *dev)
204{
205 struct resource *op_res;
206 const u32 *addrs;
207 int proplen;
208
209 addrs = of_get_property(node, "assigned-addresses", &proplen);
210 if (!addrs)
211 return;
212 if (ofpci_verbose)
213 printk(" parse addresses (%d bytes) @ %p\n",
214 proplen, addrs);
215 op_res = &op->resource[0];
216 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
217 struct resource *res;
218 unsigned long flags;
219 int i;
220
221 flags = pci_parse_of_flags(addrs[0]);
222 if (!flags)
223 continue;
224 i = addrs[0] & 0xff;
225 if (ofpci_verbose)
226 printk(" start: %llx, end: %llx, i: %x\n",
227 op_res->start, op_res->end, i);
228
229 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
230 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
231 } else if (i == dev->rom_base_reg) {
232 res = &dev->resource[PCI_ROM_RESOURCE];
233 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE
234 | IORESOURCE_SIZEALIGN;
235 } else {
236 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
237 continue;
238 }
239 res->start = op_res->start;
240 res->end = op_res->end;
241 res->flags = flags;
242 res->name = pci_name(dev);
243 }
244}
245
246static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
247 struct device_node *node,
248 struct pci_bus *bus, int devfn)
249{
250 struct dev_archdata *sd;
251 struct pci_slot *slot;
252 struct platform_device *op;
253 struct pci_dev *dev;
254 const char *type;
255 u32 class;
256
257 dev = pci_alloc_dev(bus);
258 if (!dev)
259 return NULL;
260
261 sd = &dev->dev.archdata;
262 sd->iommu = pbm->iommu;
263 sd->stc = &pbm->stc;
264 sd->host_controller = pbm;
265 sd->op = op = of_find_device_by_node(node);
266 sd->numa_node = pbm->numa_node;
267
268 sd = &op->dev.archdata;
269 sd->iommu = pbm->iommu;
270 sd->stc = &pbm->stc;
271 sd->numa_node = pbm->numa_node;
272
273 if (!strcmp(node->name, "ebus"))
274 of_propagate_archdata(op);
275
276 type = of_get_property(node, "device_type", NULL);
277 if (type == NULL)
278 type = "";
279
280 if (ofpci_verbose)
281 printk(" create device, devfn: %x, type: %s\n",
282 devfn, type);
283
284 dev->sysdata = node;
285 dev->dev.parent = bus->bridge;
286 dev->dev.bus = &pci_bus_type;
287 dev->dev.of_node = of_node_get(node);
288 dev->devfn = devfn;
289 dev->multifunction = 0; /* maybe a lie? */
290 set_pcie_port_type(dev);
291
292 list_for_each_entry(slot, &dev->bus->slots, list)
293 if (PCI_SLOT(dev->devfn) == slot->number)
294 dev->slot = slot;
295
296 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
297 dev->device = of_getintprop_default(node, "device-id", 0xffff);
298 dev->subsystem_vendor =
299 of_getintprop_default(node, "subsystem-vendor-id", 0);
300 dev->subsystem_device =
301 of_getintprop_default(node, "subsystem-id", 0);
302
303 dev->cfg_size = pci_cfg_space_size(dev);
304
305 /* We can't actually use the firmware value, we have
306 * to read what is in the register right now. One
307 * reason is that in the case of IDE interfaces the
308 * firmware can sample the value before the the IDE
309 * interface is programmed into native mode.
310 */
311 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
312 dev->class = class >> 8;
313 dev->revision = class & 0xff;
314
315 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
316 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
317
318 if (ofpci_verbose)
319 printk(" class: 0x%x device name: %s\n",
320 dev->class, pci_name(dev));
321
322 /* I have seen IDE devices which will not respond to
323 * the bmdma simplex check reads if bus mastering is
324 * disabled.
325 */
326 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
327 pci_set_master(dev);
328
329 dev->current_state = PCI_UNKNOWN; /* unknown power state */
330 dev->error_state = pci_channel_io_normal;
331 dev->dma_mask = 0xffffffff;
332
333 if (!strcmp(node->name, "pci")) {
334 /* a PCI-PCI bridge */
335 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
336 dev->rom_base_reg = PCI_ROM_ADDRESS1;
337 } else if (!strcmp(type, "cardbus")) {
338 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
339 } else {
340 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
341 dev->rom_base_reg = PCI_ROM_ADDRESS;
342
343 dev->irq = sd->op->archdata.irqs[0];
344 if (dev->irq == 0xffffffff)
345 dev->irq = PCI_IRQ_NONE;
346 }
347
348 pci_parse_of_addrs(sd->op, node, dev);
349
350 if (ofpci_verbose)
351 printk(" adding to system ...\n");
352
353 pci_device_add(dev, bus);
354
355 return dev;
356}
357
358static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
359{
360 u32 idx, first, last;
361
362 first = 8;
363 last = 0;
364 for (idx = 0; idx < 8; idx++) {
365 if ((map & (1 << idx)) != 0) {
366 if (first > idx)
367 first = idx;
368 if (last < idx)
369 last = idx;
370 }
371 }
372
373 *first_p = first;
374 *last_p = last;
375}
376
377/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
378 * a proper 'ranges' property.
379 */
380static void apb_fake_ranges(struct pci_dev *dev,
381 struct pci_bus *bus,
382 struct pci_pbm_info *pbm)
383{
384 struct pci_bus_region region;
385 struct resource *res;
386 u32 first, last;
387 u8 map;
388
389 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
390 apb_calc_first_last(map, &first, &last);
391 res = bus->resource[0];
392 res->flags = IORESOURCE_IO;
393 region.start = (first << 21);
394 region.end = (last << 21) + ((1 << 21) - 1);
395 pcibios_bus_to_resource(dev->bus, res, ®ion);
396
397 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
398 apb_calc_first_last(map, &first, &last);
399 res = bus->resource[1];
400 res->flags = IORESOURCE_MEM;
401 region.start = (first << 29);
402 region.end = (last << 29) + ((1 << 29) - 1);
403 pcibios_bus_to_resource(dev->bus, res, ®ion);
404}
405
406static void pci_of_scan_bus(struct pci_pbm_info *pbm,
407 struct device_node *node,
408 struct pci_bus *bus);
409
410#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
411
412static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
413 struct device_node *node,
414 struct pci_dev *dev)
415{
416 struct pci_bus *bus;
417 const u32 *busrange, *ranges;
418 int len, i, simba;
419 struct pci_bus_region region;
420 struct resource *res;
421 unsigned int flags;
422 u64 size;
423
424 if (ofpci_verbose)
425 printk("of_scan_pci_bridge(%s)\n", node->full_name);
426
427 /* parse bus-range property */
428 busrange = of_get_property(node, "bus-range", &len);
429 if (busrange == NULL || len != 8) {
430 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
431 node->full_name);
432 return;
433 }
434 ranges = of_get_property(node, "ranges", &len);
435 simba = 0;
436 if (ranges == NULL) {
437 const char *model = of_get_property(node, "model", NULL);
438 if (model && !strcmp(model, "SUNW,simba"))
439 simba = 1;
440 }
441
442 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
443 if (!bus) {
444 printk(KERN_ERR "Failed to create pci bus for %s\n",
445 node->full_name);
446 return;
447 }
448
449 bus->primary = dev->bus->number;
450 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
451 bus->bridge_ctl = 0;
452
453 /* parse ranges property, or cook one up by hand for Simba */
454 /* PCI #address-cells == 3 and #size-cells == 2 always */
455 res = &dev->resource[PCI_BRIDGE_RESOURCES];
456 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
457 res->flags = 0;
458 bus->resource[i] = res;
459 ++res;
460 }
461 if (simba) {
462 apb_fake_ranges(dev, bus, pbm);
463 goto after_ranges;
464 } else if (ranges == NULL) {
465 pci_read_bridge_bases(bus);
466 goto after_ranges;
467 }
468 i = 1;
469 for (; len >= 32; len -= 32, ranges += 8) {
470 flags = pci_parse_of_flags(ranges[0]);
471 size = GET_64BIT(ranges, 6);
472 if (flags == 0 || size == 0)
473 continue;
474 if (flags & IORESOURCE_IO) {
475 res = bus->resource[0];
476 if (res->flags) {
477 printk(KERN_ERR "PCI: ignoring extra I/O range"
478 " for bridge %s\n", node->full_name);
479 continue;
480 }
481 } else {
482 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
483 printk(KERN_ERR "PCI: too many memory ranges"
484 " for bridge %s\n", node->full_name);
485 continue;
486 }
487 res = bus->resource[i];
488 ++i;
489 }
490
491 res->flags = flags;
492 region.start = GET_64BIT(ranges, 1);
493 region.end = region.start + size - 1;
494 pcibios_bus_to_resource(dev->bus, res, ®ion);
495 }
496after_ranges:
497 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
498 bus->number);
499 if (ofpci_verbose)
500 printk(" bus name: %s\n", bus->name);
501
502 pci_of_scan_bus(pbm, node, bus);
503}
504
505static void pci_of_scan_bus(struct pci_pbm_info *pbm,
506 struct device_node *node,
507 struct pci_bus *bus)
508{
509 struct device_node *child;
510 const u32 *reg;
511 int reglen, devfn, prev_devfn;
512 struct pci_dev *dev;
513
514 if (ofpci_verbose)
515 printk("PCI: scan_bus[%s] bus no %d\n",
516 node->full_name, bus->number);
517
518 child = NULL;
519 prev_devfn = -1;
520 while ((child = of_get_next_child(node, child)) != NULL) {
521 if (ofpci_verbose)
522 printk(" * %s\n", child->full_name);
523 reg = of_get_property(child, "reg", ®len);
524 if (reg == NULL || reglen < 20)
525 continue;
526
527 devfn = (reg[0] >> 8) & 0xff;
528
529 /* This is a workaround for some device trees
530 * which list PCI devices twice. On the V100
531 * for example, device number 3 is listed twice.
532 * Once as "pm" and once again as "lomp".
533 */
534 if (devfn == prev_devfn)
535 continue;
536 prev_devfn = devfn;
537
538 /* create a new pci_dev for this device */
539 dev = of_create_pci_dev(pbm, child, bus, devfn);
540 if (!dev)
541 continue;
542 if (ofpci_verbose)
543 printk("PCI: dev header type: %x\n",
544 dev->hdr_type);
545
546 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
547 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
548 of_scan_pci_bridge(pbm, child, dev);
549 }
550}
551
552static ssize_t
553show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
554{
555 struct pci_dev *pdev;
556 struct device_node *dp;
557
558 pdev = to_pci_dev(dev);
559 dp = pdev->dev.of_node;
560
561 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
562}
563
564static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
565
566static void pci_bus_register_of_sysfs(struct pci_bus *bus)
567{
568 struct pci_dev *dev;
569 struct pci_bus *child_bus;
570 int err;
571
572 list_for_each_entry(dev, &bus->devices, bus_list) {
573 /* we don't really care if we can create this file or
574 * not, but we need to assign the result of the call
575 * or the world will fall under alien invasion and
576 * everybody will be frozen on a spaceship ready to be
577 * eaten on alpha centauri by some green and jelly
578 * humanoid.
579 */
580 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
581 (void) err;
582 }
583 list_for_each_entry(child_bus, &bus->children, node)
584 pci_bus_register_of_sysfs(child_bus);
585}
586
587struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
588 struct device *parent)
589{
590 LIST_HEAD(resources);
591 struct device_node *node = pbm->op->dev.of_node;
592 struct pci_bus *bus;
593
594 printk("PCI: Scanning PBM %s\n", node->full_name);
595
596 pci_add_resource_offset(&resources, &pbm->io_space,
597 pbm->io_space.start);
598 pci_add_resource_offset(&resources, &pbm->mem_space,
599 pbm->mem_space.start);
600 pbm->busn.start = pbm->pci_first_busno;
601 pbm->busn.end = pbm->pci_last_busno;
602 pbm->busn.flags = IORESOURCE_BUS;
603 pci_add_resource(&resources, &pbm->busn);
604 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
605 pbm, &resources);
606 if (!bus) {
607 printk(KERN_ERR "Failed to create bus for %s\n",
608 node->full_name);
609 pci_free_resource_list(&resources);
610 return NULL;
611 }
612
613 pci_of_scan_bus(pbm, node, bus);
614 pci_bus_add_devices(bus);
615 pci_bus_register_of_sysfs(bus);
616
617 return bus;
618}
619
620void pcibios_fixup_bus(struct pci_bus *pbus)
621{
622}
623
624resource_size_t pcibios_align_resource(void *data, const struct resource *res,
625 resource_size_t size, resource_size_t align)
626{
627 return res->start;
628}
629
630int pcibios_enable_device(struct pci_dev *dev, int mask)
631{
632 u16 cmd, oldcmd;
633 int i;
634
635 pci_read_config_word(dev, PCI_COMMAND, &cmd);
636 oldcmd = cmd;
637
638 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
639 struct resource *res = &dev->resource[i];
640
641 /* Only set up the requested stuff */
642 if (!(mask & (1<<i)))
643 continue;
644
645 if (res->flags & IORESOURCE_IO)
646 cmd |= PCI_COMMAND_IO;
647 if (res->flags & IORESOURCE_MEM)
648 cmd |= PCI_COMMAND_MEMORY;
649 }
650
651 if (cmd != oldcmd) {
652 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
653 pci_name(dev), cmd);
654 /* Enable the appropriate bits in the PCI command register. */
655 pci_write_config_word(dev, PCI_COMMAND, cmd);
656 }
657 return 0;
658}
659
660/* Platform support for /proc/bus/pci/X/Y mmap()s. */
661
662/* If the user uses a host-bridge as the PCI device, he may use
663 * this to perform a raw mmap() of the I/O or MEM space behind
664 * that controller.
665 *
666 * This can be useful for execution of x86 PCI bios initialization code
667 * on a PCI card, like the xfree86 int10 stuff does.
668 */
669static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
670 enum pci_mmap_state mmap_state)
671{
672 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
673 unsigned long space_size, user_offset, user_size;
674
675 if (mmap_state == pci_mmap_io) {
676 space_size = resource_size(&pbm->io_space);
677 } else {
678 space_size = resource_size(&pbm->mem_space);
679 }
680
681 /* Make sure the request is in range. */
682 user_offset = vma->vm_pgoff << PAGE_SHIFT;
683 user_size = vma->vm_end - vma->vm_start;
684
685 if (user_offset >= space_size ||
686 (user_offset + user_size) > space_size)
687 return -EINVAL;
688
689 if (mmap_state == pci_mmap_io) {
690 vma->vm_pgoff = (pbm->io_space.start +
691 user_offset) >> PAGE_SHIFT;
692 } else {
693 vma->vm_pgoff = (pbm->mem_space.start +
694 user_offset) >> PAGE_SHIFT;
695 }
696
697 return 0;
698}
699
700/* Adjust vm_pgoff of VMA such that it is the physical page offset
701 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
702 *
703 * Basically, the user finds the base address for his device which he wishes
704 * to mmap. They read the 32-bit value from the config space base register,
705 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
706 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
707 *
708 * Returns negative error code on failure, zero on success.
709 */
710static int __pci_mmap_make_offset(struct pci_dev *pdev,
711 struct vm_area_struct *vma,
712 enum pci_mmap_state mmap_state)
713{
714 unsigned long user_paddr, user_size;
715 int i, err;
716
717 /* First compute the physical address in vma->vm_pgoff,
718 * making sure the user offset is within range in the
719 * appropriate PCI space.
720 */
721 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
722 if (err)
723 return err;
724
725 /* If this is a mapping on a host bridge, any address
726 * is OK.
727 */
728 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
729 return err;
730
731 /* Otherwise make sure it's in the range for one of the
732 * device's resources.
733 */
734 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
735 user_size = vma->vm_end - vma->vm_start;
736
737 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
738 struct resource *rp = &pdev->resource[i];
739 resource_size_t aligned_end;
740
741 /* Active? */
742 if (!rp->flags)
743 continue;
744
745 /* Same type? */
746 if (i == PCI_ROM_RESOURCE) {
747 if (mmap_state != pci_mmap_mem)
748 continue;
749 } else {
750 if ((mmap_state == pci_mmap_io &&
751 (rp->flags & IORESOURCE_IO) == 0) ||
752 (mmap_state == pci_mmap_mem &&
753 (rp->flags & IORESOURCE_MEM) == 0))
754 continue;
755 }
756
757 /* Align the resource end to the next page address.
758 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
759 * because actually we need the address of the next byte
760 * after rp->end.
761 */
762 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
763
764 if ((rp->start <= user_paddr) &&
765 (user_paddr + user_size) <= aligned_end)
766 break;
767 }
768
769 if (i > PCI_ROM_RESOURCE)
770 return -EINVAL;
771
772 return 0;
773}
774
775/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
776 * device mapping.
777 */
778static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
779 enum pci_mmap_state mmap_state)
780{
781 /* Our io_remap_pfn_range takes care of this, do nothing. */
782}
783
784/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
785 * for this architecture. The region in the process to map is described by vm_start
786 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
787 * The pci device structure is provided so that architectures may make mapping
788 * decisions on a per-device or per-bus basis.
789 *
790 * Returns a negative error code on failure, zero on success.
791 */
792int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
793 enum pci_mmap_state mmap_state,
794 int write_combine)
795{
796 int ret;
797
798 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
799 if (ret < 0)
800 return ret;
801
802 __pci_mmap_set_pgprot(dev, vma, mmap_state);
803
804 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
805 ret = io_remap_pfn_range(vma, vma->vm_start,
806 vma->vm_pgoff,
807 vma->vm_end - vma->vm_start,
808 vma->vm_page_prot);
809 if (ret)
810 return ret;
811
812 return 0;
813}
814
815#ifdef CONFIG_NUMA
816int pcibus_to_node(struct pci_bus *pbus)
817{
818 struct pci_pbm_info *pbm = pbus->sysdata;
819
820 return pbm->numa_node;
821}
822EXPORT_SYMBOL(pcibus_to_node);
823#endif
824
825/* Return the domain number for this pci bus */
826
827int pci_domain_nr(struct pci_bus *pbus)
828{
829 struct pci_pbm_info *pbm = pbus->sysdata;
830 int ret;
831
832 if (!pbm) {
833 ret = -ENXIO;
834 } else {
835 ret = pbm->index;
836 }
837
838 return ret;
839}
840EXPORT_SYMBOL(pci_domain_nr);
841
842#ifdef CONFIG_PCI_MSI
843int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
844{
845 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
846 unsigned int irq;
847
848 if (!pbm->setup_msi_irq)
849 return -EINVAL;
850
851 return pbm->setup_msi_irq(&irq, pdev, desc);
852}
853
854void arch_teardown_msi_irq(unsigned int irq)
855{
856 struct msi_desc *entry = irq_get_msi_desc(irq);
857 struct pci_dev *pdev = entry->dev;
858 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
859
860 if (pbm->teardown_msi_irq)
861 pbm->teardown_msi_irq(irq, pdev);
862}
863#endif /* !(CONFIG_PCI_MSI) */
864
865static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
866{
867 struct pci_dev *ali_isa_bridge;
868 u8 val;
869
870 /* ALI sound chips generate 31-bits of DMA, a special register
871 * determines what bit 31 is emitted as.
872 */
873 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
874 PCI_DEVICE_ID_AL_M1533,
875 NULL);
876
877 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
878 if (set_bit)
879 val |= 0x01;
880 else
881 val &= ~0x01;
882 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
883 pci_dev_put(ali_isa_bridge);
884}
885
886int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
887{
888 u64 dma_addr_mask;
889
890 if (pdev == NULL) {
891 dma_addr_mask = 0xffffffff;
892 } else {
893 struct iommu *iommu = pdev->dev.archdata.iommu;
894
895 dma_addr_mask = iommu->dma_addr_mask;
896
897 if (pdev->vendor == PCI_VENDOR_ID_AL &&
898 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
899 device_mask == 0x7fffffff) {
900 ali_sound_dma_hack(pdev,
901 (dma_addr_mask & 0x80000000) != 0);
902 return 1;
903 }
904 }
905
906 if (device_mask >= (1UL << 32UL))
907 return 0;
908
909 return (device_mask & dma_addr_mask) == dma_addr_mask;
910}
911
912void pci_resource_to_user(const struct pci_dev *pdev, int bar,
913 const struct resource *rp, resource_size_t *start,
914 resource_size_t *end)
915{
916 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
917 unsigned long offset;
918
919 if (rp->flags & IORESOURCE_IO)
920 offset = pbm->io_space.start;
921 else
922 offset = pbm->mem_space.start;
923
924 *start = rp->start - offset;
925 *end = rp->end - offset;
926}
927
928void pcibios_set_master(struct pci_dev *dev)
929{
930 /* No special bus mastering setup handling */
931}
932
933static int __init pcibios_init(void)
934{
935 pci_dfl_cache_line_size = 64 >> 2;
936 return 0;
937}
938subsys_initcall(pcibios_init);
939
940#ifdef CONFIG_SYSFS
941static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
942{
943 const struct pci_slot_names {
944 u32 slot_mask;
945 char names[0];
946 } *prop;
947 const char *sp;
948 int len, i;
949 u32 mask;
950
951 prop = of_get_property(node, "slot-names", &len);
952 if (!prop)
953 return;
954
955 mask = prop->slot_mask;
956 sp = prop->names;
957
958 if (ofpci_verbose)
959 printk("PCI: Making slots for [%s] mask[0x%02x]\n",
960 node->full_name, mask);
961
962 i = 0;
963 while (mask) {
964 struct pci_slot *pci_slot;
965 u32 this_bit = 1 << i;
966
967 if (!(mask & this_bit)) {
968 i++;
969 continue;
970 }
971
972 if (ofpci_verbose)
973 printk("PCI: Making slot [%s]\n", sp);
974
975 pci_slot = pci_create_slot(bus, i, sp, NULL);
976 if (IS_ERR(pci_slot))
977 printk(KERN_ERR "PCI: pci_create_slot returned %ld\n",
978 PTR_ERR(pci_slot));
979
980 sp += strlen(sp) + 1;
981 mask &= ~this_bit;
982 i++;
983 }
984}
985
986static int __init of_pci_slot_init(void)
987{
988 struct pci_bus *pbus = NULL;
989
990 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
991 struct device_node *node;
992
993 if (pbus->self) {
994 /* PCI->PCI bridge */
995 node = pbus->self->dev.of_node;
996 } else {
997 struct pci_pbm_info *pbm = pbus->sysdata;
998
999 /* Host PCI controller */
1000 node = pbm->op->dev.of_node;
1001 }
1002
1003 pci_bus_slot_names(node, pbus);
1004 }
1005
1006 return 0;
1007}
1008device_initcall(of_pci_slot_init);
1009#endif