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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/bitops.h>
8#include <linux/err.h>
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/clk-provider.h>
13#include <linux/regmap.h>
14#include <linux/reset-controller.h>
15
16#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
17#include <dt-bindings/reset/qcom,mmcc-msm8974.h>
18
19#include "common.h"
20#include "clk-regmap.h"
21#include "clk-pll.h"
22#include "clk-rcg.h"
23#include "clk-branch.h"
24#include "reset.h"
25#include "gdsc.h"
26
27enum {
28 P_XO,
29 P_MMPLL0,
30 P_EDPLINK,
31 P_MMPLL1,
32 P_HDMIPLL,
33 P_GPLL0,
34 P_EDPVCO,
35 P_GPLL1,
36 P_DSI0PLL,
37 P_DSI0PLL_BYTE,
38 P_MMPLL2,
39 P_MMPLL3,
40 P_DSI1PLL,
41 P_DSI1PLL_BYTE,
42};
43
44static struct clk_pll mmpll0 = {
45 .l_reg = 0x0004,
46 .m_reg = 0x0008,
47 .n_reg = 0x000c,
48 .config_reg = 0x0014,
49 .mode_reg = 0x0000,
50 .status_reg = 0x001c,
51 .status_bit = 17,
52 .clkr.hw.init = &(struct clk_init_data){
53 .name = "mmpll0",
54 .parent_data = (const struct clk_parent_data[]){
55 { .fw_name = "xo", .name = "xo_board" },
56 },
57 .num_parents = 1,
58 .ops = &clk_pll_ops,
59 },
60};
61
62static struct clk_regmap mmpll0_vote = {
63 .enable_reg = 0x0100,
64 .enable_mask = BIT(0),
65 .hw.init = &(struct clk_init_data){
66 .name = "mmpll0_vote",
67 .parent_hws = (const struct clk_hw*[]){
68 &mmpll0.clkr.hw
69 },
70 .num_parents = 1,
71 .ops = &clk_pll_vote_ops,
72 },
73};
74
75static struct clk_pll mmpll1 = {
76 .l_reg = 0x0044,
77 .m_reg = 0x0048,
78 .n_reg = 0x004c,
79 .config_reg = 0x0050,
80 .mode_reg = 0x0040,
81 .status_reg = 0x005c,
82 .status_bit = 17,
83 .clkr.hw.init = &(struct clk_init_data){
84 .name = "mmpll1",
85 .parent_data = (const struct clk_parent_data[]){
86 { .fw_name = "xo", .name = "xo_board" },
87 },
88 .num_parents = 1,
89 .ops = &clk_pll_ops,
90 },
91};
92
93static struct clk_regmap mmpll1_vote = {
94 .enable_reg = 0x0100,
95 .enable_mask = BIT(1),
96 .hw.init = &(struct clk_init_data){
97 .name = "mmpll1_vote",
98 .parent_hws = (const struct clk_hw*[]){
99 &mmpll1.clkr.hw
100 },
101 .num_parents = 1,
102 .ops = &clk_pll_vote_ops,
103 },
104};
105
106static struct clk_pll mmpll2 = {
107 .l_reg = 0x4104,
108 .m_reg = 0x4108,
109 .n_reg = 0x410c,
110 .config_reg = 0x4110,
111 .mode_reg = 0x4100,
112 .status_reg = 0x411c,
113 .clkr.hw.init = &(struct clk_init_data){
114 .name = "mmpll2",
115 .parent_data = (const struct clk_parent_data[]){
116 { .fw_name = "xo", .name = "xo_board" },
117 },
118 .num_parents = 1,
119 .ops = &clk_pll_ops,
120 },
121};
122
123static struct clk_pll mmpll3 = {
124 .l_reg = 0x0084,
125 .m_reg = 0x0088,
126 .n_reg = 0x008c,
127 .config_reg = 0x0090,
128 .mode_reg = 0x0080,
129 .status_reg = 0x009c,
130 .status_bit = 17,
131 .clkr.hw.init = &(struct clk_init_data){
132 .name = "mmpll3",
133 .parent_data = (const struct clk_parent_data[]){
134 { .fw_name = "xo", .name = "xo_board" },
135 },
136 .num_parents = 1,
137 .ops = &clk_pll_ops,
138 },
139};
140
141static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
142 { P_XO, 0 },
143 { P_MMPLL0, 1 },
144 { P_MMPLL1, 2 },
145 { P_GPLL0, 5 }
146};
147
148static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
149 { .fw_name = "xo", .name = "xo_board" },
150 { .hw = &mmpll0_vote.hw },
151 { .hw = &mmpll1_vote.hw },
152 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
153};
154
155static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
156 { P_XO, 0 },
157 { P_MMPLL0, 1 },
158 { P_HDMIPLL, 4 },
159 { P_GPLL0, 5 },
160 { P_DSI0PLL, 2 },
161 { P_DSI1PLL, 3 }
162};
163
164static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
165 { .fw_name = "xo", .name = "xo_board" },
166 { .hw = &mmpll0_vote.hw },
167 { .fw_name = "hdmipll", .name = "hdmipll" },
168 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
169 { .fw_name = "dsi0pll", .name = "dsi0pll" },
170 { .fw_name = "dsi1pll", .name = "dsi1pll" },
171};
172
173static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
174 { P_XO, 0 },
175 { P_MMPLL0, 1 },
176 { P_MMPLL1, 2 },
177 { P_GPLL0, 5 },
178 { P_MMPLL3, 3 }
179};
180
181static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
182 { .fw_name = "xo", .name = "xo_board" },
183 { .hw = &mmpll0_vote.hw },
184 { .hw = &mmpll1_vote.hw },
185 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
186 { .hw = &mmpll3.clkr.hw },
187};
188
189static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
190 { P_XO, 0 },
191 { P_MMPLL0, 1 },
192 { P_MMPLL1, 2 },
193 { P_GPLL0, 5 },
194 { P_GPLL1, 4 }
195};
196
197static const struct clk_parent_data mmcc_xo_mmpll0_1_gpll1_0[] = {
198 { .fw_name = "xo", .name = "xo_board" },
199 { .hw = &mmpll0_vote.hw },
200 { .hw = &mmpll1_vote.hw },
201 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
202 { .fw_name = "gpll1_vote", .name = "gpll1_vote" },
203};
204
205static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
206 { P_XO, 0 },
207 { P_EDPLINK, 4 },
208 { P_HDMIPLL, 3 },
209 { P_EDPVCO, 5 },
210 { P_DSI0PLL, 1 },
211 { P_DSI1PLL, 2 }
212};
213
214static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
215 { .fw_name = "xo", .name = "xo_board" },
216 { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
217 { .fw_name = "hdmipll", .name = "hdmipll" },
218 { .fw_name = "edp_vco_div", .name = "edp_vco_div" },
219 { .fw_name = "dsi0pll", .name = "dsi0pll" },
220 { .fw_name = "dsi1pll", .name = "dsi1pll" },
221};
222
223static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
224 { P_XO, 0 },
225 { P_EDPLINK, 4 },
226 { P_HDMIPLL, 3 },
227 { P_GPLL0, 5 },
228 { P_DSI0PLL, 1 },
229 { P_DSI1PLL, 2 }
230};
231
232static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
233 { .fw_name = "xo", .name = "xo_board" },
234 { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
235 { .fw_name = "hdmipll", .name = "hdmipll" },
236 { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
237 { .fw_name = "dsi0pll", .name = "dsi0pll" },
238 { .fw_name = "dsi1pll", .name = "dsi1pll" },
239};
240
241static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
242 { P_XO, 0 },
243 { P_EDPLINK, 4 },
244 { P_HDMIPLL, 3 },
245 { P_GPLL0, 5 },
246 { P_DSI0PLL_BYTE, 1 },
247 { P_DSI1PLL_BYTE, 2 }
248};
249
250static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
251 { .fw_name = "xo", .name = "xo_board" },
252 { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
253 { .fw_name = "hdmipll", .name = "hdmipll" },
254 { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
255 { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
256 { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
257};
258
259static struct clk_rcg2 mmss_ahb_clk_src = {
260 .cmd_rcgr = 0x5000,
261 .hid_width = 5,
262 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
263 .clkr.hw.init = &(struct clk_init_data){
264 .name = "mmss_ahb_clk_src",
265 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
266 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
267 .ops = &clk_rcg2_ops,
268 },
269};
270
271static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
272 F(19200000, P_XO, 1, 0, 0),
273 F(37500000, P_GPLL0, 16, 0, 0),
274 F(50000000, P_GPLL0, 12, 0, 0),
275 F(75000000, P_GPLL0, 8, 0, 0),
276 F(100000000, P_GPLL0, 6, 0, 0),
277 F(150000000, P_GPLL0, 4, 0, 0),
278 F(200000000, P_MMPLL0, 4, 0, 0),
279 F(266666666, P_MMPLL0, 3, 0, 0),
280 { }
281};
282
283static struct freq_tbl ftbl_mmss_axi_clk[] = {
284 F( 19200000, P_XO, 1, 0, 0),
285 F( 37500000, P_GPLL0, 16, 0, 0),
286 F( 50000000, P_GPLL0, 12, 0, 0),
287 F( 75000000, P_GPLL0, 8, 0, 0),
288 F(100000000, P_GPLL0, 6, 0, 0),
289 F(150000000, P_GPLL0, 4, 0, 0),
290 F(291750000, P_MMPLL1, 4, 0, 0),
291 F(400000000, P_MMPLL0, 2, 0, 0),
292 F(466800000, P_MMPLL1, 2.5, 0, 0),
293};
294
295static struct clk_rcg2 mmss_axi_clk_src = {
296 .cmd_rcgr = 0x5040,
297 .hid_width = 5,
298 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
299 .freq_tbl = ftbl_mmss_axi_clk,
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "mmss_axi_clk_src",
302 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
303 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
304 .ops = &clk_rcg2_ops,
305 },
306};
307
308static struct freq_tbl ftbl_ocmemnoc_clk[] = {
309 F( 19200000, P_XO, 1, 0, 0),
310 F( 37500000, P_GPLL0, 16, 0, 0),
311 F( 50000000, P_GPLL0, 12, 0, 0),
312 F( 75000000, P_GPLL0, 8, 0, 0),
313 F(100000000, P_GPLL0, 6, 0, 0),
314 F(150000000, P_GPLL0, 4, 0, 0),
315 F(291750000, P_MMPLL1, 4, 0, 0),
316 F(400000000, P_MMPLL0, 2, 0, 0),
317};
318
319static struct clk_rcg2 ocmemnoc_clk_src = {
320 .cmd_rcgr = 0x5090,
321 .hid_width = 5,
322 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
323 .freq_tbl = ftbl_ocmemnoc_clk,
324 .clkr.hw.init = &(struct clk_init_data){
325 .name = "ocmemnoc_clk_src",
326 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
327 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
328 .ops = &clk_rcg2_ops,
329 },
330};
331
332static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
333 F(100000000, P_GPLL0, 6, 0, 0),
334 F(200000000, P_MMPLL0, 4, 0, 0),
335 { }
336};
337
338static struct clk_rcg2 csi0_clk_src = {
339 .cmd_rcgr = 0x3090,
340 .hid_width = 5,
341 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
342 .freq_tbl = ftbl_camss_csi0_3_clk,
343 .clkr.hw.init = &(struct clk_init_data){
344 .name = "csi0_clk_src",
345 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
346 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
347 .ops = &clk_rcg2_ops,
348 },
349};
350
351static struct clk_rcg2 csi1_clk_src = {
352 .cmd_rcgr = 0x3100,
353 .hid_width = 5,
354 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
355 .freq_tbl = ftbl_camss_csi0_3_clk,
356 .clkr.hw.init = &(struct clk_init_data){
357 .name = "csi1_clk_src",
358 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
359 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
360 .ops = &clk_rcg2_ops,
361 },
362};
363
364static struct clk_rcg2 csi2_clk_src = {
365 .cmd_rcgr = 0x3160,
366 .hid_width = 5,
367 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
368 .freq_tbl = ftbl_camss_csi0_3_clk,
369 .clkr.hw.init = &(struct clk_init_data){
370 .name = "csi2_clk_src",
371 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
372 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
373 .ops = &clk_rcg2_ops,
374 },
375};
376
377static struct clk_rcg2 csi3_clk_src = {
378 .cmd_rcgr = 0x31c0,
379 .hid_width = 5,
380 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
381 .freq_tbl = ftbl_camss_csi0_3_clk,
382 .clkr.hw.init = &(struct clk_init_data){
383 .name = "csi3_clk_src",
384 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
385 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
386 .ops = &clk_rcg2_ops,
387 },
388};
389
390static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
391 F(37500000, P_GPLL0, 16, 0, 0),
392 F(50000000, P_GPLL0, 12, 0, 0),
393 F(60000000, P_GPLL0, 10, 0, 0),
394 F(80000000, P_GPLL0, 7.5, 0, 0),
395 F(100000000, P_GPLL0, 6, 0, 0),
396 F(109090000, P_GPLL0, 5.5, 0, 0),
397 F(133330000, P_GPLL0, 4.5, 0, 0),
398 F(150000000, P_GPLL0, 4, 0, 0),
399 F(200000000, P_GPLL0, 3, 0, 0),
400 F(228570000, P_MMPLL0, 3.5, 0, 0),
401 F(266670000, P_MMPLL0, 3, 0, 0),
402 F(320000000, P_MMPLL0, 2.5, 0, 0),
403 F(400000000, P_MMPLL0, 2, 0, 0),
404 { }
405};
406
407static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
408 F(37500000, P_GPLL0, 16, 0, 0),
409 F(50000000, P_GPLL0, 12, 0, 0),
410 F(60000000, P_GPLL0, 10, 0, 0),
411 F(80000000, P_GPLL0, 7.5, 0, 0),
412 F(100000000, P_GPLL0, 6, 0, 0),
413 F(109090000, P_GPLL0, 5.5, 0, 0),
414 F(133330000, P_GPLL0, 4.5, 0, 0),
415 F(200000000, P_GPLL0, 3, 0, 0),
416 F(228570000, P_MMPLL0, 3.5, 0, 0),
417 F(266670000, P_MMPLL0, 3, 0, 0),
418 F(320000000, P_MMPLL0, 2.5, 0, 0),
419 F(400000000, P_MMPLL0, 2, 0, 0),
420 F(465000000, P_MMPLL3, 2, 0, 0),
421 { }
422};
423
424static struct clk_rcg2 vfe0_clk_src = {
425 .cmd_rcgr = 0x3600,
426 .hid_width = 5,
427 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
428 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
429 .clkr.hw.init = &(struct clk_init_data){
430 .name = "vfe0_clk_src",
431 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
432 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
433 .ops = &clk_rcg2_ops,
434 },
435};
436
437static struct clk_rcg2 vfe1_clk_src = {
438 .cmd_rcgr = 0x3620,
439 .hid_width = 5,
440 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
441 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
442 .clkr.hw.init = &(struct clk_init_data){
443 .name = "vfe1_clk_src",
444 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
445 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
446 .ops = &clk_rcg2_ops,
447 },
448};
449
450static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
451 F(37500000, P_GPLL0, 16, 0, 0),
452 F(60000000, P_GPLL0, 10, 0, 0),
453 F(75000000, P_GPLL0, 8, 0, 0),
454 F(92310000, P_GPLL0, 6.5, 0, 0),
455 F(100000000, P_GPLL0, 6, 0, 0),
456 F(133330000, P_MMPLL0, 6, 0, 0),
457 F(177780000, P_MMPLL0, 4.5, 0, 0),
458 F(200000000, P_MMPLL0, 4, 0, 0),
459 { }
460};
461
462static struct freq_tbl ftbl_mdss_mdp_clk[] = {
463 F(37500000, P_GPLL0, 16, 0, 0),
464 F(60000000, P_GPLL0, 10, 0, 0),
465 F(75000000, P_GPLL0, 8, 0, 0),
466 F(85710000, P_GPLL0, 7, 0, 0),
467 F(100000000, P_GPLL0, 6, 0, 0),
468 F(133330000, P_MMPLL0, 6, 0, 0),
469 F(160000000, P_MMPLL0, 5, 0, 0),
470 F(200000000, P_MMPLL0, 4, 0, 0),
471 F(228570000, P_MMPLL0, 3.5, 0, 0),
472 F(240000000, P_GPLL0, 2.5, 0, 0),
473 F(266670000, P_MMPLL0, 3, 0, 0),
474 F(320000000, P_MMPLL0, 2.5, 0, 0),
475 { }
476};
477
478static struct clk_rcg2 mdp_clk_src = {
479 .cmd_rcgr = 0x2040,
480 .hid_width = 5,
481 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
482 .freq_tbl = ftbl_mdss_mdp_clk,
483 .clkr.hw.init = &(struct clk_init_data){
484 .name = "mdp_clk_src",
485 .parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
486 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
487 .ops = &clk_rcg2_shared_ops,
488 },
489};
490
491static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
492 F(75000000, P_GPLL0, 8, 0, 0),
493 F(133330000, P_GPLL0, 4.5, 0, 0),
494 F(200000000, P_GPLL0, 3, 0, 0),
495 F(228570000, P_MMPLL0, 3.5, 0, 0),
496 F(266670000, P_MMPLL0, 3, 0, 0),
497 F(320000000, P_MMPLL0, 2.5, 0, 0),
498 { }
499};
500
501static struct clk_rcg2 jpeg0_clk_src = {
502 .cmd_rcgr = 0x3500,
503 .hid_width = 5,
504 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
505 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
506 .clkr.hw.init = &(struct clk_init_data){
507 .name = "jpeg0_clk_src",
508 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
509 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
510 .ops = &clk_rcg2_ops,
511 },
512};
513
514static struct clk_rcg2 jpeg1_clk_src = {
515 .cmd_rcgr = 0x3520,
516 .hid_width = 5,
517 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
518 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
519 .clkr.hw.init = &(struct clk_init_data){
520 .name = "jpeg1_clk_src",
521 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
522 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
523 .ops = &clk_rcg2_ops,
524 },
525};
526
527static struct clk_rcg2 jpeg2_clk_src = {
528 .cmd_rcgr = 0x3540,
529 .hid_width = 5,
530 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
531 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
532 .clkr.hw.init = &(struct clk_init_data){
533 .name = "jpeg2_clk_src",
534 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
535 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
536 .ops = &clk_rcg2_ops,
537 },
538};
539
540static struct clk_rcg2 pclk0_clk_src = {
541 .cmd_rcgr = 0x2000,
542 .mnd_width = 8,
543 .hid_width = 5,
544 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
545 .clkr.hw.init = &(struct clk_init_data){
546 .name = "pclk0_clk_src",
547 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
548 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
549 .ops = &clk_pixel_ops,
550 .flags = CLK_SET_RATE_PARENT,
551 },
552};
553
554static struct clk_rcg2 pclk1_clk_src = {
555 .cmd_rcgr = 0x2020,
556 .mnd_width = 8,
557 .hid_width = 5,
558 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
559 .clkr.hw.init = &(struct clk_init_data){
560 .name = "pclk1_clk_src",
561 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
562 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
563 .ops = &clk_pixel_ops,
564 .flags = CLK_SET_RATE_PARENT,
565 },
566};
567
568static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
569 F(66700000, P_GPLL0, 9, 0, 0),
570 F(100000000, P_GPLL0, 6, 0, 0),
571 F(133330000, P_MMPLL0, 6, 0, 0),
572 F(160000000, P_MMPLL0, 5, 0, 0),
573 { }
574};
575
576static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
577 F(50000000, P_GPLL0, 12, 0, 0),
578 F(100000000, P_GPLL0, 6, 0, 0),
579 F(133330000, P_MMPLL0, 6, 0, 0),
580 F(200000000, P_MMPLL0, 4, 0, 0),
581 F(266670000, P_MMPLL0, 3, 0, 0),
582 F(465000000, P_MMPLL3, 2, 0, 0),
583 { }
584};
585
586static struct clk_rcg2 vcodec0_clk_src = {
587 .cmd_rcgr = 0x1000,
588 .mnd_width = 8,
589 .hid_width = 5,
590 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
591 .freq_tbl = ftbl_venus0_vcodec0_clk,
592 .clkr.hw.init = &(struct clk_init_data){
593 .name = "vcodec0_clk_src",
594 .parent_data = mmcc_xo_mmpll0_1_3_gpll0,
595 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
596 .ops = &clk_rcg2_ops,
597 },
598};
599
600static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
601 F(19200000, P_XO, 1, 0, 0),
602 { }
603};
604
605static struct clk_rcg2 cci_clk_src = {
606 .cmd_rcgr = 0x3300,
607 .hid_width = 5,
608 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
609 .freq_tbl = ftbl_camss_cci_cci_clk,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "cci_clk_src",
612 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
613 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
614 .ops = &clk_rcg2_ops,
615 },
616};
617
618static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
619 F(10000, P_XO, 16, 1, 120),
620 F(24000, P_XO, 16, 1, 50),
621 F(6000000, P_GPLL0, 10, 1, 10),
622 F(12000000, P_GPLL0, 10, 1, 5),
623 F(13000000, P_GPLL0, 4, 13, 150),
624 F(24000000, P_GPLL0, 5, 1, 5),
625 { }
626};
627
628static struct clk_rcg2 camss_gp0_clk_src = {
629 .cmd_rcgr = 0x3420,
630 .mnd_width = 8,
631 .hid_width = 5,
632 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
633 .freq_tbl = ftbl_camss_gp0_1_clk,
634 .clkr.hw.init = &(struct clk_init_data){
635 .name = "camss_gp0_clk_src",
636 .parent_data = mmcc_xo_mmpll0_1_gpll1_0,
637 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
638 .ops = &clk_rcg2_ops,
639 },
640};
641
642static struct clk_rcg2 camss_gp1_clk_src = {
643 .cmd_rcgr = 0x3450,
644 .mnd_width = 8,
645 .hid_width = 5,
646 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
647 .freq_tbl = ftbl_camss_gp0_1_clk,
648 .clkr.hw.init = &(struct clk_init_data){
649 .name = "camss_gp1_clk_src",
650 .parent_data = mmcc_xo_mmpll0_1_gpll1_0,
651 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
652 .ops = &clk_rcg2_ops,
653 },
654};
655
656static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
657 F(19200000, P_XO, 1, 0, 0),
658 F(24000000, P_GPLL0, 5, 1, 5),
659 F(66670000, P_GPLL0, 9, 0, 0),
660 { }
661};
662
663static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
664 F(4800000, P_XO, 4, 0, 0),
665 F(6000000, P_GPLL0, 10, 1, 10),
666 F(8000000, P_GPLL0, 15, 1, 5),
667 F(9600000, P_XO, 2, 0, 0),
668 F(16000000, P_GPLL0, 12.5, 1, 3),
669 F(19200000, P_XO, 1, 0, 0),
670 F(24000000, P_GPLL0, 5, 1, 5),
671 F(32000000, P_MMPLL0, 5, 1, 5),
672 F(48000000, P_GPLL0, 12.5, 0, 0),
673 F(64000000, P_MMPLL0, 12.5, 0, 0),
674 F(66670000, P_GPLL0, 9, 0, 0),
675 { }
676};
677
678static struct clk_rcg2 mclk0_clk_src = {
679 .cmd_rcgr = 0x3360,
680 .hid_width = 5,
681 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
682 .freq_tbl = ftbl_camss_mclk0_3_clk,
683 .clkr.hw.init = &(struct clk_init_data){
684 .name = "mclk0_clk_src",
685 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
686 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
687 .ops = &clk_rcg2_ops,
688 },
689};
690
691static struct clk_rcg2 mclk1_clk_src = {
692 .cmd_rcgr = 0x3390,
693 .hid_width = 5,
694 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
695 .freq_tbl = ftbl_camss_mclk0_3_clk,
696 .clkr.hw.init = &(struct clk_init_data){
697 .name = "mclk1_clk_src",
698 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
699 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
700 .ops = &clk_rcg2_ops,
701 },
702};
703
704static struct clk_rcg2 mclk2_clk_src = {
705 .cmd_rcgr = 0x33c0,
706 .hid_width = 5,
707 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
708 .freq_tbl = ftbl_camss_mclk0_3_clk,
709 .clkr.hw.init = &(struct clk_init_data){
710 .name = "mclk2_clk_src",
711 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
712 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
713 .ops = &clk_rcg2_ops,
714 },
715};
716
717static struct clk_rcg2 mclk3_clk_src = {
718 .cmd_rcgr = 0x33f0,
719 .hid_width = 5,
720 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
721 .freq_tbl = ftbl_camss_mclk0_3_clk,
722 .clkr.hw.init = &(struct clk_init_data){
723 .name = "mclk3_clk_src",
724 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
725 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
726 .ops = &clk_rcg2_ops,
727 },
728};
729
730static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
731 F(100000000, P_GPLL0, 6, 0, 0),
732 F(200000000, P_MMPLL0, 4, 0, 0),
733 { }
734};
735
736static struct clk_rcg2 csi0phytimer_clk_src = {
737 .cmd_rcgr = 0x3000,
738 .hid_width = 5,
739 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
740 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
741 .clkr.hw.init = &(struct clk_init_data){
742 .name = "csi0phytimer_clk_src",
743 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
744 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
745 .ops = &clk_rcg2_ops,
746 },
747};
748
749static struct clk_rcg2 csi1phytimer_clk_src = {
750 .cmd_rcgr = 0x3030,
751 .hid_width = 5,
752 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
753 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
754 .clkr.hw.init = &(struct clk_init_data){
755 .name = "csi1phytimer_clk_src",
756 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
757 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
758 .ops = &clk_rcg2_ops,
759 },
760};
761
762static struct clk_rcg2 csi2phytimer_clk_src = {
763 .cmd_rcgr = 0x3060,
764 .hid_width = 5,
765 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
766 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
767 .clkr.hw.init = &(struct clk_init_data){
768 .name = "csi2phytimer_clk_src",
769 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
770 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
771 .ops = &clk_rcg2_ops,
772 },
773};
774
775static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
776 F(133330000, P_GPLL0, 4.5, 0, 0),
777 F(150000000, P_GPLL0, 4, 0, 0),
778 F(266670000, P_MMPLL0, 3, 0, 0),
779 F(320000000, P_MMPLL0, 2.5, 0, 0),
780 F(400000000, P_MMPLL0, 2, 0, 0),
781 { }
782};
783
784static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
785 F(133330000, P_GPLL0, 4.5, 0, 0),
786 F(266670000, P_MMPLL0, 3, 0, 0),
787 F(320000000, P_MMPLL0, 2.5, 0, 0),
788 F(400000000, P_MMPLL0, 2, 0, 0),
789 F(465000000, P_MMPLL3, 2, 0, 0),
790 { }
791};
792
793static struct clk_rcg2 cpp_clk_src = {
794 .cmd_rcgr = 0x3640,
795 .hid_width = 5,
796 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
797 .freq_tbl = ftbl_camss_vfe_cpp_clk,
798 .clkr.hw.init = &(struct clk_init_data){
799 .name = "cpp_clk_src",
800 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
801 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
802 .ops = &clk_rcg2_ops,
803 },
804};
805
806static struct freq_tbl byte_freq_tbl[] = {
807 { .src = P_DSI0PLL_BYTE },
808 { }
809};
810
811static struct clk_rcg2 byte0_clk_src = {
812 .cmd_rcgr = 0x2120,
813 .hid_width = 5,
814 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
815 .freq_tbl = byte_freq_tbl,
816 .clkr.hw.init = &(struct clk_init_data){
817 .name = "byte0_clk_src",
818 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
819 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
820 .ops = &clk_byte2_ops,
821 .flags = CLK_SET_RATE_PARENT,
822 },
823};
824
825static struct clk_rcg2 byte1_clk_src = {
826 .cmd_rcgr = 0x2140,
827 .hid_width = 5,
828 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
829 .freq_tbl = byte_freq_tbl,
830 .clkr.hw.init = &(struct clk_init_data){
831 .name = "byte1_clk_src",
832 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
833 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
834 .ops = &clk_byte2_ops,
835 .flags = CLK_SET_RATE_PARENT,
836 },
837};
838
839static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
840 F(19200000, P_XO, 1, 0, 0),
841 { }
842};
843
844static struct clk_rcg2 edpaux_clk_src = {
845 .cmd_rcgr = 0x20e0,
846 .hid_width = 5,
847 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
848 .freq_tbl = ftbl_mdss_edpaux_clk,
849 .clkr.hw.init = &(struct clk_init_data){
850 .name = "edpaux_clk_src",
851 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
852 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
853 .ops = &clk_rcg2_ops,
854 },
855};
856
857static struct freq_tbl ftbl_mdss_edplink_clk[] = {
858 F(135000000, P_EDPLINK, 2, 0, 0),
859 F(270000000, P_EDPLINK, 11, 0, 0),
860 { }
861};
862
863static struct clk_rcg2 edplink_clk_src = {
864 .cmd_rcgr = 0x20c0,
865 .hid_width = 5,
866 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
867 .freq_tbl = ftbl_mdss_edplink_clk,
868 .clkr.hw.init = &(struct clk_init_data){
869 .name = "edplink_clk_src",
870 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
871 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
872 .ops = &clk_rcg2_ops,
873 .flags = CLK_SET_RATE_PARENT,
874 },
875};
876
877static struct freq_tbl edp_pixel_freq_tbl[] = {
878 { .src = P_EDPVCO },
879 { }
880};
881
882static struct clk_rcg2 edppixel_clk_src = {
883 .cmd_rcgr = 0x20a0,
884 .mnd_width = 8,
885 .hid_width = 5,
886 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
887 .freq_tbl = edp_pixel_freq_tbl,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "edppixel_clk_src",
890 .parent_data = mmcc_xo_dsi_hdmi_edp,
891 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
892 .ops = &clk_edp_pixel_ops,
893 },
894};
895
896static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
897 F(19200000, P_XO, 1, 0, 0),
898 { }
899};
900
901static struct clk_rcg2 esc0_clk_src = {
902 .cmd_rcgr = 0x2160,
903 .hid_width = 5,
904 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
905 .freq_tbl = ftbl_mdss_esc0_1_clk,
906 .clkr.hw.init = &(struct clk_init_data){
907 .name = "esc0_clk_src",
908 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
909 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
910 .ops = &clk_rcg2_ops,
911 },
912};
913
914static struct clk_rcg2 esc1_clk_src = {
915 .cmd_rcgr = 0x2180,
916 .hid_width = 5,
917 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
918 .freq_tbl = ftbl_mdss_esc0_1_clk,
919 .clkr.hw.init = &(struct clk_init_data){
920 .name = "esc1_clk_src",
921 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
922 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
923 .ops = &clk_rcg2_ops,
924 },
925};
926
927static struct freq_tbl extpclk_freq_tbl[] = {
928 { .src = P_HDMIPLL },
929 { }
930};
931
932static struct clk_rcg2 extpclk_clk_src = {
933 .cmd_rcgr = 0x2060,
934 .hid_width = 5,
935 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
936 .freq_tbl = extpclk_freq_tbl,
937 .clkr.hw.init = &(struct clk_init_data){
938 .name = "extpclk_clk_src",
939 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
940 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
941 .ops = &clk_byte_ops,
942 .flags = CLK_SET_RATE_PARENT,
943 },
944};
945
946static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
947 F(19200000, P_XO, 1, 0, 0),
948 { }
949};
950
951static struct clk_rcg2 hdmi_clk_src = {
952 .cmd_rcgr = 0x2100,
953 .hid_width = 5,
954 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
955 .freq_tbl = ftbl_mdss_hdmi_clk,
956 .clkr.hw.init = &(struct clk_init_data){
957 .name = "hdmi_clk_src",
958 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
959 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
960 .ops = &clk_rcg2_ops,
961 },
962};
963
964static struct freq_tbl ftbl_mdss_vsync_clk[] = {
965 F(19200000, P_XO, 1, 0, 0),
966 { }
967};
968
969static struct clk_rcg2 vsync_clk_src = {
970 .cmd_rcgr = 0x2080,
971 .hid_width = 5,
972 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
973 .freq_tbl = ftbl_mdss_vsync_clk,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "vsync_clk_src",
976 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
977 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
978 .ops = &clk_rcg2_ops,
979 },
980};
981
982static struct clk_branch camss_cci_cci_ahb_clk = {
983 .halt_reg = 0x3348,
984 .clkr = {
985 .enable_reg = 0x3348,
986 .enable_mask = BIT(0),
987 .hw.init = &(struct clk_init_data){
988 .name = "camss_cci_cci_ahb_clk",
989 .parent_hws = (const struct clk_hw*[]){
990 &mmss_ahb_clk_src.clkr.hw
991 },
992 .num_parents = 1,
993 .ops = &clk_branch2_ops,
994 },
995 },
996};
997
998static struct clk_branch camss_cci_cci_clk = {
999 .halt_reg = 0x3344,
1000 .clkr = {
1001 .enable_reg = 0x3344,
1002 .enable_mask = BIT(0),
1003 .hw.init = &(struct clk_init_data){
1004 .name = "camss_cci_cci_clk",
1005 .parent_hws = (const struct clk_hw*[]){
1006 &cci_clk_src.clkr.hw
1007 },
1008 .num_parents = 1,
1009 .flags = CLK_SET_RATE_PARENT,
1010 .ops = &clk_branch2_ops,
1011 },
1012 },
1013};
1014
1015static struct clk_branch camss_csi0_ahb_clk = {
1016 .halt_reg = 0x30bc,
1017 .clkr = {
1018 .enable_reg = 0x30bc,
1019 .enable_mask = BIT(0),
1020 .hw.init = &(struct clk_init_data){
1021 .name = "camss_csi0_ahb_clk",
1022 .parent_hws = (const struct clk_hw*[]){
1023 &mmss_ahb_clk_src.clkr.hw
1024 },
1025 .num_parents = 1,
1026 .ops = &clk_branch2_ops,
1027 },
1028 },
1029};
1030
1031static struct clk_branch camss_csi0_clk = {
1032 .halt_reg = 0x30b4,
1033 .clkr = {
1034 .enable_reg = 0x30b4,
1035 .enable_mask = BIT(0),
1036 .hw.init = &(struct clk_init_data){
1037 .name = "camss_csi0_clk",
1038 .parent_hws = (const struct clk_hw*[]){
1039 &csi0_clk_src.clkr.hw
1040 },
1041 .num_parents = 1,
1042 .flags = CLK_SET_RATE_PARENT,
1043 .ops = &clk_branch2_ops,
1044 },
1045 },
1046};
1047
1048static struct clk_branch camss_csi0phy_clk = {
1049 .halt_reg = 0x30c4,
1050 .clkr = {
1051 .enable_reg = 0x30c4,
1052 .enable_mask = BIT(0),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "camss_csi0phy_clk",
1055 .parent_hws = (const struct clk_hw*[]){
1056 &csi0_clk_src.clkr.hw
1057 },
1058 .num_parents = 1,
1059 .flags = CLK_SET_RATE_PARENT,
1060 .ops = &clk_branch2_ops,
1061 },
1062 },
1063};
1064
1065static struct clk_branch camss_csi0pix_clk = {
1066 .halt_reg = 0x30e4,
1067 .clkr = {
1068 .enable_reg = 0x30e4,
1069 .enable_mask = BIT(0),
1070 .hw.init = &(struct clk_init_data){
1071 .name = "camss_csi0pix_clk",
1072 .parent_hws = (const struct clk_hw*[]){
1073 &csi0_clk_src.clkr.hw
1074 },
1075 .num_parents = 1,
1076 .flags = CLK_SET_RATE_PARENT,
1077 .ops = &clk_branch2_ops,
1078 },
1079 },
1080};
1081
1082static struct clk_branch camss_csi0rdi_clk = {
1083 .halt_reg = 0x30d4,
1084 .clkr = {
1085 .enable_reg = 0x30d4,
1086 .enable_mask = BIT(0),
1087 .hw.init = &(struct clk_init_data){
1088 .name = "camss_csi0rdi_clk",
1089 .parent_hws = (const struct clk_hw*[]){
1090 &csi0_clk_src.clkr.hw
1091 },
1092 .num_parents = 1,
1093 .flags = CLK_SET_RATE_PARENT,
1094 .ops = &clk_branch2_ops,
1095 },
1096 },
1097};
1098
1099static struct clk_branch camss_csi1_ahb_clk = {
1100 .halt_reg = 0x3128,
1101 .clkr = {
1102 .enable_reg = 0x3128,
1103 .enable_mask = BIT(0),
1104 .hw.init = &(struct clk_init_data){
1105 .name = "camss_csi1_ahb_clk",
1106 .parent_hws = (const struct clk_hw*[]){
1107 &mmss_ahb_clk_src.clkr.hw
1108 },
1109 .num_parents = 1,
1110 .ops = &clk_branch2_ops,
1111 },
1112 },
1113};
1114
1115static struct clk_branch camss_csi1_clk = {
1116 .halt_reg = 0x3124,
1117 .clkr = {
1118 .enable_reg = 0x3124,
1119 .enable_mask = BIT(0),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "camss_csi1_clk",
1122 .parent_hws = (const struct clk_hw*[]){
1123 &csi1_clk_src.clkr.hw
1124 },
1125 .num_parents = 1,
1126 .flags = CLK_SET_RATE_PARENT,
1127 .ops = &clk_branch2_ops,
1128 },
1129 },
1130};
1131
1132static struct clk_branch camss_csi1phy_clk = {
1133 .halt_reg = 0x3134,
1134 .clkr = {
1135 .enable_reg = 0x3134,
1136 .enable_mask = BIT(0),
1137 .hw.init = &(struct clk_init_data){
1138 .name = "camss_csi1phy_clk",
1139 .parent_hws = (const struct clk_hw*[]){
1140 &csi1_clk_src.clkr.hw
1141 },
1142 .num_parents = 1,
1143 .flags = CLK_SET_RATE_PARENT,
1144 .ops = &clk_branch2_ops,
1145 },
1146 },
1147};
1148
1149static struct clk_branch camss_csi1pix_clk = {
1150 .halt_reg = 0x3154,
1151 .clkr = {
1152 .enable_reg = 0x3154,
1153 .enable_mask = BIT(0),
1154 .hw.init = &(struct clk_init_data){
1155 .name = "camss_csi1pix_clk",
1156 .parent_hws = (const struct clk_hw*[]){
1157 &csi1_clk_src.clkr.hw
1158 },
1159 .num_parents = 1,
1160 .flags = CLK_SET_RATE_PARENT,
1161 .ops = &clk_branch2_ops,
1162 },
1163 },
1164};
1165
1166static struct clk_branch camss_csi1rdi_clk = {
1167 .halt_reg = 0x3144,
1168 .clkr = {
1169 .enable_reg = 0x3144,
1170 .enable_mask = BIT(0),
1171 .hw.init = &(struct clk_init_data){
1172 .name = "camss_csi1rdi_clk",
1173 .parent_hws = (const struct clk_hw*[]){
1174 &csi1_clk_src.clkr.hw
1175 },
1176 .num_parents = 1,
1177 .flags = CLK_SET_RATE_PARENT,
1178 .ops = &clk_branch2_ops,
1179 },
1180 },
1181};
1182
1183static struct clk_branch camss_csi2_ahb_clk = {
1184 .halt_reg = 0x3188,
1185 .clkr = {
1186 .enable_reg = 0x3188,
1187 .enable_mask = BIT(0),
1188 .hw.init = &(struct clk_init_data){
1189 .name = "camss_csi2_ahb_clk",
1190 .parent_hws = (const struct clk_hw*[]){
1191 &mmss_ahb_clk_src.clkr.hw
1192 },
1193 .num_parents = 1,
1194 .ops = &clk_branch2_ops,
1195 },
1196 },
1197};
1198
1199static struct clk_branch camss_csi2_clk = {
1200 .halt_reg = 0x3184,
1201 .clkr = {
1202 .enable_reg = 0x3184,
1203 .enable_mask = BIT(0),
1204 .hw.init = &(struct clk_init_data){
1205 .name = "camss_csi2_clk",
1206 .parent_hws = (const struct clk_hw*[]){
1207 &csi2_clk_src.clkr.hw
1208 },
1209 .num_parents = 1,
1210 .flags = CLK_SET_RATE_PARENT,
1211 .ops = &clk_branch2_ops,
1212 },
1213 },
1214};
1215
1216static struct clk_branch camss_csi2phy_clk = {
1217 .halt_reg = 0x3194,
1218 .clkr = {
1219 .enable_reg = 0x3194,
1220 .enable_mask = BIT(0),
1221 .hw.init = &(struct clk_init_data){
1222 .name = "camss_csi2phy_clk",
1223 .parent_hws = (const struct clk_hw*[]){
1224 &csi2_clk_src.clkr.hw
1225 },
1226 .num_parents = 1,
1227 .flags = CLK_SET_RATE_PARENT,
1228 .ops = &clk_branch2_ops,
1229 },
1230 },
1231};
1232
1233static struct clk_branch camss_csi2pix_clk = {
1234 .halt_reg = 0x31b4,
1235 .clkr = {
1236 .enable_reg = 0x31b4,
1237 .enable_mask = BIT(0),
1238 .hw.init = &(struct clk_init_data){
1239 .name = "camss_csi2pix_clk",
1240 .parent_hws = (const struct clk_hw*[]){
1241 &csi2_clk_src.clkr.hw
1242 },
1243 .num_parents = 1,
1244 .flags = CLK_SET_RATE_PARENT,
1245 .ops = &clk_branch2_ops,
1246 },
1247 },
1248};
1249
1250static struct clk_branch camss_csi2rdi_clk = {
1251 .halt_reg = 0x31a4,
1252 .clkr = {
1253 .enable_reg = 0x31a4,
1254 .enable_mask = BIT(0),
1255 .hw.init = &(struct clk_init_data){
1256 .name = "camss_csi2rdi_clk",
1257 .parent_hws = (const struct clk_hw*[]){
1258 &csi2_clk_src.clkr.hw
1259 },
1260 .num_parents = 1,
1261 .flags = CLK_SET_RATE_PARENT,
1262 .ops = &clk_branch2_ops,
1263 },
1264 },
1265};
1266
1267static struct clk_branch camss_csi3_ahb_clk = {
1268 .halt_reg = 0x31e8,
1269 .clkr = {
1270 .enable_reg = 0x31e8,
1271 .enable_mask = BIT(0),
1272 .hw.init = &(struct clk_init_data){
1273 .name = "camss_csi3_ahb_clk",
1274 .parent_hws = (const struct clk_hw*[]){
1275 &mmss_ahb_clk_src.clkr.hw
1276 },
1277 .num_parents = 1,
1278 .ops = &clk_branch2_ops,
1279 },
1280 },
1281};
1282
1283static struct clk_branch camss_csi3_clk = {
1284 .halt_reg = 0x31e4,
1285 .clkr = {
1286 .enable_reg = 0x31e4,
1287 .enable_mask = BIT(0),
1288 .hw.init = &(struct clk_init_data){
1289 .name = "camss_csi3_clk",
1290 .parent_hws = (const struct clk_hw*[]){
1291 &csi3_clk_src.clkr.hw
1292 },
1293 .num_parents = 1,
1294 .flags = CLK_SET_RATE_PARENT,
1295 .ops = &clk_branch2_ops,
1296 },
1297 },
1298};
1299
1300static struct clk_branch camss_csi3phy_clk = {
1301 .halt_reg = 0x31f4,
1302 .clkr = {
1303 .enable_reg = 0x31f4,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(struct clk_init_data){
1306 .name = "camss_csi3phy_clk",
1307 .parent_hws = (const struct clk_hw*[]){
1308 &csi3_clk_src.clkr.hw
1309 },
1310 .num_parents = 1,
1311 .flags = CLK_SET_RATE_PARENT,
1312 .ops = &clk_branch2_ops,
1313 },
1314 },
1315};
1316
1317static struct clk_branch camss_csi3pix_clk = {
1318 .halt_reg = 0x3214,
1319 .clkr = {
1320 .enable_reg = 0x3214,
1321 .enable_mask = BIT(0),
1322 .hw.init = &(struct clk_init_data){
1323 .name = "camss_csi3pix_clk",
1324 .parent_hws = (const struct clk_hw*[]){
1325 &csi3_clk_src.clkr.hw
1326 },
1327 .num_parents = 1,
1328 .flags = CLK_SET_RATE_PARENT,
1329 .ops = &clk_branch2_ops,
1330 },
1331 },
1332};
1333
1334static struct clk_branch camss_csi3rdi_clk = {
1335 .halt_reg = 0x3204,
1336 .clkr = {
1337 .enable_reg = 0x3204,
1338 .enable_mask = BIT(0),
1339 .hw.init = &(struct clk_init_data){
1340 .name = "camss_csi3rdi_clk",
1341 .parent_hws = (const struct clk_hw*[]){
1342 &csi3_clk_src.clkr.hw
1343 },
1344 .num_parents = 1,
1345 .flags = CLK_SET_RATE_PARENT,
1346 .ops = &clk_branch2_ops,
1347 },
1348 },
1349};
1350
1351static struct clk_branch camss_csi_vfe0_clk = {
1352 .halt_reg = 0x3704,
1353 .clkr = {
1354 .enable_reg = 0x3704,
1355 .enable_mask = BIT(0),
1356 .hw.init = &(struct clk_init_data){
1357 .name = "camss_csi_vfe0_clk",
1358 .parent_hws = (const struct clk_hw*[]){
1359 &vfe0_clk_src.clkr.hw
1360 },
1361 .num_parents = 1,
1362 .flags = CLK_SET_RATE_PARENT,
1363 .ops = &clk_branch2_ops,
1364 },
1365 },
1366};
1367
1368static struct clk_branch camss_csi_vfe1_clk = {
1369 .halt_reg = 0x3714,
1370 .clkr = {
1371 .enable_reg = 0x3714,
1372 .enable_mask = BIT(0),
1373 .hw.init = &(struct clk_init_data){
1374 .name = "camss_csi_vfe1_clk",
1375 .parent_hws = (const struct clk_hw*[]){
1376 &vfe1_clk_src.clkr.hw
1377 },
1378 .num_parents = 1,
1379 .flags = CLK_SET_RATE_PARENT,
1380 .ops = &clk_branch2_ops,
1381 },
1382 },
1383};
1384
1385static struct clk_branch camss_gp0_clk = {
1386 .halt_reg = 0x3444,
1387 .clkr = {
1388 .enable_reg = 0x3444,
1389 .enable_mask = BIT(0),
1390 .hw.init = &(struct clk_init_data){
1391 .name = "camss_gp0_clk",
1392 .parent_hws = (const struct clk_hw*[]){
1393 &camss_gp0_clk_src.clkr.hw
1394 },
1395 .num_parents = 1,
1396 .flags = CLK_SET_RATE_PARENT,
1397 .ops = &clk_branch2_ops,
1398 },
1399 },
1400};
1401
1402static struct clk_branch camss_gp1_clk = {
1403 .halt_reg = 0x3474,
1404 .clkr = {
1405 .enable_reg = 0x3474,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "camss_gp1_clk",
1409 .parent_hws = (const struct clk_hw*[]){
1410 &camss_gp1_clk_src.clkr.hw
1411 },
1412 .num_parents = 1,
1413 .flags = CLK_SET_RATE_PARENT,
1414 .ops = &clk_branch2_ops,
1415 },
1416 },
1417};
1418
1419static struct clk_branch camss_ispif_ahb_clk = {
1420 .halt_reg = 0x3224,
1421 .clkr = {
1422 .enable_reg = 0x3224,
1423 .enable_mask = BIT(0),
1424 .hw.init = &(struct clk_init_data){
1425 .name = "camss_ispif_ahb_clk",
1426 .parent_hws = (const struct clk_hw*[]){
1427 &mmss_ahb_clk_src.clkr.hw
1428 },
1429 .num_parents = 1,
1430 .ops = &clk_branch2_ops,
1431 },
1432 },
1433};
1434
1435static struct clk_branch camss_jpeg_jpeg0_clk = {
1436 .halt_reg = 0x35a8,
1437 .clkr = {
1438 .enable_reg = 0x35a8,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "camss_jpeg_jpeg0_clk",
1442 .parent_hws = (const struct clk_hw*[]){
1443 &jpeg0_clk_src.clkr.hw
1444 },
1445 .num_parents = 1,
1446 .flags = CLK_SET_RATE_PARENT,
1447 .ops = &clk_branch2_ops,
1448 },
1449 },
1450};
1451
1452static struct clk_branch camss_jpeg_jpeg1_clk = {
1453 .halt_reg = 0x35ac,
1454 .clkr = {
1455 .enable_reg = 0x35ac,
1456 .enable_mask = BIT(0),
1457 .hw.init = &(struct clk_init_data){
1458 .name = "camss_jpeg_jpeg1_clk",
1459 .parent_hws = (const struct clk_hw*[]){
1460 &jpeg1_clk_src.clkr.hw
1461 },
1462 .num_parents = 1,
1463 .flags = CLK_SET_RATE_PARENT,
1464 .ops = &clk_branch2_ops,
1465 },
1466 },
1467};
1468
1469static struct clk_branch camss_jpeg_jpeg2_clk = {
1470 .halt_reg = 0x35b0,
1471 .clkr = {
1472 .enable_reg = 0x35b0,
1473 .enable_mask = BIT(0),
1474 .hw.init = &(struct clk_init_data){
1475 .name = "camss_jpeg_jpeg2_clk",
1476 .parent_hws = (const struct clk_hw*[]){
1477 &jpeg2_clk_src.clkr.hw
1478 },
1479 .num_parents = 1,
1480 .flags = CLK_SET_RATE_PARENT,
1481 .ops = &clk_branch2_ops,
1482 },
1483 },
1484};
1485
1486static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1487 .halt_reg = 0x35b4,
1488 .clkr = {
1489 .enable_reg = 0x35b4,
1490 .enable_mask = BIT(0),
1491 .hw.init = &(struct clk_init_data){
1492 .name = "camss_jpeg_jpeg_ahb_clk",
1493 .parent_hws = (const struct clk_hw*[]){
1494 &mmss_ahb_clk_src.clkr.hw
1495 },
1496 .num_parents = 1,
1497 .ops = &clk_branch2_ops,
1498 },
1499 },
1500};
1501
1502static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1503 .halt_reg = 0x35b8,
1504 .clkr = {
1505 .enable_reg = 0x35b8,
1506 .enable_mask = BIT(0),
1507 .hw.init = &(struct clk_init_data){
1508 .name = "camss_jpeg_jpeg_axi_clk",
1509 .parent_hws = (const struct clk_hw*[]){
1510 &mmss_axi_clk_src.clkr.hw
1511 },
1512 .num_parents = 1,
1513 .ops = &clk_branch2_ops,
1514 },
1515 },
1516};
1517
1518static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1519 .halt_reg = 0x35bc,
1520 .clkr = {
1521 .enable_reg = 0x35bc,
1522 .enable_mask = BIT(0),
1523 .hw.init = &(struct clk_init_data){
1524 .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1525 .parent_hws = (const struct clk_hw*[]){
1526 &ocmemnoc_clk_src.clkr.hw
1527 },
1528 .num_parents = 1,
1529 .flags = CLK_SET_RATE_PARENT,
1530 .ops = &clk_branch2_ops,
1531 },
1532 },
1533};
1534
1535static struct clk_branch camss_mclk0_clk = {
1536 .halt_reg = 0x3384,
1537 .clkr = {
1538 .enable_reg = 0x3384,
1539 .enable_mask = BIT(0),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "camss_mclk0_clk",
1542 .parent_hws = (const struct clk_hw*[]){
1543 &mclk0_clk_src.clkr.hw
1544 },
1545 .num_parents = 1,
1546 .flags = CLK_SET_RATE_PARENT,
1547 .ops = &clk_branch2_ops,
1548 },
1549 },
1550};
1551
1552static struct clk_branch camss_mclk1_clk = {
1553 .halt_reg = 0x33b4,
1554 .clkr = {
1555 .enable_reg = 0x33b4,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "camss_mclk1_clk",
1559 .parent_hws = (const struct clk_hw*[]){
1560 &mclk1_clk_src.clkr.hw
1561 },
1562 .num_parents = 1,
1563 .flags = CLK_SET_RATE_PARENT,
1564 .ops = &clk_branch2_ops,
1565 },
1566 },
1567};
1568
1569static struct clk_branch camss_mclk2_clk = {
1570 .halt_reg = 0x33e4,
1571 .clkr = {
1572 .enable_reg = 0x33e4,
1573 .enable_mask = BIT(0),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "camss_mclk2_clk",
1576 .parent_hws = (const struct clk_hw*[]){
1577 &mclk2_clk_src.clkr.hw
1578 },
1579 .num_parents = 1,
1580 .flags = CLK_SET_RATE_PARENT,
1581 .ops = &clk_branch2_ops,
1582 },
1583 },
1584};
1585
1586static struct clk_branch camss_mclk3_clk = {
1587 .halt_reg = 0x3414,
1588 .clkr = {
1589 .enable_reg = 0x3414,
1590 .enable_mask = BIT(0),
1591 .hw.init = &(struct clk_init_data){
1592 .name = "camss_mclk3_clk",
1593 .parent_hws = (const struct clk_hw*[]){
1594 &mclk3_clk_src.clkr.hw
1595 },
1596 .num_parents = 1,
1597 .flags = CLK_SET_RATE_PARENT,
1598 .ops = &clk_branch2_ops,
1599 },
1600 },
1601};
1602
1603static struct clk_branch camss_micro_ahb_clk = {
1604 .halt_reg = 0x3494,
1605 .clkr = {
1606 .enable_reg = 0x3494,
1607 .enable_mask = BIT(0),
1608 .hw.init = &(struct clk_init_data){
1609 .name = "camss_micro_ahb_clk",
1610 .parent_hws = (const struct clk_hw*[]){
1611 &mmss_ahb_clk_src.clkr.hw
1612 },
1613 .num_parents = 1,
1614 .ops = &clk_branch2_ops,
1615 },
1616 },
1617};
1618
1619static struct clk_branch camss_phy0_csi0phytimer_clk = {
1620 .halt_reg = 0x3024,
1621 .clkr = {
1622 .enable_reg = 0x3024,
1623 .enable_mask = BIT(0),
1624 .hw.init = &(struct clk_init_data){
1625 .name = "camss_phy0_csi0phytimer_clk",
1626 .parent_hws = (const struct clk_hw*[]){
1627 &csi0phytimer_clk_src.clkr.hw
1628 },
1629 .num_parents = 1,
1630 .flags = CLK_SET_RATE_PARENT,
1631 .ops = &clk_branch2_ops,
1632 },
1633 },
1634};
1635
1636static struct clk_branch camss_phy1_csi1phytimer_clk = {
1637 .halt_reg = 0x3054,
1638 .clkr = {
1639 .enable_reg = 0x3054,
1640 .enable_mask = BIT(0),
1641 .hw.init = &(struct clk_init_data){
1642 .name = "camss_phy1_csi1phytimer_clk",
1643 .parent_hws = (const struct clk_hw*[]){
1644 &csi1phytimer_clk_src.clkr.hw
1645 },
1646 .num_parents = 1,
1647 .flags = CLK_SET_RATE_PARENT,
1648 .ops = &clk_branch2_ops,
1649 },
1650 },
1651};
1652
1653static struct clk_branch camss_phy2_csi2phytimer_clk = {
1654 .halt_reg = 0x3084,
1655 .clkr = {
1656 .enable_reg = 0x3084,
1657 .enable_mask = BIT(0),
1658 .hw.init = &(struct clk_init_data){
1659 .name = "camss_phy2_csi2phytimer_clk",
1660 .parent_hws = (const struct clk_hw*[]){
1661 &csi2phytimer_clk_src.clkr.hw
1662 },
1663 .num_parents = 1,
1664 .flags = CLK_SET_RATE_PARENT,
1665 .ops = &clk_branch2_ops,
1666 },
1667 },
1668};
1669
1670static struct clk_branch camss_top_ahb_clk = {
1671 .halt_reg = 0x3484,
1672 .clkr = {
1673 .enable_reg = 0x3484,
1674 .enable_mask = BIT(0),
1675 .hw.init = &(struct clk_init_data){
1676 .name = "camss_top_ahb_clk",
1677 .parent_hws = (const struct clk_hw*[]){
1678 &mmss_ahb_clk_src.clkr.hw
1679 },
1680 .num_parents = 1,
1681 .ops = &clk_branch2_ops,
1682 },
1683 },
1684};
1685
1686static struct clk_branch camss_vfe_cpp_ahb_clk = {
1687 .halt_reg = 0x36b4,
1688 .clkr = {
1689 .enable_reg = 0x36b4,
1690 .enable_mask = BIT(0),
1691 .hw.init = &(struct clk_init_data){
1692 .name = "camss_vfe_cpp_ahb_clk",
1693 .parent_hws = (const struct clk_hw*[]){
1694 &mmss_ahb_clk_src.clkr.hw
1695 },
1696 .num_parents = 1,
1697 .ops = &clk_branch2_ops,
1698 },
1699 },
1700};
1701
1702static struct clk_branch camss_vfe_cpp_clk = {
1703 .halt_reg = 0x36b0,
1704 .clkr = {
1705 .enable_reg = 0x36b0,
1706 .enable_mask = BIT(0),
1707 .hw.init = &(struct clk_init_data){
1708 .name = "camss_vfe_cpp_clk",
1709 .parent_hws = (const struct clk_hw*[]){
1710 &cpp_clk_src.clkr.hw
1711 },
1712 .num_parents = 1,
1713 .flags = CLK_SET_RATE_PARENT,
1714 .ops = &clk_branch2_ops,
1715 },
1716 },
1717};
1718
1719static struct clk_branch camss_vfe_vfe0_clk = {
1720 .halt_reg = 0x36a8,
1721 .clkr = {
1722 .enable_reg = 0x36a8,
1723 .enable_mask = BIT(0),
1724 .hw.init = &(struct clk_init_data){
1725 .name = "camss_vfe_vfe0_clk",
1726 .parent_hws = (const struct clk_hw*[]){
1727 &vfe0_clk_src.clkr.hw
1728 },
1729 .num_parents = 1,
1730 .flags = CLK_SET_RATE_PARENT,
1731 .ops = &clk_branch2_ops,
1732 },
1733 },
1734};
1735
1736static struct clk_branch camss_vfe_vfe1_clk = {
1737 .halt_reg = 0x36ac,
1738 .clkr = {
1739 .enable_reg = 0x36ac,
1740 .enable_mask = BIT(0),
1741 .hw.init = &(struct clk_init_data){
1742 .name = "camss_vfe_vfe1_clk",
1743 .parent_hws = (const struct clk_hw*[]){
1744 &vfe1_clk_src.clkr.hw
1745 },
1746 .num_parents = 1,
1747 .flags = CLK_SET_RATE_PARENT,
1748 .ops = &clk_branch2_ops,
1749 },
1750 },
1751};
1752
1753static struct clk_branch camss_vfe_vfe_ahb_clk = {
1754 .halt_reg = 0x36b8,
1755 .clkr = {
1756 .enable_reg = 0x36b8,
1757 .enable_mask = BIT(0),
1758 .hw.init = &(struct clk_init_data){
1759 .name = "camss_vfe_vfe_ahb_clk",
1760 .parent_hws = (const struct clk_hw*[]){
1761 &mmss_ahb_clk_src.clkr.hw
1762 },
1763 .num_parents = 1,
1764 .ops = &clk_branch2_ops,
1765 },
1766 },
1767};
1768
1769static struct clk_branch camss_vfe_vfe_axi_clk = {
1770 .halt_reg = 0x36bc,
1771 .clkr = {
1772 .enable_reg = 0x36bc,
1773 .enable_mask = BIT(0),
1774 .hw.init = &(struct clk_init_data){
1775 .name = "camss_vfe_vfe_axi_clk",
1776 .parent_hws = (const struct clk_hw*[]){
1777 &mmss_axi_clk_src.clkr.hw
1778 },
1779 .num_parents = 1,
1780 .ops = &clk_branch2_ops,
1781 },
1782 },
1783};
1784
1785static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1786 .halt_reg = 0x36c0,
1787 .clkr = {
1788 .enable_reg = 0x36c0,
1789 .enable_mask = BIT(0),
1790 .hw.init = &(struct clk_init_data){
1791 .name = "camss_vfe_vfe_ocmemnoc_clk",
1792 .parent_hws = (const struct clk_hw*[]){
1793 &ocmemnoc_clk_src.clkr.hw
1794 },
1795 .num_parents = 1,
1796 .flags = CLK_SET_RATE_PARENT,
1797 .ops = &clk_branch2_ops,
1798 },
1799 },
1800};
1801
1802static struct clk_branch mdss_ahb_clk = {
1803 .halt_reg = 0x2308,
1804 .clkr = {
1805 .enable_reg = 0x2308,
1806 .enable_mask = BIT(0),
1807 .hw.init = &(struct clk_init_data){
1808 .name = "mdss_ahb_clk",
1809 .parent_hws = (const struct clk_hw*[]){
1810 &mmss_ahb_clk_src.clkr.hw
1811 },
1812 .num_parents = 1,
1813 .ops = &clk_branch2_ops,
1814 },
1815 },
1816};
1817
1818static struct clk_branch mdss_axi_clk = {
1819 .halt_reg = 0x2310,
1820 .clkr = {
1821 .enable_reg = 0x2310,
1822 .enable_mask = BIT(0),
1823 .hw.init = &(struct clk_init_data){
1824 .name = "mdss_axi_clk",
1825 .parent_hws = (const struct clk_hw*[]){
1826 &mmss_axi_clk_src.clkr.hw
1827 },
1828 .num_parents = 1,
1829 .flags = CLK_SET_RATE_PARENT,
1830 .ops = &clk_branch2_ops,
1831 },
1832 },
1833};
1834
1835static struct clk_branch mdss_byte0_clk = {
1836 .halt_reg = 0x233c,
1837 .clkr = {
1838 .enable_reg = 0x233c,
1839 .enable_mask = BIT(0),
1840 .hw.init = &(struct clk_init_data){
1841 .name = "mdss_byte0_clk",
1842 .parent_hws = (const struct clk_hw*[]){
1843 &byte0_clk_src.clkr.hw
1844 },
1845 .num_parents = 1,
1846 .flags = CLK_SET_RATE_PARENT,
1847 .ops = &clk_branch2_ops,
1848 },
1849 },
1850};
1851
1852static struct clk_branch mdss_byte1_clk = {
1853 .halt_reg = 0x2340,
1854 .clkr = {
1855 .enable_reg = 0x2340,
1856 .enable_mask = BIT(0),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "mdss_byte1_clk",
1859 .parent_hws = (const struct clk_hw*[]){
1860 &byte1_clk_src.clkr.hw
1861 },
1862 .num_parents = 1,
1863 .flags = CLK_SET_RATE_PARENT,
1864 .ops = &clk_branch2_ops,
1865 },
1866 },
1867};
1868
1869static struct clk_branch mdss_edpaux_clk = {
1870 .halt_reg = 0x2334,
1871 .clkr = {
1872 .enable_reg = 0x2334,
1873 .enable_mask = BIT(0),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "mdss_edpaux_clk",
1876 .parent_hws = (const struct clk_hw*[]){
1877 &edpaux_clk_src.clkr.hw
1878 },
1879 .num_parents = 1,
1880 .flags = CLK_SET_RATE_PARENT,
1881 .ops = &clk_branch2_ops,
1882 },
1883 },
1884};
1885
1886static struct clk_branch mdss_edplink_clk = {
1887 .halt_reg = 0x2330,
1888 .clkr = {
1889 .enable_reg = 0x2330,
1890 .enable_mask = BIT(0),
1891 .hw.init = &(struct clk_init_data){
1892 .name = "mdss_edplink_clk",
1893 .parent_hws = (const struct clk_hw*[]){
1894 &edplink_clk_src.clkr.hw
1895 },
1896 .num_parents = 1,
1897 .flags = CLK_SET_RATE_PARENT,
1898 .ops = &clk_branch2_ops,
1899 },
1900 },
1901};
1902
1903static struct clk_branch mdss_edppixel_clk = {
1904 .halt_reg = 0x232c,
1905 .clkr = {
1906 .enable_reg = 0x232c,
1907 .enable_mask = BIT(0),
1908 .hw.init = &(struct clk_init_data){
1909 .name = "mdss_edppixel_clk",
1910 .parent_hws = (const struct clk_hw*[]){
1911 &edppixel_clk_src.clkr.hw
1912 },
1913 .num_parents = 1,
1914 .flags = CLK_SET_RATE_PARENT,
1915 .ops = &clk_branch2_ops,
1916 },
1917 },
1918};
1919
1920static struct clk_branch mdss_esc0_clk = {
1921 .halt_reg = 0x2344,
1922 .clkr = {
1923 .enable_reg = 0x2344,
1924 .enable_mask = BIT(0),
1925 .hw.init = &(struct clk_init_data){
1926 .name = "mdss_esc0_clk",
1927 .parent_hws = (const struct clk_hw*[]){
1928 &esc0_clk_src.clkr.hw
1929 },
1930 .num_parents = 1,
1931 .flags = CLK_SET_RATE_PARENT,
1932 .ops = &clk_branch2_ops,
1933 },
1934 },
1935};
1936
1937static struct clk_branch mdss_esc1_clk = {
1938 .halt_reg = 0x2348,
1939 .clkr = {
1940 .enable_reg = 0x2348,
1941 .enable_mask = BIT(0),
1942 .hw.init = &(struct clk_init_data){
1943 .name = "mdss_esc1_clk",
1944 .parent_hws = (const struct clk_hw*[]){
1945 &esc1_clk_src.clkr.hw
1946 },
1947 .num_parents = 1,
1948 .flags = CLK_SET_RATE_PARENT,
1949 .ops = &clk_branch2_ops,
1950 },
1951 },
1952};
1953
1954static struct clk_branch mdss_extpclk_clk = {
1955 .halt_reg = 0x2324,
1956 .clkr = {
1957 .enable_reg = 0x2324,
1958 .enable_mask = BIT(0),
1959 .hw.init = &(struct clk_init_data){
1960 .name = "mdss_extpclk_clk",
1961 .parent_hws = (const struct clk_hw*[]){
1962 &extpclk_clk_src.clkr.hw
1963 },
1964 .num_parents = 1,
1965 .flags = CLK_SET_RATE_PARENT,
1966 .ops = &clk_branch2_ops,
1967 },
1968 },
1969};
1970
1971static struct clk_branch mdss_hdmi_ahb_clk = {
1972 .halt_reg = 0x230c,
1973 .clkr = {
1974 .enable_reg = 0x230c,
1975 .enable_mask = BIT(0),
1976 .hw.init = &(struct clk_init_data){
1977 .name = "mdss_hdmi_ahb_clk",
1978 .parent_hws = (const struct clk_hw*[]){
1979 &mmss_ahb_clk_src.clkr.hw
1980 },
1981 .num_parents = 1,
1982 .ops = &clk_branch2_ops,
1983 },
1984 },
1985};
1986
1987static struct clk_branch mdss_hdmi_clk = {
1988 .halt_reg = 0x2338,
1989 .clkr = {
1990 .enable_reg = 0x2338,
1991 .enable_mask = BIT(0),
1992 .hw.init = &(struct clk_init_data){
1993 .name = "mdss_hdmi_clk",
1994 .parent_hws = (const struct clk_hw*[]){
1995 &hdmi_clk_src.clkr.hw
1996 },
1997 .num_parents = 1,
1998 .flags = CLK_SET_RATE_PARENT,
1999 .ops = &clk_branch2_ops,
2000 },
2001 },
2002};
2003
2004static struct clk_branch mdss_mdp_clk = {
2005 .halt_reg = 0x231c,
2006 .clkr = {
2007 .enable_reg = 0x231c,
2008 .enable_mask = BIT(0),
2009 .hw.init = &(struct clk_init_data){
2010 .name = "mdss_mdp_clk",
2011 .parent_hws = (const struct clk_hw*[]){
2012 &mdp_clk_src.clkr.hw
2013 },
2014 .num_parents = 1,
2015 .flags = CLK_SET_RATE_PARENT,
2016 .ops = &clk_branch2_ops,
2017 },
2018 },
2019};
2020
2021static struct clk_branch mdss_mdp_lut_clk = {
2022 .halt_reg = 0x2320,
2023 .clkr = {
2024 .enable_reg = 0x2320,
2025 .enable_mask = BIT(0),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "mdss_mdp_lut_clk",
2028 .parent_hws = (const struct clk_hw*[]){
2029 &mdp_clk_src.clkr.hw
2030 },
2031 .num_parents = 1,
2032 .flags = CLK_SET_RATE_PARENT,
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036};
2037
2038static struct clk_branch mdss_pclk0_clk = {
2039 .halt_reg = 0x2314,
2040 .clkr = {
2041 .enable_reg = 0x2314,
2042 .enable_mask = BIT(0),
2043 .hw.init = &(struct clk_init_data){
2044 .name = "mdss_pclk0_clk",
2045 .parent_hws = (const struct clk_hw*[]){
2046 &pclk0_clk_src.clkr.hw
2047 },
2048 .num_parents = 1,
2049 .flags = CLK_SET_RATE_PARENT,
2050 .ops = &clk_branch2_ops,
2051 },
2052 },
2053};
2054
2055static struct clk_branch mdss_pclk1_clk = {
2056 .halt_reg = 0x2318,
2057 .clkr = {
2058 .enable_reg = 0x2318,
2059 .enable_mask = BIT(0),
2060 .hw.init = &(struct clk_init_data){
2061 .name = "mdss_pclk1_clk",
2062 .parent_hws = (const struct clk_hw*[]){
2063 &pclk1_clk_src.clkr.hw
2064 },
2065 .num_parents = 1,
2066 .flags = CLK_SET_RATE_PARENT,
2067 .ops = &clk_branch2_ops,
2068 },
2069 },
2070};
2071
2072static struct clk_branch mdss_vsync_clk = {
2073 .halt_reg = 0x2328,
2074 .clkr = {
2075 .enable_reg = 0x2328,
2076 .enable_mask = BIT(0),
2077 .hw.init = &(struct clk_init_data){
2078 .name = "mdss_vsync_clk",
2079 .parent_hws = (const struct clk_hw*[]){
2080 &vsync_clk_src.clkr.hw
2081 },
2082 .num_parents = 1,
2083 .flags = CLK_SET_RATE_PARENT,
2084 .ops = &clk_branch2_ops,
2085 },
2086 },
2087};
2088
2089static struct clk_branch mmss_misc_ahb_clk = {
2090 .halt_reg = 0x502c,
2091 .clkr = {
2092 .enable_reg = 0x502c,
2093 .enable_mask = BIT(0),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "mmss_misc_ahb_clk",
2096 .parent_hws = (const struct clk_hw*[]){
2097 &mmss_ahb_clk_src.clkr.hw
2098 },
2099 .num_parents = 1,
2100 .ops = &clk_branch2_ops,
2101 },
2102 },
2103};
2104
2105static struct clk_branch mmss_mmssnoc_ahb_clk = {
2106 .halt_reg = 0x5024,
2107 .clkr = {
2108 .enable_reg = 0x5024,
2109 .enable_mask = BIT(0),
2110 .hw.init = &(struct clk_init_data){
2111 .name = "mmss_mmssnoc_ahb_clk",
2112 .parent_hws = (const struct clk_hw*[]){
2113 &mmss_ahb_clk_src.clkr.hw
2114 },
2115 .num_parents = 1,
2116 .ops = &clk_branch2_ops,
2117 .flags = CLK_IGNORE_UNUSED,
2118 },
2119 },
2120};
2121
2122static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2123 .halt_reg = 0x5028,
2124 .clkr = {
2125 .enable_reg = 0x5028,
2126 .enable_mask = BIT(0),
2127 .hw.init = &(struct clk_init_data){
2128 .name = "mmss_mmssnoc_bto_ahb_clk",
2129 .parent_hws = (const struct clk_hw*[]){
2130 &mmss_ahb_clk_src.clkr.hw
2131 },
2132 .num_parents = 1,
2133 .ops = &clk_branch2_ops,
2134 .flags = CLK_IGNORE_UNUSED,
2135 },
2136 },
2137};
2138
2139static struct clk_branch mmss_mmssnoc_axi_clk = {
2140 .halt_reg = 0x506c,
2141 .clkr = {
2142 .enable_reg = 0x506c,
2143 .enable_mask = BIT(0),
2144 .hw.init = &(struct clk_init_data){
2145 .name = "mmss_mmssnoc_axi_clk",
2146 .parent_hws = (const struct clk_hw*[]){
2147 &mmss_axi_clk_src.clkr.hw
2148 },
2149 .num_parents = 1,
2150 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2151 .ops = &clk_branch2_ops,
2152 },
2153 },
2154};
2155
2156static struct clk_branch mmss_s0_axi_clk = {
2157 .halt_reg = 0x5064,
2158 .clkr = {
2159 .enable_reg = 0x5064,
2160 .enable_mask = BIT(0),
2161 .hw.init = &(struct clk_init_data){
2162 .name = "mmss_s0_axi_clk",
2163 .parent_hws = (const struct clk_hw*[]){
2164 &mmss_axi_clk_src.clkr.hw
2165 },
2166 .num_parents = 1,
2167 .ops = &clk_branch2_ops,
2168 .flags = CLK_IGNORE_UNUSED,
2169 },
2170 },
2171};
2172
2173static struct clk_branch ocmemcx_ocmemnoc_clk = {
2174 .halt_reg = 0x4058,
2175 .clkr = {
2176 .enable_reg = 0x4058,
2177 .enable_mask = BIT(0),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "ocmemcx_ocmemnoc_clk",
2180 .parent_hws = (const struct clk_hw*[]){
2181 &ocmemnoc_clk_src.clkr.hw
2182 },
2183 .num_parents = 1,
2184 .flags = CLK_SET_RATE_PARENT,
2185 .ops = &clk_branch2_ops,
2186 },
2187 },
2188};
2189
2190static struct clk_branch ocmemnoc_clk = {
2191 .halt_reg = 0x50b4,
2192 .clkr = {
2193 .enable_reg = 0x50b4,
2194 .enable_mask = BIT(0),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "ocmemnoc_clk",
2197 .parent_hws = (const struct clk_hw*[]){
2198 &ocmemnoc_clk_src.clkr.hw
2199 },
2200 .num_parents = 1,
2201 .flags = CLK_SET_RATE_PARENT,
2202 .ops = &clk_branch2_ops,
2203 },
2204 },
2205};
2206
2207static struct clk_branch oxili_gfx3d_clk = {
2208 .halt_reg = 0x4028,
2209 .clkr = {
2210 .enable_reg = 0x4028,
2211 .enable_mask = BIT(0),
2212 .hw.init = &(struct clk_init_data){
2213 .name = "oxili_gfx3d_clk",
2214 .parent_data = (const struct clk_parent_data[]){
2215 { .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
2216 },
2217 .num_parents = 1,
2218 .flags = CLK_SET_RATE_PARENT,
2219 .ops = &clk_branch2_ops,
2220 },
2221 },
2222};
2223
2224static struct clk_branch oxilicx_ahb_clk = {
2225 .halt_reg = 0x403c,
2226 .clkr = {
2227 .enable_reg = 0x403c,
2228 .enable_mask = BIT(0),
2229 .hw.init = &(struct clk_init_data){
2230 .name = "oxilicx_ahb_clk",
2231 .parent_hws = (const struct clk_hw*[]){
2232 &mmss_ahb_clk_src.clkr.hw
2233 },
2234 .num_parents = 1,
2235 .ops = &clk_branch2_ops,
2236 },
2237 },
2238};
2239
2240static struct clk_branch oxilicx_axi_clk = {
2241 .halt_reg = 0x4038,
2242 .clkr = {
2243 .enable_reg = 0x4038,
2244 .enable_mask = BIT(0),
2245 .hw.init = &(struct clk_init_data){
2246 .name = "oxilicx_axi_clk",
2247 .parent_hws = (const struct clk_hw*[]){
2248 &mmss_axi_clk_src.clkr.hw
2249 },
2250 .num_parents = 1,
2251 .ops = &clk_branch2_ops,
2252 },
2253 },
2254};
2255
2256static struct clk_branch venus0_ahb_clk = {
2257 .halt_reg = 0x1030,
2258 .clkr = {
2259 .enable_reg = 0x1030,
2260 .enable_mask = BIT(0),
2261 .hw.init = &(struct clk_init_data){
2262 .name = "venus0_ahb_clk",
2263 .parent_hws = (const struct clk_hw*[]){
2264 &mmss_ahb_clk_src.clkr.hw
2265 },
2266 .num_parents = 1,
2267 .ops = &clk_branch2_ops,
2268 },
2269 },
2270};
2271
2272static struct clk_branch venus0_axi_clk = {
2273 .halt_reg = 0x1034,
2274 .clkr = {
2275 .enable_reg = 0x1034,
2276 .enable_mask = BIT(0),
2277 .hw.init = &(struct clk_init_data){
2278 .name = "venus0_axi_clk",
2279 .parent_hws = (const struct clk_hw*[]){
2280 &mmss_axi_clk_src.clkr.hw
2281 },
2282 .num_parents = 1,
2283 .ops = &clk_branch2_ops,
2284 },
2285 },
2286};
2287
2288static struct clk_branch venus0_ocmemnoc_clk = {
2289 .halt_reg = 0x1038,
2290 .clkr = {
2291 .enable_reg = 0x1038,
2292 .enable_mask = BIT(0),
2293 .hw.init = &(struct clk_init_data){
2294 .name = "venus0_ocmemnoc_clk",
2295 .parent_hws = (const struct clk_hw*[]){
2296 &ocmemnoc_clk_src.clkr.hw
2297 },
2298 .num_parents = 1,
2299 .flags = CLK_SET_RATE_PARENT,
2300 .ops = &clk_branch2_ops,
2301 },
2302 },
2303};
2304
2305static struct clk_branch venus0_vcodec0_clk = {
2306 .halt_reg = 0x1028,
2307 .clkr = {
2308 .enable_reg = 0x1028,
2309 .enable_mask = BIT(0),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "venus0_vcodec0_clk",
2312 .parent_hws = (const struct clk_hw*[]){
2313 &vcodec0_clk_src.clkr.hw
2314 },
2315 .num_parents = 1,
2316 .flags = CLK_SET_RATE_PARENT,
2317 .ops = &clk_branch2_ops,
2318 },
2319 },
2320};
2321
2322static const struct pll_config mmpll1_config = {
2323 .l = 60,
2324 .m = 25,
2325 .n = 32,
2326 .vco_val = 0x0,
2327 .vco_mask = 0x3 << 20,
2328 .pre_div_val = 0x0,
2329 .pre_div_mask = 0x7 << 12,
2330 .post_div_val = 0x0,
2331 .post_div_mask = 0x3 << 8,
2332 .mn_ena_mask = BIT(24),
2333 .main_output_mask = BIT(0),
2334};
2335
2336static struct pll_config mmpll3_config = {
2337 .l = 48,
2338 .m = 7,
2339 .n = 16,
2340 .vco_val = 0x0,
2341 .vco_mask = 0x3 << 20,
2342 .pre_div_val = 0x0,
2343 .pre_div_mask = 0x7 << 12,
2344 .post_div_val = 0x0,
2345 .post_div_mask = 0x3 << 8,
2346 .mn_ena_mask = BIT(24),
2347 .main_output_mask = BIT(0),
2348 .aux_output_mask = BIT(1),
2349};
2350
2351static struct gdsc venus0_gdsc = {
2352 .gdscr = 0x1024,
2353 .cxcs = (unsigned int []){ 0x1028 },
2354 .cxc_count = 1,
2355 .resets = (unsigned int []){ VENUS0_RESET },
2356 .reset_count = 1,
2357 .pd = {
2358 .name = "venus0",
2359 },
2360 .pwrsts = PWRSTS_ON,
2361};
2362
2363static struct gdsc mdss_gdsc = {
2364 .gdscr = 0x2304,
2365 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2366 .cxc_count = 2,
2367 .pd = {
2368 .name = "mdss",
2369 },
2370 .pwrsts = PWRSTS_OFF_ON,
2371};
2372
2373static struct gdsc camss_jpeg_gdsc = {
2374 .gdscr = 0x35a4,
2375 .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2376 .cxc_count = 3,
2377 .pd = {
2378 .name = "camss_jpeg",
2379 },
2380 .pwrsts = PWRSTS_OFF_ON,
2381};
2382
2383static struct gdsc camss_vfe_gdsc = {
2384 .gdscr = 0x36a4,
2385 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2386 .cxc_count = 5,
2387 .pd = {
2388 .name = "camss_vfe",
2389 },
2390 .pwrsts = PWRSTS_OFF_ON,
2391};
2392
2393static struct gdsc oxili_gdsc = {
2394 .gdscr = 0x4024,
2395 .cxcs = (unsigned int []){ 0x4028 },
2396 .cxc_count = 1,
2397 .pd = {
2398 .name = "oxili",
2399 },
2400 .pwrsts = PWRSTS_OFF_ON,
2401};
2402
2403static struct gdsc oxilicx_gdsc = {
2404 .gdscr = 0x4034,
2405 .pd = {
2406 .name = "oxilicx",
2407 },
2408 .parent = &oxili_gdsc.pd,
2409 .pwrsts = PWRSTS_OFF_ON,
2410};
2411
2412static struct gdsc oxili_cx_gdsc_msm8226 = {
2413 .gdscr = 0x4034,
2414 .cxcs = (unsigned int []){ 0x4028 },
2415 .cxc_count = 1,
2416 .pd = {
2417 .name = "oxili_cx",
2418 },
2419 .pwrsts = PWRSTS_OFF_ON,
2420};
2421
2422static struct clk_regmap *mmcc_msm8226_clocks[] = {
2423 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2424 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2425 [MMPLL0] = &mmpll0.clkr,
2426 [MMPLL0_VOTE] = &mmpll0_vote,
2427 [MMPLL1] = &mmpll1.clkr,
2428 [MMPLL1_VOTE] = &mmpll1_vote,
2429 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2430 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2431 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2432 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2433 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2434 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2435 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2436 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2437 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2438 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2439 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2440 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2441 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2442 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2443 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2444 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2445 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2446 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2447 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2448 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2449 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2450 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2451 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2452 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2453 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2454 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2455 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2456 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2457 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2458 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2459 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2460 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2461 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2462 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2463 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2464 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2465 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2466 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2467 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2468 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2469 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2470 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2471 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2472 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2473 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2474 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2475 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2476 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2477 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2478 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2479 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2480 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2481 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2482 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2483 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2484 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2485 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2486 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2487 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2488 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2489 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2490 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2491 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2492 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2493 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2494 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2495 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2496};
2497
2498static const struct qcom_reset_map mmcc_msm8226_resets[] = {
2499 [SPDM_RESET] = { 0x0200 },
2500 [SPDM_RM_RESET] = { 0x0300 },
2501 [VENUS0_RESET] = { 0x1020 },
2502 [MDSS_RESET] = { 0x2300 },
2503};
2504
2505static struct gdsc *mmcc_msm8226_gdscs[] = {
2506 [VENUS0_GDSC] = &venus0_gdsc,
2507 [MDSS_GDSC] = &mdss_gdsc,
2508 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2509 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2510 [OXILICX_GDSC] = &oxili_cx_gdsc_msm8226,
2511};
2512
2513static const struct regmap_config mmcc_msm8226_regmap_config = {
2514 .reg_bits = 32,
2515 .reg_stride = 4,
2516 .val_bits = 32,
2517 .max_register = 0x5104,
2518 .fast_io = true,
2519};
2520
2521static const struct qcom_cc_desc mmcc_msm8226_desc = {
2522 .config = &mmcc_msm8226_regmap_config,
2523 .clks = mmcc_msm8226_clocks,
2524 .num_clks = ARRAY_SIZE(mmcc_msm8226_clocks),
2525 .resets = mmcc_msm8226_resets,
2526 .num_resets = ARRAY_SIZE(mmcc_msm8226_resets),
2527 .gdscs = mmcc_msm8226_gdscs,
2528 .num_gdscs = ARRAY_SIZE(mmcc_msm8226_gdscs),
2529};
2530
2531static struct clk_regmap *mmcc_msm8974_clocks[] = {
2532 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2533 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2534 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2535 [MMPLL0] = &mmpll0.clkr,
2536 [MMPLL0_VOTE] = &mmpll0_vote,
2537 [MMPLL1] = &mmpll1.clkr,
2538 [MMPLL1_VOTE] = &mmpll1_vote,
2539 [MMPLL2] = &mmpll2.clkr,
2540 [MMPLL3] = &mmpll3.clkr,
2541 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2542 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2543 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2544 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2545 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2546 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2547 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2548 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2549 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2550 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2551 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2552 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2553 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2554 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2555 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2556 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2557 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2558 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2559 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2560 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2561 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2562 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2563 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2564 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2565 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2566 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2567 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2568 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2569 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2570 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2571 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2572 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2573 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2574 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2575 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2576 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2577 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2578 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2579 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2580 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2581 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2582 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2583 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2584 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2585 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2586 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2587 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2588 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2589 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2590 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2591 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2592 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2593 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2594 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2595 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2596 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2597 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2598 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2599 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2600 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2601 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2602 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2603 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2604 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2605 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2606 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2607 [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2608 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2609 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2610 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2611 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2612 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2613 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2614 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2615 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2616 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2617 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2618 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2619 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2620 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2621 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2622 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2623 [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2624 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2625 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2626 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2627 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2628 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2629 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2630 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2631 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2632 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2633 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2634 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2635 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2636 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2637 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2638 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2639 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2640 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2641 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2642 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2643 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2644 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2645 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2646 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2647 [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2648 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2649 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2650 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2651 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2652 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2653 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2654 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2655};
2656
2657static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2658 [SPDM_RESET] = { 0x0200 },
2659 [SPDM_RM_RESET] = { 0x0300 },
2660 [VENUS0_RESET] = { 0x1020 },
2661 [MDSS_RESET] = { 0x2300 },
2662 [CAMSS_PHY0_RESET] = { 0x3020 },
2663 [CAMSS_PHY1_RESET] = { 0x3050 },
2664 [CAMSS_PHY2_RESET] = { 0x3080 },
2665 [CAMSS_CSI0_RESET] = { 0x30b0 },
2666 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2667 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2668 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2669 [CAMSS_CSI1_RESET] = { 0x3120 },
2670 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2671 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2672 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2673 [CAMSS_CSI2_RESET] = { 0x3180 },
2674 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2675 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2676 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2677 [CAMSS_CSI3_RESET] = { 0x31e0 },
2678 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2679 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2680 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2681 [CAMSS_ISPIF_RESET] = { 0x3220 },
2682 [CAMSS_CCI_RESET] = { 0x3340 },
2683 [CAMSS_MCLK0_RESET] = { 0x3380 },
2684 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2685 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2686 [CAMSS_MCLK3_RESET] = { 0x3410 },
2687 [CAMSS_GP0_RESET] = { 0x3440 },
2688 [CAMSS_GP1_RESET] = { 0x3470 },
2689 [CAMSS_TOP_RESET] = { 0x3480 },
2690 [CAMSS_MICRO_RESET] = { 0x3490 },
2691 [CAMSS_JPEG_RESET] = { 0x35a0 },
2692 [CAMSS_VFE_RESET] = { 0x36a0 },
2693 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2694 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2695 [OXILI_RESET] = { 0x4020 },
2696 [OXILICX_RESET] = { 0x4030 },
2697 [OCMEMCX_RESET] = { 0x4050 },
2698 [MMSS_RBCRP_RESET] = { 0x4080 },
2699 [MMSSNOCAHB_RESET] = { 0x5020 },
2700 [MMSSNOCAXI_RESET] = { 0x5060 },
2701 [OCMEMNOC_RESET] = { 0x50b0 },
2702};
2703
2704static struct gdsc *mmcc_msm8974_gdscs[] = {
2705 [VENUS0_GDSC] = &venus0_gdsc,
2706 [MDSS_GDSC] = &mdss_gdsc,
2707 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2708 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2709 [OXILI_GDSC] = &oxili_gdsc,
2710 [OXILICX_GDSC] = &oxilicx_gdsc,
2711};
2712
2713static const struct regmap_config mmcc_msm8974_regmap_config = {
2714 .reg_bits = 32,
2715 .reg_stride = 4,
2716 .val_bits = 32,
2717 .max_register = 0x5104,
2718 .fast_io = true,
2719};
2720
2721static const struct qcom_cc_desc mmcc_msm8974_desc = {
2722 .config = &mmcc_msm8974_regmap_config,
2723 .clks = mmcc_msm8974_clocks,
2724 .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2725 .resets = mmcc_msm8974_resets,
2726 .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2727 .gdscs = mmcc_msm8974_gdscs,
2728 .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
2729};
2730
2731static const struct of_device_id mmcc_msm8974_match_table[] = {
2732 { .compatible = "qcom,mmcc-msm8226", .data = &mmcc_msm8226_desc },
2733 { .compatible = "qcom,mmcc-msm8974", .data = &mmcc_msm8974_desc },
2734 { }
2735};
2736MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2737
2738static void msm8226_clock_override(void)
2739{
2740 mmss_axi_clk_src.freq_tbl = ftbl_mmss_axi_clk_msm8226;
2741 vfe0_clk_src.freq_tbl = ftbl_camss_vfe_vfe0_clk_msm8226;
2742 mdp_clk_src.freq_tbl = ftbl_mdss_mdp_clk_msm8226;
2743 vcodec0_clk_src.freq_tbl = ftbl_venus0_vcodec0_clk_msm8226;
2744 mclk0_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
2745 mclk1_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
2746 cpp_clk_src.freq_tbl = ftbl_camss_vfe_cpp_clk_msm8226;
2747}
2748
2749static int mmcc_msm8974_probe(struct platform_device *pdev)
2750{
2751 struct regmap *regmap;
2752 const struct qcom_cc_desc *desc;
2753
2754 desc = of_device_get_match_data(&pdev->dev);
2755 if (!desc)
2756 return -EINVAL;
2757
2758 regmap = qcom_cc_map(pdev, desc);
2759 if (IS_ERR(regmap))
2760 return PTR_ERR(regmap);
2761
2762 if (desc == &mmcc_msm8974_desc) {
2763 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2764 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2765 } else {
2766 msm8226_clock_override();
2767 }
2768
2769 return qcom_cc_really_probe(pdev, desc, regmap);
2770}
2771
2772static struct platform_driver mmcc_msm8974_driver = {
2773 .probe = mmcc_msm8974_probe,
2774 .driver = {
2775 .name = "mmcc-msm8974",
2776 .of_match_table = mmcc_msm8974_match_table,
2777 },
2778};
2779module_platform_driver(mmcc_msm8974_driver);
2780
2781MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2782MODULE_LICENSE("GPL v2");
2783MODULE_ALIAS("platform:mmcc-msm8974");