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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/bitops.h>
8#include <linux/err.h>
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
13#include <linux/clk-provider.h>
14#include <linux/regmap.h>
15#include <linux/reset-controller.h>
16
17#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
18#include <dt-bindings/reset/qcom,mmcc-msm8974.h>
19
20#include "common.h"
21#include "clk-regmap.h"
22#include "clk-pll.h"
23#include "clk-rcg.h"
24#include "clk-branch.h"
25#include "reset.h"
26#include "gdsc.h"
27
28enum {
29 P_XO,
30 P_MMPLL0,
31 P_EDPLINK,
32 P_MMPLL1,
33 P_HDMIPLL,
34 P_GPLL0,
35 P_EDPVCO,
36 P_GPLL1,
37 P_DSI0PLL,
38 P_DSI0PLL_BYTE,
39 P_MMPLL2,
40 P_MMPLL3,
41 P_DSI1PLL,
42 P_DSI1PLL_BYTE,
43};
44
45static struct clk_pll mmpll0 = {
46 .l_reg = 0x0004,
47 .m_reg = 0x0008,
48 .n_reg = 0x000c,
49 .config_reg = 0x0014,
50 .mode_reg = 0x0000,
51 .status_reg = 0x001c,
52 .status_bit = 17,
53 .clkr.hw.init = &(struct clk_init_data){
54 .name = "mmpll0",
55 .parent_data = (const struct clk_parent_data[]){
56 { .fw_name = "xo", .name = "xo_board" },
57 },
58 .num_parents = 1,
59 .ops = &clk_pll_ops,
60 },
61};
62
63static struct clk_regmap mmpll0_vote = {
64 .enable_reg = 0x0100,
65 .enable_mask = BIT(0),
66 .hw.init = &(struct clk_init_data){
67 .name = "mmpll0_vote",
68 .parent_hws = (const struct clk_hw*[]){
69 &mmpll0.clkr.hw
70 },
71 .num_parents = 1,
72 .ops = &clk_pll_vote_ops,
73 },
74};
75
76static struct clk_pll mmpll1 = {
77 .l_reg = 0x0044,
78 .m_reg = 0x0048,
79 .n_reg = 0x004c,
80 .config_reg = 0x0050,
81 .mode_reg = 0x0040,
82 .status_reg = 0x005c,
83 .status_bit = 17,
84 .clkr.hw.init = &(struct clk_init_data){
85 .name = "mmpll1",
86 .parent_data = (const struct clk_parent_data[]){
87 { .fw_name = "xo", .name = "xo_board" },
88 },
89 .num_parents = 1,
90 .ops = &clk_pll_ops,
91 },
92};
93
94static struct clk_regmap mmpll1_vote = {
95 .enable_reg = 0x0100,
96 .enable_mask = BIT(1),
97 .hw.init = &(struct clk_init_data){
98 .name = "mmpll1_vote",
99 .parent_hws = (const struct clk_hw*[]){
100 &mmpll1.clkr.hw
101 },
102 .num_parents = 1,
103 .ops = &clk_pll_vote_ops,
104 },
105};
106
107static struct clk_pll mmpll2 = {
108 .l_reg = 0x4104,
109 .m_reg = 0x4108,
110 .n_reg = 0x410c,
111 .config_reg = 0x4110,
112 .mode_reg = 0x4100,
113 .status_reg = 0x411c,
114 .clkr.hw.init = &(struct clk_init_data){
115 .name = "mmpll2",
116 .parent_data = (const struct clk_parent_data[]){
117 { .fw_name = "xo", .name = "xo_board" },
118 },
119 .num_parents = 1,
120 .ops = &clk_pll_ops,
121 },
122};
123
124static struct clk_pll mmpll3 = {
125 .l_reg = 0x0084,
126 .m_reg = 0x0088,
127 .n_reg = 0x008c,
128 .config_reg = 0x0090,
129 .mode_reg = 0x0080,
130 .status_reg = 0x009c,
131 .status_bit = 17,
132 .clkr.hw.init = &(struct clk_init_data){
133 .name = "mmpll3",
134 .parent_data = (const struct clk_parent_data[]){
135 { .fw_name = "xo", .name = "xo_board" },
136 },
137 .num_parents = 1,
138 .ops = &clk_pll_ops,
139 },
140};
141
142static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
143 { P_XO, 0 },
144 { P_MMPLL0, 1 },
145 { P_MMPLL1, 2 },
146 { P_GPLL0, 5 }
147};
148
149static const struct clk_parent_data mmcc_xo_mmpll0_mmpll1_gpll0[] = {
150 { .fw_name = "xo", .name = "xo_board" },
151 { .hw = &mmpll0_vote.hw },
152 { .hw = &mmpll1_vote.hw },
153 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
154};
155
156static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
157 { P_XO, 0 },
158 { P_MMPLL0, 1 },
159 { P_HDMIPLL, 4 },
160 { P_GPLL0, 5 },
161 { P_DSI0PLL, 2 },
162 { P_DSI1PLL, 3 }
163};
164
165static const struct clk_parent_data mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
166 { .fw_name = "xo", .name = "xo_board" },
167 { .hw = &mmpll0_vote.hw },
168 { .fw_name = "hdmipll", .name = "hdmipll" },
169 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
170 { .fw_name = "dsi0pll", .name = "dsi0pll" },
171 { .fw_name = "dsi1pll", .name = "dsi1pll" },
172};
173
174static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
175 { P_XO, 0 },
176 { P_MMPLL0, 1 },
177 { P_MMPLL1, 2 },
178 { P_GPLL0, 5 },
179 { P_MMPLL3, 3 }
180};
181
182static const struct clk_parent_data mmcc_xo_mmpll0_1_3_gpll0[] = {
183 { .fw_name = "xo", .name = "xo_board" },
184 { .hw = &mmpll0_vote.hw },
185 { .hw = &mmpll1_vote.hw },
186 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
187 { .hw = &mmpll3.clkr.hw },
188};
189
190static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
191 { P_XO, 0 },
192 { P_MMPLL0, 1 },
193 { P_MMPLL1, 2 },
194 { P_GPLL0, 5 },
195 { P_GPLL1, 4 }
196};
197
198static const struct clk_parent_data mmcc_xo_mmpll0_1_gpll1_0[] = {
199 { .fw_name = "xo", .name = "xo_board" },
200 { .hw = &mmpll0_vote.hw },
201 { .hw = &mmpll1_vote.hw },
202 { .fw_name = "mmss_gpll0_vote", .name = "mmss_gpll0_vote" },
203 { .fw_name = "gpll1_vote", .name = "gpll1_vote" },
204};
205
206static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
207 { P_XO, 0 },
208 { P_EDPLINK, 4 },
209 { P_HDMIPLL, 3 },
210 { P_EDPVCO, 5 },
211 { P_DSI0PLL, 1 },
212 { P_DSI1PLL, 2 }
213};
214
215static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp[] = {
216 { .fw_name = "xo", .name = "xo_board" },
217 { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
218 { .fw_name = "hdmipll", .name = "hdmipll" },
219 { .fw_name = "edp_vco_div", .name = "edp_vco_div" },
220 { .fw_name = "dsi0pll", .name = "dsi0pll" },
221 { .fw_name = "dsi1pll", .name = "dsi1pll" },
222};
223
224static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
225 { P_XO, 0 },
226 { P_EDPLINK, 4 },
227 { P_HDMIPLL, 3 },
228 { P_GPLL0, 5 },
229 { P_DSI0PLL, 1 },
230 { P_DSI1PLL, 2 }
231};
232
233static const struct clk_parent_data mmcc_xo_dsi_hdmi_edp_gpll0[] = {
234 { .fw_name = "xo", .name = "xo_board" },
235 { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
236 { .fw_name = "hdmipll", .name = "hdmipll" },
237 { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
238 { .fw_name = "dsi0pll", .name = "dsi0pll" },
239 { .fw_name = "dsi1pll", .name = "dsi1pll" },
240};
241
242static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
243 { P_XO, 0 },
244 { P_EDPLINK, 4 },
245 { P_HDMIPLL, 3 },
246 { P_GPLL0, 5 },
247 { P_DSI0PLL_BYTE, 1 },
248 { P_DSI1PLL_BYTE, 2 }
249};
250
251static const struct clk_parent_data mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
252 { .fw_name = "xo", .name = "xo_board" },
253 { .fw_name = "edp_link_clk", .name = "edp_link_clk" },
254 { .fw_name = "hdmipll", .name = "hdmipll" },
255 { .fw_name = "gpll0_vote", .name = "gpll0_vote" },
256 { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
257 { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
258};
259
260static struct clk_rcg2 mmss_ahb_clk_src = {
261 .cmd_rcgr = 0x5000,
262 .hid_width = 5,
263 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
264 .clkr.hw.init = &(struct clk_init_data){
265 .name = "mmss_ahb_clk_src",
266 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
267 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
268 .ops = &clk_rcg2_ops,
269 },
270};
271
272static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
273 F(19200000, P_XO, 1, 0, 0),
274 F(37500000, P_GPLL0, 16, 0, 0),
275 F(50000000, P_GPLL0, 12, 0, 0),
276 F(75000000, P_GPLL0, 8, 0, 0),
277 F(100000000, P_GPLL0, 6, 0, 0),
278 F(150000000, P_GPLL0, 4, 0, 0),
279 F(200000000, P_MMPLL0, 4, 0, 0),
280 F(266666666, P_MMPLL0, 3, 0, 0),
281 { }
282};
283
284static struct freq_tbl ftbl_mmss_axi_clk[] = {
285 F( 19200000, P_XO, 1, 0, 0),
286 F( 37500000, P_GPLL0, 16, 0, 0),
287 F( 50000000, P_GPLL0, 12, 0, 0),
288 F( 75000000, P_GPLL0, 8, 0, 0),
289 F(100000000, P_GPLL0, 6, 0, 0),
290 F(150000000, P_GPLL0, 4, 0, 0),
291 F(291750000, P_MMPLL1, 4, 0, 0),
292 F(400000000, P_MMPLL0, 2, 0, 0),
293 F(466800000, P_MMPLL1, 2.5, 0, 0),
294};
295
296static struct clk_rcg2 mmss_axi_clk_src = {
297 .cmd_rcgr = 0x5040,
298 .hid_width = 5,
299 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
300 .freq_tbl = ftbl_mmss_axi_clk,
301 .clkr.hw.init = &(struct clk_init_data){
302 .name = "mmss_axi_clk_src",
303 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
304 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
305 .ops = &clk_rcg2_ops,
306 },
307};
308
309static struct freq_tbl ftbl_ocmemnoc_clk[] = {
310 F( 19200000, P_XO, 1, 0, 0),
311 F( 37500000, P_GPLL0, 16, 0, 0),
312 F( 50000000, P_GPLL0, 12, 0, 0),
313 F( 75000000, P_GPLL0, 8, 0, 0),
314 F(100000000, P_GPLL0, 6, 0, 0),
315 F(150000000, P_GPLL0, 4, 0, 0),
316 F(291750000, P_MMPLL1, 4, 0, 0),
317 F(400000000, P_MMPLL0, 2, 0, 0),
318};
319
320static struct clk_rcg2 ocmemnoc_clk_src = {
321 .cmd_rcgr = 0x5090,
322 .hid_width = 5,
323 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
324 .freq_tbl = ftbl_ocmemnoc_clk,
325 .clkr.hw.init = &(struct clk_init_data){
326 .name = "ocmemnoc_clk_src",
327 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
328 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
329 .ops = &clk_rcg2_ops,
330 },
331};
332
333static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
334 F(100000000, P_GPLL0, 6, 0, 0),
335 F(200000000, P_MMPLL0, 4, 0, 0),
336 { }
337};
338
339static struct clk_rcg2 csi0_clk_src = {
340 .cmd_rcgr = 0x3090,
341 .hid_width = 5,
342 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
343 .freq_tbl = ftbl_camss_csi0_3_clk,
344 .clkr.hw.init = &(struct clk_init_data){
345 .name = "csi0_clk_src",
346 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
347 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
348 .ops = &clk_rcg2_ops,
349 },
350};
351
352static struct clk_rcg2 csi1_clk_src = {
353 .cmd_rcgr = 0x3100,
354 .hid_width = 5,
355 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
356 .freq_tbl = ftbl_camss_csi0_3_clk,
357 .clkr.hw.init = &(struct clk_init_data){
358 .name = "csi1_clk_src",
359 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
360 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
361 .ops = &clk_rcg2_ops,
362 },
363};
364
365static struct clk_rcg2 csi2_clk_src = {
366 .cmd_rcgr = 0x3160,
367 .hid_width = 5,
368 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
369 .freq_tbl = ftbl_camss_csi0_3_clk,
370 .clkr.hw.init = &(struct clk_init_data){
371 .name = "csi2_clk_src",
372 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
373 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
374 .ops = &clk_rcg2_ops,
375 },
376};
377
378static struct clk_rcg2 csi3_clk_src = {
379 .cmd_rcgr = 0x31c0,
380 .hid_width = 5,
381 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
382 .freq_tbl = ftbl_camss_csi0_3_clk,
383 .clkr.hw.init = &(struct clk_init_data){
384 .name = "csi3_clk_src",
385 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
386 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
387 .ops = &clk_rcg2_ops,
388 },
389};
390
391static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
392 F(37500000, P_GPLL0, 16, 0, 0),
393 F(50000000, P_GPLL0, 12, 0, 0),
394 F(60000000, P_GPLL0, 10, 0, 0),
395 F(80000000, P_GPLL0, 7.5, 0, 0),
396 F(100000000, P_GPLL0, 6, 0, 0),
397 F(109090000, P_GPLL0, 5.5, 0, 0),
398 F(133330000, P_GPLL0, 4.5, 0, 0),
399 F(150000000, P_GPLL0, 4, 0, 0),
400 F(200000000, P_GPLL0, 3, 0, 0),
401 F(228570000, P_MMPLL0, 3.5, 0, 0),
402 F(266670000, P_MMPLL0, 3, 0, 0),
403 F(320000000, P_MMPLL0, 2.5, 0, 0),
404 F(400000000, P_MMPLL0, 2, 0, 0),
405 { }
406};
407
408static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
409 F(37500000, P_GPLL0, 16, 0, 0),
410 F(50000000, P_GPLL0, 12, 0, 0),
411 F(60000000, P_GPLL0, 10, 0, 0),
412 F(80000000, P_GPLL0, 7.5, 0, 0),
413 F(100000000, P_GPLL0, 6, 0, 0),
414 F(109090000, P_GPLL0, 5.5, 0, 0),
415 F(133330000, P_GPLL0, 4.5, 0, 0),
416 F(200000000, P_GPLL0, 3, 0, 0),
417 F(228570000, P_MMPLL0, 3.5, 0, 0),
418 F(266670000, P_MMPLL0, 3, 0, 0),
419 F(320000000, P_MMPLL0, 2.5, 0, 0),
420 F(400000000, P_MMPLL0, 2, 0, 0),
421 F(465000000, P_MMPLL3, 2, 0, 0),
422 { }
423};
424
425static struct clk_rcg2 vfe0_clk_src = {
426 .cmd_rcgr = 0x3600,
427 .hid_width = 5,
428 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
429 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
430 .clkr.hw.init = &(struct clk_init_data){
431 .name = "vfe0_clk_src",
432 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
433 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
434 .ops = &clk_rcg2_ops,
435 },
436};
437
438static struct clk_rcg2 vfe1_clk_src = {
439 .cmd_rcgr = 0x3620,
440 .hid_width = 5,
441 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
442 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
443 .clkr.hw.init = &(struct clk_init_data){
444 .name = "vfe1_clk_src",
445 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
446 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
447 .ops = &clk_rcg2_ops,
448 },
449};
450
451static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
452 F(37500000, P_GPLL0, 16, 0, 0),
453 F(60000000, P_GPLL0, 10, 0, 0),
454 F(75000000, P_GPLL0, 8, 0, 0),
455 F(92310000, P_GPLL0, 6.5, 0, 0),
456 F(100000000, P_GPLL0, 6, 0, 0),
457 F(133330000, P_MMPLL0, 6, 0, 0),
458 F(177780000, P_MMPLL0, 4.5, 0, 0),
459 F(200000000, P_MMPLL0, 4, 0, 0),
460 { }
461};
462
463static struct freq_tbl ftbl_mdss_mdp_clk[] = {
464 F(37500000, P_GPLL0, 16, 0, 0),
465 F(60000000, P_GPLL0, 10, 0, 0),
466 F(75000000, P_GPLL0, 8, 0, 0),
467 F(85710000, P_GPLL0, 7, 0, 0),
468 F(100000000, P_GPLL0, 6, 0, 0),
469 F(133330000, P_MMPLL0, 6, 0, 0),
470 F(160000000, P_MMPLL0, 5, 0, 0),
471 F(200000000, P_MMPLL0, 4, 0, 0),
472 F(228570000, P_MMPLL0, 3.5, 0, 0),
473 F(240000000, P_GPLL0, 2.5, 0, 0),
474 F(266670000, P_MMPLL0, 3, 0, 0),
475 F(320000000, P_MMPLL0, 2.5, 0, 0),
476 { }
477};
478
479static struct clk_rcg2 mdp_clk_src = {
480 .cmd_rcgr = 0x2040,
481 .hid_width = 5,
482 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
483 .freq_tbl = ftbl_mdss_mdp_clk,
484 .clkr.hw.init = &(struct clk_init_data){
485 .name = "mdp_clk_src",
486 .parent_data = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
487 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
488 .ops = &clk_rcg2_ops,
489 },
490};
491
492static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
493 F(75000000, P_GPLL0, 8, 0, 0),
494 F(133330000, P_GPLL0, 4.5, 0, 0),
495 F(200000000, P_GPLL0, 3, 0, 0),
496 F(228570000, P_MMPLL0, 3.5, 0, 0),
497 F(266670000, P_MMPLL0, 3, 0, 0),
498 F(320000000, P_MMPLL0, 2.5, 0, 0),
499 { }
500};
501
502static struct clk_rcg2 jpeg0_clk_src = {
503 .cmd_rcgr = 0x3500,
504 .hid_width = 5,
505 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
506 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
507 .clkr.hw.init = &(struct clk_init_data){
508 .name = "jpeg0_clk_src",
509 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
510 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
511 .ops = &clk_rcg2_ops,
512 },
513};
514
515static struct clk_rcg2 jpeg1_clk_src = {
516 .cmd_rcgr = 0x3520,
517 .hid_width = 5,
518 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
519 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
520 .clkr.hw.init = &(struct clk_init_data){
521 .name = "jpeg1_clk_src",
522 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
523 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
524 .ops = &clk_rcg2_ops,
525 },
526};
527
528static struct clk_rcg2 jpeg2_clk_src = {
529 .cmd_rcgr = 0x3540,
530 .hid_width = 5,
531 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
532 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
533 .clkr.hw.init = &(struct clk_init_data){
534 .name = "jpeg2_clk_src",
535 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
536 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
537 .ops = &clk_rcg2_ops,
538 },
539};
540
541static struct clk_rcg2 pclk0_clk_src = {
542 .cmd_rcgr = 0x2000,
543 .mnd_width = 8,
544 .hid_width = 5,
545 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
546 .clkr.hw.init = &(struct clk_init_data){
547 .name = "pclk0_clk_src",
548 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
549 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
550 .ops = &clk_pixel_ops,
551 .flags = CLK_SET_RATE_PARENT,
552 },
553};
554
555static struct clk_rcg2 pclk1_clk_src = {
556 .cmd_rcgr = 0x2020,
557 .mnd_width = 8,
558 .hid_width = 5,
559 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
560 .clkr.hw.init = &(struct clk_init_data){
561 .name = "pclk1_clk_src",
562 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
563 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
564 .ops = &clk_pixel_ops,
565 .flags = CLK_SET_RATE_PARENT,
566 },
567};
568
569static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
570 F(66700000, P_GPLL0, 9, 0, 0),
571 F(100000000, P_GPLL0, 6, 0, 0),
572 F(133330000, P_MMPLL0, 6, 0, 0),
573 F(160000000, P_MMPLL0, 5, 0, 0),
574 { }
575};
576
577static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
578 F(50000000, P_GPLL0, 12, 0, 0),
579 F(100000000, P_GPLL0, 6, 0, 0),
580 F(133330000, P_MMPLL0, 6, 0, 0),
581 F(200000000, P_MMPLL0, 4, 0, 0),
582 F(266670000, P_MMPLL0, 3, 0, 0),
583 F(465000000, P_MMPLL3, 2, 0, 0),
584 { }
585};
586
587static struct clk_rcg2 vcodec0_clk_src = {
588 .cmd_rcgr = 0x1000,
589 .mnd_width = 8,
590 .hid_width = 5,
591 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
592 .freq_tbl = ftbl_venus0_vcodec0_clk,
593 .clkr.hw.init = &(struct clk_init_data){
594 .name = "vcodec0_clk_src",
595 .parent_data = mmcc_xo_mmpll0_1_3_gpll0,
596 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
597 .ops = &clk_rcg2_ops,
598 },
599};
600
601static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
602 F(19200000, P_XO, 1, 0, 0),
603 { }
604};
605
606static struct clk_rcg2 cci_clk_src = {
607 .cmd_rcgr = 0x3300,
608 .hid_width = 5,
609 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
610 .freq_tbl = ftbl_camss_cci_cci_clk,
611 .clkr.hw.init = &(struct clk_init_data){
612 .name = "cci_clk_src",
613 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
614 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
615 .ops = &clk_rcg2_ops,
616 },
617};
618
619static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
620 F(10000, P_XO, 16, 1, 120),
621 F(24000, P_XO, 16, 1, 50),
622 F(6000000, P_GPLL0, 10, 1, 10),
623 F(12000000, P_GPLL0, 10, 1, 5),
624 F(13000000, P_GPLL0, 4, 13, 150),
625 F(24000000, P_GPLL0, 5, 1, 5),
626 { }
627};
628
629static struct clk_rcg2 camss_gp0_clk_src = {
630 .cmd_rcgr = 0x3420,
631 .mnd_width = 8,
632 .hid_width = 5,
633 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
634 .freq_tbl = ftbl_camss_gp0_1_clk,
635 .clkr.hw.init = &(struct clk_init_data){
636 .name = "camss_gp0_clk_src",
637 .parent_data = mmcc_xo_mmpll0_1_gpll1_0,
638 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
639 .ops = &clk_rcg2_ops,
640 },
641};
642
643static struct clk_rcg2 camss_gp1_clk_src = {
644 .cmd_rcgr = 0x3450,
645 .mnd_width = 8,
646 .hid_width = 5,
647 .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
648 .freq_tbl = ftbl_camss_gp0_1_clk,
649 .clkr.hw.init = &(struct clk_init_data){
650 .name = "camss_gp1_clk_src",
651 .parent_data = mmcc_xo_mmpll0_1_gpll1_0,
652 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0),
653 .ops = &clk_rcg2_ops,
654 },
655};
656
657static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
658 F(19200000, P_XO, 1, 0, 0),
659 F(24000000, P_GPLL0, 5, 1, 5),
660 F(66670000, P_GPLL0, 9, 0, 0),
661 { }
662};
663
664static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
665 F(4800000, P_XO, 4, 0, 0),
666 F(6000000, P_GPLL0, 10, 1, 10),
667 F(8000000, P_GPLL0, 15, 1, 5),
668 F(9600000, P_XO, 2, 0, 0),
669 F(16000000, P_GPLL0, 12.5, 1, 3),
670 F(19200000, P_XO, 1, 0, 0),
671 F(24000000, P_GPLL0, 5, 1, 5),
672 F(32000000, P_MMPLL0, 5, 1, 5),
673 F(48000000, P_GPLL0, 12.5, 0, 0),
674 F(64000000, P_MMPLL0, 12.5, 0, 0),
675 F(66670000, P_GPLL0, 9, 0, 0),
676 { }
677};
678
679static struct clk_rcg2 mclk0_clk_src = {
680 .cmd_rcgr = 0x3360,
681 .hid_width = 5,
682 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
683 .freq_tbl = ftbl_camss_mclk0_3_clk,
684 .clkr.hw.init = &(struct clk_init_data){
685 .name = "mclk0_clk_src",
686 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
687 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
688 .ops = &clk_rcg2_ops,
689 },
690};
691
692static struct clk_rcg2 mclk1_clk_src = {
693 .cmd_rcgr = 0x3390,
694 .hid_width = 5,
695 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
696 .freq_tbl = ftbl_camss_mclk0_3_clk,
697 .clkr.hw.init = &(struct clk_init_data){
698 .name = "mclk1_clk_src",
699 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
700 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
701 .ops = &clk_rcg2_ops,
702 },
703};
704
705static struct clk_rcg2 mclk2_clk_src = {
706 .cmd_rcgr = 0x33c0,
707 .hid_width = 5,
708 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
709 .freq_tbl = ftbl_camss_mclk0_3_clk,
710 .clkr.hw.init = &(struct clk_init_data){
711 .name = "mclk2_clk_src",
712 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
713 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
714 .ops = &clk_rcg2_ops,
715 },
716};
717
718static struct clk_rcg2 mclk3_clk_src = {
719 .cmd_rcgr = 0x33f0,
720 .hid_width = 5,
721 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
722 .freq_tbl = ftbl_camss_mclk0_3_clk,
723 .clkr.hw.init = &(struct clk_init_data){
724 .name = "mclk3_clk_src",
725 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
726 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
727 .ops = &clk_rcg2_ops,
728 },
729};
730
731static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
732 F(100000000, P_GPLL0, 6, 0, 0),
733 F(200000000, P_MMPLL0, 4, 0, 0),
734 { }
735};
736
737static struct clk_rcg2 csi0phytimer_clk_src = {
738 .cmd_rcgr = 0x3000,
739 .hid_width = 5,
740 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
741 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
742 .clkr.hw.init = &(struct clk_init_data){
743 .name = "csi0phytimer_clk_src",
744 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
745 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
746 .ops = &clk_rcg2_ops,
747 },
748};
749
750static struct clk_rcg2 csi1phytimer_clk_src = {
751 .cmd_rcgr = 0x3030,
752 .hid_width = 5,
753 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
754 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
755 .clkr.hw.init = &(struct clk_init_data){
756 .name = "csi1phytimer_clk_src",
757 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
758 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
759 .ops = &clk_rcg2_ops,
760 },
761};
762
763static struct clk_rcg2 csi2phytimer_clk_src = {
764 .cmd_rcgr = 0x3060,
765 .hid_width = 5,
766 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
767 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
768 .clkr.hw.init = &(struct clk_init_data){
769 .name = "csi2phytimer_clk_src",
770 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
771 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
772 .ops = &clk_rcg2_ops,
773 },
774};
775
776static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
777 F(133330000, P_GPLL0, 4.5, 0, 0),
778 F(150000000, P_GPLL0, 4, 0, 0),
779 F(266670000, P_MMPLL0, 3, 0, 0),
780 F(320000000, P_MMPLL0, 2.5, 0, 0),
781 F(400000000, P_MMPLL0, 2, 0, 0),
782 { }
783};
784
785static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
786 F(133330000, P_GPLL0, 4.5, 0, 0),
787 F(266670000, P_MMPLL0, 3, 0, 0),
788 F(320000000, P_MMPLL0, 2.5, 0, 0),
789 F(400000000, P_MMPLL0, 2, 0, 0),
790 F(465000000, P_MMPLL3, 2, 0, 0),
791 { }
792};
793
794static struct clk_rcg2 cpp_clk_src = {
795 .cmd_rcgr = 0x3640,
796 .hid_width = 5,
797 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
798 .freq_tbl = ftbl_camss_vfe_cpp_clk,
799 .clkr.hw.init = &(struct clk_init_data){
800 .name = "cpp_clk_src",
801 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
802 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
803 .ops = &clk_rcg2_ops,
804 },
805};
806
807static struct freq_tbl byte_freq_tbl[] = {
808 { .src = P_DSI0PLL_BYTE },
809 { }
810};
811
812static struct clk_rcg2 byte0_clk_src = {
813 .cmd_rcgr = 0x2120,
814 .hid_width = 5,
815 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
816 .freq_tbl = byte_freq_tbl,
817 .clkr.hw.init = &(struct clk_init_data){
818 .name = "byte0_clk_src",
819 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
820 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
821 .ops = &clk_byte2_ops,
822 .flags = CLK_SET_RATE_PARENT,
823 },
824};
825
826static struct clk_rcg2 byte1_clk_src = {
827 .cmd_rcgr = 0x2140,
828 .hid_width = 5,
829 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
830 .freq_tbl = byte_freq_tbl,
831 .clkr.hw.init = &(struct clk_init_data){
832 .name = "byte1_clk_src",
833 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
834 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
835 .ops = &clk_byte2_ops,
836 .flags = CLK_SET_RATE_PARENT,
837 },
838};
839
840static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
841 F(19200000, P_XO, 1, 0, 0),
842 { }
843};
844
845static struct clk_rcg2 edpaux_clk_src = {
846 .cmd_rcgr = 0x20e0,
847 .hid_width = 5,
848 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
849 .freq_tbl = ftbl_mdss_edpaux_clk,
850 .clkr.hw.init = &(struct clk_init_data){
851 .name = "edpaux_clk_src",
852 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
853 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
854 .ops = &clk_rcg2_ops,
855 },
856};
857
858static struct freq_tbl ftbl_mdss_edplink_clk[] = {
859 F(135000000, P_EDPLINK, 2, 0, 0),
860 F(270000000, P_EDPLINK, 11, 0, 0),
861 { }
862};
863
864static struct clk_rcg2 edplink_clk_src = {
865 .cmd_rcgr = 0x20c0,
866 .hid_width = 5,
867 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
868 .freq_tbl = ftbl_mdss_edplink_clk,
869 .clkr.hw.init = &(struct clk_init_data){
870 .name = "edplink_clk_src",
871 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
872 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
873 .ops = &clk_rcg2_ops,
874 .flags = CLK_SET_RATE_PARENT,
875 },
876};
877
878static struct freq_tbl edp_pixel_freq_tbl[] = {
879 { .src = P_EDPVCO },
880 { }
881};
882
883static struct clk_rcg2 edppixel_clk_src = {
884 .cmd_rcgr = 0x20a0,
885 .mnd_width = 8,
886 .hid_width = 5,
887 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
888 .freq_tbl = edp_pixel_freq_tbl,
889 .clkr.hw.init = &(struct clk_init_data){
890 .name = "edppixel_clk_src",
891 .parent_data = mmcc_xo_dsi_hdmi_edp,
892 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
893 .ops = &clk_edp_pixel_ops,
894 },
895};
896
897static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
898 F(19200000, P_XO, 1, 0, 0),
899 { }
900};
901
902static struct clk_rcg2 esc0_clk_src = {
903 .cmd_rcgr = 0x2160,
904 .hid_width = 5,
905 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
906 .freq_tbl = ftbl_mdss_esc0_1_clk,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "esc0_clk_src",
909 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
910 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
911 .ops = &clk_rcg2_ops,
912 },
913};
914
915static struct clk_rcg2 esc1_clk_src = {
916 .cmd_rcgr = 0x2180,
917 .hid_width = 5,
918 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
919 .freq_tbl = ftbl_mdss_esc0_1_clk,
920 .clkr.hw.init = &(struct clk_init_data){
921 .name = "esc1_clk_src",
922 .parent_data = mmcc_xo_dsibyte_hdmi_edp_gpll0,
923 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
924 .ops = &clk_rcg2_ops,
925 },
926};
927
928static struct freq_tbl extpclk_freq_tbl[] = {
929 { .src = P_HDMIPLL },
930 { }
931};
932
933static struct clk_rcg2 extpclk_clk_src = {
934 .cmd_rcgr = 0x2060,
935 .hid_width = 5,
936 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
937 .freq_tbl = extpclk_freq_tbl,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "extpclk_clk_src",
940 .parent_data = mmcc_xo_dsi_hdmi_edp_gpll0,
941 .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
942 .ops = &clk_byte_ops,
943 .flags = CLK_SET_RATE_PARENT,
944 },
945};
946
947static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
948 F(19200000, P_XO, 1, 0, 0),
949 { }
950};
951
952static struct clk_rcg2 hdmi_clk_src = {
953 .cmd_rcgr = 0x2100,
954 .hid_width = 5,
955 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
956 .freq_tbl = ftbl_mdss_hdmi_clk,
957 .clkr.hw.init = &(struct clk_init_data){
958 .name = "hdmi_clk_src",
959 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
960 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
961 .ops = &clk_rcg2_ops,
962 },
963};
964
965static struct freq_tbl ftbl_mdss_vsync_clk[] = {
966 F(19200000, P_XO, 1, 0, 0),
967 { }
968};
969
970static struct clk_rcg2 vsync_clk_src = {
971 .cmd_rcgr = 0x2080,
972 .hid_width = 5,
973 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
974 .freq_tbl = ftbl_mdss_vsync_clk,
975 .clkr.hw.init = &(struct clk_init_data){
976 .name = "vsync_clk_src",
977 .parent_data = mmcc_xo_mmpll0_mmpll1_gpll0,
978 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
979 .ops = &clk_rcg2_ops,
980 },
981};
982
983static struct clk_branch camss_cci_cci_ahb_clk = {
984 .halt_reg = 0x3348,
985 .clkr = {
986 .enable_reg = 0x3348,
987 .enable_mask = BIT(0),
988 .hw.init = &(struct clk_init_data){
989 .name = "camss_cci_cci_ahb_clk",
990 .parent_hws = (const struct clk_hw*[]){
991 &mmss_ahb_clk_src.clkr.hw
992 },
993 .num_parents = 1,
994 .ops = &clk_branch2_ops,
995 },
996 },
997};
998
999static struct clk_branch camss_cci_cci_clk = {
1000 .halt_reg = 0x3344,
1001 .clkr = {
1002 .enable_reg = 0x3344,
1003 .enable_mask = BIT(0),
1004 .hw.init = &(struct clk_init_data){
1005 .name = "camss_cci_cci_clk",
1006 .parent_hws = (const struct clk_hw*[]){
1007 &cci_clk_src.clkr.hw
1008 },
1009 .num_parents = 1,
1010 .flags = CLK_SET_RATE_PARENT,
1011 .ops = &clk_branch2_ops,
1012 },
1013 },
1014};
1015
1016static struct clk_branch camss_csi0_ahb_clk = {
1017 .halt_reg = 0x30bc,
1018 .clkr = {
1019 .enable_reg = 0x30bc,
1020 .enable_mask = BIT(0),
1021 .hw.init = &(struct clk_init_data){
1022 .name = "camss_csi0_ahb_clk",
1023 .parent_hws = (const struct clk_hw*[]){
1024 &mmss_ahb_clk_src.clkr.hw
1025 },
1026 .num_parents = 1,
1027 .ops = &clk_branch2_ops,
1028 },
1029 },
1030};
1031
1032static struct clk_branch camss_csi0_clk = {
1033 .halt_reg = 0x30b4,
1034 .clkr = {
1035 .enable_reg = 0x30b4,
1036 .enable_mask = BIT(0),
1037 .hw.init = &(struct clk_init_data){
1038 .name = "camss_csi0_clk",
1039 .parent_hws = (const struct clk_hw*[]){
1040 &csi0_clk_src.clkr.hw
1041 },
1042 .num_parents = 1,
1043 .flags = CLK_SET_RATE_PARENT,
1044 .ops = &clk_branch2_ops,
1045 },
1046 },
1047};
1048
1049static struct clk_branch camss_csi0phy_clk = {
1050 .halt_reg = 0x30c4,
1051 .clkr = {
1052 .enable_reg = 0x30c4,
1053 .enable_mask = BIT(0),
1054 .hw.init = &(struct clk_init_data){
1055 .name = "camss_csi0phy_clk",
1056 .parent_hws = (const struct clk_hw*[]){
1057 &csi0_clk_src.clkr.hw
1058 },
1059 .num_parents = 1,
1060 .flags = CLK_SET_RATE_PARENT,
1061 .ops = &clk_branch2_ops,
1062 },
1063 },
1064};
1065
1066static struct clk_branch camss_csi0pix_clk = {
1067 .halt_reg = 0x30e4,
1068 .clkr = {
1069 .enable_reg = 0x30e4,
1070 .enable_mask = BIT(0),
1071 .hw.init = &(struct clk_init_data){
1072 .name = "camss_csi0pix_clk",
1073 .parent_hws = (const struct clk_hw*[]){
1074 &csi0_clk_src.clkr.hw
1075 },
1076 .num_parents = 1,
1077 .flags = CLK_SET_RATE_PARENT,
1078 .ops = &clk_branch2_ops,
1079 },
1080 },
1081};
1082
1083static struct clk_branch camss_csi0rdi_clk = {
1084 .halt_reg = 0x30d4,
1085 .clkr = {
1086 .enable_reg = 0x30d4,
1087 .enable_mask = BIT(0),
1088 .hw.init = &(struct clk_init_data){
1089 .name = "camss_csi0rdi_clk",
1090 .parent_hws = (const struct clk_hw*[]){
1091 &csi0_clk_src.clkr.hw
1092 },
1093 .num_parents = 1,
1094 .flags = CLK_SET_RATE_PARENT,
1095 .ops = &clk_branch2_ops,
1096 },
1097 },
1098};
1099
1100static struct clk_branch camss_csi1_ahb_clk = {
1101 .halt_reg = 0x3128,
1102 .clkr = {
1103 .enable_reg = 0x3128,
1104 .enable_mask = BIT(0),
1105 .hw.init = &(struct clk_init_data){
1106 .name = "camss_csi1_ahb_clk",
1107 .parent_hws = (const struct clk_hw*[]){
1108 &mmss_ahb_clk_src.clkr.hw
1109 },
1110 .num_parents = 1,
1111 .ops = &clk_branch2_ops,
1112 },
1113 },
1114};
1115
1116static struct clk_branch camss_csi1_clk = {
1117 .halt_reg = 0x3124,
1118 .clkr = {
1119 .enable_reg = 0x3124,
1120 .enable_mask = BIT(0),
1121 .hw.init = &(struct clk_init_data){
1122 .name = "camss_csi1_clk",
1123 .parent_hws = (const struct clk_hw*[]){
1124 &csi1_clk_src.clkr.hw
1125 },
1126 .num_parents = 1,
1127 .flags = CLK_SET_RATE_PARENT,
1128 .ops = &clk_branch2_ops,
1129 },
1130 },
1131};
1132
1133static struct clk_branch camss_csi1phy_clk = {
1134 .halt_reg = 0x3134,
1135 .clkr = {
1136 .enable_reg = 0x3134,
1137 .enable_mask = BIT(0),
1138 .hw.init = &(struct clk_init_data){
1139 .name = "camss_csi1phy_clk",
1140 .parent_hws = (const struct clk_hw*[]){
1141 &csi1_clk_src.clkr.hw
1142 },
1143 .num_parents = 1,
1144 .flags = CLK_SET_RATE_PARENT,
1145 .ops = &clk_branch2_ops,
1146 },
1147 },
1148};
1149
1150static struct clk_branch camss_csi1pix_clk = {
1151 .halt_reg = 0x3154,
1152 .clkr = {
1153 .enable_reg = 0x3154,
1154 .enable_mask = BIT(0),
1155 .hw.init = &(struct clk_init_data){
1156 .name = "camss_csi1pix_clk",
1157 .parent_hws = (const struct clk_hw*[]){
1158 &csi1_clk_src.clkr.hw
1159 },
1160 .num_parents = 1,
1161 .flags = CLK_SET_RATE_PARENT,
1162 .ops = &clk_branch2_ops,
1163 },
1164 },
1165};
1166
1167static struct clk_branch camss_csi1rdi_clk = {
1168 .halt_reg = 0x3144,
1169 .clkr = {
1170 .enable_reg = 0x3144,
1171 .enable_mask = BIT(0),
1172 .hw.init = &(struct clk_init_data){
1173 .name = "camss_csi1rdi_clk",
1174 .parent_hws = (const struct clk_hw*[]){
1175 &csi1_clk_src.clkr.hw
1176 },
1177 .num_parents = 1,
1178 .flags = CLK_SET_RATE_PARENT,
1179 .ops = &clk_branch2_ops,
1180 },
1181 },
1182};
1183
1184static struct clk_branch camss_csi2_ahb_clk = {
1185 .halt_reg = 0x3188,
1186 .clkr = {
1187 .enable_reg = 0x3188,
1188 .enable_mask = BIT(0),
1189 .hw.init = &(struct clk_init_data){
1190 .name = "camss_csi2_ahb_clk",
1191 .parent_hws = (const struct clk_hw*[]){
1192 &mmss_ahb_clk_src.clkr.hw
1193 },
1194 .num_parents = 1,
1195 .ops = &clk_branch2_ops,
1196 },
1197 },
1198};
1199
1200static struct clk_branch camss_csi2_clk = {
1201 .halt_reg = 0x3184,
1202 .clkr = {
1203 .enable_reg = 0x3184,
1204 .enable_mask = BIT(0),
1205 .hw.init = &(struct clk_init_data){
1206 .name = "camss_csi2_clk",
1207 .parent_hws = (const struct clk_hw*[]){
1208 &csi2_clk_src.clkr.hw
1209 },
1210 .num_parents = 1,
1211 .flags = CLK_SET_RATE_PARENT,
1212 .ops = &clk_branch2_ops,
1213 },
1214 },
1215};
1216
1217static struct clk_branch camss_csi2phy_clk = {
1218 .halt_reg = 0x3194,
1219 .clkr = {
1220 .enable_reg = 0x3194,
1221 .enable_mask = BIT(0),
1222 .hw.init = &(struct clk_init_data){
1223 .name = "camss_csi2phy_clk",
1224 .parent_hws = (const struct clk_hw*[]){
1225 &csi2_clk_src.clkr.hw
1226 },
1227 .num_parents = 1,
1228 .flags = CLK_SET_RATE_PARENT,
1229 .ops = &clk_branch2_ops,
1230 },
1231 },
1232};
1233
1234static struct clk_branch camss_csi2pix_clk = {
1235 .halt_reg = 0x31b4,
1236 .clkr = {
1237 .enable_reg = 0x31b4,
1238 .enable_mask = BIT(0),
1239 .hw.init = &(struct clk_init_data){
1240 .name = "camss_csi2pix_clk",
1241 .parent_hws = (const struct clk_hw*[]){
1242 &csi2_clk_src.clkr.hw
1243 },
1244 .num_parents = 1,
1245 .flags = CLK_SET_RATE_PARENT,
1246 .ops = &clk_branch2_ops,
1247 },
1248 },
1249};
1250
1251static struct clk_branch camss_csi2rdi_clk = {
1252 .halt_reg = 0x31a4,
1253 .clkr = {
1254 .enable_reg = 0x31a4,
1255 .enable_mask = BIT(0),
1256 .hw.init = &(struct clk_init_data){
1257 .name = "camss_csi2rdi_clk",
1258 .parent_hws = (const struct clk_hw*[]){
1259 &csi2_clk_src.clkr.hw
1260 },
1261 .num_parents = 1,
1262 .flags = CLK_SET_RATE_PARENT,
1263 .ops = &clk_branch2_ops,
1264 },
1265 },
1266};
1267
1268static struct clk_branch camss_csi3_ahb_clk = {
1269 .halt_reg = 0x31e8,
1270 .clkr = {
1271 .enable_reg = 0x31e8,
1272 .enable_mask = BIT(0),
1273 .hw.init = &(struct clk_init_data){
1274 .name = "camss_csi3_ahb_clk",
1275 .parent_hws = (const struct clk_hw*[]){
1276 &mmss_ahb_clk_src.clkr.hw
1277 },
1278 .num_parents = 1,
1279 .ops = &clk_branch2_ops,
1280 },
1281 },
1282};
1283
1284static struct clk_branch camss_csi3_clk = {
1285 .halt_reg = 0x31e4,
1286 .clkr = {
1287 .enable_reg = 0x31e4,
1288 .enable_mask = BIT(0),
1289 .hw.init = &(struct clk_init_data){
1290 .name = "camss_csi3_clk",
1291 .parent_hws = (const struct clk_hw*[]){
1292 &csi3_clk_src.clkr.hw
1293 },
1294 .num_parents = 1,
1295 .flags = CLK_SET_RATE_PARENT,
1296 .ops = &clk_branch2_ops,
1297 },
1298 },
1299};
1300
1301static struct clk_branch camss_csi3phy_clk = {
1302 .halt_reg = 0x31f4,
1303 .clkr = {
1304 .enable_reg = 0x31f4,
1305 .enable_mask = BIT(0),
1306 .hw.init = &(struct clk_init_data){
1307 .name = "camss_csi3phy_clk",
1308 .parent_hws = (const struct clk_hw*[]){
1309 &csi3_clk_src.clkr.hw
1310 },
1311 .num_parents = 1,
1312 .flags = CLK_SET_RATE_PARENT,
1313 .ops = &clk_branch2_ops,
1314 },
1315 },
1316};
1317
1318static struct clk_branch camss_csi3pix_clk = {
1319 .halt_reg = 0x3214,
1320 .clkr = {
1321 .enable_reg = 0x3214,
1322 .enable_mask = BIT(0),
1323 .hw.init = &(struct clk_init_data){
1324 .name = "camss_csi3pix_clk",
1325 .parent_hws = (const struct clk_hw*[]){
1326 &csi3_clk_src.clkr.hw
1327 },
1328 .num_parents = 1,
1329 .flags = CLK_SET_RATE_PARENT,
1330 .ops = &clk_branch2_ops,
1331 },
1332 },
1333};
1334
1335static struct clk_branch camss_csi3rdi_clk = {
1336 .halt_reg = 0x3204,
1337 .clkr = {
1338 .enable_reg = 0x3204,
1339 .enable_mask = BIT(0),
1340 .hw.init = &(struct clk_init_data){
1341 .name = "camss_csi3rdi_clk",
1342 .parent_hws = (const struct clk_hw*[]){
1343 &csi3_clk_src.clkr.hw
1344 },
1345 .num_parents = 1,
1346 .flags = CLK_SET_RATE_PARENT,
1347 .ops = &clk_branch2_ops,
1348 },
1349 },
1350};
1351
1352static struct clk_branch camss_csi_vfe0_clk = {
1353 .halt_reg = 0x3704,
1354 .clkr = {
1355 .enable_reg = 0x3704,
1356 .enable_mask = BIT(0),
1357 .hw.init = &(struct clk_init_data){
1358 .name = "camss_csi_vfe0_clk",
1359 .parent_hws = (const struct clk_hw*[]){
1360 &vfe0_clk_src.clkr.hw
1361 },
1362 .num_parents = 1,
1363 .flags = CLK_SET_RATE_PARENT,
1364 .ops = &clk_branch2_ops,
1365 },
1366 },
1367};
1368
1369static struct clk_branch camss_csi_vfe1_clk = {
1370 .halt_reg = 0x3714,
1371 .clkr = {
1372 .enable_reg = 0x3714,
1373 .enable_mask = BIT(0),
1374 .hw.init = &(struct clk_init_data){
1375 .name = "camss_csi_vfe1_clk",
1376 .parent_hws = (const struct clk_hw*[]){
1377 &vfe1_clk_src.clkr.hw
1378 },
1379 .num_parents = 1,
1380 .flags = CLK_SET_RATE_PARENT,
1381 .ops = &clk_branch2_ops,
1382 },
1383 },
1384};
1385
1386static struct clk_branch camss_gp0_clk = {
1387 .halt_reg = 0x3444,
1388 .clkr = {
1389 .enable_reg = 0x3444,
1390 .enable_mask = BIT(0),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "camss_gp0_clk",
1393 .parent_hws = (const struct clk_hw*[]){
1394 &camss_gp0_clk_src.clkr.hw
1395 },
1396 .num_parents = 1,
1397 .flags = CLK_SET_RATE_PARENT,
1398 .ops = &clk_branch2_ops,
1399 },
1400 },
1401};
1402
1403static struct clk_branch camss_gp1_clk = {
1404 .halt_reg = 0x3474,
1405 .clkr = {
1406 .enable_reg = 0x3474,
1407 .enable_mask = BIT(0),
1408 .hw.init = &(struct clk_init_data){
1409 .name = "camss_gp1_clk",
1410 .parent_hws = (const struct clk_hw*[]){
1411 &camss_gp1_clk_src.clkr.hw
1412 },
1413 .num_parents = 1,
1414 .flags = CLK_SET_RATE_PARENT,
1415 .ops = &clk_branch2_ops,
1416 },
1417 },
1418};
1419
1420static struct clk_branch camss_ispif_ahb_clk = {
1421 .halt_reg = 0x3224,
1422 .clkr = {
1423 .enable_reg = 0x3224,
1424 .enable_mask = BIT(0),
1425 .hw.init = &(struct clk_init_data){
1426 .name = "camss_ispif_ahb_clk",
1427 .parent_hws = (const struct clk_hw*[]){
1428 &mmss_ahb_clk_src.clkr.hw
1429 },
1430 .num_parents = 1,
1431 .ops = &clk_branch2_ops,
1432 },
1433 },
1434};
1435
1436static struct clk_branch camss_jpeg_jpeg0_clk = {
1437 .halt_reg = 0x35a8,
1438 .clkr = {
1439 .enable_reg = 0x35a8,
1440 .enable_mask = BIT(0),
1441 .hw.init = &(struct clk_init_data){
1442 .name = "camss_jpeg_jpeg0_clk",
1443 .parent_hws = (const struct clk_hw*[]){
1444 &jpeg0_clk_src.clkr.hw
1445 },
1446 .num_parents = 1,
1447 .flags = CLK_SET_RATE_PARENT,
1448 .ops = &clk_branch2_ops,
1449 },
1450 },
1451};
1452
1453static struct clk_branch camss_jpeg_jpeg1_clk = {
1454 .halt_reg = 0x35ac,
1455 .clkr = {
1456 .enable_reg = 0x35ac,
1457 .enable_mask = BIT(0),
1458 .hw.init = &(struct clk_init_data){
1459 .name = "camss_jpeg_jpeg1_clk",
1460 .parent_hws = (const struct clk_hw*[]){
1461 &jpeg1_clk_src.clkr.hw
1462 },
1463 .num_parents = 1,
1464 .flags = CLK_SET_RATE_PARENT,
1465 .ops = &clk_branch2_ops,
1466 },
1467 },
1468};
1469
1470static struct clk_branch camss_jpeg_jpeg2_clk = {
1471 .halt_reg = 0x35b0,
1472 .clkr = {
1473 .enable_reg = 0x35b0,
1474 .enable_mask = BIT(0),
1475 .hw.init = &(struct clk_init_data){
1476 .name = "camss_jpeg_jpeg2_clk",
1477 .parent_hws = (const struct clk_hw*[]){
1478 &jpeg2_clk_src.clkr.hw
1479 },
1480 .num_parents = 1,
1481 .flags = CLK_SET_RATE_PARENT,
1482 .ops = &clk_branch2_ops,
1483 },
1484 },
1485};
1486
1487static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1488 .halt_reg = 0x35b4,
1489 .clkr = {
1490 .enable_reg = 0x35b4,
1491 .enable_mask = BIT(0),
1492 .hw.init = &(struct clk_init_data){
1493 .name = "camss_jpeg_jpeg_ahb_clk",
1494 .parent_hws = (const struct clk_hw*[]){
1495 &mmss_ahb_clk_src.clkr.hw
1496 },
1497 .num_parents = 1,
1498 .ops = &clk_branch2_ops,
1499 },
1500 },
1501};
1502
1503static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1504 .halt_reg = 0x35b8,
1505 .clkr = {
1506 .enable_reg = 0x35b8,
1507 .enable_mask = BIT(0),
1508 .hw.init = &(struct clk_init_data){
1509 .name = "camss_jpeg_jpeg_axi_clk",
1510 .parent_hws = (const struct clk_hw*[]){
1511 &mmss_axi_clk_src.clkr.hw
1512 },
1513 .num_parents = 1,
1514 .ops = &clk_branch2_ops,
1515 },
1516 },
1517};
1518
1519static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1520 .halt_reg = 0x35bc,
1521 .clkr = {
1522 .enable_reg = 0x35bc,
1523 .enable_mask = BIT(0),
1524 .hw.init = &(struct clk_init_data){
1525 .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1526 .parent_hws = (const struct clk_hw*[]){
1527 &ocmemnoc_clk_src.clkr.hw
1528 },
1529 .num_parents = 1,
1530 .flags = CLK_SET_RATE_PARENT,
1531 .ops = &clk_branch2_ops,
1532 },
1533 },
1534};
1535
1536static struct clk_branch camss_mclk0_clk = {
1537 .halt_reg = 0x3384,
1538 .clkr = {
1539 .enable_reg = 0x3384,
1540 .enable_mask = BIT(0),
1541 .hw.init = &(struct clk_init_data){
1542 .name = "camss_mclk0_clk",
1543 .parent_hws = (const struct clk_hw*[]){
1544 &mclk0_clk_src.clkr.hw
1545 },
1546 .num_parents = 1,
1547 .flags = CLK_SET_RATE_PARENT,
1548 .ops = &clk_branch2_ops,
1549 },
1550 },
1551};
1552
1553static struct clk_branch camss_mclk1_clk = {
1554 .halt_reg = 0x33b4,
1555 .clkr = {
1556 .enable_reg = 0x33b4,
1557 .enable_mask = BIT(0),
1558 .hw.init = &(struct clk_init_data){
1559 .name = "camss_mclk1_clk",
1560 .parent_hws = (const struct clk_hw*[]){
1561 &mclk1_clk_src.clkr.hw
1562 },
1563 .num_parents = 1,
1564 .flags = CLK_SET_RATE_PARENT,
1565 .ops = &clk_branch2_ops,
1566 },
1567 },
1568};
1569
1570static struct clk_branch camss_mclk2_clk = {
1571 .halt_reg = 0x33e4,
1572 .clkr = {
1573 .enable_reg = 0x33e4,
1574 .enable_mask = BIT(0),
1575 .hw.init = &(struct clk_init_data){
1576 .name = "camss_mclk2_clk",
1577 .parent_hws = (const struct clk_hw*[]){
1578 &mclk2_clk_src.clkr.hw
1579 },
1580 .num_parents = 1,
1581 .flags = CLK_SET_RATE_PARENT,
1582 .ops = &clk_branch2_ops,
1583 },
1584 },
1585};
1586
1587static struct clk_branch camss_mclk3_clk = {
1588 .halt_reg = 0x3414,
1589 .clkr = {
1590 .enable_reg = 0x3414,
1591 .enable_mask = BIT(0),
1592 .hw.init = &(struct clk_init_data){
1593 .name = "camss_mclk3_clk",
1594 .parent_hws = (const struct clk_hw*[]){
1595 &mclk3_clk_src.clkr.hw
1596 },
1597 .num_parents = 1,
1598 .flags = CLK_SET_RATE_PARENT,
1599 .ops = &clk_branch2_ops,
1600 },
1601 },
1602};
1603
1604static struct clk_branch camss_micro_ahb_clk = {
1605 .halt_reg = 0x3494,
1606 .clkr = {
1607 .enable_reg = 0x3494,
1608 .enable_mask = BIT(0),
1609 .hw.init = &(struct clk_init_data){
1610 .name = "camss_micro_ahb_clk",
1611 .parent_hws = (const struct clk_hw*[]){
1612 &mmss_ahb_clk_src.clkr.hw
1613 },
1614 .num_parents = 1,
1615 .ops = &clk_branch2_ops,
1616 },
1617 },
1618};
1619
1620static struct clk_branch camss_phy0_csi0phytimer_clk = {
1621 .halt_reg = 0x3024,
1622 .clkr = {
1623 .enable_reg = 0x3024,
1624 .enable_mask = BIT(0),
1625 .hw.init = &(struct clk_init_data){
1626 .name = "camss_phy0_csi0phytimer_clk",
1627 .parent_hws = (const struct clk_hw*[]){
1628 &csi0phytimer_clk_src.clkr.hw
1629 },
1630 .num_parents = 1,
1631 .flags = CLK_SET_RATE_PARENT,
1632 .ops = &clk_branch2_ops,
1633 },
1634 },
1635};
1636
1637static struct clk_branch camss_phy1_csi1phytimer_clk = {
1638 .halt_reg = 0x3054,
1639 .clkr = {
1640 .enable_reg = 0x3054,
1641 .enable_mask = BIT(0),
1642 .hw.init = &(struct clk_init_data){
1643 .name = "camss_phy1_csi1phytimer_clk",
1644 .parent_hws = (const struct clk_hw*[]){
1645 &csi1phytimer_clk_src.clkr.hw
1646 },
1647 .num_parents = 1,
1648 .flags = CLK_SET_RATE_PARENT,
1649 .ops = &clk_branch2_ops,
1650 },
1651 },
1652};
1653
1654static struct clk_branch camss_phy2_csi2phytimer_clk = {
1655 .halt_reg = 0x3084,
1656 .clkr = {
1657 .enable_reg = 0x3084,
1658 .enable_mask = BIT(0),
1659 .hw.init = &(struct clk_init_data){
1660 .name = "camss_phy2_csi2phytimer_clk",
1661 .parent_hws = (const struct clk_hw*[]){
1662 &csi2phytimer_clk_src.clkr.hw
1663 },
1664 .num_parents = 1,
1665 .flags = CLK_SET_RATE_PARENT,
1666 .ops = &clk_branch2_ops,
1667 },
1668 },
1669};
1670
1671static struct clk_branch camss_top_ahb_clk = {
1672 .halt_reg = 0x3484,
1673 .clkr = {
1674 .enable_reg = 0x3484,
1675 .enable_mask = BIT(0),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "camss_top_ahb_clk",
1678 .parent_hws = (const struct clk_hw*[]){
1679 &mmss_ahb_clk_src.clkr.hw
1680 },
1681 .num_parents = 1,
1682 .ops = &clk_branch2_ops,
1683 },
1684 },
1685};
1686
1687static struct clk_branch camss_vfe_cpp_ahb_clk = {
1688 .halt_reg = 0x36b4,
1689 .clkr = {
1690 .enable_reg = 0x36b4,
1691 .enable_mask = BIT(0),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "camss_vfe_cpp_ahb_clk",
1694 .parent_hws = (const struct clk_hw*[]){
1695 &mmss_ahb_clk_src.clkr.hw
1696 },
1697 .num_parents = 1,
1698 .ops = &clk_branch2_ops,
1699 },
1700 },
1701};
1702
1703static struct clk_branch camss_vfe_cpp_clk = {
1704 .halt_reg = 0x36b0,
1705 .clkr = {
1706 .enable_reg = 0x36b0,
1707 .enable_mask = BIT(0),
1708 .hw.init = &(struct clk_init_data){
1709 .name = "camss_vfe_cpp_clk",
1710 .parent_hws = (const struct clk_hw*[]){
1711 &cpp_clk_src.clkr.hw
1712 },
1713 .num_parents = 1,
1714 .flags = CLK_SET_RATE_PARENT,
1715 .ops = &clk_branch2_ops,
1716 },
1717 },
1718};
1719
1720static struct clk_branch camss_vfe_vfe0_clk = {
1721 .halt_reg = 0x36a8,
1722 .clkr = {
1723 .enable_reg = 0x36a8,
1724 .enable_mask = BIT(0),
1725 .hw.init = &(struct clk_init_data){
1726 .name = "camss_vfe_vfe0_clk",
1727 .parent_hws = (const struct clk_hw*[]){
1728 &vfe0_clk_src.clkr.hw
1729 },
1730 .num_parents = 1,
1731 .flags = CLK_SET_RATE_PARENT,
1732 .ops = &clk_branch2_ops,
1733 },
1734 },
1735};
1736
1737static struct clk_branch camss_vfe_vfe1_clk = {
1738 .halt_reg = 0x36ac,
1739 .clkr = {
1740 .enable_reg = 0x36ac,
1741 .enable_mask = BIT(0),
1742 .hw.init = &(struct clk_init_data){
1743 .name = "camss_vfe_vfe1_clk",
1744 .parent_hws = (const struct clk_hw*[]){
1745 &vfe1_clk_src.clkr.hw
1746 },
1747 .num_parents = 1,
1748 .flags = CLK_SET_RATE_PARENT,
1749 .ops = &clk_branch2_ops,
1750 },
1751 },
1752};
1753
1754static struct clk_branch camss_vfe_vfe_ahb_clk = {
1755 .halt_reg = 0x36b8,
1756 .clkr = {
1757 .enable_reg = 0x36b8,
1758 .enable_mask = BIT(0),
1759 .hw.init = &(struct clk_init_data){
1760 .name = "camss_vfe_vfe_ahb_clk",
1761 .parent_hws = (const struct clk_hw*[]){
1762 &mmss_ahb_clk_src.clkr.hw
1763 },
1764 .num_parents = 1,
1765 .ops = &clk_branch2_ops,
1766 },
1767 },
1768};
1769
1770static struct clk_branch camss_vfe_vfe_axi_clk = {
1771 .halt_reg = 0x36bc,
1772 .clkr = {
1773 .enable_reg = 0x36bc,
1774 .enable_mask = BIT(0),
1775 .hw.init = &(struct clk_init_data){
1776 .name = "camss_vfe_vfe_axi_clk",
1777 .parent_hws = (const struct clk_hw*[]){
1778 &mmss_axi_clk_src.clkr.hw
1779 },
1780 .num_parents = 1,
1781 .ops = &clk_branch2_ops,
1782 },
1783 },
1784};
1785
1786static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1787 .halt_reg = 0x36c0,
1788 .clkr = {
1789 .enable_reg = 0x36c0,
1790 .enable_mask = BIT(0),
1791 .hw.init = &(struct clk_init_data){
1792 .name = "camss_vfe_vfe_ocmemnoc_clk",
1793 .parent_hws = (const struct clk_hw*[]){
1794 &ocmemnoc_clk_src.clkr.hw
1795 },
1796 .num_parents = 1,
1797 .flags = CLK_SET_RATE_PARENT,
1798 .ops = &clk_branch2_ops,
1799 },
1800 },
1801};
1802
1803static struct clk_branch mdss_ahb_clk = {
1804 .halt_reg = 0x2308,
1805 .clkr = {
1806 .enable_reg = 0x2308,
1807 .enable_mask = BIT(0),
1808 .hw.init = &(struct clk_init_data){
1809 .name = "mdss_ahb_clk",
1810 .parent_hws = (const struct clk_hw*[]){
1811 &mmss_ahb_clk_src.clkr.hw
1812 },
1813 .num_parents = 1,
1814 .ops = &clk_branch2_ops,
1815 },
1816 },
1817};
1818
1819static struct clk_branch mdss_axi_clk = {
1820 .halt_reg = 0x2310,
1821 .clkr = {
1822 .enable_reg = 0x2310,
1823 .enable_mask = BIT(0),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "mdss_axi_clk",
1826 .parent_hws = (const struct clk_hw*[]){
1827 &mmss_axi_clk_src.clkr.hw
1828 },
1829 .num_parents = 1,
1830 .flags = CLK_SET_RATE_PARENT,
1831 .ops = &clk_branch2_ops,
1832 },
1833 },
1834};
1835
1836static struct clk_branch mdss_byte0_clk = {
1837 .halt_reg = 0x233c,
1838 .clkr = {
1839 .enable_reg = 0x233c,
1840 .enable_mask = BIT(0),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "mdss_byte0_clk",
1843 .parent_hws = (const struct clk_hw*[]){
1844 &byte0_clk_src.clkr.hw
1845 },
1846 .num_parents = 1,
1847 .flags = CLK_SET_RATE_PARENT,
1848 .ops = &clk_branch2_ops,
1849 },
1850 },
1851};
1852
1853static struct clk_branch mdss_byte1_clk = {
1854 .halt_reg = 0x2340,
1855 .clkr = {
1856 .enable_reg = 0x2340,
1857 .enable_mask = BIT(0),
1858 .hw.init = &(struct clk_init_data){
1859 .name = "mdss_byte1_clk",
1860 .parent_hws = (const struct clk_hw*[]){
1861 &byte1_clk_src.clkr.hw
1862 },
1863 .num_parents = 1,
1864 .flags = CLK_SET_RATE_PARENT,
1865 .ops = &clk_branch2_ops,
1866 },
1867 },
1868};
1869
1870static struct clk_branch mdss_edpaux_clk = {
1871 .halt_reg = 0x2334,
1872 .clkr = {
1873 .enable_reg = 0x2334,
1874 .enable_mask = BIT(0),
1875 .hw.init = &(struct clk_init_data){
1876 .name = "mdss_edpaux_clk",
1877 .parent_hws = (const struct clk_hw*[]){
1878 &edpaux_clk_src.clkr.hw
1879 },
1880 .num_parents = 1,
1881 .flags = CLK_SET_RATE_PARENT,
1882 .ops = &clk_branch2_ops,
1883 },
1884 },
1885};
1886
1887static struct clk_branch mdss_edplink_clk = {
1888 .halt_reg = 0x2330,
1889 .clkr = {
1890 .enable_reg = 0x2330,
1891 .enable_mask = BIT(0),
1892 .hw.init = &(struct clk_init_data){
1893 .name = "mdss_edplink_clk",
1894 .parent_hws = (const struct clk_hw*[]){
1895 &edplink_clk_src.clkr.hw
1896 },
1897 .num_parents = 1,
1898 .flags = CLK_SET_RATE_PARENT,
1899 .ops = &clk_branch2_ops,
1900 },
1901 },
1902};
1903
1904static struct clk_branch mdss_edppixel_clk = {
1905 .halt_reg = 0x232c,
1906 .clkr = {
1907 .enable_reg = 0x232c,
1908 .enable_mask = BIT(0),
1909 .hw.init = &(struct clk_init_data){
1910 .name = "mdss_edppixel_clk",
1911 .parent_hws = (const struct clk_hw*[]){
1912 &edppixel_clk_src.clkr.hw
1913 },
1914 .num_parents = 1,
1915 .flags = CLK_SET_RATE_PARENT,
1916 .ops = &clk_branch2_ops,
1917 },
1918 },
1919};
1920
1921static struct clk_branch mdss_esc0_clk = {
1922 .halt_reg = 0x2344,
1923 .clkr = {
1924 .enable_reg = 0x2344,
1925 .enable_mask = BIT(0),
1926 .hw.init = &(struct clk_init_data){
1927 .name = "mdss_esc0_clk",
1928 .parent_hws = (const struct clk_hw*[]){
1929 &esc0_clk_src.clkr.hw
1930 },
1931 .num_parents = 1,
1932 .flags = CLK_SET_RATE_PARENT,
1933 .ops = &clk_branch2_ops,
1934 },
1935 },
1936};
1937
1938static struct clk_branch mdss_esc1_clk = {
1939 .halt_reg = 0x2348,
1940 .clkr = {
1941 .enable_reg = 0x2348,
1942 .enable_mask = BIT(0),
1943 .hw.init = &(struct clk_init_data){
1944 .name = "mdss_esc1_clk",
1945 .parent_hws = (const struct clk_hw*[]){
1946 &esc1_clk_src.clkr.hw
1947 },
1948 .num_parents = 1,
1949 .flags = CLK_SET_RATE_PARENT,
1950 .ops = &clk_branch2_ops,
1951 },
1952 },
1953};
1954
1955static struct clk_branch mdss_extpclk_clk = {
1956 .halt_reg = 0x2324,
1957 .clkr = {
1958 .enable_reg = 0x2324,
1959 .enable_mask = BIT(0),
1960 .hw.init = &(struct clk_init_data){
1961 .name = "mdss_extpclk_clk",
1962 .parent_hws = (const struct clk_hw*[]){
1963 &extpclk_clk_src.clkr.hw
1964 },
1965 .num_parents = 1,
1966 .flags = CLK_SET_RATE_PARENT,
1967 .ops = &clk_branch2_ops,
1968 },
1969 },
1970};
1971
1972static struct clk_branch mdss_hdmi_ahb_clk = {
1973 .halt_reg = 0x230c,
1974 .clkr = {
1975 .enable_reg = 0x230c,
1976 .enable_mask = BIT(0),
1977 .hw.init = &(struct clk_init_data){
1978 .name = "mdss_hdmi_ahb_clk",
1979 .parent_hws = (const struct clk_hw*[]){
1980 &mmss_ahb_clk_src.clkr.hw
1981 },
1982 .num_parents = 1,
1983 .ops = &clk_branch2_ops,
1984 },
1985 },
1986};
1987
1988static struct clk_branch mdss_hdmi_clk = {
1989 .halt_reg = 0x2338,
1990 .clkr = {
1991 .enable_reg = 0x2338,
1992 .enable_mask = BIT(0),
1993 .hw.init = &(struct clk_init_data){
1994 .name = "mdss_hdmi_clk",
1995 .parent_hws = (const struct clk_hw*[]){
1996 &hdmi_clk_src.clkr.hw
1997 },
1998 .num_parents = 1,
1999 .flags = CLK_SET_RATE_PARENT,
2000 .ops = &clk_branch2_ops,
2001 },
2002 },
2003};
2004
2005static struct clk_branch mdss_mdp_clk = {
2006 .halt_reg = 0x231c,
2007 .clkr = {
2008 .enable_reg = 0x231c,
2009 .enable_mask = BIT(0),
2010 .hw.init = &(struct clk_init_data){
2011 .name = "mdss_mdp_clk",
2012 .parent_hws = (const struct clk_hw*[]){
2013 &mdp_clk_src.clkr.hw
2014 },
2015 .num_parents = 1,
2016 .flags = CLK_SET_RATE_PARENT,
2017 .ops = &clk_branch2_ops,
2018 },
2019 },
2020};
2021
2022static struct clk_branch mdss_mdp_lut_clk = {
2023 .halt_reg = 0x2320,
2024 .clkr = {
2025 .enable_reg = 0x2320,
2026 .enable_mask = BIT(0),
2027 .hw.init = &(struct clk_init_data){
2028 .name = "mdss_mdp_lut_clk",
2029 .parent_hws = (const struct clk_hw*[]){
2030 &mdp_clk_src.clkr.hw
2031 },
2032 .num_parents = 1,
2033 .flags = CLK_SET_RATE_PARENT,
2034 .ops = &clk_branch2_ops,
2035 },
2036 },
2037};
2038
2039static struct clk_branch mdss_pclk0_clk = {
2040 .halt_reg = 0x2314,
2041 .clkr = {
2042 .enable_reg = 0x2314,
2043 .enable_mask = BIT(0),
2044 .hw.init = &(struct clk_init_data){
2045 .name = "mdss_pclk0_clk",
2046 .parent_hws = (const struct clk_hw*[]){
2047 &pclk0_clk_src.clkr.hw
2048 },
2049 .num_parents = 1,
2050 .flags = CLK_SET_RATE_PARENT,
2051 .ops = &clk_branch2_ops,
2052 },
2053 },
2054};
2055
2056static struct clk_branch mdss_pclk1_clk = {
2057 .halt_reg = 0x2318,
2058 .clkr = {
2059 .enable_reg = 0x2318,
2060 .enable_mask = BIT(0),
2061 .hw.init = &(struct clk_init_data){
2062 .name = "mdss_pclk1_clk",
2063 .parent_hws = (const struct clk_hw*[]){
2064 &pclk1_clk_src.clkr.hw
2065 },
2066 .num_parents = 1,
2067 .flags = CLK_SET_RATE_PARENT,
2068 .ops = &clk_branch2_ops,
2069 },
2070 },
2071};
2072
2073static struct clk_branch mdss_vsync_clk = {
2074 .halt_reg = 0x2328,
2075 .clkr = {
2076 .enable_reg = 0x2328,
2077 .enable_mask = BIT(0),
2078 .hw.init = &(struct clk_init_data){
2079 .name = "mdss_vsync_clk",
2080 .parent_hws = (const struct clk_hw*[]){
2081 &vsync_clk_src.clkr.hw
2082 },
2083 .num_parents = 1,
2084 .flags = CLK_SET_RATE_PARENT,
2085 .ops = &clk_branch2_ops,
2086 },
2087 },
2088};
2089
2090static struct clk_branch mmss_misc_ahb_clk = {
2091 .halt_reg = 0x502c,
2092 .clkr = {
2093 .enable_reg = 0x502c,
2094 .enable_mask = BIT(0),
2095 .hw.init = &(struct clk_init_data){
2096 .name = "mmss_misc_ahb_clk",
2097 .parent_hws = (const struct clk_hw*[]){
2098 &mmss_ahb_clk_src.clkr.hw
2099 },
2100 .num_parents = 1,
2101 .ops = &clk_branch2_ops,
2102 },
2103 },
2104};
2105
2106static struct clk_branch mmss_mmssnoc_ahb_clk = {
2107 .halt_reg = 0x5024,
2108 .clkr = {
2109 .enable_reg = 0x5024,
2110 .enable_mask = BIT(0),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "mmss_mmssnoc_ahb_clk",
2113 .parent_hws = (const struct clk_hw*[]){
2114 &mmss_ahb_clk_src.clkr.hw
2115 },
2116 .num_parents = 1,
2117 .ops = &clk_branch2_ops,
2118 .flags = CLK_IGNORE_UNUSED,
2119 },
2120 },
2121};
2122
2123static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2124 .halt_reg = 0x5028,
2125 .clkr = {
2126 .enable_reg = 0x5028,
2127 .enable_mask = BIT(0),
2128 .hw.init = &(struct clk_init_data){
2129 .name = "mmss_mmssnoc_bto_ahb_clk",
2130 .parent_hws = (const struct clk_hw*[]){
2131 &mmss_ahb_clk_src.clkr.hw
2132 },
2133 .num_parents = 1,
2134 .ops = &clk_branch2_ops,
2135 .flags = CLK_IGNORE_UNUSED,
2136 },
2137 },
2138};
2139
2140static struct clk_branch mmss_mmssnoc_axi_clk = {
2141 .halt_reg = 0x506c,
2142 .clkr = {
2143 .enable_reg = 0x506c,
2144 .enable_mask = BIT(0),
2145 .hw.init = &(struct clk_init_data){
2146 .name = "mmss_mmssnoc_axi_clk",
2147 .parent_hws = (const struct clk_hw*[]){
2148 &mmss_axi_clk_src.clkr.hw
2149 },
2150 .num_parents = 1,
2151 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2152 .ops = &clk_branch2_ops,
2153 },
2154 },
2155};
2156
2157static struct clk_branch mmss_s0_axi_clk = {
2158 .halt_reg = 0x5064,
2159 .clkr = {
2160 .enable_reg = 0x5064,
2161 .enable_mask = BIT(0),
2162 .hw.init = &(struct clk_init_data){
2163 .name = "mmss_s0_axi_clk",
2164 .parent_hws = (const struct clk_hw*[]){
2165 &mmss_axi_clk_src.clkr.hw
2166 },
2167 .num_parents = 1,
2168 .ops = &clk_branch2_ops,
2169 .flags = CLK_IGNORE_UNUSED,
2170 },
2171 },
2172};
2173
2174static struct clk_branch ocmemcx_ahb_clk = {
2175 .halt_reg = 0x405c,
2176 .clkr = {
2177 .enable_reg = 0x405c,
2178 .enable_mask = BIT(0),
2179 .hw.init = &(struct clk_init_data){
2180 .name = "ocmemcx_ahb_clk",
2181 .parent_hws = (const struct clk_hw*[]){
2182 &mmss_ahb_clk_src.clkr.hw
2183 },
2184 .num_parents = 1,
2185 .ops = &clk_branch2_ops,
2186 },
2187 },
2188};
2189
2190static struct clk_branch ocmemcx_ocmemnoc_clk = {
2191 .halt_reg = 0x4058,
2192 .clkr = {
2193 .enable_reg = 0x4058,
2194 .enable_mask = BIT(0),
2195 .hw.init = &(struct clk_init_data){
2196 .name = "ocmemcx_ocmemnoc_clk",
2197 .parent_hws = (const struct clk_hw*[]){
2198 &ocmemnoc_clk_src.clkr.hw
2199 },
2200 .num_parents = 1,
2201 .flags = CLK_SET_RATE_PARENT,
2202 .ops = &clk_branch2_ops,
2203 },
2204 },
2205};
2206
2207static struct clk_branch oxili_ocmemgx_clk = {
2208 .halt_reg = 0x402c,
2209 .clkr = {
2210 .enable_reg = 0x402c,
2211 .enable_mask = BIT(0),
2212 .hw.init = &(struct clk_init_data){
2213 .name = "oxili_ocmemgx_clk",
2214 .parent_data = (const struct clk_parent_data[]){
2215 { .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
2216 },
2217 .num_parents = 1,
2218 .flags = CLK_SET_RATE_PARENT,
2219 .ops = &clk_branch2_ops,
2220 },
2221 },
2222};
2223
2224static struct clk_branch ocmemnoc_clk = {
2225 .halt_reg = 0x50b4,
2226 .clkr = {
2227 .enable_reg = 0x50b4,
2228 .enable_mask = BIT(0),
2229 .hw.init = &(struct clk_init_data){
2230 .name = "ocmemnoc_clk",
2231 .parent_hws = (const struct clk_hw*[]){
2232 &ocmemnoc_clk_src.clkr.hw
2233 },
2234 .num_parents = 1,
2235 .flags = CLK_SET_RATE_PARENT,
2236 .ops = &clk_branch2_ops,
2237 },
2238 },
2239};
2240
2241static struct clk_branch oxili_gfx3d_clk = {
2242 .halt_reg = 0x4028,
2243 .clkr = {
2244 .enable_reg = 0x4028,
2245 .enable_mask = BIT(0),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "oxili_gfx3d_clk",
2248 .parent_data = (const struct clk_parent_data[]){
2249 { .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
2250 },
2251 .num_parents = 1,
2252 .flags = CLK_SET_RATE_PARENT,
2253 .ops = &clk_branch2_ops,
2254 },
2255 },
2256};
2257
2258static struct clk_branch oxilicx_ahb_clk = {
2259 .halt_reg = 0x403c,
2260 .clkr = {
2261 .enable_reg = 0x403c,
2262 .enable_mask = BIT(0),
2263 .hw.init = &(struct clk_init_data){
2264 .name = "oxilicx_ahb_clk",
2265 .parent_hws = (const struct clk_hw*[]){
2266 &mmss_ahb_clk_src.clkr.hw
2267 },
2268 .num_parents = 1,
2269 .ops = &clk_branch2_ops,
2270 },
2271 },
2272};
2273
2274static struct clk_branch oxilicx_axi_clk = {
2275 .halt_reg = 0x4038,
2276 .clkr = {
2277 .enable_reg = 0x4038,
2278 .enable_mask = BIT(0),
2279 .hw.init = &(struct clk_init_data){
2280 .name = "oxilicx_axi_clk",
2281 .parent_hws = (const struct clk_hw*[]){
2282 &mmss_axi_clk_src.clkr.hw
2283 },
2284 .num_parents = 1,
2285 .ops = &clk_branch2_ops,
2286 },
2287 },
2288};
2289
2290static struct clk_branch venus0_ahb_clk = {
2291 .halt_reg = 0x1030,
2292 .clkr = {
2293 .enable_reg = 0x1030,
2294 .enable_mask = BIT(0),
2295 .hw.init = &(struct clk_init_data){
2296 .name = "venus0_ahb_clk",
2297 .parent_hws = (const struct clk_hw*[]){
2298 &mmss_ahb_clk_src.clkr.hw
2299 },
2300 .num_parents = 1,
2301 .ops = &clk_branch2_ops,
2302 },
2303 },
2304};
2305
2306static struct clk_branch venus0_axi_clk = {
2307 .halt_reg = 0x1034,
2308 .clkr = {
2309 .enable_reg = 0x1034,
2310 .enable_mask = BIT(0),
2311 .hw.init = &(struct clk_init_data){
2312 .name = "venus0_axi_clk",
2313 .parent_hws = (const struct clk_hw*[]){
2314 &mmss_axi_clk_src.clkr.hw
2315 },
2316 .num_parents = 1,
2317 .ops = &clk_branch2_ops,
2318 },
2319 },
2320};
2321
2322static struct clk_branch venus0_ocmemnoc_clk = {
2323 .halt_reg = 0x1038,
2324 .clkr = {
2325 .enable_reg = 0x1038,
2326 .enable_mask = BIT(0),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "venus0_ocmemnoc_clk",
2329 .parent_hws = (const struct clk_hw*[]){
2330 &ocmemnoc_clk_src.clkr.hw
2331 },
2332 .num_parents = 1,
2333 .flags = CLK_SET_RATE_PARENT,
2334 .ops = &clk_branch2_ops,
2335 },
2336 },
2337};
2338
2339static struct clk_branch venus0_vcodec0_clk = {
2340 .halt_reg = 0x1028,
2341 .clkr = {
2342 .enable_reg = 0x1028,
2343 .enable_mask = BIT(0),
2344 .hw.init = &(struct clk_init_data){
2345 .name = "venus0_vcodec0_clk",
2346 .parent_hws = (const struct clk_hw*[]){
2347 &vcodec0_clk_src.clkr.hw
2348 },
2349 .num_parents = 1,
2350 .flags = CLK_SET_RATE_PARENT,
2351 .ops = &clk_branch2_ops,
2352 },
2353 },
2354};
2355
2356static const struct pll_config mmpll1_config = {
2357 .l = 60,
2358 .m = 25,
2359 .n = 32,
2360 .vco_val = 0x0,
2361 .vco_mask = 0x3 << 20,
2362 .pre_div_val = 0x0,
2363 .pre_div_mask = 0x7 << 12,
2364 .post_div_val = 0x0,
2365 .post_div_mask = 0x3 << 8,
2366 .mn_ena_mask = BIT(24),
2367 .main_output_mask = BIT(0),
2368};
2369
2370static struct pll_config mmpll3_config = {
2371 .l = 48,
2372 .m = 7,
2373 .n = 16,
2374 .vco_val = 0x0,
2375 .vco_mask = 0x3 << 20,
2376 .pre_div_val = 0x0,
2377 .pre_div_mask = 0x7 << 12,
2378 .post_div_val = 0x0,
2379 .post_div_mask = 0x3 << 8,
2380 .mn_ena_mask = BIT(24),
2381 .main_output_mask = BIT(0),
2382 .aux_output_mask = BIT(1),
2383};
2384
2385static struct gdsc venus0_gdsc = {
2386 .gdscr = 0x1024,
2387 .cxcs = (unsigned int []){ 0x1028 },
2388 .cxc_count = 1,
2389 .resets = (unsigned int []){ VENUS0_RESET },
2390 .reset_count = 1,
2391 .pd = {
2392 .name = "venus0",
2393 },
2394 .pwrsts = PWRSTS_ON,
2395};
2396
2397static struct gdsc mdss_gdsc = {
2398 .gdscr = 0x2304,
2399 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2400 .cxc_count = 2,
2401 .pd = {
2402 .name = "mdss",
2403 },
2404 .pwrsts = PWRSTS_RET_ON,
2405};
2406
2407static struct gdsc camss_jpeg_gdsc = {
2408 .gdscr = 0x35a4,
2409 .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2410 .cxc_count = 3,
2411 .pd = {
2412 .name = "camss_jpeg",
2413 },
2414 .pwrsts = PWRSTS_OFF_ON,
2415};
2416
2417static struct gdsc camss_vfe_gdsc = {
2418 .gdscr = 0x36a4,
2419 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2420 .cxc_count = 5,
2421 .pd = {
2422 .name = "camss_vfe",
2423 },
2424 .pwrsts = PWRSTS_OFF_ON,
2425};
2426
2427static struct gdsc oxili_gdsc = {
2428 .gdscr = 0x4024,
2429 .cxcs = (unsigned int []){ 0x4028 },
2430 .cxc_count = 1,
2431 .pd = {
2432 .name = "oxili",
2433 },
2434 .pwrsts = PWRSTS_OFF_ON,
2435};
2436
2437static struct gdsc oxilicx_gdsc = {
2438 .gdscr = 0x4034,
2439 .pd = {
2440 .name = "oxilicx",
2441 },
2442 .parent = &oxili_gdsc.pd,
2443 .pwrsts = PWRSTS_OFF_ON,
2444};
2445
2446static struct clk_regmap *mmcc_msm8226_clocks[] = {
2447 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2448 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2449 [MMPLL0] = &mmpll0.clkr,
2450 [MMPLL0_VOTE] = &mmpll0_vote,
2451 [MMPLL1] = &mmpll1.clkr,
2452 [MMPLL1_VOTE] = &mmpll1_vote,
2453 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2454 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2455 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2456 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2457 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2458 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2459 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2460 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2461 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2462 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2463 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2464 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2465 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2466 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2467 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2468 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2469 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2470 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2471 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2472 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2473 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2474 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2475 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2476 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2477 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2478 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2479 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2480 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2481 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2482 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2483 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2484 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2485 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2486 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2487 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2488 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2489 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2490 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2491 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2492 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2493 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2494 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2495 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2496 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2497 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2498 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2499 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2500 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2501 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2502 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2503 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2504 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2505 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2506 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2507 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2508 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2509 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2510 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2511 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2512 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2513 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2514 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2515 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2516 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2517 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2518 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2519 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2520 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2521 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2522};
2523
2524static const struct qcom_reset_map mmcc_msm8226_resets[] = {
2525 [SPDM_RESET] = { 0x0200 },
2526 [SPDM_RM_RESET] = { 0x0300 },
2527 [VENUS0_RESET] = { 0x1020 },
2528 [MDSS_RESET] = { 0x2300 },
2529};
2530
2531static struct gdsc *mmcc_msm8226_gdscs[] = {
2532 [VENUS0_GDSC] = &venus0_gdsc,
2533 [MDSS_GDSC] = &mdss_gdsc,
2534 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2535 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2536};
2537
2538static const struct regmap_config mmcc_msm8226_regmap_config = {
2539 .reg_bits = 32,
2540 .reg_stride = 4,
2541 .val_bits = 32,
2542 .max_register = 0x5104,
2543 .fast_io = true,
2544};
2545
2546static const struct qcom_cc_desc mmcc_msm8226_desc = {
2547 .config = &mmcc_msm8226_regmap_config,
2548 .clks = mmcc_msm8226_clocks,
2549 .num_clks = ARRAY_SIZE(mmcc_msm8226_clocks),
2550 .resets = mmcc_msm8226_resets,
2551 .num_resets = ARRAY_SIZE(mmcc_msm8226_resets),
2552 .gdscs = mmcc_msm8226_gdscs,
2553 .num_gdscs = ARRAY_SIZE(mmcc_msm8226_gdscs),
2554};
2555
2556static struct clk_regmap *mmcc_msm8974_clocks[] = {
2557 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2558 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2559 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2560 [MMPLL0] = &mmpll0.clkr,
2561 [MMPLL0_VOTE] = &mmpll0_vote,
2562 [MMPLL1] = &mmpll1.clkr,
2563 [MMPLL1_VOTE] = &mmpll1_vote,
2564 [MMPLL2] = &mmpll2.clkr,
2565 [MMPLL3] = &mmpll3.clkr,
2566 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2567 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2568 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2569 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2570 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2571 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2572 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2573 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2574 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2575 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2576 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2577 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2578 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2579 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2580 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2581 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2582 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2583 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2584 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2585 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2586 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2587 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2588 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2589 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2590 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2591 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2592 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2593 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2594 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2595 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2596 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2597 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2598 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2599 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2600 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2601 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2602 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2603 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2604 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2605 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2606 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2607 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2608 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2609 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2610 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2611 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2612 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2613 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2614 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2615 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2616 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2617 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2618 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2619 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2620 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2621 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2622 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2623 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2624 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2625 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2626 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2627 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2628 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2629 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2630 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2631 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2632 [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2633 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2634 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2635 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2636 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2637 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2638 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2639 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2640 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2641 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2642 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2643 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2644 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2645 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2646 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2647 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2648 [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2649 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2650 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2651 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2652 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2653 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2654 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2655 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2656 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2657 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2658 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2659 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2660 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2661 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2662 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2663 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2664 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2665 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2666 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2667 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2668 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2669 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2670 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2671 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2672 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2673 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2674 [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2675 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2676 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2677 [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2678 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2679 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2680 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2681 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2682};
2683
2684static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2685 [SPDM_RESET] = { 0x0200 },
2686 [SPDM_RM_RESET] = { 0x0300 },
2687 [VENUS0_RESET] = { 0x1020 },
2688 [MDSS_RESET] = { 0x2300 },
2689 [CAMSS_PHY0_RESET] = { 0x3020 },
2690 [CAMSS_PHY1_RESET] = { 0x3050 },
2691 [CAMSS_PHY2_RESET] = { 0x3080 },
2692 [CAMSS_CSI0_RESET] = { 0x30b0 },
2693 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2694 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2695 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2696 [CAMSS_CSI1_RESET] = { 0x3120 },
2697 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2698 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2699 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2700 [CAMSS_CSI2_RESET] = { 0x3180 },
2701 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2702 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2703 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2704 [CAMSS_CSI3_RESET] = { 0x31e0 },
2705 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2706 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2707 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2708 [CAMSS_ISPIF_RESET] = { 0x3220 },
2709 [CAMSS_CCI_RESET] = { 0x3340 },
2710 [CAMSS_MCLK0_RESET] = { 0x3380 },
2711 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2712 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2713 [CAMSS_MCLK3_RESET] = { 0x3410 },
2714 [CAMSS_GP0_RESET] = { 0x3440 },
2715 [CAMSS_GP1_RESET] = { 0x3470 },
2716 [CAMSS_TOP_RESET] = { 0x3480 },
2717 [CAMSS_MICRO_RESET] = { 0x3490 },
2718 [CAMSS_JPEG_RESET] = { 0x35a0 },
2719 [CAMSS_VFE_RESET] = { 0x36a0 },
2720 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2721 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2722 [OXILI_RESET] = { 0x4020 },
2723 [OXILICX_RESET] = { 0x4030 },
2724 [OCMEMCX_RESET] = { 0x4050 },
2725 [MMSS_RBCRP_RESET] = { 0x4080 },
2726 [MMSSNOCAHB_RESET] = { 0x5020 },
2727 [MMSSNOCAXI_RESET] = { 0x5060 },
2728 [OCMEMNOC_RESET] = { 0x50b0 },
2729};
2730
2731static struct gdsc *mmcc_msm8974_gdscs[] = {
2732 [VENUS0_GDSC] = &venus0_gdsc,
2733 [MDSS_GDSC] = &mdss_gdsc,
2734 [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2735 [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2736 [OXILI_GDSC] = &oxili_gdsc,
2737 [OXILICX_GDSC] = &oxilicx_gdsc,
2738};
2739
2740static const struct regmap_config mmcc_msm8974_regmap_config = {
2741 .reg_bits = 32,
2742 .reg_stride = 4,
2743 .val_bits = 32,
2744 .max_register = 0x5104,
2745 .fast_io = true,
2746};
2747
2748static const struct qcom_cc_desc mmcc_msm8974_desc = {
2749 .config = &mmcc_msm8974_regmap_config,
2750 .clks = mmcc_msm8974_clocks,
2751 .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2752 .resets = mmcc_msm8974_resets,
2753 .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2754 .gdscs = mmcc_msm8974_gdscs,
2755 .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
2756};
2757
2758static const struct of_device_id mmcc_msm8974_match_table[] = {
2759 { .compatible = "qcom,mmcc-msm8226", .data = &mmcc_msm8226_desc },
2760 { .compatible = "qcom,mmcc-msm8974", .data = &mmcc_msm8974_desc },
2761 { }
2762};
2763MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2764
2765static void msm8226_clock_override(void)
2766{
2767 mmss_axi_clk_src.freq_tbl = ftbl_mmss_axi_clk_msm8226;
2768 vfe0_clk_src.freq_tbl = ftbl_camss_vfe_vfe0_clk_msm8226;
2769 mdp_clk_src.freq_tbl = ftbl_mdss_mdp_clk_msm8226;
2770 vcodec0_clk_src.freq_tbl = ftbl_venus0_vcodec0_clk_msm8226;
2771 mclk0_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
2772 mclk1_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
2773 cpp_clk_src.freq_tbl = ftbl_camss_vfe_cpp_clk_msm8226;
2774}
2775
2776static int mmcc_msm8974_probe(struct platform_device *pdev)
2777{
2778 struct regmap *regmap;
2779 const struct qcom_cc_desc *desc;
2780
2781 desc = of_device_get_match_data(&pdev->dev);
2782 if (!desc)
2783 return -EINVAL;
2784
2785 regmap = qcom_cc_map(pdev, desc);
2786 if (IS_ERR(regmap))
2787 return PTR_ERR(regmap);
2788
2789 if (desc == &mmcc_msm8974_desc) {
2790 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2791 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2792 } else {
2793 msm8226_clock_override();
2794 }
2795
2796 return qcom_cc_really_probe(pdev, desc, regmap);
2797}
2798
2799static struct platform_driver mmcc_msm8974_driver = {
2800 .probe = mmcc_msm8974_probe,
2801 .driver = {
2802 .name = "mmcc-msm8974",
2803 .of_match_table = mmcc_msm8974_match_table,
2804 },
2805};
2806module_platform_driver(mmcc_msm8974_driver);
2807
2808MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2809MODULE_LICENSE("GPL v2");
2810MODULE_ALIAS("platform:mmcc-msm8974");