Loading...
Note: File does not exist in v3.5.6.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PLL clock driver for TI Davinci SoCs
4 *
5 * Copyright (C) 2018 David Lechner <david@lechnology.com>
6 *
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/clk.h>
14#include <linux/clk/davinci.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/mfd/syscon.h>
20#include <linux/notifier.h>
21#include <linux/of.h>
22#include <linux/platform_data/clk-davinci-pll.h>
23#include <linux/platform_device.h>
24#include <linux/property.h>
25#include <linux/regmap.h>
26#include <linux/slab.h>
27#include <linux/types.h>
28
29#include "pll.h"
30
31#define MAX_NAME_SIZE 20
32#define OSCIN_CLK_NAME "oscin"
33
34#define REVID 0x000
35#define PLLCTL 0x100
36#define OCSEL 0x104
37#define PLLSECCTL 0x108
38#define PLLM 0x110
39#define PREDIV 0x114
40#define PLLDIV1 0x118
41#define PLLDIV2 0x11c
42#define PLLDIV3 0x120
43#define OSCDIV 0x124
44#define POSTDIV 0x128
45#define BPDIV 0x12c
46#define PLLCMD 0x138
47#define PLLSTAT 0x13c
48#define ALNCTL 0x140
49#define DCHANGE 0x144
50#define CKEN 0x148
51#define CKSTAT 0x14c
52#define SYSTAT 0x150
53#define PLLDIV4 0x160
54#define PLLDIV5 0x164
55#define PLLDIV6 0x168
56#define PLLDIV7 0x16c
57#define PLLDIV8 0x170
58#define PLLDIV9 0x174
59
60#define PLLCTL_PLLEN BIT(0)
61#define PLLCTL_PLLPWRDN BIT(1)
62#define PLLCTL_PLLRST BIT(3)
63#define PLLCTL_PLLDIS BIT(4)
64#define PLLCTL_PLLENSRC BIT(5)
65#define PLLCTL_CLKMODE BIT(8)
66
67/* shared by most *DIV registers */
68#define DIV_RATIO_SHIFT 0
69#define DIV_RATIO_WIDTH 5
70#define DIV_ENABLE_SHIFT 15
71
72#define PLLCMD_GOSET BIT(0)
73#define PLLSTAT_GOSTAT BIT(0)
74
75#define CKEN_OBSCLK_SHIFT 1
76#define CKEN_AUXEN_SHIFT 0
77
78/*
79 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
80 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
81 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
82 * is ~25MHz. Units are micro seconds.
83 */
84#define PLL_BYPASS_TIME 1
85
86/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
87#define PLL_RESET_TIME 1
88
89/*
90 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
91 * Units are micro seconds.
92 */
93#define PLL_LOCK_TIME 20
94
95/**
96 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
97 * @hw: clk_hw for the pll
98 * @base: Base memory address
99 * @pllm_min: The minimum allowable PLLM[PLLM] value
100 * @pllm_max: The maximum allowable PLLM[PLLM] value
101 * @pllm_mask: Bitmask for PLLM[PLLM] value
102 */
103struct davinci_pll_clk {
104 struct clk_hw hw;
105 void __iomem *base;
106 u32 pllm_min;
107 u32 pllm_max;
108 u32 pllm_mask;
109};
110
111#define to_davinci_pll_clk(_hw) \
112 container_of((_hw), struct davinci_pll_clk, hw)
113
114static unsigned long davinci_pll_recalc_rate(struct clk_hw *hw,
115 unsigned long parent_rate)
116{
117 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
118 unsigned long rate = parent_rate;
119 u32 mult;
120
121 mult = readl(pll->base + PLLM) & pll->pllm_mask;
122 rate *= mult + 1;
123
124 return rate;
125}
126
127static int davinci_pll_determine_rate(struct clk_hw *hw,
128 struct clk_rate_request *req)
129{
130 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
131 struct clk_hw *parent = req->best_parent_hw;
132 unsigned long parent_rate = req->best_parent_rate;
133 unsigned long rate = req->rate;
134 unsigned long best_rate, r;
135 u32 mult;
136
137 /* there is a limited range of valid outputs (see datasheet) */
138 if (rate < req->min_rate)
139 return -EINVAL;
140
141 rate = min(rate, req->max_rate);
142 mult = rate / parent_rate;
143 best_rate = parent_rate * mult;
144
145 /* easy case when there is no PREDIV */
146 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
147 if (best_rate < req->min_rate)
148 return -EINVAL;
149
150 if (mult < pll->pllm_min || mult > pll->pllm_max)
151 return -EINVAL;
152
153 req->rate = best_rate;
154
155 return 0;
156 }
157
158 /* see if the PREDIV clock can help us */
159 best_rate = 0;
160
161 for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) {
162 parent_rate = clk_hw_round_rate(parent, rate / mult);
163 r = parent_rate * mult;
164 if (r < req->min_rate)
165 continue;
166 if (r > rate || r > req->max_rate)
167 break;
168 if (r > best_rate) {
169 best_rate = r;
170 req->rate = best_rate;
171 req->best_parent_rate = parent_rate;
172 if (best_rate == rate)
173 break;
174 }
175 }
176
177 return 0;
178}
179
180static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate,
181 unsigned long parent_rate)
182{
183 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
184 u32 mult;
185
186 mult = rate / parent_rate;
187 writel(mult - 1, pll->base + PLLM);
188
189 return 0;
190}
191
192#ifdef CONFIG_DEBUG_FS
193static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry);
194#else
195#define davinci_pll_debug_init NULL
196#endif
197
198static const struct clk_ops davinci_pll_ops = {
199 .recalc_rate = davinci_pll_recalc_rate,
200 .determine_rate = davinci_pll_determine_rate,
201 .set_rate = davinci_pll_set_rate,
202 .debug_init = davinci_pll_debug_init,
203};
204
205/* PLLM works differently on DM365 */
206static unsigned long dm365_pll_recalc_rate(struct clk_hw *hw,
207 unsigned long parent_rate)
208{
209 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
210 unsigned long rate = parent_rate;
211 u32 mult;
212
213 mult = readl(pll->base + PLLM) & pll->pllm_mask;
214 rate *= mult * 2;
215
216 return rate;
217}
218
219static const struct clk_ops dm365_pll_ops = {
220 .recalc_rate = dm365_pll_recalc_rate,
221 .debug_init = davinci_pll_debug_init,
222};
223
224/**
225 * davinci_pll_div_register - common *DIV clock implementation
226 * @dev: The PLL platform device or NULL
227 * @name: the clock name
228 * @parent_name: the parent clock name
229 * @reg: the *DIV register
230 * @fixed: if true, the divider is a fixed value
231 * @flags: bitmap of CLK_* flags from clock-provider.h
232 */
233static struct clk *davinci_pll_div_register(struct device *dev,
234 const char *name,
235 const char *parent_name,
236 void __iomem *reg,
237 bool fixed, u32 flags)
238{
239 const char * const *parent_names = parent_name ? &parent_name : NULL;
240 int num_parents = parent_name ? 1 : 0;
241 const struct clk_ops *divider_ops = &clk_divider_ops;
242 struct clk_gate *gate;
243 struct clk_divider *divider;
244 struct clk *clk;
245 int ret;
246
247 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
248 if (!gate)
249 return ERR_PTR(-ENOMEM);
250
251 gate->reg = reg;
252 gate->bit_idx = DIV_ENABLE_SHIFT;
253
254 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
255 if (!divider) {
256 ret = -ENOMEM;
257 goto err_free_gate;
258 }
259
260 divider->reg = reg;
261 divider->shift = DIV_RATIO_SHIFT;
262 divider->width = DIV_RATIO_WIDTH;
263
264 if (fixed) {
265 divider->flags |= CLK_DIVIDER_READ_ONLY;
266 divider_ops = &clk_divider_ro_ops;
267 }
268
269 clk = clk_register_composite(dev, name, parent_names, num_parents,
270 NULL, NULL, ÷r->hw, divider_ops,
271 &gate->hw, &clk_gate_ops, flags);
272 if (IS_ERR(clk)) {
273 ret = PTR_ERR(clk);
274 goto err_free_divider;
275 }
276
277 return clk;
278
279err_free_divider:
280 kfree(divider);
281err_free_gate:
282 kfree(gate);
283
284 return ERR_PTR(ret);
285}
286
287struct davinci_pllen_clk {
288 struct clk_hw hw;
289 void __iomem *base;
290};
291
292#define to_davinci_pllen_clk(_hw) \
293 container_of((_hw), struct davinci_pllen_clk, hw)
294
295static const struct clk_ops davinci_pllen_ops = {
296 /* this clocks just uses the clock notification feature */
297};
298
299/*
300 * The PLL has to be switched into bypass mode while we are chaning the rate,
301 * so we do that on the PLLEN clock since it is the end of the line. This will
302 * switch to bypass before any of the parent clocks (PREDIV, PLL, POSTDIV) are
303 * changed and will switch back to the PLL after the changes have been made.
304 */
305static int davinci_pllen_rate_change(struct notifier_block *nb,
306 unsigned long flags, void *data)
307{
308 struct clk_notifier_data *cnd = data;
309 struct clk_hw *hw = __clk_get_hw(cnd->clk);
310 struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
311 u32 ctrl;
312
313 ctrl = readl(pll->base + PLLCTL);
314
315 if (flags == PRE_RATE_CHANGE) {
316 /* Switch the PLL to bypass mode */
317 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
318 writel(ctrl, pll->base + PLLCTL);
319
320 udelay(PLL_BYPASS_TIME);
321
322 /* Reset and enable PLL */
323 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
324 writel(ctrl, pll->base + PLLCTL);
325 } else {
326 udelay(PLL_RESET_TIME);
327
328 /* Bring PLL out of reset */
329 ctrl |= PLLCTL_PLLRST;
330 writel(ctrl, pll->base + PLLCTL);
331
332 udelay(PLL_LOCK_TIME);
333
334 /* Remove PLL from bypass mode */
335 ctrl |= PLLCTL_PLLEN;
336 writel(ctrl, pll->base + PLLCTL);
337 }
338
339 return NOTIFY_OK;
340}
341
342static struct notifier_block davinci_pllen_notifier = {
343 .notifier_call = davinci_pllen_rate_change,
344};
345
346/**
347 * davinci_pll_clk_register - Register a PLL clock
348 * @dev: The PLL platform device or NULL
349 * @info: The device-specific clock info
350 * @parent_name: The parent clock name
351 * @base: The PLL's memory region
352 * @cfgchip: CFGCHIP syscon regmap for info->unlock_reg or NULL
353 *
354 * This creates a series of clocks that represent the PLL.
355 *
356 * OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN
357 *
358 * - OSCIN is the parent clock (on secondary PLL, may come from primary PLL)
359 * - PREDIV and POSTDIV are optional (depends on the PLL controller)
360 * - PLL is the PLL output (aka PLLOUT)
361 * - PLLEN is the bypass multiplexer
362 *
363 * Returns: The PLLOUT clock or a negative error code.
364 */
365struct clk *davinci_pll_clk_register(struct device *dev,
366 const struct davinci_pll_clk_info *info,
367 const char *parent_name,
368 void __iomem *base,
369 struct regmap *cfgchip)
370{
371 char prediv_name[MAX_NAME_SIZE];
372 char pllout_name[MAX_NAME_SIZE];
373 char postdiv_name[MAX_NAME_SIZE];
374 char pllen_name[MAX_NAME_SIZE];
375 struct clk_init_data init;
376 struct davinci_pll_clk *pllout;
377 struct davinci_pllen_clk *pllen;
378 struct clk *oscin_clk = NULL;
379 struct clk *prediv_clk = NULL;
380 struct clk *pllout_clk;
381 struct clk *postdiv_clk = NULL;
382 struct clk *pllen_clk;
383 int ret;
384
385 if (info->flags & PLL_HAS_CLKMODE) {
386 /*
387 * If a PLL has PLLCTL[CLKMODE], then it is the primary PLL.
388 * We register a clock named "oscin" that serves as the internal
389 * "input clock" domain shared by both PLLs (if there are 2)
390 * and will be the parent clock to the AUXCLK, SYSCLKBP and
391 * OBSCLK domains. NB: The various TRMs use "OSCIN" to mean
392 * a number of different things. In this driver we use it to
393 * mean the signal after the PLLCTL[CLKMODE] switch.
394 */
395 oscin_clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME,
396 parent_name, 0, 1, 1);
397 if (IS_ERR(oscin_clk))
398 return oscin_clk;
399
400 parent_name = OSCIN_CLK_NAME;
401 }
402
403 if (info->flags & PLL_HAS_PREDIV) {
404 bool fixed = info->flags & PLL_PREDIV_FIXED_DIV;
405 u32 flags = 0;
406
407 snprintf(prediv_name, MAX_NAME_SIZE, "%s_prediv", info->name);
408
409 if (info->flags & PLL_PREDIV_ALWAYS_ENABLED)
410 flags |= CLK_IS_CRITICAL;
411
412 /* Some? DM355 chips don't correctly report the PREDIV value */
413 if (info->flags & PLL_PREDIV_FIXED8)
414 prediv_clk = clk_register_fixed_factor(dev, prediv_name,
415 parent_name, flags, 1, 8);
416 else
417 prediv_clk = davinci_pll_div_register(dev, prediv_name,
418 parent_name, base + PREDIV, fixed, flags);
419 if (IS_ERR(prediv_clk)) {
420 ret = PTR_ERR(prediv_clk);
421 goto err_unregister_oscin;
422 }
423
424 parent_name = prediv_name;
425 }
426
427 /* Unlock writing to PLL registers */
428 if (info->unlock_reg) {
429 if (IS_ERR_OR_NULL(cfgchip))
430 dev_warn(dev, "Failed to get CFGCHIP (%ld)\n",
431 PTR_ERR(cfgchip));
432 else
433 regmap_write_bits(cfgchip, info->unlock_reg,
434 info->unlock_mask, 0);
435 }
436
437 pllout = kzalloc(sizeof(*pllout), GFP_KERNEL);
438 if (!pllout) {
439 ret = -ENOMEM;
440 goto err_unregister_prediv;
441 }
442
443 snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name);
444
445 init.name = pllout_name;
446 if (info->flags & PLL_PLLM_2X)
447 init.ops = &dm365_pll_ops;
448 else
449 init.ops = &davinci_pll_ops;
450 init.parent_names = &parent_name;
451 init.num_parents = 1;
452 init.flags = 0;
453
454 if (info->flags & PLL_HAS_PREDIV)
455 init.flags |= CLK_SET_RATE_PARENT;
456
457 pllout->hw.init = &init;
458 pllout->base = base;
459 pllout->pllm_mask = info->pllm_mask;
460 pllout->pllm_min = info->pllm_min;
461 pllout->pllm_max = info->pllm_max;
462
463 pllout_clk = clk_register(dev, &pllout->hw);
464 if (IS_ERR(pllout_clk)) {
465 ret = PTR_ERR(pllout_clk);
466 goto err_free_pllout;
467 }
468
469 clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate,
470 info->pllout_max_rate);
471
472 parent_name = pllout_name;
473
474 if (info->flags & PLL_HAS_POSTDIV) {
475 bool fixed = info->flags & PLL_POSTDIV_FIXED_DIV;
476 u32 flags = CLK_SET_RATE_PARENT;
477
478 snprintf(postdiv_name, MAX_NAME_SIZE, "%s_postdiv", info->name);
479
480 if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED)
481 flags |= CLK_IS_CRITICAL;
482
483 postdiv_clk = davinci_pll_div_register(dev, postdiv_name,
484 parent_name, base + POSTDIV, fixed, flags);
485 if (IS_ERR(postdiv_clk)) {
486 ret = PTR_ERR(postdiv_clk);
487 goto err_unregister_pllout;
488 }
489
490 parent_name = postdiv_name;
491 }
492
493 pllen = kzalloc(sizeof(*pllen), GFP_KERNEL);
494 if (!pllen) {
495 ret = -ENOMEM;
496 goto err_unregister_postdiv;
497 }
498
499 snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name);
500
501 init.name = pllen_name;
502 init.ops = &davinci_pllen_ops;
503 init.parent_names = &parent_name;
504 init.num_parents = 1;
505 init.flags = CLK_SET_RATE_PARENT;
506
507 pllen->hw.init = &init;
508 pllen->base = base;
509
510 pllen_clk = clk_register(dev, &pllen->hw);
511 if (IS_ERR(pllen_clk)) {
512 ret = PTR_ERR(pllen_clk);
513 goto err_free_pllen;
514 }
515
516 clk_notifier_register(pllen_clk, &davinci_pllen_notifier);
517
518 return pllout_clk;
519
520err_free_pllen:
521 kfree(pllen);
522err_unregister_postdiv:
523 clk_unregister(postdiv_clk);
524err_unregister_pllout:
525 clk_unregister(pllout_clk);
526err_free_pllout:
527 kfree(pllout);
528err_unregister_prediv:
529 clk_unregister(prediv_clk);
530err_unregister_oscin:
531 clk_unregister(oscin_clk);
532
533 return ERR_PTR(ret);
534}
535
536/**
537 * davinci_pll_auxclk_register - Register bypass clock (AUXCLK)
538 * @dev: The PLL platform device or NULL
539 * @name: The clock name
540 * @base: The PLL memory region
541 */
542struct clk *davinci_pll_auxclk_register(struct device *dev,
543 const char *name,
544 void __iomem *base)
545{
546 return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN,
547 CKEN_AUXEN_SHIFT, 0, NULL);
548}
549
550/**
551 * davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP)
552 * @dev: The PLL platform device or NULL
553 * @name: The clock name
554 * @base: The PLL memory region
555 */
556struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
557 const char *name,
558 void __iomem *base)
559{
560 return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV,
561 DIV_RATIO_SHIFT, DIV_RATIO_WIDTH,
562 CLK_DIVIDER_READ_ONLY, NULL);
563}
564
565/**
566 * davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK)
567 * @dev: The PLL platform device or NULL
568 * @info: The clock info
569 * @base: The PLL memory region
570 */
571struct clk *
572davinci_pll_obsclk_register(struct device *dev,
573 const struct davinci_pll_obsclk_info *info,
574 void __iomem *base)
575{
576 struct clk_mux *mux;
577 struct clk_gate *gate;
578 struct clk_divider *divider;
579 struct clk *clk;
580 u32 oscdiv;
581 int ret;
582
583 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
584 if (!mux)
585 return ERR_PTR(-ENOMEM);
586
587 mux->reg = base + OCSEL;
588 mux->table = info->table;
589 mux->mask = info->ocsrc_mask;
590
591 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
592 if (!gate) {
593 ret = -ENOMEM;
594 goto err_free_mux;
595 }
596
597 gate->reg = base + CKEN;
598 gate->bit_idx = CKEN_OBSCLK_SHIFT;
599
600 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
601 if (!divider) {
602 ret = -ENOMEM;
603 goto err_free_gate;
604 }
605
606 divider->reg = base + OSCDIV;
607 divider->shift = DIV_RATIO_SHIFT;
608 divider->width = DIV_RATIO_WIDTH;
609
610 /* make sure divider is enabled just in case bootloader disabled it */
611 oscdiv = readl(base + OSCDIV);
612 oscdiv |= BIT(DIV_ENABLE_SHIFT);
613 writel(oscdiv, base + OSCDIV);
614
615 clk = clk_register_composite(dev, info->name, info->parent_names,
616 info->num_parents,
617 &mux->hw, &clk_mux_ops,
618 ÷r->hw, &clk_divider_ops,
619 &gate->hw, &clk_gate_ops, 0);
620
621 if (IS_ERR(clk)) {
622 ret = PTR_ERR(clk);
623 goto err_free_divider;
624 }
625
626 return clk;
627
628err_free_divider:
629 kfree(divider);
630err_free_gate:
631 kfree(gate);
632err_free_mux:
633 kfree(mux);
634
635 return ERR_PTR(ret);
636}
637
638/* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */
639static int davinci_pll_sysclk_rate_change(struct notifier_block *nb,
640 unsigned long flags, void *data)
641{
642 struct clk_notifier_data *cnd = data;
643 struct clk_hw *hw = __clk_get_hw(clk_get_parent(cnd->clk));
644 struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
645 u32 pllcmd, pllstat;
646
647 switch (flags) {
648 case POST_RATE_CHANGE:
649 /* apply the changes */
650 pllcmd = readl(pll->base + PLLCMD);
651 pllcmd |= PLLCMD_GOSET;
652 writel(pllcmd, pll->base + PLLCMD);
653 fallthrough;
654 case PRE_RATE_CHANGE:
655 /* Wait until for outstanding changes to take effect */
656 do {
657 pllstat = readl(pll->base + PLLSTAT);
658 } while (pllstat & PLLSTAT_GOSTAT);
659 break;
660 }
661
662 return NOTIFY_OK;
663}
664
665static struct notifier_block davinci_pll_sysclk_notifier = {
666 .notifier_call = davinci_pll_sysclk_rate_change,
667};
668
669/**
670 * davinci_pll_sysclk_register - Register divider clocks (SYSCLKn)
671 * @dev: The PLL platform device or NULL
672 * @info: The clock info
673 * @base: The PLL memory region
674 */
675struct clk *
676davinci_pll_sysclk_register(struct device *dev,
677 const struct davinci_pll_sysclk_info *info,
678 void __iomem *base)
679{
680 const struct clk_ops *divider_ops = &clk_divider_ops;
681 struct clk_gate *gate;
682 struct clk_divider *divider;
683 struct clk *clk;
684 u32 reg;
685 u32 flags = 0;
686 int ret;
687
688 /* PLLDIVn registers are not entirely consecutive */
689 if (info->id < 4)
690 reg = PLLDIV1 + 4 * (info->id - 1);
691 else
692 reg = PLLDIV4 + 4 * (info->id - 4);
693
694 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
695 if (!gate)
696 return ERR_PTR(-ENOMEM);
697
698 gate->reg = base + reg;
699 gate->bit_idx = DIV_ENABLE_SHIFT;
700
701 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
702 if (!divider) {
703 ret = -ENOMEM;
704 goto err_free_gate;
705 }
706
707 divider->reg = base + reg;
708 divider->shift = DIV_RATIO_SHIFT;
709 divider->width = info->ratio_width;
710 divider->flags = 0;
711
712 if (info->flags & SYSCLK_FIXED_DIV) {
713 divider->flags |= CLK_DIVIDER_READ_ONLY;
714 divider_ops = &clk_divider_ro_ops;
715 }
716
717 /* Only the ARM clock can change the parent PLL rate */
718 if (info->flags & SYSCLK_ARM_RATE)
719 flags |= CLK_SET_RATE_PARENT;
720
721 if (info->flags & SYSCLK_ALWAYS_ENABLED)
722 flags |= CLK_IS_CRITICAL;
723
724 clk = clk_register_composite(dev, info->name, &info->parent_name, 1,
725 NULL, NULL, ÷r->hw, divider_ops,
726 &gate->hw, &clk_gate_ops, flags);
727 if (IS_ERR(clk)) {
728 ret = PTR_ERR(clk);
729 goto err_free_divider;
730 }
731
732 clk_notifier_register(clk, &davinci_pll_sysclk_notifier);
733
734 return clk;
735
736err_free_divider:
737 kfree(divider);
738err_free_gate:
739 kfree(gate);
740
741 return ERR_PTR(ret);
742}
743
744int of_davinci_pll_init(struct device *dev, struct device_node *node,
745 const struct davinci_pll_clk_info *info,
746 const struct davinci_pll_obsclk_info *obsclk_info,
747 const struct davinci_pll_sysclk_info **div_info,
748 u8 max_sysclk_id,
749 void __iomem *base,
750 struct regmap *cfgchip)
751{
752 struct device_node *child;
753 const char *parent_name;
754 struct clk *clk;
755
756 if (info->flags & PLL_HAS_CLKMODE)
757 parent_name = of_clk_get_parent_name(node, 0);
758 else
759 parent_name = OSCIN_CLK_NAME;
760
761 clk = davinci_pll_clk_register(dev, info, parent_name, base, cfgchip);
762 if (IS_ERR(clk)) {
763 dev_err(dev, "failed to register %s\n", info->name);
764 return PTR_ERR(clk);
765 }
766
767 child = of_get_child_by_name(node, "pllout");
768 if (of_device_is_available(child))
769 of_clk_add_provider(child, of_clk_src_simple_get, clk);
770 of_node_put(child);
771
772 child = of_get_child_by_name(node, "sysclk");
773 if (of_device_is_available(child)) {
774 struct clk_onecell_data *clk_data;
775 struct clk **clks;
776 int n_clks = max_sysclk_id + 1;
777 int i;
778
779 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
780 if (!clk_data) {
781 of_node_put(child);
782 return -ENOMEM;
783 }
784
785 clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL);
786 if (!clks) {
787 kfree(clk_data);
788 of_node_put(child);
789 return -ENOMEM;
790 }
791
792 clk_data->clks = clks;
793 clk_data->clk_num = n_clks;
794
795 for (i = 0; i < n_clks; i++)
796 clks[i] = ERR_PTR(-ENOENT);
797
798 for (; *div_info; div_info++) {
799 clk = davinci_pll_sysclk_register(dev, *div_info, base);
800 if (IS_ERR(clk))
801 dev_warn(dev, "failed to register %s (%ld)\n",
802 (*div_info)->name, PTR_ERR(clk));
803 else
804 clks[(*div_info)->id] = clk;
805 }
806 of_clk_add_provider(child, of_clk_src_onecell_get, clk_data);
807 }
808 of_node_put(child);
809
810 child = of_get_child_by_name(node, "auxclk");
811 if (of_device_is_available(child)) {
812 char child_name[MAX_NAME_SIZE];
813
814 snprintf(child_name, MAX_NAME_SIZE, "%s_auxclk", info->name);
815
816 clk = davinci_pll_auxclk_register(dev, child_name, base);
817 if (IS_ERR(clk))
818 dev_warn(dev, "failed to register %s (%ld)\n",
819 child_name, PTR_ERR(clk));
820 else
821 of_clk_add_provider(child, of_clk_src_simple_get, clk);
822 }
823 of_node_put(child);
824
825 child = of_get_child_by_name(node, "obsclk");
826 if (of_device_is_available(child)) {
827 if (obsclk_info)
828 clk = davinci_pll_obsclk_register(dev, obsclk_info, base);
829 else
830 clk = ERR_PTR(-EINVAL);
831
832 if (IS_ERR(clk))
833 dev_warn(dev, "failed to register obsclk (%ld)\n",
834 PTR_ERR(clk));
835 else
836 of_clk_add_provider(child, of_clk_src_simple_get, clk);
837 }
838 of_node_put(child);
839
840 return 0;
841}
842
843static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev)
844{
845 struct davinci_pll_platform_data *pdata = dev_get_platdata(dev);
846
847 /*
848 * Platform data is optional, so allocate a new struct if one was not
849 * provided. For device tree, this will always be the case.
850 */
851 if (!pdata)
852 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
853 if (!pdata)
854 return NULL;
855
856 /* for device tree, we need to fill in the struct */
857 if (dev->of_node)
858 pdata->cfgchip =
859 syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
860
861 return pdata;
862}
863
864/* needed in early boot for clocksource/clockevent */
865#ifdef CONFIG_ARCH_DAVINCI_DA850
866CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init);
867#endif
868
869static const struct of_device_id davinci_pll_of_match[] = {
870#ifdef CONFIG_ARCH_DAVINCI_DA850
871 { .compatible = "ti,da850-pll1", .data = of_da850_pll1_init },
872#endif
873 { }
874};
875
876static const struct platform_device_id davinci_pll_id_table[] = {
877#ifdef CONFIG_ARCH_DAVINCI_DA830
878 { .name = "da830-pll", .driver_data = (kernel_ulong_t)da830_pll_init },
879#endif
880#ifdef CONFIG_ARCH_DAVINCI_DA850
881 { .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init },
882 { .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init },
883#endif
884 { }
885};
886
887typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base,
888 struct regmap *cfgchip);
889
890static int davinci_pll_probe(struct platform_device *pdev)
891{
892 struct device *dev = &pdev->dev;
893 struct davinci_pll_platform_data *pdata;
894 davinci_pll_init pll_init = NULL;
895 void __iomem *base;
896
897 pll_init = device_get_match_data(dev);
898 if (!pll_init && pdev->id_entry)
899 pll_init = (void *)pdev->id_entry->driver_data;
900
901 if (!pll_init) {
902 dev_err(dev, "unable to find driver data\n");
903 return -EINVAL;
904 }
905
906 pdata = davinci_pll_get_pdata(dev);
907 if (!pdata) {
908 dev_err(dev, "missing platform data\n");
909 return -EINVAL;
910 }
911
912 base = devm_platform_ioremap_resource(pdev, 0);
913 if (IS_ERR(base))
914 return PTR_ERR(base);
915
916 return pll_init(dev, base, pdata->cfgchip);
917}
918
919static struct platform_driver davinci_pll_driver = {
920 .probe = davinci_pll_probe,
921 .driver = {
922 .name = "davinci-pll-clk",
923 .of_match_table = davinci_pll_of_match,
924 },
925 .id_table = davinci_pll_id_table,
926};
927
928static int __init davinci_pll_driver_init(void)
929{
930 return platform_driver_register(&davinci_pll_driver);
931}
932
933/* has to be postcore_initcall because PSC devices depend on PLL parent clocks */
934postcore_initcall(davinci_pll_driver_init);
935
936#ifdef CONFIG_DEBUG_FS
937#include <linux/debugfs.h>
938
939#define DEBUG_REG(n) \
940{ \
941 .name = #n, \
942 .offset = n, \
943}
944
945static const struct debugfs_reg32 davinci_pll_regs[] = {
946 DEBUG_REG(REVID),
947 DEBUG_REG(PLLCTL),
948 DEBUG_REG(OCSEL),
949 DEBUG_REG(PLLSECCTL),
950 DEBUG_REG(PLLM),
951 DEBUG_REG(PREDIV),
952 DEBUG_REG(PLLDIV1),
953 DEBUG_REG(PLLDIV2),
954 DEBUG_REG(PLLDIV3),
955 DEBUG_REG(OSCDIV),
956 DEBUG_REG(POSTDIV),
957 DEBUG_REG(BPDIV),
958 DEBUG_REG(PLLCMD),
959 DEBUG_REG(PLLSTAT),
960 DEBUG_REG(ALNCTL),
961 DEBUG_REG(DCHANGE),
962 DEBUG_REG(CKEN),
963 DEBUG_REG(CKSTAT),
964 DEBUG_REG(SYSTAT),
965 DEBUG_REG(PLLDIV4),
966 DEBUG_REG(PLLDIV5),
967 DEBUG_REG(PLLDIV6),
968 DEBUG_REG(PLLDIV7),
969 DEBUG_REG(PLLDIV8),
970 DEBUG_REG(PLLDIV9),
971};
972
973static void davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
974{
975 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
976 struct debugfs_regset32 *regset;
977
978 regset = kzalloc(sizeof(*regset), GFP_KERNEL);
979 if (!regset)
980 return;
981
982 regset->regs = davinci_pll_regs;
983 regset->nregs = ARRAY_SIZE(davinci_pll_regs);
984 regset->base = pll->base;
985
986 debugfs_create_regset32("registers", 0400, dentry, regset);
987}
988#endif