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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PLL clock driver for TI Davinci SoCs
4 *
5 * Copyright (C) 2018 David Lechner <david@lechnology.com>
6 *
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/mfd/syscon.h>
19#include <linux/notifier.h>
20#include <linux/of_address.h>
21#include <linux/of_device.h>
22#include <linux/of.h>
23#include <linux/platform_data/clk-davinci-pll.h>
24#include <linux/platform_device.h>
25#include <linux/regmap.h>
26#include <linux/slab.h>
27#include <linux/types.h>
28
29#include "pll.h"
30
31#define MAX_NAME_SIZE 20
32#define OSCIN_CLK_NAME "oscin"
33
34#define REVID 0x000
35#define PLLCTL 0x100
36#define OCSEL 0x104
37#define PLLSECCTL 0x108
38#define PLLM 0x110
39#define PREDIV 0x114
40#define PLLDIV1 0x118
41#define PLLDIV2 0x11c
42#define PLLDIV3 0x120
43#define OSCDIV 0x124
44#define POSTDIV 0x128
45#define BPDIV 0x12c
46#define PLLCMD 0x138
47#define PLLSTAT 0x13c
48#define ALNCTL 0x140
49#define DCHANGE 0x144
50#define CKEN 0x148
51#define CKSTAT 0x14c
52#define SYSTAT 0x150
53#define PLLDIV4 0x160
54#define PLLDIV5 0x164
55#define PLLDIV6 0x168
56#define PLLDIV7 0x16c
57#define PLLDIV8 0x170
58#define PLLDIV9 0x174
59
60#define PLLCTL_PLLEN BIT(0)
61#define PLLCTL_PLLPWRDN BIT(1)
62#define PLLCTL_PLLRST BIT(3)
63#define PLLCTL_PLLDIS BIT(4)
64#define PLLCTL_PLLENSRC BIT(5)
65#define PLLCTL_CLKMODE BIT(8)
66
67/* shared by most *DIV registers */
68#define DIV_RATIO_SHIFT 0
69#define DIV_RATIO_WIDTH 5
70#define DIV_ENABLE_SHIFT 15
71
72#define PLLCMD_GOSET BIT(0)
73#define PLLSTAT_GOSTAT BIT(0)
74
75#define CKEN_OBSCLK_SHIFT 1
76#define CKEN_AUXEN_SHIFT 0
77
78/*
79 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
80 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
81 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
82 * is ~25MHz. Units are micro seconds.
83 */
84#define PLL_BYPASS_TIME 1
85
86/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
87#define PLL_RESET_TIME 1
88
89/*
90 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
91 * Units are micro seconds.
92 */
93#define PLL_LOCK_TIME 20
94
95/**
96 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
97 * @hw: clk_hw for the pll
98 * @base: Base memory address
99 * @pllm_min: The minimum allowable PLLM[PLLM] value
100 * @pllm_max: The maxiumum allowable PLLM[PLLM] value
101 * @pllm_mask: Bitmask for PLLM[PLLM] value
102 */
103struct davinci_pll_clk {
104 struct clk_hw hw;
105 void __iomem *base;
106 u32 pllm_min;
107 u32 pllm_max;
108 u32 pllm_mask;
109};
110
111#define to_davinci_pll_clk(_hw) \
112 container_of((_hw), struct davinci_pll_clk, hw)
113
114static unsigned long davinci_pll_recalc_rate(struct clk_hw *hw,
115 unsigned long parent_rate)
116{
117 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
118 unsigned long rate = parent_rate;
119 u32 mult;
120
121 mult = readl(pll->base + PLLM) & pll->pllm_mask;
122 rate *= mult + 1;
123
124 return rate;
125}
126
127static int davinci_pll_determine_rate(struct clk_hw *hw,
128 struct clk_rate_request *req)
129{
130 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
131 struct clk_hw *parent = req->best_parent_hw;
132 unsigned long parent_rate = req->best_parent_rate;
133 unsigned long rate = req->rate;
134 unsigned long best_rate, r;
135 u32 mult;
136
137 /* there is a limited range of valid outputs (see datasheet) */
138 if (rate < req->min_rate)
139 return -EINVAL;
140
141 rate = min(rate, req->max_rate);
142 mult = rate / parent_rate;
143 best_rate = parent_rate * mult;
144
145 /* easy case when there is no PREDIV */
146 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
147 if (best_rate < req->min_rate)
148 return -EINVAL;
149
150 if (mult < pll->pllm_min || mult > pll->pllm_max)
151 return -EINVAL;
152
153 req->rate = best_rate;
154
155 return 0;
156 }
157
158 /* see if the PREDIV clock can help us */
159 best_rate = 0;
160
161 for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) {
162 parent_rate = clk_hw_round_rate(parent, rate / mult);
163 r = parent_rate * mult;
164 if (r < req->min_rate)
165 continue;
166 if (r > rate || r > req->max_rate)
167 break;
168 if (r > best_rate) {
169 best_rate = r;
170 req->rate = best_rate;
171 req->best_parent_rate = parent_rate;
172 if (best_rate == rate)
173 break;
174 }
175 }
176
177 return 0;
178}
179
180static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate,
181 unsigned long parent_rate)
182{
183 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
184 u32 mult;
185
186 mult = rate / parent_rate;
187 writel(mult - 1, pll->base + PLLM);
188
189 return 0;
190}
191
192#ifdef CONFIG_DEBUG_FS
193static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry);
194#else
195#define davinci_pll_debug_init NULL
196#endif
197
198static const struct clk_ops davinci_pll_ops = {
199 .recalc_rate = davinci_pll_recalc_rate,
200 .determine_rate = davinci_pll_determine_rate,
201 .set_rate = davinci_pll_set_rate,
202 .debug_init = davinci_pll_debug_init,
203};
204
205/* PLLM works differently on DM365 */
206static unsigned long dm365_pll_recalc_rate(struct clk_hw *hw,
207 unsigned long parent_rate)
208{
209 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
210 unsigned long rate = parent_rate;
211 u32 mult;
212
213 mult = readl(pll->base + PLLM) & pll->pllm_mask;
214 rate *= mult * 2;
215
216 return rate;
217}
218
219static const struct clk_ops dm365_pll_ops = {
220 .recalc_rate = dm365_pll_recalc_rate,
221 .debug_init = davinci_pll_debug_init,
222};
223
224/**
225 * davinci_pll_div_register - common *DIV clock implementation
226 * @name: the clock name
227 * @parent_name: the parent clock name
228 * @reg: the *DIV register
229 * @fixed: if true, the divider is a fixed value
230 * @flags: bitmap of CLK_* flags from clock-provider.h
231 */
232static struct clk *davinci_pll_div_register(struct device *dev,
233 const char *name,
234 const char *parent_name,
235 void __iomem *reg,
236 bool fixed, u32 flags)
237{
238 const char * const *parent_names = parent_name ? &parent_name : NULL;
239 int num_parents = parent_name ? 1 : 0;
240 const struct clk_ops *divider_ops = &clk_divider_ops;
241 struct clk_gate *gate;
242 struct clk_divider *divider;
243
244 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
245 if (!gate)
246 return ERR_PTR(-ENOMEM);
247
248 gate->reg = reg;
249 gate->bit_idx = DIV_ENABLE_SHIFT;
250
251 divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL);
252 if (!divider)
253 return ERR_PTR(-ENOMEM);
254
255 divider->reg = reg;
256 divider->shift = DIV_RATIO_SHIFT;
257 divider->width = DIV_RATIO_WIDTH;
258
259 if (fixed) {
260 divider->flags |= CLK_DIVIDER_READ_ONLY;
261 divider_ops = &clk_divider_ro_ops;
262 }
263
264 return clk_register_composite(dev, name, parent_names, num_parents,
265 NULL, NULL, ÷r->hw, divider_ops,
266 &gate->hw, &clk_gate_ops, flags);
267}
268
269struct davinci_pllen_clk {
270 struct clk_hw hw;
271 void __iomem *base;
272};
273
274#define to_davinci_pllen_clk(_hw) \
275 container_of((_hw), struct davinci_pllen_clk, hw)
276
277static const struct clk_ops davinci_pllen_ops = {
278 /* this clocks just uses the clock notification feature */
279};
280
281/*
282 * The PLL has to be switched into bypass mode while we are chaning the rate,
283 * so we do that on the PLLEN clock since it is the end of the line. This will
284 * switch to bypass before any of the parent clocks (PREDIV, PLL, POSTDIV) are
285 * changed and will switch back to the PLL after the changes have been made.
286 */
287static int davinci_pllen_rate_change(struct notifier_block *nb,
288 unsigned long flags, void *data)
289{
290 struct clk_notifier_data *cnd = data;
291 struct clk_hw *hw = __clk_get_hw(cnd->clk);
292 struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
293 u32 ctrl;
294
295 ctrl = readl(pll->base + PLLCTL);
296
297 if (flags == PRE_RATE_CHANGE) {
298 /* Switch the PLL to bypass mode */
299 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
300 writel(ctrl, pll->base + PLLCTL);
301
302 udelay(PLL_BYPASS_TIME);
303
304 /* Reset and enable PLL */
305 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
306 writel(ctrl, pll->base + PLLCTL);
307 } else {
308 udelay(PLL_RESET_TIME);
309
310 /* Bring PLL out of reset */
311 ctrl |= PLLCTL_PLLRST;
312 writel(ctrl, pll->base + PLLCTL);
313
314 udelay(PLL_LOCK_TIME);
315
316 /* Remove PLL from bypass mode */
317 ctrl |= PLLCTL_PLLEN;
318 writel(ctrl, pll->base + PLLCTL);
319 }
320
321 return NOTIFY_OK;
322}
323
324static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev)
325{
326 struct davinci_pll_platform_data *pdata = dev_get_platdata(dev);
327
328 /*
329 * Platform data is optional, so allocate a new struct if one was not
330 * provided. For device tree, this will always be the case.
331 */
332 if (!pdata)
333 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
334 if (!pdata)
335 return NULL;
336
337 /* for device tree, we need to fill in the struct */
338 if (dev->of_node)
339 pdata->cfgchip =
340 syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
341
342 return pdata;
343}
344
345static struct notifier_block davinci_pllen_notifier = {
346 .notifier_call = davinci_pllen_rate_change,
347};
348
349/**
350 * davinci_pll_clk_register - Register a PLL clock
351 * @info: The device-specific clock info
352 * @parent_name: The parent clock name
353 * @base: The PLL's memory region
354 *
355 * This creates a series of clocks that represent the PLL.
356 *
357 * OSCIN > [PREDIV >] PLL > [POSTDIV >] PLLEN
358 *
359 * - OSCIN is the parent clock (on secondary PLL, may come from primary PLL)
360 * - PREDIV and POSTDIV are optional (depends on the PLL controller)
361 * - PLL is the PLL output (aka PLLOUT)
362 * - PLLEN is the bypass multiplexer
363 *
364 * Returns: The PLLOUT clock or a negative error code.
365 */
366struct clk *davinci_pll_clk_register(struct device *dev,
367 const struct davinci_pll_clk_info *info,
368 const char *parent_name,
369 void __iomem *base)
370{
371 struct davinci_pll_platform_data *pdata;
372 char prediv_name[MAX_NAME_SIZE];
373 char pllout_name[MAX_NAME_SIZE];
374 char postdiv_name[MAX_NAME_SIZE];
375 char pllen_name[MAX_NAME_SIZE];
376 struct clk_init_data init;
377 struct davinci_pll_clk *pllout;
378 struct davinci_pllen_clk *pllen;
379 struct clk *pllout_clk, *clk;
380
381 pdata = davinci_pll_get_pdata(dev);
382 if (!pdata)
383 return ERR_PTR(-ENOMEM);
384
385 if (info->flags & PLL_HAS_CLKMODE) {
386 /*
387 * If a PLL has PLLCTL[CLKMODE], then it is the primary PLL.
388 * We register a clock named "oscin" that serves as the internal
389 * "input clock" domain shared by both PLLs (if there are 2)
390 * and will be the parent clock to the AUXCLK, SYSCLKBP and
391 * OBSCLK domains. NB: The various TRMs use "OSCIN" to mean
392 * a number of different things. In this driver we use it to
393 * mean the signal after the PLLCTL[CLKMODE] switch.
394 */
395 clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME,
396 parent_name, 0, 1, 1);
397 if (IS_ERR(clk))
398 return clk;
399
400 parent_name = OSCIN_CLK_NAME;
401 }
402
403 if (info->flags & PLL_HAS_PREDIV) {
404 bool fixed = info->flags & PLL_PREDIV_FIXED_DIV;
405 u32 flags = 0;
406
407 snprintf(prediv_name, MAX_NAME_SIZE, "%s_prediv", info->name);
408
409 if (info->flags & PLL_PREDIV_ALWAYS_ENABLED)
410 flags |= CLK_IS_CRITICAL;
411
412 /* Some? DM355 chips don't correctly report the PREDIV value */
413 if (info->flags & PLL_PREDIV_FIXED8)
414 clk = clk_register_fixed_factor(dev, prediv_name,
415 parent_name, flags, 1, 8);
416 else
417 clk = davinci_pll_div_register(dev, prediv_name,
418 parent_name, base + PREDIV, fixed, flags);
419 if (IS_ERR(clk))
420 return clk;
421
422 parent_name = prediv_name;
423 }
424
425 /* Unlock writing to PLL registers */
426 if (info->unlock_reg) {
427 if (IS_ERR_OR_NULL(pdata->cfgchip))
428 dev_warn(dev, "Failed to get CFGCHIP (%ld)\n",
429 PTR_ERR(pdata->cfgchip));
430 else
431 regmap_write_bits(pdata->cfgchip, info->unlock_reg,
432 info->unlock_mask, 0);
433 }
434
435 pllout = devm_kzalloc(dev, sizeof(*pllout), GFP_KERNEL);
436 if (!pllout)
437 return ERR_PTR(-ENOMEM);
438
439 snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name);
440
441 init.name = pllout_name;
442 if (info->flags & PLL_PLLM_2X)
443 init.ops = &dm365_pll_ops;
444 else
445 init.ops = &davinci_pll_ops;
446 init.parent_names = &parent_name;
447 init.num_parents = 1;
448 init.flags = 0;
449
450 if (info->flags & PLL_HAS_PREDIV)
451 init.flags |= CLK_SET_RATE_PARENT;
452
453 pllout->hw.init = &init;
454 pllout->base = base;
455 pllout->pllm_mask = info->pllm_mask;
456 pllout->pllm_min = info->pllm_min;
457 pllout->pllm_max = info->pllm_max;
458
459 pllout_clk = devm_clk_register(dev, &pllout->hw);
460 if (IS_ERR(pllout_clk))
461 return pllout_clk;
462
463 clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate,
464 info->pllout_max_rate);
465
466 parent_name = pllout_name;
467
468 if (info->flags & PLL_HAS_POSTDIV) {
469 bool fixed = info->flags & PLL_POSTDIV_FIXED_DIV;
470 u32 flags = CLK_SET_RATE_PARENT;
471
472 snprintf(postdiv_name, MAX_NAME_SIZE, "%s_postdiv", info->name);
473
474 if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED)
475 flags |= CLK_IS_CRITICAL;
476
477 clk = davinci_pll_div_register(dev, postdiv_name, parent_name,
478 base + POSTDIV, fixed, flags);
479 if (IS_ERR(clk))
480 return clk;
481
482 parent_name = postdiv_name;
483 }
484
485 pllen = devm_kzalloc(dev, sizeof(*pllout), GFP_KERNEL);
486 if (!pllen)
487 return ERR_PTR(-ENOMEM);
488
489 snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name);
490
491 init.name = pllen_name;
492 init.ops = &davinci_pllen_ops;
493 init.parent_names = &parent_name;
494 init.num_parents = 1;
495 init.flags = CLK_SET_RATE_PARENT;
496
497 pllen->hw.init = &init;
498 pllen->base = base;
499
500 clk = devm_clk_register(dev, &pllen->hw);
501 if (IS_ERR(clk))
502 return clk;
503
504 clk_notifier_register(clk, &davinci_pllen_notifier);
505
506 return pllout_clk;
507}
508
509/**
510 * davinci_pll_auxclk_register - Register bypass clock (AUXCLK)
511 * @name: The clock name
512 * @base: The PLL memory region
513 */
514struct clk *davinci_pll_auxclk_register(struct device *dev,
515 const char *name,
516 void __iomem *base)
517{
518 return clk_register_gate(dev, name, OSCIN_CLK_NAME, 0, base + CKEN,
519 CKEN_AUXEN_SHIFT, 0, NULL);
520}
521
522/**
523 * davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP)
524 * @name: The clock name
525 * @base: The PLL memory region
526 */
527struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
528 const char *name,
529 void __iomem *base)
530{
531 return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV,
532 DIV_RATIO_SHIFT, DIV_RATIO_WIDTH,
533 CLK_DIVIDER_READ_ONLY, NULL);
534}
535
536/**
537 * davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK)
538 * @info: The clock info
539 * @base: The PLL memory region
540 */
541struct clk *
542davinci_pll_obsclk_register(struct device *dev,
543 const struct davinci_pll_obsclk_info *info,
544 void __iomem *base)
545{
546 struct clk_mux *mux;
547 struct clk_gate *gate;
548 struct clk_divider *divider;
549 u32 oscdiv;
550
551 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
552 if (!mux)
553 return ERR_PTR(-ENOMEM);
554
555 mux->reg = base + OCSEL;
556 mux->table = info->table;
557 mux->mask = info->ocsrc_mask;
558
559 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
560 if (!gate)
561 return ERR_PTR(-ENOMEM);
562
563 gate->reg = base + CKEN;
564 gate->bit_idx = CKEN_OBSCLK_SHIFT;
565
566 divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL);
567 if (!divider)
568 return ERR_PTR(-ENOMEM);
569
570 divider->reg = base + OSCDIV;
571 divider->shift = DIV_RATIO_SHIFT;
572 divider->width = DIV_RATIO_WIDTH;
573
574 /* make sure divider is enabled just in case bootloader disabled it */
575 oscdiv = readl(base + OSCDIV);
576 oscdiv |= BIT(DIV_ENABLE_SHIFT);
577 writel(oscdiv, base + OSCDIV);
578
579 return clk_register_composite(dev, info->name, info->parent_names,
580 info->num_parents,
581 &mux->hw, &clk_mux_ops,
582 ÷r->hw, &clk_divider_ops,
583 &gate->hw, &clk_gate_ops, 0);
584}
585
586/* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */
587static int davinci_pll_sysclk_rate_change(struct notifier_block *nb,
588 unsigned long flags, void *data)
589{
590 struct clk_notifier_data *cnd = data;
591 struct clk_hw *hw = __clk_get_hw(clk_get_parent(cnd->clk));
592 struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw);
593 u32 pllcmd, pllstat;
594
595 switch (flags) {
596 case POST_RATE_CHANGE:
597 /* apply the changes */
598 pllcmd = readl(pll->base + PLLCMD);
599 pllcmd |= PLLCMD_GOSET;
600 writel(pllcmd, pll->base + PLLCMD);
601 /* fallthrough */
602 case PRE_RATE_CHANGE:
603 /* Wait until for outstanding changes to take effect */
604 do {
605 pllstat = readl(pll->base + PLLSTAT);
606 } while (pllstat & PLLSTAT_GOSTAT);
607 break;
608 }
609
610 return NOTIFY_OK;
611}
612
613static struct notifier_block davinci_pll_sysclk_notifier = {
614 .notifier_call = davinci_pll_sysclk_rate_change,
615};
616
617/**
618 * davinci_pll_sysclk_register - Register divider clocks (SYSCLKn)
619 * @info: The clock info
620 * @base: The PLL memory region
621 */
622struct clk *
623davinci_pll_sysclk_register(struct device *dev,
624 const struct davinci_pll_sysclk_info *info,
625 void __iomem *base)
626{
627 const struct clk_ops *divider_ops = &clk_divider_ops;
628 struct clk_gate *gate;
629 struct clk_divider *divider;
630 struct clk *clk;
631 u32 reg;
632 u32 flags = 0;
633
634 /* PLLDIVn registers are not entirely consecutive */
635 if (info->id < 4)
636 reg = PLLDIV1 + 4 * (info->id - 1);
637 else
638 reg = PLLDIV4 + 4 * (info->id - 4);
639
640 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
641 if (!gate)
642 return ERR_PTR(-ENOMEM);
643
644 gate->reg = base + reg;
645 gate->bit_idx = DIV_ENABLE_SHIFT;
646
647 divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL);
648 if (!divider)
649 return ERR_PTR(-ENOMEM);
650
651 divider->reg = base + reg;
652 divider->shift = DIV_RATIO_SHIFT;
653 divider->width = info->ratio_width;
654 divider->flags = 0;
655
656 if (info->flags & SYSCLK_FIXED_DIV) {
657 divider->flags |= CLK_DIVIDER_READ_ONLY;
658 divider_ops = &clk_divider_ro_ops;
659 }
660
661 /* Only the ARM clock can change the parent PLL rate */
662 if (info->flags & SYSCLK_ARM_RATE)
663 flags |= CLK_SET_RATE_PARENT;
664
665 if (info->flags & SYSCLK_ALWAYS_ENABLED)
666 flags |= CLK_IS_CRITICAL;
667
668 clk = clk_register_composite(dev, info->name, &info->parent_name, 1,
669 NULL, NULL, ÷r->hw, divider_ops,
670 &gate->hw, &clk_gate_ops, flags);
671 if (IS_ERR(clk))
672 return clk;
673
674 clk_notifier_register(clk, &davinci_pll_sysclk_notifier);
675
676 return clk;
677}
678
679int of_davinci_pll_init(struct device *dev,
680 const struct davinci_pll_clk_info *info,
681 const struct davinci_pll_obsclk_info *obsclk_info,
682 const struct davinci_pll_sysclk_info **div_info,
683 u8 max_sysclk_id,
684 void __iomem *base)
685{
686 struct device_node *node = dev->of_node;
687 struct device_node *child;
688 const char *parent_name;
689 struct clk *clk;
690
691 if (info->flags & PLL_HAS_CLKMODE)
692 parent_name = of_clk_get_parent_name(node, 0);
693 else
694 parent_name = OSCIN_CLK_NAME;
695
696 clk = davinci_pll_clk_register(dev, info, parent_name, base);
697 if (IS_ERR(clk)) {
698 dev_err(dev, "failed to register %s\n", info->name);
699 return PTR_ERR(clk);
700 }
701
702 child = of_get_child_by_name(node, "pllout");
703 if (of_device_is_available(child))
704 of_clk_add_provider(child, of_clk_src_simple_get, clk);
705 of_node_put(child);
706
707 child = of_get_child_by_name(node, "sysclk");
708 if (of_device_is_available(child)) {
709 struct clk_onecell_data *clk_data;
710 struct clk **clks;
711 int n_clks = max_sysclk_id + 1;
712 int i;
713
714 clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
715 if (!clk_data)
716 return -ENOMEM;
717
718 clks = devm_kmalloc_array(dev, n_clks, sizeof(*clks), GFP_KERNEL);
719 if (!clks)
720 return -ENOMEM;
721
722 clk_data->clks = clks;
723 clk_data->clk_num = n_clks;
724
725 for (i = 0; i < n_clks; i++)
726 clks[i] = ERR_PTR(-ENOENT);
727
728 for (; *div_info; div_info++) {
729 clk = davinci_pll_sysclk_register(dev, *div_info, base);
730 if (IS_ERR(clk))
731 dev_warn(dev, "failed to register %s (%ld)\n",
732 (*div_info)->name, PTR_ERR(clk));
733 else
734 clks[(*div_info)->id] = clk;
735 }
736 of_clk_add_provider(child, of_clk_src_onecell_get, clk_data);
737 }
738 of_node_put(child);
739
740 child = of_get_child_by_name(node, "auxclk");
741 if (of_device_is_available(child)) {
742 char child_name[MAX_NAME_SIZE];
743
744 snprintf(child_name, MAX_NAME_SIZE, "%s_auxclk", info->name);
745
746 clk = davinci_pll_auxclk_register(dev, child_name, base);
747 if (IS_ERR(clk))
748 dev_warn(dev, "failed to register %s (%ld)\n",
749 child_name, PTR_ERR(clk));
750 else
751 of_clk_add_provider(child, of_clk_src_simple_get, clk);
752 }
753 of_node_put(child);
754
755 child = of_get_child_by_name(node, "obsclk");
756 if (of_device_is_available(child)) {
757 if (obsclk_info)
758 clk = davinci_pll_obsclk_register(dev, obsclk_info, base);
759 else
760 clk = ERR_PTR(-EINVAL);
761
762 if (IS_ERR(clk))
763 dev_warn(dev, "failed to register obsclk (%ld)\n",
764 PTR_ERR(clk));
765 else
766 of_clk_add_provider(child, of_clk_src_simple_get, clk);
767 }
768 of_node_put(child);
769
770 return 0;
771}
772
773static const struct of_device_id davinci_pll_of_match[] = {
774 { .compatible = "ti,da850-pll0", .data = of_da850_pll0_init },
775 { .compatible = "ti,da850-pll1", .data = of_da850_pll1_init },
776 { }
777};
778
779static const struct platform_device_id davinci_pll_id_table[] = {
780 { .name = "da830-pll", .driver_data = (kernel_ulong_t)da830_pll_init },
781 { .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init },
782 { .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init },
783 { .name = "dm355-pll1", .driver_data = (kernel_ulong_t)dm355_pll1_init },
784 { .name = "dm355-pll2", .driver_data = (kernel_ulong_t)dm355_pll2_init },
785 { .name = "dm365-pll1", .driver_data = (kernel_ulong_t)dm365_pll1_init },
786 { .name = "dm365-pll2", .driver_data = (kernel_ulong_t)dm365_pll2_init },
787 { .name = "dm644x-pll1", .driver_data = (kernel_ulong_t)dm644x_pll1_init },
788 { .name = "dm644x-pll2", .driver_data = (kernel_ulong_t)dm644x_pll2_init },
789 { .name = "dm646x-pll1", .driver_data = (kernel_ulong_t)dm646x_pll1_init },
790 { .name = "dm646x-pll2", .driver_data = (kernel_ulong_t)dm646x_pll2_init },
791 { }
792};
793
794typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base);
795
796static int davinci_pll_probe(struct platform_device *pdev)
797{
798 struct device *dev = &pdev->dev;
799 const struct of_device_id *of_id;
800 davinci_pll_init pll_init = NULL;
801 struct resource *res;
802 void __iomem *base;
803
804 of_id = of_match_device(davinci_pll_of_match, dev);
805 if (of_id)
806 pll_init = of_id->data;
807 else if (pdev->id_entry)
808 pll_init = (void *)pdev->id_entry->driver_data;
809
810 if (!pll_init) {
811 dev_err(dev, "unable to find driver data\n");
812 return -EINVAL;
813 }
814
815 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
816 base = devm_ioremap_resource(dev, res);
817 if (IS_ERR(base))
818 return PTR_ERR(base);
819
820 return pll_init(dev, base);
821}
822
823static struct platform_driver davinci_pll_driver = {
824 .probe = davinci_pll_probe,
825 .driver = {
826 .name = "davinci-pll-clk",
827 .of_match_table = davinci_pll_of_match,
828 },
829 .id_table = davinci_pll_id_table,
830};
831
832static int __init davinci_pll_driver_init(void)
833{
834 return platform_driver_register(&davinci_pll_driver);
835}
836
837/* has to be postcore_initcall because PSC devices depend on PLL parent clocks */
838postcore_initcall(davinci_pll_driver_init);
839
840#ifdef CONFIG_DEBUG_FS
841#include <linux/debugfs.h>
842
843#define DEBUG_REG(n) \
844{ \
845 .name = #n, \
846 .offset = n, \
847}
848
849static const struct debugfs_reg32 davinci_pll_regs[] = {
850 DEBUG_REG(REVID),
851 DEBUG_REG(PLLCTL),
852 DEBUG_REG(OCSEL),
853 DEBUG_REG(PLLSECCTL),
854 DEBUG_REG(PLLM),
855 DEBUG_REG(PREDIV),
856 DEBUG_REG(PLLDIV1),
857 DEBUG_REG(PLLDIV2),
858 DEBUG_REG(PLLDIV3),
859 DEBUG_REG(OSCDIV),
860 DEBUG_REG(POSTDIV),
861 DEBUG_REG(BPDIV),
862 DEBUG_REG(PLLCMD),
863 DEBUG_REG(PLLSTAT),
864 DEBUG_REG(ALNCTL),
865 DEBUG_REG(DCHANGE),
866 DEBUG_REG(CKEN),
867 DEBUG_REG(CKSTAT),
868 DEBUG_REG(SYSTAT),
869 DEBUG_REG(PLLDIV4),
870 DEBUG_REG(PLLDIV5),
871 DEBUG_REG(PLLDIV6),
872 DEBUG_REG(PLLDIV7),
873 DEBUG_REG(PLLDIV8),
874 DEBUG_REG(PLLDIV9),
875};
876
877static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
878{
879 struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
880 struct debugfs_regset32 *regset;
881 struct dentry *d;
882
883 regset = kzalloc(sizeof(*regset), GFP_KERNEL);
884 if (!regset)
885 return -ENOMEM;
886
887 regset->regs = davinci_pll_regs;
888 regset->nregs = ARRAY_SIZE(davinci_pll_regs);
889 regset->base = pll->base;
890
891 d = debugfs_create_regset32("registers", 0400, dentry, regset);
892 if (IS_ERR(d)) {
893 kfree(regset);
894 return PTR_ERR(d);
895 }
896
897 return 0;
898}
899#endif