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1/*
2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 * Copyright (C) 2011 Don Zickus Red Hat, Inc.
5 *
6 * Pentium III FXSR, SSE support
7 * Gareth Hughes <gareth@valinux.com>, May 2000
8 */
9
10/*
11 * Handle hardware traps and faults.
12 */
13#include <linux/spinlock.h>
14#include <linux/kprobes.h>
15#include <linux/kdebug.h>
16#include <linux/nmi.h>
17#include <linux/delay.h>
18#include <linux/hardirq.h>
19#include <linux/slab.h>
20#include <linux/export.h>
21
22#if defined(CONFIG_EDAC)
23#include <linux/edac.h>
24#endif
25
26#include <linux/atomic.h>
27#include <asm/traps.h>
28#include <asm/mach_traps.h>
29#include <asm/nmi.h>
30#include <asm/x86_init.h>
31
32struct nmi_desc {
33 spinlock_t lock;
34 struct list_head head;
35};
36
37static struct nmi_desc nmi_desc[NMI_MAX] =
38{
39 {
40 .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[0].lock),
41 .head = LIST_HEAD_INIT(nmi_desc[0].head),
42 },
43 {
44 .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock),
45 .head = LIST_HEAD_INIT(nmi_desc[1].head),
46 },
47 {
48 .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[2].lock),
49 .head = LIST_HEAD_INIT(nmi_desc[2].head),
50 },
51 {
52 .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock),
53 .head = LIST_HEAD_INIT(nmi_desc[3].head),
54 },
55
56};
57
58struct nmi_stats {
59 unsigned int normal;
60 unsigned int unknown;
61 unsigned int external;
62 unsigned int swallow;
63};
64
65static DEFINE_PER_CPU(struct nmi_stats, nmi_stats);
66
67static int ignore_nmis;
68
69int unknown_nmi_panic;
70/*
71 * Prevent NMI reason port (0x61) being accessed simultaneously, can
72 * only be used in NMI handler.
73 */
74static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
75
76static int __init setup_unknown_nmi_panic(char *str)
77{
78 unknown_nmi_panic = 1;
79 return 1;
80}
81__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
82
83#define nmi_to_desc(type) (&nmi_desc[type])
84
85static int __kprobes nmi_handle(unsigned int type, struct pt_regs *regs, bool b2b)
86{
87 struct nmi_desc *desc = nmi_to_desc(type);
88 struct nmiaction *a;
89 int handled=0;
90
91 rcu_read_lock();
92
93 /*
94 * NMIs are edge-triggered, which means if you have enough
95 * of them concurrently, you can lose some because only one
96 * can be latched at any given time. Walk the whole list
97 * to handle those situations.
98 */
99 list_for_each_entry_rcu(a, &desc->head, list)
100 handled += a->handler(type, regs);
101
102 rcu_read_unlock();
103
104 /* return total number of NMI events handled */
105 return handled;
106}
107
108int __register_nmi_handler(unsigned int type, struct nmiaction *action)
109{
110 struct nmi_desc *desc = nmi_to_desc(type);
111 unsigned long flags;
112
113 if (!action->handler)
114 return -EINVAL;
115
116 spin_lock_irqsave(&desc->lock, flags);
117
118 /*
119 * most handlers of type NMI_UNKNOWN never return because
120 * they just assume the NMI is theirs. Just a sanity check
121 * to manage expectations
122 */
123 WARN_ON_ONCE(type == NMI_UNKNOWN && !list_empty(&desc->head));
124 WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head));
125 WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head));
126
127 /*
128 * some handlers need to be executed first otherwise a fake
129 * event confuses some handlers (kdump uses this flag)
130 */
131 if (action->flags & NMI_FLAG_FIRST)
132 list_add_rcu(&action->list, &desc->head);
133 else
134 list_add_tail_rcu(&action->list, &desc->head);
135
136 spin_unlock_irqrestore(&desc->lock, flags);
137 return 0;
138}
139EXPORT_SYMBOL(__register_nmi_handler);
140
141void unregister_nmi_handler(unsigned int type, const char *name)
142{
143 struct nmi_desc *desc = nmi_to_desc(type);
144 struct nmiaction *n;
145 unsigned long flags;
146
147 spin_lock_irqsave(&desc->lock, flags);
148
149 list_for_each_entry_rcu(n, &desc->head, list) {
150 /*
151 * the name passed in to describe the nmi handler
152 * is used as the lookup key
153 */
154 if (!strcmp(n->name, name)) {
155 WARN(in_nmi(),
156 "Trying to free NMI (%s) from NMI context!\n", n->name);
157 list_del_rcu(&n->list);
158 break;
159 }
160 }
161
162 spin_unlock_irqrestore(&desc->lock, flags);
163 synchronize_rcu();
164}
165EXPORT_SYMBOL_GPL(unregister_nmi_handler);
166
167static __kprobes void
168pci_serr_error(unsigned char reason, struct pt_regs *regs)
169{
170 /* check to see if anyone registered against these types of errors */
171 if (nmi_handle(NMI_SERR, regs, false))
172 return;
173
174 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
175 reason, smp_processor_id());
176
177 /*
178 * On some machines, PCI SERR line is used to report memory
179 * errors. EDAC makes use of it.
180 */
181#if defined(CONFIG_EDAC)
182 if (edac_handler_set()) {
183 edac_atomic_assert_error();
184 return;
185 }
186#endif
187
188 if (panic_on_unrecovered_nmi)
189 panic("NMI: Not continuing");
190
191 pr_emerg("Dazed and confused, but trying to continue\n");
192
193 /* Clear and disable the PCI SERR error line. */
194 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR;
195 outb(reason, NMI_REASON_PORT);
196}
197
198static __kprobes void
199io_check_error(unsigned char reason, struct pt_regs *regs)
200{
201 unsigned long i;
202
203 /* check to see if anyone registered against these types of errors */
204 if (nmi_handle(NMI_IO_CHECK, regs, false))
205 return;
206
207 pr_emerg(
208 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
209 reason, smp_processor_id());
210 show_regs(regs);
211
212 if (panic_on_io_nmi)
213 panic("NMI IOCK error: Not continuing");
214
215 /* Re-enable the IOCK line, wait for a few seconds */
216 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK;
217 outb(reason, NMI_REASON_PORT);
218
219 i = 20000;
220 while (--i) {
221 touch_nmi_watchdog();
222 udelay(100);
223 }
224
225 reason &= ~NMI_REASON_CLEAR_IOCHK;
226 outb(reason, NMI_REASON_PORT);
227}
228
229static __kprobes void
230unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
231{
232 int handled;
233
234 /*
235 * Use 'false' as back-to-back NMIs are dealt with one level up.
236 * Of course this makes having multiple 'unknown' handlers useless
237 * as only the first one is ever run (unless it can actually determine
238 * if it caused the NMI)
239 */
240 handled = nmi_handle(NMI_UNKNOWN, regs, false);
241 if (handled) {
242 __this_cpu_add(nmi_stats.unknown, handled);
243 return;
244 }
245
246 __this_cpu_add(nmi_stats.unknown, 1);
247
248 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
249 reason, smp_processor_id());
250
251 pr_emerg("Do you have a strange power saving mode enabled?\n");
252 if (unknown_nmi_panic || panic_on_unrecovered_nmi)
253 panic("NMI: Not continuing");
254
255 pr_emerg("Dazed and confused, but trying to continue\n");
256}
257
258static DEFINE_PER_CPU(bool, swallow_nmi);
259static DEFINE_PER_CPU(unsigned long, last_nmi_rip);
260
261static __kprobes void default_do_nmi(struct pt_regs *regs)
262{
263 unsigned char reason = 0;
264 int handled;
265 bool b2b = false;
266
267 /*
268 * CPU-specific NMI must be processed before non-CPU-specific
269 * NMI, otherwise we may lose it, because the CPU-specific
270 * NMI can not be detected/processed on other CPUs.
271 */
272
273 /*
274 * Back-to-back NMIs are interesting because they can either
275 * be two NMI or more than two NMIs (any thing over two is dropped
276 * due to NMI being edge-triggered). If this is the second half
277 * of the back-to-back NMI, assume we dropped things and process
278 * more handlers. Otherwise reset the 'swallow' NMI behaviour
279 */
280 if (regs->ip == __this_cpu_read(last_nmi_rip))
281 b2b = true;
282 else
283 __this_cpu_write(swallow_nmi, false);
284
285 __this_cpu_write(last_nmi_rip, regs->ip);
286
287 handled = nmi_handle(NMI_LOCAL, regs, b2b);
288 __this_cpu_add(nmi_stats.normal, handled);
289 if (handled) {
290 /*
291 * There are cases when a NMI handler handles multiple
292 * events in the current NMI. One of these events may
293 * be queued for in the next NMI. Because the event is
294 * already handled, the next NMI will result in an unknown
295 * NMI. Instead lets flag this for a potential NMI to
296 * swallow.
297 */
298 if (handled > 1)
299 __this_cpu_write(swallow_nmi, true);
300 return;
301 }
302
303 /* Non-CPU-specific NMI: NMI sources can be processed on any CPU */
304 raw_spin_lock(&nmi_reason_lock);
305 reason = x86_platform.get_nmi_reason();
306
307 if (reason & NMI_REASON_MASK) {
308 if (reason & NMI_REASON_SERR)
309 pci_serr_error(reason, regs);
310 else if (reason & NMI_REASON_IOCHK)
311 io_check_error(reason, regs);
312#ifdef CONFIG_X86_32
313 /*
314 * Reassert NMI in case it became active
315 * meanwhile as it's edge-triggered:
316 */
317 reassert_nmi();
318#endif
319 __this_cpu_add(nmi_stats.external, 1);
320 raw_spin_unlock(&nmi_reason_lock);
321 return;
322 }
323 raw_spin_unlock(&nmi_reason_lock);
324
325 /*
326 * Only one NMI can be latched at a time. To handle
327 * this we may process multiple nmi handlers at once to
328 * cover the case where an NMI is dropped. The downside
329 * to this approach is we may process an NMI prematurely,
330 * while its real NMI is sitting latched. This will cause
331 * an unknown NMI on the next run of the NMI processing.
332 *
333 * We tried to flag that condition above, by setting the
334 * swallow_nmi flag when we process more than one event.
335 * This condition is also only present on the second half
336 * of a back-to-back NMI, so we flag that condition too.
337 *
338 * If both are true, we assume we already processed this
339 * NMI previously and we swallow it. Otherwise we reset
340 * the logic.
341 *
342 * There are scenarios where we may accidentally swallow
343 * a 'real' unknown NMI. For example, while processing
344 * a perf NMI another perf NMI comes in along with a
345 * 'real' unknown NMI. These two NMIs get combined into
346 * one (as descibed above). When the next NMI gets
347 * processed, it will be flagged by perf as handled, but
348 * noone will know that there was a 'real' unknown NMI sent
349 * also. As a result it gets swallowed. Or if the first
350 * perf NMI returns two events handled then the second
351 * NMI will get eaten by the logic below, again losing a
352 * 'real' unknown NMI. But this is the best we can do
353 * for now.
354 */
355 if (b2b && __this_cpu_read(swallow_nmi))
356 __this_cpu_add(nmi_stats.swallow, 1);
357 else
358 unknown_nmi_error(reason, regs);
359}
360
361/*
362 * NMIs can hit breakpoints which will cause it to lose its
363 * NMI context with the CPU when the breakpoint does an iret.
364 */
365#ifdef CONFIG_X86_32
366/*
367 * For i386, NMIs use the same stack as the kernel, and we can
368 * add a workaround to the iret problem in C. Simply have 3 states
369 * the NMI can be in.
370 *
371 * 1) not running
372 * 2) executing
373 * 3) latched
374 *
375 * When no NMI is in progress, it is in the "not running" state.
376 * When an NMI comes in, it goes into the "executing" state.
377 * Normally, if another NMI is triggered, it does not interrupt
378 * the running NMI and the HW will simply latch it so that when
379 * the first NMI finishes, it will restart the second NMI.
380 * (Note, the latch is binary, thus multiple NMIs triggering,
381 * when one is running, are ignored. Only one NMI is restarted.)
382 *
383 * If an NMI hits a breakpoint that executes an iret, another
384 * NMI can preempt it. We do not want to allow this new NMI
385 * to run, but we want to execute it when the first one finishes.
386 * We set the state to "latched", and the first NMI will perform
387 * an cmpxchg on the state, and if it doesn't successfully
388 * reset the state to "not running" it will restart the next
389 * NMI.
390 */
391enum nmi_states {
392 NMI_NOT_RUNNING,
393 NMI_EXECUTING,
394 NMI_LATCHED,
395};
396static DEFINE_PER_CPU(enum nmi_states, nmi_state);
397
398#define nmi_nesting_preprocess(regs) \
399 do { \
400 if (__get_cpu_var(nmi_state) != NMI_NOT_RUNNING) { \
401 __get_cpu_var(nmi_state) = NMI_LATCHED; \
402 return; \
403 } \
404 nmi_restart: \
405 __get_cpu_var(nmi_state) = NMI_EXECUTING; \
406 } while (0)
407
408#define nmi_nesting_postprocess() \
409 do { \
410 if (cmpxchg(&__get_cpu_var(nmi_state), \
411 NMI_EXECUTING, NMI_NOT_RUNNING) != NMI_EXECUTING) \
412 goto nmi_restart; \
413 } while (0)
414#else /* x86_64 */
415/*
416 * In x86_64 things are a bit more difficult. This has the same problem
417 * where an NMI hitting a breakpoint that calls iret will remove the
418 * NMI context, allowing a nested NMI to enter. What makes this more
419 * difficult is that both NMIs and breakpoints have their own stack.
420 * When a new NMI or breakpoint is executed, the stack is set to a fixed
421 * point. If an NMI is nested, it will have its stack set at that same
422 * fixed address that the first NMI had, and will start corrupting the
423 * stack. This is handled in entry_64.S, but the same problem exists with
424 * the breakpoint stack.
425 *
426 * If a breakpoint is being processed, and the debug stack is being used,
427 * if an NMI comes in and also hits a breakpoint, the stack pointer
428 * will be set to the same fixed address as the breakpoint that was
429 * interrupted, causing that stack to be corrupted. To handle this case,
430 * check if the stack that was interrupted is the debug stack, and if
431 * so, change the IDT so that new breakpoints will use the current stack
432 * and not switch to the fixed address. On return of the NMI, switch back
433 * to the original IDT.
434 */
435static DEFINE_PER_CPU(int, update_debug_stack);
436
437static inline void nmi_nesting_preprocess(struct pt_regs *regs)
438{
439 /*
440 * If we interrupted a breakpoint, it is possible that
441 * the nmi handler will have breakpoints too. We need to
442 * change the IDT such that breakpoints that happen here
443 * continue to use the NMI stack.
444 */
445 if (unlikely(is_debug_stack(regs->sp))) {
446 debug_stack_set_zero();
447 this_cpu_write(update_debug_stack, 1);
448 }
449}
450
451static inline void nmi_nesting_postprocess(void)
452{
453 if (unlikely(this_cpu_read(update_debug_stack))) {
454 debug_stack_reset();
455 this_cpu_write(update_debug_stack, 0);
456 }
457}
458#endif
459
460dotraplinkage notrace __kprobes void
461do_nmi(struct pt_regs *regs, long error_code)
462{
463 nmi_nesting_preprocess(regs);
464
465 nmi_enter();
466
467 inc_irq_stat(__nmi_count);
468
469 if (!ignore_nmis)
470 default_do_nmi(regs);
471
472 nmi_exit();
473
474 /* On i386, may loop back to preprocess */
475 nmi_nesting_postprocess();
476}
477
478void stop_nmi(void)
479{
480 ignore_nmis++;
481}
482
483void restart_nmi(void)
484{
485 ignore_nmis--;
486}
487
488/* reset the back-to-back NMI logic */
489void local_touch_nmi(void)
490{
491 __this_cpu_write(last_nmi_rip, 0);
492}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 1991, 1992 Linus Torvalds
4 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
5 * Copyright (C) 2011 Don Zickus Red Hat, Inc.
6 *
7 * Pentium III FXSR, SSE support
8 * Gareth Hughes <gareth@valinux.com>, May 2000
9 */
10
11/*
12 * Handle hardware traps and faults.
13 */
14#include <linux/spinlock.h>
15#include <linux/kprobes.h>
16#include <linux/kdebug.h>
17#include <linux/sched/debug.h>
18#include <linux/nmi.h>
19#include <linux/debugfs.h>
20#include <linux/delay.h>
21#include <linux/hardirq.h>
22#include <linux/ratelimit.h>
23#include <linux/slab.h>
24#include <linux/export.h>
25#include <linux/atomic.h>
26#include <linux/sched/clock.h>
27
28#include <asm/cpu_entry_area.h>
29#include <asm/traps.h>
30#include <asm/mach_traps.h>
31#include <asm/nmi.h>
32#include <asm/x86_init.h>
33#include <asm/reboot.h>
34#include <asm/cache.h>
35#include <asm/nospec-branch.h>
36#include <asm/microcode.h>
37#include <asm/sev.h>
38
39#define CREATE_TRACE_POINTS
40#include <trace/events/nmi.h>
41
42struct nmi_desc {
43 raw_spinlock_t lock;
44 struct list_head head;
45};
46
47static struct nmi_desc nmi_desc[NMI_MAX] =
48{
49 {
50 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[0].lock),
51 .head = LIST_HEAD_INIT(nmi_desc[0].head),
52 },
53 {
54 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock),
55 .head = LIST_HEAD_INIT(nmi_desc[1].head),
56 },
57 {
58 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[2].lock),
59 .head = LIST_HEAD_INIT(nmi_desc[2].head),
60 },
61 {
62 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock),
63 .head = LIST_HEAD_INIT(nmi_desc[3].head),
64 },
65
66};
67
68struct nmi_stats {
69 unsigned int normal;
70 unsigned int unknown;
71 unsigned int external;
72 unsigned int swallow;
73 unsigned long recv_jiffies;
74 unsigned long idt_seq;
75 unsigned long idt_nmi_seq;
76 unsigned long idt_ignored;
77 atomic_long_t idt_calls;
78 unsigned long idt_seq_snap;
79 unsigned long idt_nmi_seq_snap;
80 unsigned long idt_ignored_snap;
81 long idt_calls_snap;
82};
83
84static DEFINE_PER_CPU(struct nmi_stats, nmi_stats);
85
86static int ignore_nmis __read_mostly;
87
88int unknown_nmi_panic;
89/*
90 * Prevent NMI reason port (0x61) being accessed simultaneously, can
91 * only be used in NMI handler.
92 */
93static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
94
95static int __init setup_unknown_nmi_panic(char *str)
96{
97 unknown_nmi_panic = 1;
98 return 1;
99}
100__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
101
102#define nmi_to_desc(type) (&nmi_desc[type])
103
104static u64 nmi_longest_ns = 1 * NSEC_PER_MSEC;
105
106static int __init nmi_warning_debugfs(void)
107{
108 debugfs_create_u64("nmi_longest_ns", 0644,
109 arch_debugfs_dir, &nmi_longest_ns);
110 return 0;
111}
112fs_initcall(nmi_warning_debugfs);
113
114static void nmi_check_duration(struct nmiaction *action, u64 duration)
115{
116 int remainder_ns, decimal_msecs;
117
118 if (duration < nmi_longest_ns || duration < action->max_duration)
119 return;
120
121 action->max_duration = duration;
122
123 remainder_ns = do_div(duration, (1000 * 1000));
124 decimal_msecs = remainder_ns / 1000;
125
126 printk_ratelimited(KERN_INFO
127 "INFO: NMI handler (%ps) took too long to run: %lld.%03d msecs\n",
128 action->handler, duration, decimal_msecs);
129}
130
131static int nmi_handle(unsigned int type, struct pt_regs *regs)
132{
133 struct nmi_desc *desc = nmi_to_desc(type);
134 struct nmiaction *a;
135 int handled=0;
136
137 rcu_read_lock();
138
139 /*
140 * NMIs are edge-triggered, which means if you have enough
141 * of them concurrently, you can lose some because only one
142 * can be latched at any given time. Walk the whole list
143 * to handle those situations.
144 */
145 list_for_each_entry_rcu(a, &desc->head, list) {
146 int thishandled;
147 u64 delta;
148
149 delta = sched_clock();
150 thishandled = a->handler(type, regs);
151 handled += thishandled;
152 delta = sched_clock() - delta;
153 trace_nmi_handler(a->handler, (int)delta, thishandled);
154
155 nmi_check_duration(a, delta);
156 }
157
158 rcu_read_unlock();
159
160 /* return total number of NMI events handled */
161 return handled;
162}
163NOKPROBE_SYMBOL(nmi_handle);
164
165int __register_nmi_handler(unsigned int type, struct nmiaction *action)
166{
167 struct nmi_desc *desc = nmi_to_desc(type);
168 unsigned long flags;
169
170 if (WARN_ON_ONCE(!action->handler || !list_empty(&action->list)))
171 return -EINVAL;
172
173 raw_spin_lock_irqsave(&desc->lock, flags);
174
175 /*
176 * Indicate if there are multiple registrations on the
177 * internal NMI handler call chains (SERR and IO_CHECK).
178 */
179 WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head));
180 WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head));
181
182 /*
183 * some handlers need to be executed first otherwise a fake
184 * event confuses some handlers (kdump uses this flag)
185 */
186 if (action->flags & NMI_FLAG_FIRST)
187 list_add_rcu(&action->list, &desc->head);
188 else
189 list_add_tail_rcu(&action->list, &desc->head);
190
191 raw_spin_unlock_irqrestore(&desc->lock, flags);
192 return 0;
193}
194EXPORT_SYMBOL(__register_nmi_handler);
195
196void unregister_nmi_handler(unsigned int type, const char *name)
197{
198 struct nmi_desc *desc = nmi_to_desc(type);
199 struct nmiaction *n, *found = NULL;
200 unsigned long flags;
201
202 raw_spin_lock_irqsave(&desc->lock, flags);
203
204 list_for_each_entry_rcu(n, &desc->head, list) {
205 /*
206 * the name passed in to describe the nmi handler
207 * is used as the lookup key
208 */
209 if (!strcmp(n->name, name)) {
210 WARN(in_nmi(),
211 "Trying to free NMI (%s) from NMI context!\n", n->name);
212 list_del_rcu(&n->list);
213 found = n;
214 break;
215 }
216 }
217
218 raw_spin_unlock_irqrestore(&desc->lock, flags);
219 if (found) {
220 synchronize_rcu();
221 INIT_LIST_HEAD(&found->list);
222 }
223}
224EXPORT_SYMBOL_GPL(unregister_nmi_handler);
225
226static void
227pci_serr_error(unsigned char reason, struct pt_regs *regs)
228{
229 /* check to see if anyone registered against these types of errors */
230 if (nmi_handle(NMI_SERR, regs))
231 return;
232
233 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
234 reason, smp_processor_id());
235
236 if (panic_on_unrecovered_nmi)
237 nmi_panic(regs, "NMI: Not continuing");
238
239 pr_emerg("Dazed and confused, but trying to continue\n");
240
241 /* Clear and disable the PCI SERR error line. */
242 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR;
243 outb(reason, NMI_REASON_PORT);
244}
245NOKPROBE_SYMBOL(pci_serr_error);
246
247static void
248io_check_error(unsigned char reason, struct pt_regs *regs)
249{
250 unsigned long i;
251
252 /* check to see if anyone registered against these types of errors */
253 if (nmi_handle(NMI_IO_CHECK, regs))
254 return;
255
256 pr_emerg(
257 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
258 reason, smp_processor_id());
259 show_regs(regs);
260
261 if (panic_on_io_nmi) {
262 nmi_panic(regs, "NMI IOCK error: Not continuing");
263
264 /*
265 * If we end up here, it means we have received an NMI while
266 * processing panic(). Simply return without delaying and
267 * re-enabling NMIs.
268 */
269 return;
270 }
271
272 /* Re-enable the IOCK line, wait for a few seconds */
273 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK;
274 outb(reason, NMI_REASON_PORT);
275
276 i = 20000;
277 while (--i) {
278 touch_nmi_watchdog();
279 udelay(100);
280 }
281
282 reason &= ~NMI_REASON_CLEAR_IOCHK;
283 outb(reason, NMI_REASON_PORT);
284}
285NOKPROBE_SYMBOL(io_check_error);
286
287static void
288unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
289{
290 int handled;
291
292 /*
293 * Use 'false' as back-to-back NMIs are dealt with one level up.
294 * Of course this makes having multiple 'unknown' handlers useless
295 * as only the first one is ever run (unless it can actually determine
296 * if it caused the NMI)
297 */
298 handled = nmi_handle(NMI_UNKNOWN, regs);
299 if (handled) {
300 __this_cpu_add(nmi_stats.unknown, handled);
301 return;
302 }
303
304 __this_cpu_add(nmi_stats.unknown, 1);
305
306 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
307 reason, smp_processor_id());
308
309 if (unknown_nmi_panic || panic_on_unrecovered_nmi)
310 nmi_panic(regs, "NMI: Not continuing");
311
312 pr_emerg("Dazed and confused, but trying to continue\n");
313}
314NOKPROBE_SYMBOL(unknown_nmi_error);
315
316static DEFINE_PER_CPU(bool, swallow_nmi);
317static DEFINE_PER_CPU(unsigned long, last_nmi_rip);
318
319static noinstr void default_do_nmi(struct pt_regs *regs)
320{
321 unsigned char reason = 0;
322 int handled;
323 bool b2b = false;
324
325 /*
326 * CPU-specific NMI must be processed before non-CPU-specific
327 * NMI, otherwise we may lose it, because the CPU-specific
328 * NMI can not be detected/processed on other CPUs.
329 */
330
331 /*
332 * Back-to-back NMIs are interesting because they can either
333 * be two NMI or more than two NMIs (any thing over two is dropped
334 * due to NMI being edge-triggered). If this is the second half
335 * of the back-to-back NMI, assume we dropped things and process
336 * more handlers. Otherwise reset the 'swallow' NMI behaviour
337 */
338 if (regs->ip == __this_cpu_read(last_nmi_rip))
339 b2b = true;
340 else
341 __this_cpu_write(swallow_nmi, false);
342
343 __this_cpu_write(last_nmi_rip, regs->ip);
344
345 instrumentation_begin();
346
347 if (microcode_nmi_handler_enabled() && microcode_nmi_handler())
348 goto out;
349
350 handled = nmi_handle(NMI_LOCAL, regs);
351 __this_cpu_add(nmi_stats.normal, handled);
352 if (handled) {
353 /*
354 * There are cases when a NMI handler handles multiple
355 * events in the current NMI. One of these events may
356 * be queued for in the next NMI. Because the event is
357 * already handled, the next NMI will result in an unknown
358 * NMI. Instead lets flag this for a potential NMI to
359 * swallow.
360 */
361 if (handled > 1)
362 __this_cpu_write(swallow_nmi, true);
363 goto out;
364 }
365
366 /*
367 * Non-CPU-specific NMI: NMI sources can be processed on any CPU.
368 *
369 * Another CPU may be processing panic routines while holding
370 * nmi_reason_lock. Check if the CPU issued the IPI for crash dumping,
371 * and if so, call its callback directly. If there is no CPU preparing
372 * crash dump, we simply loop here.
373 */
374 while (!raw_spin_trylock(&nmi_reason_lock)) {
375 run_crash_ipi_callback(regs);
376 cpu_relax();
377 }
378
379 reason = x86_platform.get_nmi_reason();
380
381 if (reason & NMI_REASON_MASK) {
382 if (reason & NMI_REASON_SERR)
383 pci_serr_error(reason, regs);
384 else if (reason & NMI_REASON_IOCHK)
385 io_check_error(reason, regs);
386#ifdef CONFIG_X86_32
387 /*
388 * Reassert NMI in case it became active
389 * meanwhile as it's edge-triggered:
390 */
391 reassert_nmi();
392#endif
393 __this_cpu_add(nmi_stats.external, 1);
394 raw_spin_unlock(&nmi_reason_lock);
395 goto out;
396 }
397 raw_spin_unlock(&nmi_reason_lock);
398
399 /*
400 * Only one NMI can be latched at a time. To handle
401 * this we may process multiple nmi handlers at once to
402 * cover the case where an NMI is dropped. The downside
403 * to this approach is we may process an NMI prematurely,
404 * while its real NMI is sitting latched. This will cause
405 * an unknown NMI on the next run of the NMI processing.
406 *
407 * We tried to flag that condition above, by setting the
408 * swallow_nmi flag when we process more than one event.
409 * This condition is also only present on the second half
410 * of a back-to-back NMI, so we flag that condition too.
411 *
412 * If both are true, we assume we already processed this
413 * NMI previously and we swallow it. Otherwise we reset
414 * the logic.
415 *
416 * There are scenarios where we may accidentally swallow
417 * a 'real' unknown NMI. For example, while processing
418 * a perf NMI another perf NMI comes in along with a
419 * 'real' unknown NMI. These two NMIs get combined into
420 * one (as described above). When the next NMI gets
421 * processed, it will be flagged by perf as handled, but
422 * no one will know that there was a 'real' unknown NMI sent
423 * also. As a result it gets swallowed. Or if the first
424 * perf NMI returns two events handled then the second
425 * NMI will get eaten by the logic below, again losing a
426 * 'real' unknown NMI. But this is the best we can do
427 * for now.
428 */
429 if (b2b && __this_cpu_read(swallow_nmi))
430 __this_cpu_add(nmi_stats.swallow, 1);
431 else
432 unknown_nmi_error(reason, regs);
433
434out:
435 instrumentation_end();
436}
437
438/*
439 * NMIs can page fault or hit breakpoints which will cause it to lose
440 * its NMI context with the CPU when the breakpoint or page fault does an IRET.
441 *
442 * As a result, NMIs can nest if NMIs get unmasked due an IRET during
443 * NMI processing. On x86_64, the asm glue protects us from nested NMIs
444 * if the outer NMI came from kernel mode, but we can still nest if the
445 * outer NMI came from user mode.
446 *
447 * To handle these nested NMIs, we have three states:
448 *
449 * 1) not running
450 * 2) executing
451 * 3) latched
452 *
453 * When no NMI is in progress, it is in the "not running" state.
454 * When an NMI comes in, it goes into the "executing" state.
455 * Normally, if another NMI is triggered, it does not interrupt
456 * the running NMI and the HW will simply latch it so that when
457 * the first NMI finishes, it will restart the second NMI.
458 * (Note, the latch is binary, thus multiple NMIs triggering,
459 * when one is running, are ignored. Only one NMI is restarted.)
460 *
461 * If an NMI executes an iret, another NMI can preempt it. We do not
462 * want to allow this new NMI to run, but we want to execute it when the
463 * first one finishes. We set the state to "latched", and the exit of
464 * the first NMI will perform a dec_return, if the result is zero
465 * (NOT_RUNNING), then it will simply exit the NMI handler. If not, the
466 * dec_return would have set the state to NMI_EXECUTING (what we want it
467 * to be when we are running). In this case, we simply jump back to
468 * rerun the NMI handler again, and restart the 'latched' NMI.
469 *
470 * No trap (breakpoint or page fault) should be hit before nmi_restart,
471 * thus there is no race between the first check of state for NOT_RUNNING
472 * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs
473 * at this point.
474 *
475 * In case the NMI takes a page fault, we need to save off the CR2
476 * because the NMI could have preempted another page fault and corrupt
477 * the CR2 that is about to be read. As nested NMIs must be restarted
478 * and they can not take breakpoints or page faults, the update of the
479 * CR2 must be done before converting the nmi state back to NOT_RUNNING.
480 * Otherwise, there would be a race of another nested NMI coming in
481 * after setting state to NOT_RUNNING but before updating the nmi_cr2.
482 */
483enum nmi_states {
484 NMI_NOT_RUNNING = 0,
485 NMI_EXECUTING,
486 NMI_LATCHED,
487};
488static DEFINE_PER_CPU(enum nmi_states, nmi_state);
489static DEFINE_PER_CPU(unsigned long, nmi_cr2);
490static DEFINE_PER_CPU(unsigned long, nmi_dr7);
491
492DEFINE_IDTENTRY_RAW(exc_nmi)
493{
494 irqentry_state_t irq_state;
495 struct nmi_stats *nsp = this_cpu_ptr(&nmi_stats);
496
497 /*
498 * Re-enable NMIs right here when running as an SEV-ES guest. This might
499 * cause nested NMIs, but those can be handled safely.
500 */
501 sev_es_nmi_complete();
502 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU))
503 raw_atomic_long_inc(&nsp->idt_calls);
504
505 if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) {
506 if (microcode_nmi_handler_enabled())
507 microcode_offline_nmi_handler();
508 return;
509 }
510
511 if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) {
512 this_cpu_write(nmi_state, NMI_LATCHED);
513 return;
514 }
515 this_cpu_write(nmi_state, NMI_EXECUTING);
516 this_cpu_write(nmi_cr2, read_cr2());
517
518nmi_restart:
519 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) {
520 WRITE_ONCE(nsp->idt_seq, nsp->idt_seq + 1);
521 WARN_ON_ONCE(!(nsp->idt_seq & 0x1));
522 WRITE_ONCE(nsp->recv_jiffies, jiffies);
523 }
524
525 /*
526 * Needs to happen before DR7 is accessed, because the hypervisor can
527 * intercept DR7 reads/writes, turning those into #VC exceptions.
528 */
529 sev_es_ist_enter(regs);
530
531 this_cpu_write(nmi_dr7, local_db_save());
532
533 irq_state = irqentry_nmi_enter(regs);
534
535 inc_irq_stat(__nmi_count);
536
537 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU) && ignore_nmis) {
538 WRITE_ONCE(nsp->idt_ignored, nsp->idt_ignored + 1);
539 } else if (!ignore_nmis) {
540 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) {
541 WRITE_ONCE(nsp->idt_nmi_seq, nsp->idt_nmi_seq + 1);
542 WARN_ON_ONCE(!(nsp->idt_nmi_seq & 0x1));
543 }
544 default_do_nmi(regs);
545 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) {
546 WRITE_ONCE(nsp->idt_nmi_seq, nsp->idt_nmi_seq + 1);
547 WARN_ON_ONCE(nsp->idt_nmi_seq & 0x1);
548 }
549 }
550
551 irqentry_nmi_exit(regs, irq_state);
552
553 local_db_restore(this_cpu_read(nmi_dr7));
554
555 sev_es_ist_exit();
556
557 if (unlikely(this_cpu_read(nmi_cr2) != read_cr2()))
558 write_cr2(this_cpu_read(nmi_cr2));
559 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) {
560 WRITE_ONCE(nsp->idt_seq, nsp->idt_seq + 1);
561 WARN_ON_ONCE(nsp->idt_seq & 0x1);
562 WRITE_ONCE(nsp->recv_jiffies, jiffies);
563 }
564 if (this_cpu_dec_return(nmi_state))
565 goto nmi_restart;
566}
567
568#if IS_ENABLED(CONFIG_KVM_INTEL)
569DEFINE_IDTENTRY_RAW(exc_nmi_kvm_vmx)
570{
571 exc_nmi(regs);
572}
573#if IS_MODULE(CONFIG_KVM_INTEL)
574EXPORT_SYMBOL_GPL(asm_exc_nmi_kvm_vmx);
575#endif
576#endif
577
578#ifdef CONFIG_NMI_CHECK_CPU
579
580static char *nmi_check_stall_msg[] = {
581/* */
582/* +--------- nsp->idt_seq_snap & 0x1: CPU is in NMI handler. */
583/* | +------ cpu_is_offline(cpu) */
584/* | | +--- nsp->idt_calls_snap != atomic_long_read(&nsp->idt_calls): */
585/* | | | NMI handler has been invoked. */
586/* | | | */
587/* V V V */
588/* 0 0 0 */ "NMIs are not reaching exc_nmi() handler",
589/* 0 0 1 */ "exc_nmi() handler is ignoring NMIs",
590/* 0 1 0 */ "CPU is offline and NMIs are not reaching exc_nmi() handler",
591/* 0 1 1 */ "CPU is offline and exc_nmi() handler is legitimately ignoring NMIs",
592/* 1 0 0 */ "CPU is in exc_nmi() handler and no further NMIs are reaching handler",
593/* 1 0 1 */ "CPU is in exc_nmi() handler which is legitimately ignoring NMIs",
594/* 1 1 0 */ "CPU is offline in exc_nmi() handler and no more NMIs are reaching exc_nmi() handler",
595/* 1 1 1 */ "CPU is offline in exc_nmi() handler which is legitimately ignoring NMIs",
596};
597
598void nmi_backtrace_stall_snap(const struct cpumask *btp)
599{
600 int cpu;
601 struct nmi_stats *nsp;
602
603 for_each_cpu(cpu, btp) {
604 nsp = per_cpu_ptr(&nmi_stats, cpu);
605 nsp->idt_seq_snap = READ_ONCE(nsp->idt_seq);
606 nsp->idt_nmi_seq_snap = READ_ONCE(nsp->idt_nmi_seq);
607 nsp->idt_ignored_snap = READ_ONCE(nsp->idt_ignored);
608 nsp->idt_calls_snap = atomic_long_read(&nsp->idt_calls);
609 }
610}
611
612void nmi_backtrace_stall_check(const struct cpumask *btp)
613{
614 int cpu;
615 int idx;
616 unsigned long nmi_seq;
617 unsigned long j = jiffies;
618 char *modp;
619 char *msgp;
620 char *msghp;
621 struct nmi_stats *nsp;
622
623 for_each_cpu(cpu, btp) {
624 nsp = per_cpu_ptr(&nmi_stats, cpu);
625 modp = "";
626 msghp = "";
627 nmi_seq = READ_ONCE(nsp->idt_nmi_seq);
628 if (nsp->idt_nmi_seq_snap + 1 == nmi_seq && (nmi_seq & 0x1)) {
629 msgp = "CPU entered NMI handler function, but has not exited";
630 } else if ((nsp->idt_nmi_seq_snap & 0x1) != (nmi_seq & 0x1)) {
631 msgp = "CPU is handling NMIs";
632 } else {
633 idx = ((nsp->idt_seq_snap & 0x1) << 2) |
634 (cpu_is_offline(cpu) << 1) |
635 (nsp->idt_calls_snap != atomic_long_read(&nsp->idt_calls));
636 msgp = nmi_check_stall_msg[idx];
637 if (nsp->idt_ignored_snap != READ_ONCE(nsp->idt_ignored) && (idx & 0x1))
638 modp = ", but OK because ignore_nmis was set";
639 if (nmi_seq & ~0x1)
640 msghp = " (CPU currently in NMI handler function)";
641 else if (nsp->idt_nmi_seq_snap + 1 == nmi_seq)
642 msghp = " (CPU exited one NMI handler function)";
643 }
644 pr_alert("%s: CPU %d: %s%s%s, last activity: %lu jiffies ago.\n",
645 __func__, cpu, msgp, modp, msghp, j - READ_ONCE(nsp->recv_jiffies));
646 }
647}
648
649#endif
650
651void stop_nmi(void)
652{
653 ignore_nmis++;
654}
655
656void restart_nmi(void)
657{
658 ignore_nmis--;
659}
660
661/* reset the back-to-back NMI logic */
662void local_touch_nmi(void)
663{
664 __this_cpu_write(last_nmi_rip, 0);
665}
666EXPORT_SYMBOL_GPL(local_touch_nmi);