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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * linux/arch/x86_64/entry.S
4 *
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
8 *
9 * entry.S contains the system-call and fault low-level handling routines.
10 *
11 * Some of this is documented in Documentation/x86/entry_64.rst
12 *
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
16 *
17 * Some macro usage:
18 * - SYM_FUNC_START/END:Define functions in the symbol table.
19 * - idtentry: Define exception entry points.
20 */
21#include <linux/linkage.h>
22#include <asm/segment.h>
23#include <asm/cache.h>
24#include <asm/errno.h>
25#include <asm/asm-offsets.h>
26#include <asm/msr.h>
27#include <asm/unistd.h>
28#include <asm/thread_info.h>
29#include <asm/hw_irq.h>
30#include <asm/page_types.h>
31#include <asm/irqflags.h>
32#include <asm/paravirt.h>
33#include <asm/percpu.h>
34#include <asm/asm.h>
35#include <asm/smap.h>
36#include <asm/pgtable_types.h>
37#include <asm/export.h>
38#include <asm/frame.h>
39#include <asm/trapnr.h>
40#include <asm/nospec-branch.h>
41#include <asm/fsgsbase.h>
42#include <linux/err.h>
43
44#include "calling.h"
45
46.code64
47.section .entry.text, "ax"
48
49/*
50 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
51 *
52 * This is the only entry point used for 64-bit system calls. The
53 * hardware interface is reasonably well designed and the register to
54 * argument mapping Linux uses fits well with the registers that are
55 * available when SYSCALL is used.
56 *
57 * SYSCALL instructions can be found inlined in libc implementations as
58 * well as some other programs and libraries. There are also a handful
59 * of SYSCALL instructions in the vDSO used, for example, as a
60 * clock_gettimeofday fallback.
61 *
62 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
63 * then loads new ss, cs, and rip from previously programmed MSRs.
64 * rflags gets masked by a value from another MSR (so CLD and CLAC
65 * are not needed). SYSCALL does not save anything on the stack
66 * and does not change rsp.
67 *
68 * Registers on entry:
69 * rax system call number
70 * rcx return address
71 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
72 * rdi arg0
73 * rsi arg1
74 * rdx arg2
75 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
76 * r8 arg4
77 * r9 arg5
78 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
79 *
80 * Only called from user space.
81 *
82 * When user can change pt_regs->foo always force IRET. That is because
83 * it deals with uncanonical addresses better. SYSRET has trouble
84 * with them due to bugs in both AMD and Intel CPUs.
85 */
86
87SYM_CODE_START(entry_SYSCALL_64)
88 UNWIND_HINT_ENTRY
89 ENDBR
90
91 swapgs
92 /* tss.sp2 is scratch space. */
93 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2)
94 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
95 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp
96
97SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL)
98 ANNOTATE_NOENDBR
99
100 /* Construct struct pt_regs on stack */
101 pushq $__USER_DS /* pt_regs->ss */
102 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */
103 pushq %r11 /* pt_regs->flags */
104 pushq $__USER_CS /* pt_regs->cs */
105 pushq %rcx /* pt_regs->ip */
106SYM_INNER_LABEL(entry_SYSCALL_64_after_hwframe, SYM_L_GLOBAL)
107 pushq %rax /* pt_regs->orig_ax */
108
109 PUSH_AND_CLEAR_REGS rax=$-ENOSYS
110
111 /* IRQs are off. */
112 movq %rsp, %rdi
113 /* Sign extend the lower 32bit as syscall numbers are treated as int */
114 movslq %eax, %rsi
115
116 /* clobbers %rax, make sure it is after saving the syscall nr */
117 IBRS_ENTER
118 UNTRAIN_RET
119
120 call do_syscall_64 /* returns with IRQs disabled */
121
122 /*
123 * Try to use SYSRET instead of IRET if we're returning to
124 * a completely clean 64-bit userspace context. If we're not,
125 * go to the slow exit path.
126 * In the Xen PV case we must use iret anyway.
127 */
128
129 ALTERNATIVE "", "jmp swapgs_restore_regs_and_return_to_usermode", \
130 X86_FEATURE_XENPV
131
132 movq RCX(%rsp), %rcx
133 movq RIP(%rsp), %r11
134
135 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
136 jne swapgs_restore_regs_and_return_to_usermode
137
138 /*
139 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
140 * in kernel space. This essentially lets the user take over
141 * the kernel, since userspace controls RSP.
142 *
143 * If width of "canonical tail" ever becomes variable, this will need
144 * to be updated to remain correct on both old and new CPUs.
145 *
146 * Change top bits to match most significant bit (47th or 56th bit
147 * depending on paging mode) in the address.
148 */
149#ifdef CONFIG_X86_5LEVEL
150 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \
151 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57
152#else
153 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
154 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
155#endif
156
157 /* If this changed %rcx, it was not canonical */
158 cmpq %rcx, %r11
159 jne swapgs_restore_regs_and_return_to_usermode
160
161 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
162 jne swapgs_restore_regs_and_return_to_usermode
163
164 movq R11(%rsp), %r11
165 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
166 jne swapgs_restore_regs_and_return_to_usermode
167
168 /*
169 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
170 * restore RF properly. If the slowpath sets it for whatever reason, we
171 * need to restore it correctly.
172 *
173 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
174 * trap from userspace immediately after SYSRET. This would cause an
175 * infinite loop whenever #DB happens with register state that satisfies
176 * the opportunistic SYSRET conditions. For example, single-stepping
177 * this user code:
178 *
179 * movq $stuck_here, %rcx
180 * pushfq
181 * popq %r11
182 * stuck_here:
183 *
184 * would never get past 'stuck_here'.
185 */
186 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
187 jnz swapgs_restore_regs_and_return_to_usermode
188
189 /* nothing to check for RSP */
190
191 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
192 jne swapgs_restore_regs_and_return_to_usermode
193
194 /*
195 * We win! This label is here just for ease of understanding
196 * perf profiles. Nothing jumps here.
197 */
198syscall_return_via_sysret:
199 IBRS_EXIT
200 POP_REGS pop_rdi=0
201
202 /*
203 * Now all regs are restored except RSP and RDI.
204 * Save old stack pointer and switch to trampoline stack.
205 */
206 movq %rsp, %rdi
207 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
208 UNWIND_HINT_EMPTY
209
210 pushq RSP-RDI(%rdi) /* RSP */
211 pushq (%rdi) /* RDI */
212
213 /*
214 * We are on the trampoline stack. All regs except RDI are live.
215 * We can do future final exit work right here.
216 */
217 STACKLEAK_ERASE_NOCLOBBER
218
219 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
220
221 popq %rdi
222 popq %rsp
223SYM_INNER_LABEL(entry_SYSRETQ_unsafe_stack, SYM_L_GLOBAL)
224 ANNOTATE_NOENDBR
225 swapgs
226 sysretq
227SYM_INNER_LABEL(entry_SYSRETQ_end, SYM_L_GLOBAL)
228 ANNOTATE_NOENDBR
229 int3
230SYM_CODE_END(entry_SYSCALL_64)
231
232/*
233 * %rdi: prev task
234 * %rsi: next task
235 */
236.pushsection .text, "ax"
237SYM_FUNC_START(__switch_to_asm)
238 /*
239 * Save callee-saved registers
240 * This must match the order in inactive_task_frame
241 */
242 pushq %rbp
243 pushq %rbx
244 pushq %r12
245 pushq %r13
246 pushq %r14
247 pushq %r15
248
249 /* switch stack */
250 movq %rsp, TASK_threadsp(%rdi)
251 movq TASK_threadsp(%rsi), %rsp
252
253#ifdef CONFIG_STACKPROTECTOR
254 movq TASK_stack_canary(%rsi), %rbx
255 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + FIXED_stack_canary
256#endif
257
258 /*
259 * When switching from a shallower to a deeper call stack
260 * the RSB may either underflow or use entries populated
261 * with userspace addresses. On CPUs where those concerns
262 * exist, overwrite the RSB with entries which capture
263 * speculative execution to prevent attack.
264 */
265 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
266
267 /* restore callee-saved registers */
268 popq %r15
269 popq %r14
270 popq %r13
271 popq %r12
272 popq %rbx
273 popq %rbp
274
275 jmp __switch_to
276SYM_FUNC_END(__switch_to_asm)
277.popsection
278
279/*
280 * A newly forked process directly context switches into this address.
281 *
282 * rax: prev task we switched from
283 * rbx: kernel thread func (NULL for user thread)
284 * r12: kernel thread arg
285 */
286.pushsection .text, "ax"
287 __FUNC_ALIGN
288SYM_CODE_START_NOALIGN(ret_from_fork)
289 UNWIND_HINT_EMPTY
290 ANNOTATE_NOENDBR // copy_thread
291 CALL_DEPTH_ACCOUNT
292 movq %rax, %rdi
293 call schedule_tail /* rdi: 'prev' task parameter */
294
295 testq %rbx, %rbx /* from kernel_thread? */
296 jnz 1f /* kernel threads are uncommon */
297
2982:
299 UNWIND_HINT_REGS
300 movq %rsp, %rdi
301 call syscall_exit_to_user_mode /* returns with IRQs disabled */
302 jmp swapgs_restore_regs_and_return_to_usermode
303
3041:
305 /* kernel thread */
306 UNWIND_HINT_EMPTY
307 movq %r12, %rdi
308 CALL_NOSPEC rbx
309 /*
310 * A kernel thread is allowed to return here after successfully
311 * calling kernel_execve(). Exit to userspace to complete the execve()
312 * syscall.
313 */
314 movq $0, RAX(%rsp)
315 jmp 2b
316SYM_CODE_END(ret_from_fork)
317.popsection
318
319.macro DEBUG_ENTRY_ASSERT_IRQS_OFF
320#ifdef CONFIG_DEBUG_ENTRY
321 pushq %rax
322 SAVE_FLAGS
323 testl $X86_EFLAGS_IF, %eax
324 jz .Lokay_\@
325 ud2
326.Lokay_\@:
327 popq %rax
328#endif
329.endm
330
331SYM_CODE_START(xen_error_entry)
332 ANNOTATE_NOENDBR
333 UNWIND_HINT_FUNC
334 PUSH_AND_CLEAR_REGS save_ret=1
335 ENCODE_FRAME_POINTER 8
336 UNTRAIN_RET_FROM_CALL
337 RET
338SYM_CODE_END(xen_error_entry)
339
340/**
341 * idtentry_body - Macro to emit code calling the C function
342 * @cfunc: C function to be called
343 * @has_error_code: Hardware pushed error code on stack
344 */
345.macro idtentry_body cfunc has_error_code:req
346
347 /*
348 * Call error_entry() and switch to the task stack if from userspace.
349 *
350 * When in XENPV, it is already in the task stack, and it can't fault
351 * for native_iret() nor native_load_gs_index() since XENPV uses its
352 * own pvops for IRET and load_gs_index(). And it doesn't need to
353 * switch the CR3. So it can skip invoking error_entry().
354 */
355 ALTERNATIVE "call error_entry; movq %rax, %rsp", \
356 "call xen_error_entry", X86_FEATURE_XENPV
357
358 ENCODE_FRAME_POINTER
359 UNWIND_HINT_REGS
360
361 movq %rsp, %rdi /* pt_regs pointer into 1st argument*/
362
363 .if \has_error_code == 1
364 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
365 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
366 .endif
367
368 call \cfunc
369
370 /* For some configurations \cfunc ends up being a noreturn. */
371 REACHABLE
372
373 jmp error_return
374.endm
375
376/**
377 * idtentry - Macro to generate entry stubs for simple IDT entries
378 * @vector: Vector number
379 * @asmsym: ASM symbol for the entry point
380 * @cfunc: C function to be called
381 * @has_error_code: Hardware pushed error code on stack
382 *
383 * The macro emits code to set up the kernel context for straight forward
384 * and simple IDT entries. No IST stack, no paranoid entry checks.
385 */
386.macro idtentry vector asmsym cfunc has_error_code:req
387SYM_CODE_START(\asmsym)
388 UNWIND_HINT_IRET_REGS offset=\has_error_code*8
389 ENDBR
390 ASM_CLAC
391 cld
392
393 .if \has_error_code == 0
394 pushq $-1 /* ORIG_RAX: no syscall to restart */
395 .endif
396
397 .if \vector == X86_TRAP_BP
398 /*
399 * If coming from kernel space, create a 6-word gap to allow the
400 * int3 handler to emulate a call instruction.
401 */
402 testb $3, CS-ORIG_RAX(%rsp)
403 jnz .Lfrom_usermode_no_gap_\@
404 .rept 6
405 pushq 5*8(%rsp)
406 .endr
407 UNWIND_HINT_IRET_REGS offset=8
408.Lfrom_usermode_no_gap_\@:
409 .endif
410
411 idtentry_body \cfunc \has_error_code
412
413_ASM_NOKPROBE(\asmsym)
414SYM_CODE_END(\asmsym)
415.endm
416
417/*
418 * Interrupt entry/exit.
419 *
420 + The interrupt stubs push (vector) onto the stack, which is the error_code
421 * position of idtentry exceptions, and jump to one of the two idtentry points
422 * (common/spurious).
423 *
424 * common_interrupt is a hotpath, align it to a cache line
425 */
426.macro idtentry_irq vector cfunc
427 .p2align CONFIG_X86_L1_CACHE_SHIFT
428 idtentry \vector asm_\cfunc \cfunc has_error_code=1
429.endm
430
431/*
432 * System vectors which invoke their handlers directly and are not
433 * going through the regular common device interrupt handling code.
434 */
435.macro idtentry_sysvec vector cfunc
436 idtentry \vector asm_\cfunc \cfunc has_error_code=0
437.endm
438
439/**
440 * idtentry_mce_db - Macro to generate entry stubs for #MC and #DB
441 * @vector: Vector number
442 * @asmsym: ASM symbol for the entry point
443 * @cfunc: C function to be called
444 *
445 * The macro emits code to set up the kernel context for #MC and #DB
446 *
447 * If the entry comes from user space it uses the normal entry path
448 * including the return to user space work and preemption checks on
449 * exit.
450 *
451 * If hits in kernel mode then it needs to go through the paranoid
452 * entry as the exception can hit any random state. No preemption
453 * check on exit to keep the paranoid path simple.
454 */
455.macro idtentry_mce_db vector asmsym cfunc
456SYM_CODE_START(\asmsym)
457 UNWIND_HINT_IRET_REGS
458 ENDBR
459 ASM_CLAC
460 cld
461
462 pushq $-1 /* ORIG_RAX: no syscall to restart */
463
464 /*
465 * If the entry is from userspace, switch stacks and treat it as
466 * a normal entry.
467 */
468 testb $3, CS-ORIG_RAX(%rsp)
469 jnz .Lfrom_usermode_switch_stack_\@
470
471 /* paranoid_entry returns GS information for paranoid_exit in EBX. */
472 call paranoid_entry
473
474 UNWIND_HINT_REGS
475
476 movq %rsp, %rdi /* pt_regs pointer */
477
478 call \cfunc
479
480 jmp paranoid_exit
481
482 /* Switch to the regular task stack and use the noist entry point */
483.Lfrom_usermode_switch_stack_\@:
484 idtentry_body noist_\cfunc, has_error_code=0
485
486_ASM_NOKPROBE(\asmsym)
487SYM_CODE_END(\asmsym)
488.endm
489
490#ifdef CONFIG_AMD_MEM_ENCRYPT
491/**
492 * idtentry_vc - Macro to generate entry stub for #VC
493 * @vector: Vector number
494 * @asmsym: ASM symbol for the entry point
495 * @cfunc: C function to be called
496 *
497 * The macro emits code to set up the kernel context for #VC. The #VC handler
498 * runs on an IST stack and needs to be able to cause nested #VC exceptions.
499 *
500 * To make this work the #VC entry code tries its best to pretend it doesn't use
501 * an IST stack by switching to the task stack if coming from user-space (which
502 * includes early SYSCALL entry path) or back to the stack in the IRET frame if
503 * entered from kernel-mode.
504 *
505 * If entered from kernel-mode the return stack is validated first, and if it is
506 * not safe to use (e.g. because it points to the entry stack) the #VC handler
507 * will switch to a fall-back stack (VC2) and call a special handler function.
508 *
509 * The macro is only used for one vector, but it is planned to be extended in
510 * the future for the #HV exception.
511 */
512.macro idtentry_vc vector asmsym cfunc
513SYM_CODE_START(\asmsym)
514 UNWIND_HINT_IRET_REGS
515 ENDBR
516 ASM_CLAC
517 cld
518
519 /*
520 * If the entry is from userspace, switch stacks and treat it as
521 * a normal entry.
522 */
523 testb $3, CS-ORIG_RAX(%rsp)
524 jnz .Lfrom_usermode_switch_stack_\@
525
526 /*
527 * paranoid_entry returns SWAPGS flag for paranoid_exit in EBX.
528 * EBX == 0 -> SWAPGS, EBX == 1 -> no SWAPGS
529 */
530 call paranoid_entry
531
532 UNWIND_HINT_REGS
533
534 /*
535 * Switch off the IST stack to make it free for nested exceptions. The
536 * vc_switch_off_ist() function will switch back to the interrupted
537 * stack if it is safe to do so. If not it switches to the VC fall-back
538 * stack.
539 */
540 movq %rsp, %rdi /* pt_regs pointer */
541 call vc_switch_off_ist
542 movq %rax, %rsp /* Switch to new stack */
543
544 ENCODE_FRAME_POINTER
545 UNWIND_HINT_REGS
546
547 /* Update pt_regs */
548 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
549 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
550
551 movq %rsp, %rdi /* pt_regs pointer */
552
553 call kernel_\cfunc
554
555 /*
556 * No need to switch back to the IST stack. The current stack is either
557 * identical to the stack in the IRET frame or the VC fall-back stack,
558 * so it is definitely mapped even with PTI enabled.
559 */
560 jmp paranoid_exit
561
562 /* Switch to the regular task stack */
563.Lfrom_usermode_switch_stack_\@:
564 idtentry_body user_\cfunc, has_error_code=1
565
566_ASM_NOKPROBE(\asmsym)
567SYM_CODE_END(\asmsym)
568.endm
569#endif
570
571/*
572 * Double fault entry. Straight paranoid. No checks from which context
573 * this comes because for the espfix induced #DF this would do the wrong
574 * thing.
575 */
576.macro idtentry_df vector asmsym cfunc
577SYM_CODE_START(\asmsym)
578 UNWIND_HINT_IRET_REGS offset=8
579 ENDBR
580 ASM_CLAC
581 cld
582
583 /* paranoid_entry returns GS information for paranoid_exit in EBX. */
584 call paranoid_entry
585 UNWIND_HINT_REGS
586
587 movq %rsp, %rdi /* pt_regs pointer into first argument */
588 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
589 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
590 call \cfunc
591
592 /* For some configurations \cfunc ends up being a noreturn. */
593 REACHABLE
594
595 jmp paranoid_exit
596
597_ASM_NOKPROBE(\asmsym)
598SYM_CODE_END(\asmsym)
599.endm
600
601/*
602 * Include the defines which emit the idt entries which are shared
603 * shared between 32 and 64 bit and emit the __irqentry_text_* markers
604 * so the stacktrace boundary checks work.
605 */
606 __ALIGN
607 .globl __irqentry_text_start
608__irqentry_text_start:
609
610#include <asm/idtentry.h>
611
612 __ALIGN
613 .globl __irqentry_text_end
614__irqentry_text_end:
615 ANNOTATE_NOENDBR
616
617SYM_CODE_START_LOCAL(common_interrupt_return)
618SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL)
619 IBRS_EXIT
620#ifdef CONFIG_DEBUG_ENTRY
621 /* Assert that pt_regs indicates user mode. */
622 testb $3, CS(%rsp)
623 jnz 1f
624 ud2
6251:
626#endif
627#ifdef CONFIG_XEN_PV
628 ALTERNATIVE "", "jmp xenpv_restore_regs_and_return_to_usermode", X86_FEATURE_XENPV
629#endif
630
631 POP_REGS pop_rdi=0
632
633 /*
634 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
635 * Save old stack pointer and switch to trampoline stack.
636 */
637 movq %rsp, %rdi
638 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
639 UNWIND_HINT_EMPTY
640
641 /* Copy the IRET frame to the trampoline stack. */
642 pushq 6*8(%rdi) /* SS */
643 pushq 5*8(%rdi) /* RSP */
644 pushq 4*8(%rdi) /* EFLAGS */
645 pushq 3*8(%rdi) /* CS */
646 pushq 2*8(%rdi) /* RIP */
647
648 /* Push user RDI on the trampoline stack. */
649 pushq (%rdi)
650
651 /*
652 * We are on the trampoline stack. All regs except RDI are live.
653 * We can do future final exit work right here.
654 */
655 STACKLEAK_ERASE_NOCLOBBER
656
657 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
658
659 /* Restore RDI. */
660 popq %rdi
661 swapgs
662 jmp .Lnative_iret
663
664
665SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL)
666#ifdef CONFIG_DEBUG_ENTRY
667 /* Assert that pt_regs indicates kernel mode. */
668 testb $3, CS(%rsp)
669 jz 1f
670 ud2
6711:
672#endif
673 POP_REGS
674 addq $8, %rsp /* skip regs->orig_ax */
675 /*
676 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
677 * when returning from IPI handler.
678 */
679#ifdef CONFIG_XEN_PV
680SYM_INNER_LABEL(early_xen_iret_patch, SYM_L_GLOBAL)
681 ANNOTATE_NOENDBR
682 .byte 0xe9
683 .long .Lnative_iret - (. + 4)
684#endif
685
686.Lnative_iret:
687 UNWIND_HINT_IRET_REGS
688 /*
689 * Are we returning to a stack segment from the LDT? Note: in
690 * 64-bit mode SS:RSP on the exception stack is always valid.
691 */
692#ifdef CONFIG_X86_ESPFIX64
693 testb $4, (SS-RIP)(%rsp)
694 jnz native_irq_return_ldt
695#endif
696
697SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL)
698 ANNOTATE_NOENDBR // exc_double_fault
699 /*
700 * This may fault. Non-paranoid faults on return to userspace are
701 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
702 * Double-faults due to espfix64 are handled in exc_double_fault.
703 * Other faults here are fatal.
704 */
705 iretq
706
707#ifdef CONFIG_X86_ESPFIX64
708native_irq_return_ldt:
709 /*
710 * We are running with user GSBASE. All GPRs contain their user
711 * values. We have a percpu ESPFIX stack that is eight slots
712 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
713 * of the ESPFIX stack.
714 *
715 * We clobber RAX and RDI in this code. We stash RDI on the
716 * normal stack and RAX on the ESPFIX stack.
717 *
718 * The ESPFIX stack layout we set up looks like this:
719 *
720 * --- top of ESPFIX stack ---
721 * SS
722 * RSP
723 * RFLAGS
724 * CS
725 * RIP <-- RSP points here when we're done
726 * RAX <-- espfix_waddr points here
727 * --- bottom of ESPFIX stack ---
728 */
729
730 pushq %rdi /* Stash user RDI */
731 swapgs /* to kernel GS */
732 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
733
734 movq PER_CPU_VAR(espfix_waddr), %rdi
735 movq %rax, (0*8)(%rdi) /* user RAX */
736 movq (1*8)(%rsp), %rax /* user RIP */
737 movq %rax, (1*8)(%rdi)
738 movq (2*8)(%rsp), %rax /* user CS */
739 movq %rax, (2*8)(%rdi)
740 movq (3*8)(%rsp), %rax /* user RFLAGS */
741 movq %rax, (3*8)(%rdi)
742 movq (5*8)(%rsp), %rax /* user SS */
743 movq %rax, (5*8)(%rdi)
744 movq (4*8)(%rsp), %rax /* user RSP */
745 movq %rax, (4*8)(%rdi)
746 /* Now RAX == RSP. */
747
748 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
749
750 /*
751 * espfix_stack[31:16] == 0. The page tables are set up such that
752 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
753 * espfix_waddr for any X. That is, there are 65536 RO aliases of
754 * the same page. Set up RSP so that RSP[31:16] contains the
755 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
756 * still points to an RO alias of the ESPFIX stack.
757 */
758 orq PER_CPU_VAR(espfix_stack), %rax
759
760 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
761 swapgs /* to user GS */
762 popq %rdi /* Restore user RDI */
763
764 movq %rax, %rsp
765 UNWIND_HINT_IRET_REGS offset=8
766
767 /*
768 * At this point, we cannot write to the stack any more, but we can
769 * still read.
770 */
771 popq %rax /* Restore user RAX */
772
773 /*
774 * RSP now points to an ordinary IRET frame, except that the page
775 * is read-only and RSP[31:16] are preloaded with the userspace
776 * values. We can now IRET back to userspace.
777 */
778 jmp native_irq_return_iret
779#endif
780SYM_CODE_END(common_interrupt_return)
781_ASM_NOKPROBE(common_interrupt_return)
782
783/*
784 * Reload gs selector with exception handling
785 * edi: new selector
786 *
787 * Is in entry.text as it shouldn't be instrumented.
788 */
789SYM_FUNC_START(asm_load_gs_index)
790 FRAME_BEGIN
791 swapgs
792.Lgs_change:
793 ANNOTATE_NOENDBR // error_entry
794 movl %edi, %gs
7952: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
796 swapgs
797 FRAME_END
798 RET
799
800 /* running with kernelgs */
801.Lbad_gs:
802 swapgs /* switch back to user gs */
803.macro ZAP_GS
804 /* This can't be a string because the preprocessor needs to see it. */
805 movl $__USER_DS, %eax
806 movl %eax, %gs
807.endm
808 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
809 xorl %eax, %eax
810 movl %eax, %gs
811 jmp 2b
812
813 _ASM_EXTABLE(.Lgs_change, .Lbad_gs)
814
815SYM_FUNC_END(asm_load_gs_index)
816EXPORT_SYMBOL(asm_load_gs_index)
817
818#ifdef CONFIG_XEN_PV
819/*
820 * A note on the "critical region" in our callback handler.
821 * We want to avoid stacking callback handlers due to events occurring
822 * during handling of the last event. To do this, we keep events disabled
823 * until we've done all processing. HOWEVER, we must enable events before
824 * popping the stack frame (can't be done atomically) and so it would still
825 * be possible to get enough handler activations to overflow the stack.
826 * Although unlikely, bugs of that kind are hard to track down, so we'd
827 * like to avoid the possibility.
828 * So, on entry to the handler we detect whether we interrupted an
829 * existing activation in its critical region -- if so, we pop the current
830 * activation and restart the handler using the previous one.
831 *
832 * C calling convention: exc_xen_hypervisor_callback(struct *pt_regs)
833 */
834 __FUNC_ALIGN
835SYM_CODE_START_LOCAL_NOALIGN(exc_xen_hypervisor_callback)
836
837/*
838 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
839 * see the correct pointer to the pt_regs
840 */
841 UNWIND_HINT_FUNC
842 movq %rdi, %rsp /* we don't return, adjust the stack frame */
843 UNWIND_HINT_REGS
844
845 call xen_pv_evtchn_do_upcall
846
847 jmp error_return
848SYM_CODE_END(exc_xen_hypervisor_callback)
849
850/*
851 * Hypervisor uses this for application faults while it executes.
852 * We get here for two reasons:
853 * 1. Fault while reloading DS, ES, FS or GS
854 * 2. Fault while executing IRET
855 * Category 1 we do not need to fix up as Xen has already reloaded all segment
856 * registers that could be reloaded and zeroed the others.
857 * Category 2 we fix up by killing the current process. We cannot use the
858 * normal Linux return path in this case because if we use the IRET hypercall
859 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
860 * We distinguish between categories by comparing each saved segment register
861 * with its current contents: any discrepancy means we in category 1.
862 */
863 __FUNC_ALIGN
864SYM_CODE_START_NOALIGN(xen_failsafe_callback)
865 UNWIND_HINT_EMPTY
866 ENDBR
867 movl %ds, %ecx
868 cmpw %cx, 0x10(%rsp)
869 jne 1f
870 movl %es, %ecx
871 cmpw %cx, 0x18(%rsp)
872 jne 1f
873 movl %fs, %ecx
874 cmpw %cx, 0x20(%rsp)
875 jne 1f
876 movl %gs, %ecx
877 cmpw %cx, 0x28(%rsp)
878 jne 1f
879 /* All segments match their saved values => Category 2 (Bad IRET). */
880 movq (%rsp), %rcx
881 movq 8(%rsp), %r11
882 addq $0x30, %rsp
883 pushq $0 /* RIP */
884 UNWIND_HINT_IRET_REGS offset=8
885 jmp asm_exc_general_protection
8861: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
887 movq (%rsp), %rcx
888 movq 8(%rsp), %r11
889 addq $0x30, %rsp
890 UNWIND_HINT_IRET_REGS
891 pushq $-1 /* orig_ax = -1 => not a system call */
892 PUSH_AND_CLEAR_REGS
893 ENCODE_FRAME_POINTER
894 jmp error_return
895SYM_CODE_END(xen_failsafe_callback)
896#endif /* CONFIG_XEN_PV */
897
898/*
899 * Save all registers in pt_regs. Return GSBASE related information
900 * in EBX depending on the availability of the FSGSBASE instructions:
901 *
902 * FSGSBASE R/EBX
903 * N 0 -> SWAPGS on exit
904 * 1 -> no SWAPGS on exit
905 *
906 * Y GSBASE value at entry, must be restored in paranoid_exit
907 *
908 * R14 - old CR3
909 * R15 - old SPEC_CTRL
910 */
911SYM_CODE_START(paranoid_entry)
912 ANNOTATE_NOENDBR
913 UNWIND_HINT_FUNC
914 PUSH_AND_CLEAR_REGS save_ret=1
915 ENCODE_FRAME_POINTER 8
916
917 /*
918 * Always stash CR3 in %r14. This value will be restored,
919 * verbatim, at exit. Needed if paranoid_entry interrupted
920 * another entry that already switched to the user CR3 value
921 * but has not yet returned to userspace.
922 *
923 * This is also why CS (stashed in the "iret frame" by the
924 * hardware at entry) can not be used: this may be a return
925 * to kernel code, but with a user CR3 value.
926 *
927 * Switching CR3 does not depend on kernel GSBASE so it can
928 * be done before switching to the kernel GSBASE. This is
929 * required for FSGSBASE because the kernel GSBASE has to
930 * be retrieved from a kernel internal table.
931 */
932 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
933
934 /*
935 * Handling GSBASE depends on the availability of FSGSBASE.
936 *
937 * Without FSGSBASE the kernel enforces that negative GSBASE
938 * values indicate kernel GSBASE. With FSGSBASE no assumptions
939 * can be made about the GSBASE value when entering from user
940 * space.
941 */
942 ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE
943
944 /*
945 * Read the current GSBASE and store it in %rbx unconditionally,
946 * retrieve and set the current CPUs kernel GSBASE. The stored value
947 * has to be restored in paranoid_exit unconditionally.
948 *
949 * The unconditional write to GS base below ensures that no subsequent
950 * loads based on a mispredicted GS base can happen, therefore no LFENCE
951 * is needed here.
952 */
953 SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx
954 jmp .Lparanoid_gsbase_done
955
956.Lparanoid_entry_checkgs:
957 /* EBX = 1 -> kernel GSBASE active, no restore required */
958 movl $1, %ebx
959
960 /*
961 * The kernel-enforced convention is a negative GSBASE indicates
962 * a kernel value. No SWAPGS needed on entry and exit.
963 */
964 movl $MSR_GS_BASE, %ecx
965 rdmsr
966 testl %edx, %edx
967 js .Lparanoid_kernel_gsbase
968
969 /* EBX = 0 -> SWAPGS required on exit */
970 xorl %ebx, %ebx
971 swapgs
972.Lparanoid_kernel_gsbase:
973 FENCE_SWAPGS_KERNEL_ENTRY
974.Lparanoid_gsbase_done:
975
976 /*
977 * Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like
978 * CR3 above, keep the old value in a callee saved register.
979 */
980 IBRS_ENTER save_reg=%r15
981 UNTRAIN_RET_FROM_CALL
982
983 RET
984SYM_CODE_END(paranoid_entry)
985
986/*
987 * "Paranoid" exit path from exception stack. This is invoked
988 * only on return from non-NMI IST interrupts that came
989 * from kernel space.
990 *
991 * We may be returning to very strange contexts (e.g. very early
992 * in syscall entry), so checking for preemption here would
993 * be complicated. Fortunately, there's no good reason to try
994 * to handle preemption here.
995 *
996 * R/EBX contains the GSBASE related information depending on the
997 * availability of the FSGSBASE instructions:
998 *
999 * FSGSBASE R/EBX
1000 * N 0 -> SWAPGS on exit
1001 * 1 -> no SWAPGS on exit
1002 *
1003 * Y User space GSBASE, must be restored unconditionally
1004 *
1005 * R14 - old CR3
1006 * R15 - old SPEC_CTRL
1007 */
1008SYM_CODE_START_LOCAL(paranoid_exit)
1009 UNWIND_HINT_REGS
1010
1011 /*
1012 * Must restore IBRS state before both CR3 and %GS since we need access
1013 * to the per-CPU x86_spec_ctrl_shadow variable.
1014 */
1015 IBRS_EXIT save_reg=%r15
1016
1017 /*
1018 * The order of operations is important. RESTORE_CR3 requires
1019 * kernel GSBASE.
1020 *
1021 * NB to anyone to try to optimize this code: this code does
1022 * not execute at all for exceptions from user mode. Those
1023 * exceptions go through error_exit instead.
1024 */
1025 RESTORE_CR3 scratch_reg=%rax save_reg=%r14
1026
1027 /* Handle the three GSBASE cases */
1028 ALTERNATIVE "jmp .Lparanoid_exit_checkgs", "", X86_FEATURE_FSGSBASE
1029
1030 /* With FSGSBASE enabled, unconditionally restore GSBASE */
1031 wrgsbase %rbx
1032 jmp restore_regs_and_return_to_kernel
1033
1034.Lparanoid_exit_checkgs:
1035 /* On non-FSGSBASE systems, conditionally do SWAPGS */
1036 testl %ebx, %ebx
1037 jnz restore_regs_and_return_to_kernel
1038
1039 /* We are returning to a context with user GSBASE */
1040 swapgs
1041 jmp restore_regs_and_return_to_kernel
1042SYM_CODE_END(paranoid_exit)
1043
1044/*
1045 * Switch GS and CR3 if needed.
1046 */
1047SYM_CODE_START(error_entry)
1048 ANNOTATE_NOENDBR
1049 UNWIND_HINT_FUNC
1050
1051 PUSH_AND_CLEAR_REGS save_ret=1
1052 ENCODE_FRAME_POINTER 8
1053
1054 testb $3, CS+8(%rsp)
1055 jz .Lerror_kernelspace
1056
1057 /*
1058 * We entered from user mode or we're pretending to have entered
1059 * from user mode due to an IRET fault.
1060 */
1061 swapgs
1062 FENCE_SWAPGS_USER_ENTRY
1063 /* We have user CR3. Change to kernel CR3. */
1064 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1065 IBRS_ENTER
1066 UNTRAIN_RET_FROM_CALL
1067
1068 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
1069 /* Put us onto the real thread stack. */
1070 jmp sync_regs
1071
1072 /*
1073 * There are two places in the kernel that can potentially fault with
1074 * usergs. Handle them here. B stepping K8s sometimes report a
1075 * truncated RIP for IRET exceptions returning to compat mode. Check
1076 * for these here too.
1077 */
1078.Lerror_kernelspace:
1079 leaq native_irq_return_iret(%rip), %rcx
1080 cmpq %rcx, RIP+8(%rsp)
1081 je .Lerror_bad_iret
1082 movl %ecx, %eax /* zero extend */
1083 cmpq %rax, RIP+8(%rsp)
1084 je .Lbstep_iret
1085 cmpq $.Lgs_change, RIP+8(%rsp)
1086 jne .Lerror_entry_done_lfence
1087
1088 /*
1089 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1090 * gsbase and proceed. We'll fix up the exception and land in
1091 * .Lgs_change's error handler with kernel gsbase.
1092 */
1093 swapgs
1094
1095 /*
1096 * Issue an LFENCE to prevent GS speculation, regardless of whether it is a
1097 * kernel or user gsbase.
1098 */
1099.Lerror_entry_done_lfence:
1100 FENCE_SWAPGS_KERNEL_ENTRY
1101 CALL_DEPTH_ACCOUNT
1102 leaq 8(%rsp), %rax /* return pt_regs pointer */
1103 ANNOTATE_UNRET_END
1104 RET
1105
1106.Lbstep_iret:
1107 /* Fix truncated RIP */
1108 movq %rcx, RIP+8(%rsp)
1109 /* fall through */
1110
1111.Lerror_bad_iret:
1112 /*
1113 * We came from an IRET to user mode, so we have user
1114 * gsbase and CR3. Switch to kernel gsbase and CR3:
1115 */
1116 swapgs
1117 FENCE_SWAPGS_USER_ENTRY
1118 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1119 IBRS_ENTER
1120 UNTRAIN_RET_FROM_CALL
1121
1122 /*
1123 * Pretend that the exception came from user mode: set up pt_regs
1124 * as if we faulted immediately after IRET.
1125 */
1126 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
1127 call fixup_bad_iret
1128 mov %rax, %rdi
1129 jmp sync_regs
1130SYM_CODE_END(error_entry)
1131
1132SYM_CODE_START_LOCAL(error_return)
1133 UNWIND_HINT_REGS
1134 DEBUG_ENTRY_ASSERT_IRQS_OFF
1135 testb $3, CS(%rsp)
1136 jz restore_regs_and_return_to_kernel
1137 jmp swapgs_restore_regs_and_return_to_usermode
1138SYM_CODE_END(error_return)
1139
1140/*
1141 * Runs on exception stack. Xen PV does not go through this path at all,
1142 * so we can use real assembly here.
1143 *
1144 * Registers:
1145 * %r14: Used to save/restore the CR3 of the interrupted context
1146 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1147 */
1148SYM_CODE_START(asm_exc_nmi)
1149 UNWIND_HINT_IRET_REGS
1150 ENDBR
1151
1152 /*
1153 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1154 * the iretq it performs will take us out of NMI context.
1155 * This means that we can have nested NMIs where the next
1156 * NMI is using the top of the stack of the previous NMI. We
1157 * can't let it execute because the nested NMI will corrupt the
1158 * stack of the previous NMI. NMI handlers are not re-entrant
1159 * anyway.
1160 *
1161 * To handle this case we do the following:
1162 * Check the a special location on the stack that contains
1163 * a variable that is set when NMIs are executing.
1164 * The interrupted task's stack is also checked to see if it
1165 * is an NMI stack.
1166 * If the variable is not set and the stack is not the NMI
1167 * stack then:
1168 * o Set the special variable on the stack
1169 * o Copy the interrupt frame into an "outermost" location on the
1170 * stack
1171 * o Copy the interrupt frame into an "iret" location on the stack
1172 * o Continue processing the NMI
1173 * If the variable is set or the previous stack is the NMI stack:
1174 * o Modify the "iret" location to jump to the repeat_nmi
1175 * o return back to the first NMI
1176 *
1177 * Now on exit of the first NMI, we first clear the stack variable
1178 * The NMI stack will tell any nested NMIs at that point that it is
1179 * nested. Then we pop the stack normally with iret, and if there was
1180 * a nested NMI that updated the copy interrupt stack frame, a
1181 * jump will be made to the repeat_nmi code that will handle the second
1182 * NMI.
1183 *
1184 * However, espfix prevents us from directly returning to userspace
1185 * with a single IRET instruction. Similarly, IRET to user mode
1186 * can fault. We therefore handle NMIs from user space like
1187 * other IST entries.
1188 */
1189
1190 ASM_CLAC
1191 cld
1192
1193 /* Use %rdx as our temp variable throughout */
1194 pushq %rdx
1195
1196 testb $3, CS-RIP+8(%rsp)
1197 jz .Lnmi_from_kernel
1198
1199 /*
1200 * NMI from user mode. We need to run on the thread stack, but we
1201 * can't go through the normal entry paths: NMIs are masked, and
1202 * we don't want to enable interrupts, because then we'll end
1203 * up in an awkward situation in which IRQs are on but NMIs
1204 * are off.
1205 *
1206 * We also must not push anything to the stack before switching
1207 * stacks lest we corrupt the "NMI executing" variable.
1208 */
1209
1210 swapgs
1211 FENCE_SWAPGS_USER_ENTRY
1212 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1213 movq %rsp, %rdx
1214 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp
1215 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1216 pushq 5*8(%rdx) /* pt_regs->ss */
1217 pushq 4*8(%rdx) /* pt_regs->rsp */
1218 pushq 3*8(%rdx) /* pt_regs->flags */
1219 pushq 2*8(%rdx) /* pt_regs->cs */
1220 pushq 1*8(%rdx) /* pt_regs->rip */
1221 UNWIND_HINT_IRET_REGS
1222 pushq $-1 /* pt_regs->orig_ax */
1223 PUSH_AND_CLEAR_REGS rdx=(%rdx)
1224 ENCODE_FRAME_POINTER
1225
1226 IBRS_ENTER
1227 UNTRAIN_RET
1228
1229 /*
1230 * At this point we no longer need to worry about stack damage
1231 * due to nesting -- we're on the normal thread stack and we're
1232 * done with the NMI stack.
1233 */
1234
1235 movq %rsp, %rdi
1236 movq $-1, %rsi
1237 call exc_nmi
1238
1239 /*
1240 * Return back to user mode. We must *not* do the normal exit
1241 * work, because we don't want to enable interrupts.
1242 */
1243 jmp swapgs_restore_regs_and_return_to_usermode
1244
1245.Lnmi_from_kernel:
1246 /*
1247 * Here's what our stack frame will look like:
1248 * +---------------------------------------------------------+
1249 * | original SS |
1250 * | original Return RSP |
1251 * | original RFLAGS |
1252 * | original CS |
1253 * | original RIP |
1254 * +---------------------------------------------------------+
1255 * | temp storage for rdx |
1256 * +---------------------------------------------------------+
1257 * | "NMI executing" variable |
1258 * +---------------------------------------------------------+
1259 * | iret SS } Copied from "outermost" frame |
1260 * | iret Return RSP } on each loop iteration; overwritten |
1261 * | iret RFLAGS } by a nested NMI to force another |
1262 * | iret CS } iteration if needed. |
1263 * | iret RIP } |
1264 * +---------------------------------------------------------+
1265 * | outermost SS } initialized in first_nmi; |
1266 * | outermost Return RSP } will not be changed before |
1267 * | outermost RFLAGS } NMI processing is done. |
1268 * | outermost CS } Copied to "iret" frame on each |
1269 * | outermost RIP } iteration. |
1270 * +---------------------------------------------------------+
1271 * | pt_regs |
1272 * +---------------------------------------------------------+
1273 *
1274 * The "original" frame is used by hardware. Before re-enabling
1275 * NMIs, we need to be done with it, and we need to leave enough
1276 * space for the asm code here.
1277 *
1278 * We return by executing IRET while RSP points to the "iret" frame.
1279 * That will either return for real or it will loop back into NMI
1280 * processing.
1281 *
1282 * The "outermost" frame is copied to the "iret" frame on each
1283 * iteration of the loop, so each iteration starts with the "iret"
1284 * frame pointing to the final return target.
1285 */
1286
1287 /*
1288 * Determine whether we're a nested NMI.
1289 *
1290 * If we interrupted kernel code between repeat_nmi and
1291 * end_repeat_nmi, then we are a nested NMI. We must not
1292 * modify the "iret" frame because it's being written by
1293 * the outer NMI. That's okay; the outer NMI handler is
1294 * about to about to call exc_nmi() anyway, so we can just
1295 * resume the outer NMI.
1296 */
1297
1298 movq $repeat_nmi, %rdx
1299 cmpq 8(%rsp), %rdx
1300 ja 1f
1301 movq $end_repeat_nmi, %rdx
1302 cmpq 8(%rsp), %rdx
1303 ja nested_nmi_out
13041:
1305
1306 /*
1307 * Now check "NMI executing". If it's set, then we're nested.
1308 * This will not detect if we interrupted an outer NMI just
1309 * before IRET.
1310 */
1311 cmpl $1, -8(%rsp)
1312 je nested_nmi
1313
1314 /*
1315 * Now test if the previous stack was an NMI stack. This covers
1316 * the case where we interrupt an outer NMI after it clears
1317 * "NMI executing" but before IRET. We need to be careful, though:
1318 * there is one case in which RSP could point to the NMI stack
1319 * despite there being no NMI active: naughty userspace controls
1320 * RSP at the very beginning of the SYSCALL targets. We can
1321 * pull a fast one on naughty userspace, though: we program
1322 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1323 * if it controls the kernel's RSP. We set DF before we clear
1324 * "NMI executing".
1325 */
1326 lea 6*8(%rsp), %rdx
1327 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1328 cmpq %rdx, 4*8(%rsp)
1329 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1330 ja first_nmi
1331
1332 subq $EXCEPTION_STKSZ, %rdx
1333 cmpq %rdx, 4*8(%rsp)
1334 /* If it is below the NMI stack, it is a normal NMI */
1335 jb first_nmi
1336
1337 /* Ah, it is within the NMI stack. */
1338
1339 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1340 jz first_nmi /* RSP was user controlled. */
1341
1342 /* This is a nested NMI. */
1343
1344nested_nmi:
1345 /*
1346 * Modify the "iret" frame to point to repeat_nmi, forcing another
1347 * iteration of NMI handling.
1348 */
1349 subq $8, %rsp
1350 leaq -10*8(%rsp), %rdx
1351 pushq $__KERNEL_DS
1352 pushq %rdx
1353 pushfq
1354 pushq $__KERNEL_CS
1355 pushq $repeat_nmi
1356
1357 /* Put stack back */
1358 addq $(6*8), %rsp
1359
1360nested_nmi_out:
1361 popq %rdx
1362
1363 /* We are returning to kernel mode, so this cannot result in a fault. */
1364 iretq
1365
1366first_nmi:
1367 /* Restore rdx. */
1368 movq (%rsp), %rdx
1369
1370 /* Make room for "NMI executing". */
1371 pushq $0
1372
1373 /* Leave room for the "iret" frame */
1374 subq $(5*8), %rsp
1375
1376 /* Copy the "original" frame to the "outermost" frame */
1377 .rept 5
1378 pushq 11*8(%rsp)
1379 .endr
1380 UNWIND_HINT_IRET_REGS
1381
1382 /* Everything up to here is safe from nested NMIs */
1383
1384#ifdef CONFIG_DEBUG_ENTRY
1385 /*
1386 * For ease of testing, unmask NMIs right away. Disabled by
1387 * default because IRET is very expensive.
1388 */
1389 pushq $0 /* SS */
1390 pushq %rsp /* RSP (minus 8 because of the previous push) */
1391 addq $8, (%rsp) /* Fix up RSP */
1392 pushfq /* RFLAGS */
1393 pushq $__KERNEL_CS /* CS */
1394 pushq $1f /* RIP */
1395 iretq /* continues at repeat_nmi below */
1396 UNWIND_HINT_IRET_REGS
13971:
1398#endif
1399
1400repeat_nmi:
1401 ANNOTATE_NOENDBR // this code
1402 /*
1403 * If there was a nested NMI, the first NMI's iret will return
1404 * here. But NMIs are still enabled and we can take another
1405 * nested NMI. The nested NMI checks the interrupted RIP to see
1406 * if it is between repeat_nmi and end_repeat_nmi, and if so
1407 * it will just return, as we are about to repeat an NMI anyway.
1408 * This makes it safe to copy to the stack frame that a nested
1409 * NMI will update.
1410 *
1411 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1412 * we're repeating an NMI, gsbase has the same value that it had on
1413 * the first iteration. paranoid_entry will load the kernel
1414 * gsbase if needed before we call exc_nmi(). "NMI executing"
1415 * is zero.
1416 */
1417 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1418
1419 /*
1420 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1421 * here must not modify the "iret" frame while we're writing to
1422 * it or it will end up containing garbage.
1423 */
1424 addq $(10*8), %rsp
1425 .rept 5
1426 pushq -6*8(%rsp)
1427 .endr
1428 subq $(5*8), %rsp
1429end_repeat_nmi:
1430 ANNOTATE_NOENDBR // this code
1431
1432 /*
1433 * Everything below this point can be preempted by a nested NMI.
1434 * If this happens, then the inner NMI will change the "iret"
1435 * frame to point back to repeat_nmi.
1436 */
1437 pushq $-1 /* ORIG_RAX: no syscall to restart */
1438
1439 /*
1440 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1441 * as we should not be calling schedule in NMI context.
1442 * Even with normal interrupts enabled. An NMI should not be
1443 * setting NEED_RESCHED or anything that normal interrupts and
1444 * exceptions might do.
1445 */
1446 call paranoid_entry
1447 UNWIND_HINT_REGS
1448
1449 movq %rsp, %rdi
1450 movq $-1, %rsi
1451 call exc_nmi
1452
1453 /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */
1454 IBRS_EXIT save_reg=%r15
1455
1456 /* Always restore stashed CR3 value (see paranoid_entry) */
1457 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1458
1459 /*
1460 * The above invocation of paranoid_entry stored the GSBASE
1461 * related information in R/EBX depending on the availability
1462 * of FSGSBASE.
1463 *
1464 * If FSGSBASE is enabled, restore the saved GSBASE value
1465 * unconditionally, otherwise take the conditional SWAPGS path.
1466 */
1467 ALTERNATIVE "jmp nmi_no_fsgsbase", "", X86_FEATURE_FSGSBASE
1468
1469 wrgsbase %rbx
1470 jmp nmi_restore
1471
1472nmi_no_fsgsbase:
1473 /* EBX == 0 -> invoke SWAPGS */
1474 testl %ebx, %ebx
1475 jnz nmi_restore
1476
1477nmi_swapgs:
1478 swapgs
1479
1480nmi_restore:
1481 POP_REGS
1482
1483 /*
1484 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1485 * at the "iret" frame.
1486 */
1487 addq $6*8, %rsp
1488
1489 /*
1490 * Clear "NMI executing". Set DF first so that we can easily
1491 * distinguish the remaining code between here and IRET from
1492 * the SYSCALL entry and exit paths.
1493 *
1494 * We arguably should just inspect RIP instead, but I (Andy) wrote
1495 * this code when I had the misapprehension that Xen PV supported
1496 * NMIs, and Xen PV would break that approach.
1497 */
1498 std
1499 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1500
1501 /*
1502 * iretq reads the "iret" frame and exits the NMI stack in a
1503 * single instruction. We are returning to kernel mode, so this
1504 * cannot result in a fault. Similarly, we don't need to worry
1505 * about espfix64 on the way back to kernel mode.
1506 */
1507 iretq
1508SYM_CODE_END(asm_exc_nmi)
1509
1510#ifndef CONFIG_IA32_EMULATION
1511/*
1512 * This handles SYSCALL from 32-bit code. There is no way to program
1513 * MSRs to fully disable 32-bit SYSCALL.
1514 */
1515SYM_CODE_START(ignore_sysret)
1516 UNWIND_HINT_EMPTY
1517 ENDBR
1518 mov $-ENOSYS, %eax
1519 sysretl
1520SYM_CODE_END(ignore_sysret)
1521#endif
1522
1523.pushsection .text, "ax"
1524 __FUNC_ALIGN
1525SYM_CODE_START_NOALIGN(rewind_stack_and_make_dead)
1526 UNWIND_HINT_FUNC
1527 /* Prevent any naive code from trying to unwind to our caller. */
1528 xorl %ebp, %ebp
1529
1530 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rax
1531 leaq -PTREGS_SIZE(%rax), %rsp
1532 UNWIND_HINT_REGS
1533
1534 call make_task_dead
1535SYM_CODE_END(rewind_stack_and_make_dead)
1536.popsection