Loading...
1/*
2 * OMAP4 Power Management Routines
3 *
4 * Copyright (C) 2010-2011 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/pm.h>
14#include <linux/suspend.h>
15#include <linux/module.h>
16#include <linux/list.h>
17#include <linux/err.h>
18#include <linux/slab.h>
19#include <asm/system_misc.h>
20
21#include "common.h"
22#include "clockdomain.h"
23#include "powerdomain.h"
24#include "pm.h"
25
26struct power_state {
27 struct powerdomain *pwrdm;
28 u32 next_state;
29#ifdef CONFIG_SUSPEND
30 u32 saved_state;
31 u32 saved_logic_state;
32#endif
33 struct list_head node;
34};
35
36static LIST_HEAD(pwrst_list);
37
38#ifdef CONFIG_SUSPEND
39static int omap4_pm_suspend(void)
40{
41 struct power_state *pwrst;
42 int state, ret = 0;
43 u32 cpu_id = smp_processor_id();
44
45 /* Save current powerdomain state */
46 list_for_each_entry(pwrst, &pwrst_list, node) {
47 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
48 pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
49 }
50
51 /* Set targeted power domain states by suspend */
52 list_for_each_entry(pwrst, &pwrst_list, node) {
53 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
54 pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
55 }
56
57 /*
58 * For MPUSS to hit power domain retention(CSWR or OSWR),
59 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
60 * since CPU power domain CSWR is not supported by hardware
61 * Only master CPU follows suspend path. All other CPUs follow
62 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
63 * domain CSWR is not supported by hardware.
64 * More details can be found in OMAP4430 TRM section 4.3.4.2.
65 */
66 omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
67
68 /* Restore next powerdomain state */
69 list_for_each_entry(pwrst, &pwrst_list, node) {
70 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
71 if (state > pwrst->next_state) {
72 pr_info("Powerdomain (%s) didn't enter "
73 "target state %d\n",
74 pwrst->pwrdm->name, pwrst->next_state);
75 ret = -1;
76 }
77 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
78 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
79 }
80 if (ret)
81 pr_crit("Could not enter target state in pm_suspend\n");
82 else
83 pr_info("Successfully put all powerdomains to target state\n");
84
85 return 0;
86}
87#endif /* CONFIG_SUSPEND */
88
89static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
90{
91 struct power_state *pwrst;
92
93 if (!pwrdm->pwrsts)
94 return 0;
95
96 /*
97 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
98 * through hotplug path and CPU0 explicitly programmed
99 * further down in the code path
100 */
101 if (!strncmp(pwrdm->name, "cpu", 3))
102 return 0;
103
104 /*
105 * FIXME: Remove this check when core retention is supported
106 * Only MPUSS power domain is added in the list.
107 */
108 if (strcmp(pwrdm->name, "mpu_pwrdm"))
109 return 0;
110
111 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
112 if (!pwrst)
113 return -ENOMEM;
114
115 pwrst->pwrdm = pwrdm;
116 pwrst->next_state = PWRDM_POWER_RET;
117 list_add(&pwrst->node, &pwrst_list);
118
119 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
120}
121
122/**
123 * omap_default_idle - OMAP4 default ilde routine.'
124 *
125 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
126 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
127 * by secondary CPU with CONFIG_CPUIDLE.
128 */
129static void omap_default_idle(void)
130{
131 local_fiq_disable();
132
133 omap_do_wfi();
134
135 local_fiq_enable();
136}
137
138/**
139 * omap4_pm_init - Init routine for OMAP4 PM
140 *
141 * Initializes all powerdomain and clockdomain target states
142 * and all PRCM settings.
143 */
144int __init omap4_pm_init(void)
145{
146 int ret;
147 struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
148 struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
149
150 if (omap_rev() == OMAP4430_REV_ES1_0) {
151 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
152 return -ENODEV;
153 }
154
155 pr_err("Power Management for TI OMAP4.\n");
156
157 ret = pwrdm_for_each(pwrdms_setup, NULL);
158 if (ret) {
159 pr_err("Failed to setup powerdomains\n");
160 goto err2;
161 }
162
163 /*
164 * The dynamic dependency between MPUSS -> MEMIF and
165 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
166 * expected. The hardware recommendation is to enable static
167 * dependencies for these to avoid system lock ups or random crashes.
168 * The L4 wakeup depedency is added to workaround the OCP sync hardware
169 * BUG with 32K synctimer which lead to incorrect timer value read
170 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
171 * are part of L4 wakeup clockdomain.
172 */
173 mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
174 emif_clkdm = clkdm_lookup("l3_emif_clkdm");
175 l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
176 l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
177 l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
178 l4wkup = clkdm_lookup("l4_wkup_clkdm");
179 ducati_clkdm = clkdm_lookup("ducati_clkdm");
180 if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) ||
181 (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
182 goto err2;
183
184 ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
185 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
186 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
187 ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
188 ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
189 ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
190 ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
191 if (ret) {
192 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
193 "wakeup dependency\n");
194 goto err2;
195 }
196
197 ret = omap4_mpuss_init();
198 if (ret) {
199 pr_err("Failed to initialise OMAP4 MPUSS\n");
200 goto err2;
201 }
202
203 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
204
205#ifdef CONFIG_SUSPEND
206 omap_pm_suspend = omap4_pm_suspend;
207#endif
208
209 /* Overwrite the default cpu_do_idle() */
210 arm_pm_idle = omap_default_idle;
211
212 omap4_idle_init();
213
214err2:
215 return ret;
216}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * OMAP4+ Power Management Routines
4 *
5 * Copyright (C) 2010-2013 Texas Instruments, Inc.
6 * Rajendra Nayak <rnayak@ti.com>
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 */
9
10#include <linux/pm.h>
11#include <linux/suspend.h>
12#include <linux/module.h>
13#include <linux/list.h>
14#include <linux/err.h>
15#include <linux/slab.h>
16#include <asm/system_misc.h>
17
18#include "soc.h"
19#include "common.h"
20#include "clockdomain.h"
21#include "powerdomain.h"
22#include "pm.h"
23
24u16 pm44xx_errata;
25
26struct power_state {
27 struct powerdomain *pwrdm;
28 u32 next_state;
29 u32 next_logic_state;
30#ifdef CONFIG_SUSPEND
31 u32 saved_state;
32 u32 saved_logic_state;
33#endif
34 struct list_head node;
35};
36
37/**
38 * struct static_dep_map - Static dependency map
39 * @from: from clockdomain
40 * @to: to clockdomain
41 */
42struct static_dep_map {
43 const char *from;
44 const char *to;
45};
46
47static u32 cpu_suspend_state = PWRDM_POWER_OFF;
48
49static LIST_HEAD(pwrst_list);
50
51#ifdef CONFIG_SUSPEND
52static int omap4_pm_suspend(void)
53{
54 struct power_state *pwrst;
55 int state, ret = 0;
56 u32 cpu_id = smp_processor_id();
57
58 /* Save current powerdomain state */
59 list_for_each_entry(pwrst, &pwrst_list, node) {
60 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
61 pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
62 }
63
64 /* Set targeted power domain states by suspend */
65 list_for_each_entry(pwrst, &pwrst_list, node) {
66 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
67 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
68 }
69
70 /*
71 * For MPUSS to hit power domain retention(CSWR or OSWR),
72 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
73 * since CPU power domain CSWR is not supported by hardware
74 * Only master CPU follows suspend path. All other CPUs follow
75 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
76 * domain CSWR is not supported by hardware.
77 * More details can be found in OMAP4430 TRM section 4.3.4.2.
78 */
79 omap4_enter_lowpower(cpu_id, cpu_suspend_state, false);
80
81 /* Restore next powerdomain state */
82 list_for_each_entry(pwrst, &pwrst_list, node) {
83 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
84 if (state > pwrst->next_state) {
85 pr_info("Powerdomain (%s) didn't enter target state %d\n",
86 pwrst->pwrdm->name, pwrst->next_state);
87 ret = -1;
88 }
89 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
90 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
91 }
92 if (ret) {
93 pr_crit("Could not enter target state in pm_suspend\n");
94 /*
95 * OMAP4 chip PM currently works only with certain (newer)
96 * versions of bootloaders. This is due to missing code in the
97 * kernel to properly reset and initialize some devices.
98 * Warn the user about the bootloader version being one of the
99 * possible causes.
100 * http://www.spinics.net/lists/arm-kernel/msg218641.html
101 */
102 pr_debug("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
103 } else {
104 pr_info("Successfully put all powerdomains to target state\n");
105 }
106
107 return 0;
108}
109#else
110#define omap4_pm_suspend NULL
111#endif /* CONFIG_SUSPEND */
112
113static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
114{
115 struct power_state *pwrst;
116
117 if (!pwrdm->pwrsts)
118 return 0;
119
120 /*
121 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
122 * through hotplug path and CPU0 explicitly programmed
123 * further down in the code path
124 */
125 if (!strncmp(pwrdm->name, "cpu", 3)) {
126 if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
127 cpu_suspend_state = PWRDM_POWER_RET;
128 return 0;
129 }
130
131 if (!strncmp(pwrdm->name, "core", 4) ||
132 !strncmp(pwrdm->name, "l4per", 5))
133 pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_OFF);
134
135 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
136 if (!pwrst)
137 return -ENOMEM;
138
139 pwrst->pwrdm = pwrdm;
140 pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
141 PWRDM_POWER_RET);
142 pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
143 PWRDM_POWER_OFF);
144
145 list_add(&pwrst->node, &pwrst_list);
146
147 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
148}
149
150/**
151 * omap_default_idle - OMAP4 default ilde routine.'
152 *
153 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
154 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
155 * by secondary CPU with CONFIG_CPU_IDLE.
156 */
157static void omap_default_idle(void)
158{
159 omap_do_wfi();
160}
161
162/*
163 * The dynamic dependency between MPUSS -> MEMIF and
164 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
165 * expected. The hardware recommendation is to enable static
166 * dependencies for these to avoid system lock ups or random crashes.
167 * The L4 wakeup depedency is added to workaround the OCP sync hardware
168 * BUG with 32K synctimer which lead to incorrect timer value read
169 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
170 * are part of L4 wakeup clockdomain.
171 */
172static const struct static_dep_map omap4_static_dep_map[] = {
173 {.from = "mpuss_clkdm", .to = "l3_emif_clkdm"},
174 {.from = "mpuss_clkdm", .to = "l3_1_clkdm"},
175 {.from = "mpuss_clkdm", .to = "l3_2_clkdm"},
176 {.from = "ducati_clkdm", .to = "l3_1_clkdm"},
177 {.from = "ducati_clkdm", .to = "l3_2_clkdm"},
178 {.from = NULL} /* TERMINATION */
179};
180
181static const struct static_dep_map omap5_dra7_static_dep_map[] = {
182 {.from = "mpu_clkdm", .to = "emif_clkdm"},
183 {.from = NULL} /* TERMINATION */
184};
185
186/**
187 * omap4plus_init_static_deps() - Initialize a static dependency map
188 * @map: Mapping of clock domains
189 */
190static inline int omap4plus_init_static_deps(const struct static_dep_map *map)
191{
192 int ret;
193 struct clockdomain *from, *to;
194
195 if (!map)
196 return 0;
197
198 while (map->from) {
199 from = clkdm_lookup(map->from);
200 to = clkdm_lookup(map->to);
201 if (!from || !to) {
202 pr_err("Failed lookup %s or %s for wakeup dependency\n",
203 map->from, map->to);
204 return -EINVAL;
205 }
206 ret = clkdm_add_wkdep(from, to);
207 if (ret) {
208 pr_err("Failed to add %s -> %s wakeup dependency(%d)\n",
209 map->from, map->to, ret);
210 return ret;
211 }
212
213 map++;
214 }
215
216 return 0;
217}
218
219/**
220 * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
221 *
222 * Initializes basic stuff for power management functionality.
223 */
224int __init omap4_pm_init_early(void)
225{
226 if (cpu_is_omap446x())
227 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
228
229 if (soc_is_omap54xx() || soc_is_dra7xx())
230 pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE;
231
232 return 0;
233}
234
235/**
236 * omap4_pm_init - Init routine for OMAP4+ devices
237 *
238 * Initializes all powerdomain and clockdomain target states
239 * and all PRCM settings.
240 * Return: Returns the error code returned by called functions.
241 */
242int __init omap4_pm_init(void)
243{
244 int ret = 0;
245
246 if (omap_rev() == OMAP4430_REV_ES1_0) {
247 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
248 return -ENODEV;
249 }
250
251 pr_info("Power Management for TI OMAP4+ devices.\n");
252
253 /*
254 * OMAP4 chip PM currently works only with certain (newer)
255 * versions of bootloaders. This is due to missing code in the
256 * kernel to properly reset and initialize some devices.
257 * http://www.spinics.net/lists/arm-kernel/msg218641.html
258 */
259 if (cpu_is_omap44xx())
260 pr_debug("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
261
262 ret = pwrdm_for_each(pwrdms_setup, NULL);
263 if (ret) {
264 pr_err("Failed to setup powerdomains.\n");
265 goto err2;
266 }
267
268 if (cpu_is_omap44xx())
269 ret = omap4plus_init_static_deps(omap4_static_dep_map);
270 else if (soc_is_omap54xx() || soc_is_dra7xx())
271 ret = omap4plus_init_static_deps(omap5_dra7_static_dep_map);
272
273 if (ret) {
274 pr_err("Failed to initialise static dependencies.\n");
275 goto err2;
276 }
277
278 ret = omap4_mpuss_init();
279 if (ret) {
280 pr_err("Failed to initialise OMAP4 MPUSS\n");
281 goto err2;
282 }
283
284 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
285
286 omap_common_suspend_init(omap4_pm_suspend);
287
288 /* Overwrite the default cpu_do_idle() */
289 arm_pm_idle = omap_default_idle;
290
291 if (cpu_is_omap44xx() || soc_is_omap54xx())
292 omap4_idle_init();
293
294err2:
295 return ret;
296}