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1/*
2 * OMAP Secure API infrastructure.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 *
7 *
8 * This program is free software,you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/memblock.h>
17
18#include <asm/cacheflush.h>
19#include <asm/memblock.h>
20
21#include <plat/omap-secure.h>
22#include <mach/omap-secure.h>
23
24static phys_addr_t omap_secure_memblock_base;
25
26/**
27 * omap_sec_dispatcher: Routine to dispatch low power secure
28 * service routines
29 * @idx: The HAL API index
30 * @flag: The flag indicating criticality of operation
31 * @nargs: Number of valid arguments out of four.
32 * @arg1, arg2, arg3 args4: Parameters passed to secure API
33 *
34 * Return the non-zero error value on failure.
35 */
36u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
37 u32 arg3, u32 arg4)
38{
39 u32 ret;
40 u32 param[5];
41
42 param[0] = nargs;
43 param[1] = arg1;
44 param[2] = arg2;
45 param[3] = arg3;
46 param[4] = arg4;
47
48 /*
49 * Secure API needs physical address
50 * pointer for the parameters
51 */
52 flush_cache_all();
53 outer_clean_range(__pa(param), __pa(param + 5));
54 ret = omap_smc2(idx, flag, __pa(param));
55
56 return ret;
57}
58
59/* Allocate the memory to save secure ram */
60int __init omap_secure_ram_reserve_memblock(void)
61{
62 u32 size = OMAP_SECURE_RAM_STORAGE;
63
64 size = ALIGN(size, SZ_1M);
65 omap_secure_memblock_base = arm_memblock_steal(size, SZ_1M);
66
67 return 0;
68}
69
70phys_addr_t omap_secure_ram_mempool_base(void)
71{
72 return omap_secure_memblock_base;
73}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * OMAP Secure API infrastructure.
4 *
5 * Copyright (C) 2011 Texas Instruments, Inc.
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
8 * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
9 */
10
11#include <linux/arm-smccc.h>
12#include <linux/cpu_pm.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/memblock.h>
17#include <linux/of.h>
18
19#include <asm/cacheflush.h>
20#include <asm/memblock.h>
21
22#include "common.h"
23#include "omap-secure.h"
24#include "soc.h"
25
26static phys_addr_t omap_secure_memblock_base;
27
28bool optee_available;
29
30#define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \
31 ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \
32 ARM_SMCCC_OWNER_SIP, (func_num))
33
34static void __init omap_optee_init_check(void)
35{
36 struct device_node *np;
37
38 /*
39 * We only check that the OP-TEE node is present and available. The
40 * OP-TEE kernel driver is not needed for the type of interaction made
41 * with OP-TEE here so the driver's status is not checked.
42 */
43 np = of_find_node_by_path("/firmware/optee");
44 if (np && of_device_is_available(np))
45 optee_available = true;
46 of_node_put(np);
47}
48
49/**
50 * omap_secure_dispatcher - Routine to dispatch low power secure
51 * service routines
52 * @idx: The HAL API index
53 * @flag: The flag indicating criticality of operation
54 * @nargs: Number of valid arguments out of four.
55 * @arg1, arg2, arg3 args4: Parameters passed to secure API
56 *
57 * Return the non-zero error value on failure.
58 */
59u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
60 u32 arg3, u32 arg4)
61{
62 static u32 buf[NR_CPUS][5];
63 u32 *param;
64 int cpu;
65 u32 ret;
66
67 cpu = get_cpu();
68 param = buf[cpu];
69
70 param[0] = nargs;
71 param[1] = arg1;
72 param[2] = arg2;
73 param[3] = arg3;
74 param[4] = arg4;
75
76 /*
77 * Secure API needs physical address
78 * pointer for the parameters
79 */
80 flush_cache_all();
81 outer_clean_range(__pa(param), __pa(param + 5));
82 ret = omap_smc2(idx, flag, __pa(param));
83
84 put_cpu();
85
86 return ret;
87}
88
89void omap_smccc_smc(u32 fn, u32 arg)
90{
91 struct arm_smccc_res res;
92
93 arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg,
94 0, 0, 0, 0, 0, 0, &res);
95 WARN(res.a0, "Secure function call 0x%08x failed\n", fn);
96}
97
98void omap_smc1(u32 fn, u32 arg)
99{
100 /*
101 * If this platform has OP-TEE installed we use ARM SMC calls
102 * otherwise fall back to the OMAP ROM style calls.
103 */
104 if (optee_available)
105 omap_smccc_smc(fn, arg);
106 else
107 _omap_smc1(fn, arg);
108}
109
110/* Allocate the memory to save secure ram */
111int __init omap_secure_ram_reserve_memblock(void)
112{
113 u32 size = OMAP_SECURE_RAM_STORAGE;
114
115 size = ALIGN(size, SECTION_SIZE);
116 omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
117
118 return 0;
119}
120
121#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
122u32 omap3_save_secure_ram(void *addr, int size)
123{
124 static u32 param[5];
125 u32 ret;
126
127 if (size != OMAP3_SAVE_SECURE_RAM_SZ)
128 return OMAP3_SAVE_SECURE_RAM_SZ;
129
130 param[0] = 4; /* Number of arguments */
131 param[1] = __pa(addr); /* Physical address for saving */
132 param[2] = 0;
133 param[3] = 1;
134 param[4] = 1;
135
136 ret = save_secure_ram_context(__pa(param));
137
138 return ret;
139}
140#endif
141
142/**
143 * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
144 * @idx: The PPA API index
145 * @process: Process ID
146 * @flag: The flag indicating criticality of operation
147 * @nargs: Number of valid arguments out of four.
148 * @arg1, arg2, arg3 args4: Parameters passed to secure API
149 *
150 * Return the non-zero error value on failure.
151 *
152 * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
153 * it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
154 */
155static u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
156 u32 arg1, u32 arg2, u32 arg3, u32 arg4)
157{
158 static u32 param[5];
159 u32 ret;
160
161 param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
162 param[1] = arg1;
163 param[2] = arg2;
164 param[3] = arg3;
165 param[4] = arg4;
166
167 /*
168 * Secure API needs physical address
169 * pointer for the parameters
170 */
171 local_irq_disable();
172 local_fiq_disable();
173 flush_cache_all();
174 outer_clean_range(__pa(param), __pa(param + 5));
175 ret = omap_smc3(idx, process, flag, __pa(param));
176 flush_cache_all();
177 local_fiq_enable();
178 local_irq_enable();
179
180 return ret;
181}
182
183/**
184 * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register
185 * @set_bits: bits to set in ACR
186 * @clear_bits: bits to clear in ACR
187 *
188 * Return the non-zero error value on failure.
189*/
190u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
191{
192 u32 acr;
193
194 /* Read ACR */
195 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
196 acr &= ~clear_bits;
197 acr |= set_bits;
198
199 return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
200 0,
201 FLAG_START_CRITICAL,
202 1, acr, 0, 0, 0);
203}
204
205/**
206 * rx51_secure_rng_call: Routine for HW random generator
207 */
208u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
209{
210 return rx51_secure_dispatcher(RX51_PPA_HWRNG,
211 0,
212 NO_FLAG,
213 3, ptr, count, flag, 0);
214}
215
216void __init omap_secure_init(void)
217{
218 omap_optee_init_check();
219}
220
221/*
222 * Dummy dispatcher call after core OSWR and MPU off. Updates the ROM return
223 * address after MMU has been re-enabled after CPU1 has been woken up again.
224 * Otherwise the ROM code will attempt to use the earlier physical return
225 * address that got set with MMU off when waking up CPU1. Only used on secure
226 * devices.
227 */
228static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
229{
230 switch (cmd) {
231 case CPU_CLUSTER_PM_EXIT:
232 omap_secure_dispatcher(OMAP4_PPA_SERVICE_0,
233 FLAG_START_CRITICAL,
234 0, 0, 0, 0, 0);
235 break;
236 default:
237 break;
238 }
239
240 return NOTIFY_OK;
241}
242
243static struct notifier_block secure_notifier_block = {
244 .notifier_call = cpu_notifier,
245};
246
247static int __init secure_pm_init(void)
248{
249 if (omap_type() == OMAP2_DEVICE_TYPE_GP || !soc_is_omap44xx())
250 return 0;
251
252 cpu_pm_register_notifier(&secure_notifier_block);
253
254 return 0;
255}
256omap_arch_initcall(secure_pm_init);