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1/*
2 * OMAP Secure API infrastructure.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 *
7 *
8 * This program is free software,you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/memblock.h>
17
18#include <asm/cacheflush.h>
19#include <asm/memblock.h>
20
21#include <plat/omap-secure.h>
22#include <mach/omap-secure.h>
23
24static phys_addr_t omap_secure_memblock_base;
25
26/**
27 * omap_sec_dispatcher: Routine to dispatch low power secure
28 * service routines
29 * @idx: The HAL API index
30 * @flag: The flag indicating criticality of operation
31 * @nargs: Number of valid arguments out of four.
32 * @arg1, arg2, arg3 args4: Parameters passed to secure API
33 *
34 * Return the non-zero error value on failure.
35 */
36u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
37 u32 arg3, u32 arg4)
38{
39 u32 ret;
40 u32 param[5];
41
42 param[0] = nargs;
43 param[1] = arg1;
44 param[2] = arg2;
45 param[3] = arg3;
46 param[4] = arg4;
47
48 /*
49 * Secure API needs physical address
50 * pointer for the parameters
51 */
52 flush_cache_all();
53 outer_clean_range(__pa(param), __pa(param + 5));
54 ret = omap_smc2(idx, flag, __pa(param));
55
56 return ret;
57}
58
59/* Allocate the memory to save secure ram */
60int __init omap_secure_ram_reserve_memblock(void)
61{
62 u32 size = OMAP_SECURE_RAM_STORAGE;
63
64 size = ALIGN(size, SZ_1M);
65 omap_secure_memblock_base = arm_memblock_steal(size, SZ_1M);
66
67 return 0;
68}
69
70phys_addr_t omap_secure_ram_mempool_base(void)
71{
72 return omap_secure_memblock_base;
73}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * OMAP Secure API infrastructure.
4 *
5 * Copyright (C) 2011 Texas Instruments, Inc.
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
8 * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
9 */
10
11#include <linux/arm-smccc.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/memblock.h>
16#include <linux/of.h>
17
18#include <asm/cacheflush.h>
19#include <asm/memblock.h>
20
21#include "common.h"
22#include "omap-secure.h"
23
24static phys_addr_t omap_secure_memblock_base;
25
26bool optee_available;
27
28#define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \
29 ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \
30 ARM_SMCCC_OWNER_SIP, (func_num))
31
32static void __init omap_optee_init_check(void)
33{
34 struct device_node *np;
35
36 /*
37 * We only check that the OP-TEE node is present and available. The
38 * OP-TEE kernel driver is not needed for the type of interaction made
39 * with OP-TEE here so the driver's status is not checked.
40 */
41 np = of_find_node_by_path("/firmware/optee");
42 if (np && of_device_is_available(np))
43 optee_available = true;
44 of_node_put(np);
45}
46
47/**
48 * omap_sec_dispatcher: Routine to dispatch low power secure
49 * service routines
50 * @idx: The HAL API index
51 * @flag: The flag indicating criticality of operation
52 * @nargs: Number of valid arguments out of four.
53 * @arg1, arg2, arg3 args4: Parameters passed to secure API
54 *
55 * Return the non-zero error value on failure.
56 */
57u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
58 u32 arg3, u32 arg4)
59{
60 u32 ret;
61 u32 param[5];
62
63 param[0] = nargs;
64 param[1] = arg1;
65 param[2] = arg2;
66 param[3] = arg3;
67 param[4] = arg4;
68
69 /*
70 * Secure API needs physical address
71 * pointer for the parameters
72 */
73 flush_cache_all();
74 outer_clean_range(__pa(param), __pa(param + 5));
75 ret = omap_smc2(idx, flag, __pa(param));
76
77 return ret;
78}
79
80void omap_smccc_smc(u32 fn, u32 arg)
81{
82 struct arm_smccc_res res;
83
84 arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg,
85 0, 0, 0, 0, 0, 0, &res);
86 WARN(res.a0, "Secure function call 0x%08x failed\n", fn);
87}
88
89void omap_smc1(u32 fn, u32 arg)
90{
91 /*
92 * If this platform has OP-TEE installed we use ARM SMC calls
93 * otherwise fall back to the OMAP ROM style calls.
94 */
95 if (optee_available)
96 omap_smccc_smc(fn, arg);
97 else
98 _omap_smc1(fn, arg);
99}
100
101/* Allocate the memory to save secure ram */
102int __init omap_secure_ram_reserve_memblock(void)
103{
104 u32 size = OMAP_SECURE_RAM_STORAGE;
105
106 size = ALIGN(size, SECTION_SIZE);
107 omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
108
109 return 0;
110}
111
112phys_addr_t omap_secure_ram_mempool_base(void)
113{
114 return omap_secure_memblock_base;
115}
116
117#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
118u32 omap3_save_secure_ram(void __iomem *addr, int size)
119{
120 u32 ret;
121 u32 param[5];
122
123 if (size != OMAP3_SAVE_SECURE_RAM_SZ)
124 return OMAP3_SAVE_SECURE_RAM_SZ;
125
126 param[0] = 4; /* Number of arguments */
127 param[1] = __pa(addr); /* Physical address for saving */
128 param[2] = 0;
129 param[3] = 1;
130 param[4] = 1;
131
132 ret = save_secure_ram_context(__pa(param));
133
134 return ret;
135}
136#endif
137
138/**
139 * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
140 * @idx: The PPA API index
141 * @process: Process ID
142 * @flag: The flag indicating criticality of operation
143 * @nargs: Number of valid arguments out of four.
144 * @arg1, arg2, arg3 args4: Parameters passed to secure API
145 *
146 * Return the non-zero error value on failure.
147 *
148 * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
149 * it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
150 */
151u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
152 u32 arg1, u32 arg2, u32 arg3, u32 arg4)
153{
154 u32 ret;
155 u32 param[5];
156
157 param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
158 param[1] = arg1;
159 param[2] = arg2;
160 param[3] = arg3;
161 param[4] = arg4;
162
163 /*
164 * Secure API needs physical address
165 * pointer for the parameters
166 */
167 local_irq_disable();
168 local_fiq_disable();
169 flush_cache_all();
170 outer_clean_range(__pa(param), __pa(param + 5));
171 ret = omap_smc3(idx, process, flag, __pa(param));
172 flush_cache_all();
173 local_fiq_enable();
174 local_irq_enable();
175
176 return ret;
177}
178
179/**
180 * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register
181 * @set_bits: bits to set in ACR
182 * @clr_bits: bits to clear in ACR
183 *
184 * Return the non-zero error value on failure.
185*/
186u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
187{
188 u32 acr;
189
190 /* Read ACR */
191 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
192 acr &= ~clear_bits;
193 acr |= set_bits;
194
195 return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
196 0,
197 FLAG_START_CRITICAL,
198 1, acr, 0, 0, 0);
199}
200
201/**
202 * rx51_secure_rng_call: Routine for HW random generator
203 */
204u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
205{
206 return rx51_secure_dispatcher(RX51_PPA_HWRNG,
207 0,
208 NO_FLAG,
209 3, ptr, count, flag, 0);
210}
211
212void __init omap_secure_init(void)
213{
214 omap_optee_init_check();
215}