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1/*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/gpio.h>
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18
19#include <asm/mach/irq.h>
20
21struct davinci_gpio_regs {
22 u32 dir;
23 u32 out_data;
24 u32 set_data;
25 u32 clr_data;
26 u32 in_data;
27 u32 set_rising;
28 u32 clr_rising;
29 u32 set_falling;
30 u32 clr_falling;
31 u32 intstat;
32};
33
34#define chip2controller(chip) \
35 container_of(chip, struct davinci_gpio_controller, chip)
36
37static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
38static void __iomem *gpio_base;
39
40static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
41{
42 void __iomem *ptr;
43
44 if (gpio < 32 * 1)
45 ptr = gpio_base + 0x10;
46 else if (gpio < 32 * 2)
47 ptr = gpio_base + 0x38;
48 else if (gpio < 32 * 3)
49 ptr = gpio_base + 0x60;
50 else if (gpio < 32 * 4)
51 ptr = gpio_base + 0x88;
52 else if (gpio < 32 * 5)
53 ptr = gpio_base + 0xb0;
54 else
55 ptr = NULL;
56 return ptr;
57}
58
59static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
60{
61 struct davinci_gpio_regs __iomem *g;
62
63 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
64
65 return g;
66}
67
68static int __init davinci_gpio_irq_setup(void);
69
70/*--------------------------------------------------------------------------*/
71
72/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
73static inline int __davinci_direction(struct gpio_chip *chip,
74 unsigned offset, bool out, int value)
75{
76 struct davinci_gpio_controller *d = chip2controller(chip);
77 struct davinci_gpio_regs __iomem *g = d->regs;
78 unsigned long flags;
79 u32 temp;
80 u32 mask = 1 << offset;
81
82 spin_lock_irqsave(&d->lock, flags);
83 temp = __raw_readl(&g->dir);
84 if (out) {
85 temp &= ~mask;
86 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
87 } else {
88 temp |= mask;
89 }
90 __raw_writel(temp, &g->dir);
91 spin_unlock_irqrestore(&d->lock, flags);
92
93 return 0;
94}
95
96static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
97{
98 return __davinci_direction(chip, offset, false, 0);
99}
100
101static int
102davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
103{
104 return __davinci_direction(chip, offset, true, value);
105}
106
107/*
108 * Read the pin's value (works even if it's set up as output);
109 * returns zero/nonzero.
110 *
111 * Note that changes are synched to the GPIO clock, so reading values back
112 * right after you've set them may give old values.
113 */
114static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
115{
116 struct davinci_gpio_controller *d = chip2controller(chip);
117 struct davinci_gpio_regs __iomem *g = d->regs;
118
119 return (1 << offset) & __raw_readl(&g->in_data);
120}
121
122/*
123 * Assuming the pin is muxed as a gpio output, set its output value.
124 */
125static void
126davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
127{
128 struct davinci_gpio_controller *d = chip2controller(chip);
129 struct davinci_gpio_regs __iomem *g = d->regs;
130
131 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
132}
133
134static int __init davinci_gpio_setup(void)
135{
136 int i, base;
137 unsigned ngpio;
138 struct davinci_soc_info *soc_info = &davinci_soc_info;
139 struct davinci_gpio_regs *regs;
140
141 if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
142 return 0;
143
144 /*
145 * The gpio banks conceptually expose a segmented bitmap,
146 * and "ngpio" is one more than the largest zero-based
147 * bit index that's valid.
148 */
149 ngpio = soc_info->gpio_num;
150 if (ngpio == 0) {
151 pr_err("GPIO setup: how many GPIOs?\n");
152 return -EINVAL;
153 }
154
155 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
156 ngpio = DAVINCI_N_GPIO;
157
158 gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
159 if (WARN_ON(!gpio_base))
160 return -ENOMEM;
161
162 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
163 chips[i].chip.label = "DaVinci";
164
165 chips[i].chip.direction_input = davinci_direction_in;
166 chips[i].chip.get = davinci_gpio_get;
167 chips[i].chip.direction_output = davinci_direction_out;
168 chips[i].chip.set = davinci_gpio_set;
169
170 chips[i].chip.base = base;
171 chips[i].chip.ngpio = ngpio - base;
172 if (chips[i].chip.ngpio > 32)
173 chips[i].chip.ngpio = 32;
174
175 spin_lock_init(&chips[i].lock);
176
177 regs = gpio2regs(base);
178 chips[i].regs = regs;
179 chips[i].set_data = ®s->set_data;
180 chips[i].clr_data = ®s->clr_data;
181 chips[i].in_data = ®s->in_data;
182
183 gpiochip_add(&chips[i].chip);
184 }
185
186 soc_info->gpio_ctlrs = chips;
187 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
188
189 davinci_gpio_irq_setup();
190 return 0;
191}
192pure_initcall(davinci_gpio_setup);
193
194/*--------------------------------------------------------------------------*/
195/*
196 * We expect irqs will normally be set up as input pins, but they can also be
197 * used as output pins ... which is convenient for testing.
198 *
199 * NOTE: The first few GPIOs also have direct INTC hookups in addition
200 * to their GPIOBNK0 irq, with a bit less overhead.
201 *
202 * All those INTC hookups (direct, plus several IRQ banks) can also
203 * serve as EDMA event triggers.
204 */
205
206static void gpio_irq_disable(struct irq_data *d)
207{
208 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
209 u32 mask = (u32) irq_data_get_irq_handler_data(d);
210
211 __raw_writel(mask, &g->clr_falling);
212 __raw_writel(mask, &g->clr_rising);
213}
214
215static void gpio_irq_enable(struct irq_data *d)
216{
217 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
218 u32 mask = (u32) irq_data_get_irq_handler_data(d);
219 unsigned status = irqd_get_trigger_type(d);
220
221 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
222 if (!status)
223 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
224
225 if (status & IRQ_TYPE_EDGE_FALLING)
226 __raw_writel(mask, &g->set_falling);
227 if (status & IRQ_TYPE_EDGE_RISING)
228 __raw_writel(mask, &g->set_rising);
229}
230
231static int gpio_irq_type(struct irq_data *d, unsigned trigger)
232{
233 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
234 return -EINVAL;
235
236 return 0;
237}
238
239static struct irq_chip gpio_irqchip = {
240 .name = "GPIO",
241 .irq_enable = gpio_irq_enable,
242 .irq_disable = gpio_irq_disable,
243 .irq_set_type = gpio_irq_type,
244 .flags = IRQCHIP_SET_TYPE_MASKED,
245};
246
247static void
248gpio_irq_handler(unsigned irq, struct irq_desc *desc)
249{
250 struct davinci_gpio_regs __iomem *g;
251 u32 mask = 0xffff;
252 struct davinci_gpio_controller *d;
253
254 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
255 g = (struct davinci_gpio_regs __iomem *)d->regs;
256
257 /* we only care about one bank */
258 if (irq & 1)
259 mask <<= 16;
260
261 /* temporarily mask (level sensitive) parent IRQ */
262 desc->irq_data.chip->irq_mask(&desc->irq_data);
263 desc->irq_data.chip->irq_ack(&desc->irq_data);
264 while (1) {
265 u32 status;
266 int n;
267 int res;
268
269 /* ack any irqs */
270 status = __raw_readl(&g->intstat) & mask;
271 if (!status)
272 break;
273 __raw_writel(status, &g->intstat);
274
275 /* now demux them to the right lowlevel handler */
276 n = d->irq_base;
277 if (irq & 1) {
278 n += 16;
279 status >>= 16;
280 }
281
282 while (status) {
283 res = ffs(status);
284 n += res;
285 generic_handle_irq(n - 1);
286 status >>= res;
287 }
288 }
289 desc->irq_data.chip->irq_unmask(&desc->irq_data);
290 /* now it may re-trigger */
291}
292
293static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
294{
295 struct davinci_gpio_controller *d = chip2controller(chip);
296
297 if (d->irq_base >= 0)
298 return d->irq_base + offset;
299 else
300 return -ENODEV;
301}
302
303static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
304{
305 struct davinci_soc_info *soc_info = &davinci_soc_info;
306
307 /* NOTE: we assume for now that only irqs in the first gpio_chip
308 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
309 */
310 if (offset < soc_info->gpio_unbanked)
311 return soc_info->gpio_irq + offset;
312 else
313 return -ENODEV;
314}
315
316static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
317{
318 struct davinci_gpio_controller *d;
319 struct davinci_gpio_regs __iomem *g;
320 struct davinci_soc_info *soc_info = &davinci_soc_info;
321 u32 mask;
322
323 d = (struct davinci_gpio_controller *)data->handler_data;
324 g = (struct davinci_gpio_regs __iomem *)d->regs;
325 mask = __gpio_mask(data->irq - soc_info->gpio_irq);
326
327 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
328 return -EINVAL;
329
330 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
331 ? &g->set_falling : &g->clr_falling);
332 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
333 ? &g->set_rising : &g->clr_rising);
334
335 return 0;
336}
337
338/*
339 * NOTE: for suspend/resume, probably best to make a platform_device with
340 * suspend_late/resume_resume calls hooking into results of the set_wake()
341 * calls ... so if no gpios are wakeup events the clock can be disabled,
342 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
343 * (dm6446) can be set appropriately for GPIOV33 pins.
344 */
345
346static int __init davinci_gpio_irq_setup(void)
347{
348 unsigned gpio, irq, bank;
349 struct clk *clk;
350 u32 binten = 0;
351 unsigned ngpio, bank_irq;
352 struct davinci_soc_info *soc_info = &davinci_soc_info;
353 struct davinci_gpio_regs __iomem *g;
354
355 ngpio = soc_info->gpio_num;
356
357 bank_irq = soc_info->gpio_irq;
358 if (bank_irq == 0) {
359 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
360 return -EINVAL;
361 }
362
363 clk = clk_get(NULL, "gpio");
364 if (IS_ERR(clk)) {
365 printk(KERN_ERR "Error %ld getting gpio clock?\n",
366 PTR_ERR(clk));
367 return PTR_ERR(clk);
368 }
369 clk_enable(clk);
370
371 /* Arrange gpio_to_irq() support, handling either direct IRQs or
372 * banked IRQs. Having GPIOs in the first GPIO bank use direct
373 * IRQs, while the others use banked IRQs, would need some setup
374 * tweaks to recognize hardware which can do that.
375 */
376 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
377 chips[bank].chip.to_irq = gpio_to_irq_banked;
378 chips[bank].irq_base = soc_info->gpio_unbanked
379 ? -EINVAL
380 : (soc_info->intc_irq_num + gpio);
381 }
382
383 /*
384 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
385 * controller only handling trigger modes. We currently assume no
386 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
387 */
388 if (soc_info->gpio_unbanked) {
389 static struct irq_chip_type gpio_unbanked;
390
391 /* pass "bank 0" GPIO IRQs to AINTC */
392 chips[0].chip.to_irq = gpio_to_irq_unbanked;
393 binten = BIT(0);
394
395 /* AINTC handles mask/unmask; GPIO handles triggering */
396 irq = bank_irq;
397 gpio_unbanked = *container_of(irq_get_chip(irq),
398 struct irq_chip_type, chip);
399 gpio_unbanked.chip.name = "GPIO-AINTC";
400 gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;
401
402 /* default trigger: both edges */
403 g = gpio2regs(0);
404 __raw_writel(~0, &g->set_falling);
405 __raw_writel(~0, &g->set_rising);
406
407 /* set the direct IRQs up to use that irqchip */
408 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
409 irq_set_chip(irq, &gpio_unbanked.chip);
410 irq_set_handler_data(irq, &chips[gpio / 32]);
411 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
412 }
413
414 goto done;
415 }
416
417 /*
418 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
419 * then chain through our own handler.
420 */
421 for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
422 gpio < ngpio;
423 bank++, bank_irq++) {
424 unsigned i;
425
426 /* disabled by default, enabled only as needed */
427 g = gpio2regs(gpio);
428 __raw_writel(~0, &g->clr_falling);
429 __raw_writel(~0, &g->clr_rising);
430
431 /* set up all irqs in this bank */
432 irq_set_chained_handler(bank_irq, gpio_irq_handler);
433
434 /*
435 * Each chip handles 32 gpios, and each irq bank consists of 16
436 * gpio irqs. Pass the irq bank's corresponding controller to
437 * the chained irq handler.
438 */
439 irq_set_handler_data(bank_irq, &chips[gpio / 32]);
440
441 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
442 irq_set_chip(irq, &gpio_irqchip);
443 irq_set_chip_data(irq, (__force void *)g);
444 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
445 irq_set_handler(irq, handle_simple_irq);
446 set_irq_flags(irq, IRQF_VALID);
447 }
448
449 binten |= BIT(bank);
450 }
451
452done:
453 /* BINTEN -- per-bank interrupt enable. genirq would also let these
454 * bits be set/cleared dynamically.
455 */
456 __raw_writel(binten, gpio_base + 0x08);
457
458 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
459
460 return 0;
461}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TI DaVinci GPIO Support
4 *
5 * Copyright (c) 2006-2007 David Brownell
6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/platform_device.h>
22#include <linux/platform_data/gpio-davinci.h>
23#include <linux/irqchip/chained_irq.h>
24#include <linux/spinlock.h>
25
26#include <asm-generic/gpio.h>
27
28#define MAX_REGS_BANKS 5
29#define MAX_INT_PER_BANK 32
30
31struct davinci_gpio_regs {
32 u32 dir;
33 u32 out_data;
34 u32 set_data;
35 u32 clr_data;
36 u32 in_data;
37 u32 set_rising;
38 u32 clr_rising;
39 u32 set_falling;
40 u32 clr_falling;
41 u32 intstat;
42};
43
44typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
45
46#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
47
48static void __iomem *gpio_base;
49static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
50
51struct davinci_gpio_irq_data {
52 void __iomem *regs;
53 struct davinci_gpio_controller *chip;
54 int bank_num;
55};
56
57struct davinci_gpio_controller {
58 struct gpio_chip chip;
59 struct irq_domain *irq_domain;
60 /* Serialize access to GPIO registers */
61 spinlock_t lock;
62 void __iomem *regs[MAX_REGS_BANKS];
63 int gpio_unbanked;
64 int irqs[MAX_INT_PER_BANK];
65};
66
67static inline u32 __gpio_mask(unsigned gpio)
68{
69 return 1 << (gpio % 32);
70}
71
72static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
73{
74 struct davinci_gpio_regs __iomem *g;
75
76 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
77
78 return g;
79}
80
81static int davinci_gpio_irq_setup(struct platform_device *pdev);
82
83/*--------------------------------------------------------------------------*/
84
85/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
86static inline int __davinci_direction(struct gpio_chip *chip,
87 unsigned offset, bool out, int value)
88{
89 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
90 struct davinci_gpio_regs __iomem *g;
91 unsigned long flags;
92 u32 temp;
93 int bank = offset / 32;
94 u32 mask = __gpio_mask(offset);
95
96 g = d->regs[bank];
97 spin_lock_irqsave(&d->lock, flags);
98 temp = readl_relaxed(&g->dir);
99 if (out) {
100 temp &= ~mask;
101 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
102 } else {
103 temp |= mask;
104 }
105 writel_relaxed(temp, &g->dir);
106 spin_unlock_irqrestore(&d->lock, flags);
107
108 return 0;
109}
110
111static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
112{
113 return __davinci_direction(chip, offset, false, 0);
114}
115
116static int
117davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
118{
119 return __davinci_direction(chip, offset, true, value);
120}
121
122/*
123 * Read the pin's value (works even if it's set up as output);
124 * returns zero/nonzero.
125 *
126 * Note that changes are synched to the GPIO clock, so reading values back
127 * right after you've set them may give old values.
128 */
129static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
130{
131 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
132 struct davinci_gpio_regs __iomem *g;
133 int bank = offset / 32;
134
135 g = d->regs[bank];
136
137 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
138}
139
140/*
141 * Assuming the pin is muxed as a gpio output, set its output value.
142 */
143static void
144davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
145{
146 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
147 struct davinci_gpio_regs __iomem *g;
148 int bank = offset / 32;
149
150 g = d->regs[bank];
151
152 writel_relaxed(__gpio_mask(offset),
153 value ? &g->set_data : &g->clr_data);
154}
155
156static struct davinci_gpio_platform_data *
157davinci_gpio_get_pdata(struct platform_device *pdev)
158{
159 struct device_node *dn = pdev->dev.of_node;
160 struct davinci_gpio_platform_data *pdata;
161 int ret;
162 u32 val;
163
164 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
165 return dev_get_platdata(&pdev->dev);
166
167 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
168 if (!pdata)
169 return NULL;
170
171 ret = of_property_read_u32(dn, "ti,ngpio", &val);
172 if (ret)
173 goto of_err;
174
175 pdata->ngpio = val;
176
177 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
178 if (ret)
179 goto of_err;
180
181 pdata->gpio_unbanked = val;
182
183 return pdata;
184
185of_err:
186 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
187 return NULL;
188}
189
190static int davinci_gpio_probe(struct platform_device *pdev)
191{
192 int bank, i, ret = 0;
193 unsigned int ngpio, nbank, nirq;
194 struct davinci_gpio_controller *chips;
195 struct davinci_gpio_platform_data *pdata;
196 struct device *dev = &pdev->dev;
197
198 pdata = davinci_gpio_get_pdata(pdev);
199 if (!pdata) {
200 dev_err(dev, "No platform data found\n");
201 return -EINVAL;
202 }
203
204 dev->platform_data = pdata;
205
206 /*
207 * The gpio banks conceptually expose a segmented bitmap,
208 * and "ngpio" is one more than the largest zero-based
209 * bit index that's valid.
210 */
211 ngpio = pdata->ngpio;
212 if (ngpio == 0) {
213 dev_err(dev, "How many GPIOs?\n");
214 return -EINVAL;
215 }
216
217 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
218 ngpio = ARCH_NR_GPIOS;
219
220 /*
221 * If there are unbanked interrupts then the number of
222 * interrupts is equal to number of gpios else all are banked so
223 * number of interrupts is equal to number of banks(each with 16 gpios)
224 */
225 if (pdata->gpio_unbanked)
226 nirq = pdata->gpio_unbanked;
227 else
228 nirq = DIV_ROUND_UP(ngpio, 16);
229
230 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
231 if (!chips)
232 return -ENOMEM;
233
234 gpio_base = devm_platform_ioremap_resource(pdev, 0);
235 if (IS_ERR(gpio_base))
236 return PTR_ERR(gpio_base);
237
238 for (i = 0; i < nirq; i++) {
239 chips->irqs[i] = platform_get_irq(pdev, i);
240 if (chips->irqs[i] < 0) {
241 if (chips->irqs[i] != -EPROBE_DEFER)
242 dev_info(dev, "IRQ not populated, err = %d\n",
243 chips->irqs[i]);
244 return chips->irqs[i];
245 }
246 }
247
248 chips->chip.label = dev_name(dev);
249
250 chips->chip.direction_input = davinci_direction_in;
251 chips->chip.get = davinci_gpio_get;
252 chips->chip.direction_output = davinci_direction_out;
253 chips->chip.set = davinci_gpio_set;
254
255 chips->chip.ngpio = ngpio;
256 chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
257
258#ifdef CONFIG_OF_GPIO
259 chips->chip.of_gpio_n_cells = 2;
260 chips->chip.parent = dev;
261 chips->chip.of_node = dev->of_node;
262 chips->chip.request = gpiochip_generic_request;
263 chips->chip.free = gpiochip_generic_free;
264#endif
265 spin_lock_init(&chips->lock);
266
267 nbank = DIV_ROUND_UP(ngpio, 32);
268 for (bank = 0; bank < nbank; bank++)
269 chips->regs[bank] = gpio_base + offset_array[bank];
270
271 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
272 if (ret)
273 return ret;
274
275 platform_set_drvdata(pdev, chips);
276 ret = davinci_gpio_irq_setup(pdev);
277 if (ret)
278 return ret;
279
280 return 0;
281}
282
283/*--------------------------------------------------------------------------*/
284/*
285 * We expect irqs will normally be set up as input pins, but they can also be
286 * used as output pins ... which is convenient for testing.
287 *
288 * NOTE: The first few GPIOs also have direct INTC hookups in addition
289 * to their GPIOBNK0 irq, with a bit less overhead.
290 *
291 * All those INTC hookups (direct, plus several IRQ banks) can also
292 * serve as EDMA event triggers.
293 */
294
295static void gpio_irq_disable(struct irq_data *d)
296{
297 struct davinci_gpio_regs __iomem *g = irq2regs(d);
298 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
299
300 writel_relaxed(mask, &g->clr_falling);
301 writel_relaxed(mask, &g->clr_rising);
302}
303
304static void gpio_irq_enable(struct irq_data *d)
305{
306 struct davinci_gpio_regs __iomem *g = irq2regs(d);
307 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
308 unsigned status = irqd_get_trigger_type(d);
309
310 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
311 if (!status)
312 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
313
314 if (status & IRQ_TYPE_EDGE_FALLING)
315 writel_relaxed(mask, &g->set_falling);
316 if (status & IRQ_TYPE_EDGE_RISING)
317 writel_relaxed(mask, &g->set_rising);
318}
319
320static int gpio_irq_type(struct irq_data *d, unsigned trigger)
321{
322 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
323 return -EINVAL;
324
325 return 0;
326}
327
328static struct irq_chip gpio_irqchip = {
329 .name = "GPIO",
330 .irq_enable = gpio_irq_enable,
331 .irq_disable = gpio_irq_disable,
332 .irq_set_type = gpio_irq_type,
333 .flags = IRQCHIP_SET_TYPE_MASKED,
334};
335
336static void gpio_irq_handler(struct irq_desc *desc)
337{
338 struct davinci_gpio_regs __iomem *g;
339 u32 mask = 0xffff;
340 int bank_num;
341 struct davinci_gpio_controller *d;
342 struct davinci_gpio_irq_data *irqdata;
343
344 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
345 bank_num = irqdata->bank_num;
346 g = irqdata->regs;
347 d = irqdata->chip;
348
349 /* we only care about one bank */
350 if ((bank_num % 2) == 1)
351 mask <<= 16;
352
353 /* temporarily mask (level sensitive) parent IRQ */
354 chained_irq_enter(irq_desc_get_chip(desc), desc);
355 while (1) {
356 u32 status;
357 int bit;
358 irq_hw_number_t hw_irq;
359
360 /* ack any irqs */
361 status = readl_relaxed(&g->intstat) & mask;
362 if (!status)
363 break;
364 writel_relaxed(status, &g->intstat);
365
366 /* now demux them to the right lowlevel handler */
367
368 while (status) {
369 bit = __ffs(status);
370 status &= ~BIT(bit);
371 /* Max number of gpios per controller is 144 so
372 * hw_irq will be in [0..143]
373 */
374 hw_irq = (bank_num / 2) * 32 + bit;
375
376 generic_handle_irq(
377 irq_find_mapping(d->irq_domain, hw_irq));
378 }
379 }
380 chained_irq_exit(irq_desc_get_chip(desc), desc);
381 /* now it may re-trigger */
382}
383
384static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
385{
386 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
387
388 if (d->irq_domain)
389 return irq_create_mapping(d->irq_domain, offset);
390 else
391 return -ENXIO;
392}
393
394static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
395{
396 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
397
398 /*
399 * NOTE: we assume for now that only irqs in the first gpio_chip
400 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
401 */
402 if (offset < d->gpio_unbanked)
403 return d->irqs[offset];
404 else
405 return -ENODEV;
406}
407
408static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
409{
410 struct davinci_gpio_controller *d;
411 struct davinci_gpio_regs __iomem *g;
412 u32 mask, i;
413
414 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
415 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
416 for (i = 0; i < MAX_INT_PER_BANK; i++)
417 if (data->irq == d->irqs[i])
418 break;
419
420 if (i == MAX_INT_PER_BANK)
421 return -EINVAL;
422
423 mask = __gpio_mask(i);
424
425 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
426 return -EINVAL;
427
428 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
429 ? &g->set_falling : &g->clr_falling);
430 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
431 ? &g->set_rising : &g->clr_rising);
432
433 return 0;
434}
435
436static int
437davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
438 irq_hw_number_t hw)
439{
440 struct davinci_gpio_controller *chips =
441 (struct davinci_gpio_controller *)d->host_data;
442 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
443
444 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
445 "davinci_gpio");
446 irq_set_irq_type(irq, IRQ_TYPE_NONE);
447 irq_set_chip_data(irq, (__force void *)g);
448 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
449
450 return 0;
451}
452
453static const struct irq_domain_ops davinci_gpio_irq_ops = {
454 .map = davinci_gpio_irq_map,
455 .xlate = irq_domain_xlate_onetwocell,
456};
457
458static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
459{
460 static struct irq_chip_type gpio_unbanked;
461
462 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
463
464 return &gpio_unbanked.chip;
465};
466
467static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
468{
469 static struct irq_chip gpio_unbanked;
470
471 gpio_unbanked = *irq_get_chip(irq);
472 return &gpio_unbanked;
473};
474
475static const struct of_device_id davinci_gpio_ids[];
476
477/*
478 * NOTE: for suspend/resume, probably best to make a platform_device with
479 * suspend_late/resume_resume calls hooking into results of the set_wake()
480 * calls ... so if no gpios are wakeup events the clock can be disabled,
481 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
482 * (dm6446) can be set appropriately for GPIOV33 pins.
483 */
484
485static int davinci_gpio_irq_setup(struct platform_device *pdev)
486{
487 unsigned gpio, bank;
488 int irq;
489 int ret;
490 struct clk *clk;
491 u32 binten = 0;
492 unsigned ngpio;
493 struct device *dev = &pdev->dev;
494 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
495 struct davinci_gpio_platform_data *pdata = dev->platform_data;
496 struct davinci_gpio_regs __iomem *g;
497 struct irq_domain *irq_domain = NULL;
498 const struct of_device_id *match;
499 struct irq_chip *irq_chip;
500 struct davinci_gpio_irq_data *irqdata;
501 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
502
503 /*
504 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
505 */
506 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
507 match = of_match_device(of_match_ptr(davinci_gpio_ids),
508 dev);
509 if (match)
510 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
511
512 ngpio = pdata->ngpio;
513
514 clk = devm_clk_get(dev, "gpio");
515 if (IS_ERR(clk)) {
516 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
517 return PTR_ERR(clk);
518 }
519
520 ret = clk_prepare_enable(clk);
521 if (ret)
522 return ret;
523
524 if (!pdata->gpio_unbanked) {
525 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
526 if (irq < 0) {
527 dev_err(dev, "Couldn't allocate IRQ numbers\n");
528 clk_disable_unprepare(clk);
529 return irq;
530 }
531
532 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
533 &davinci_gpio_irq_ops,
534 chips);
535 if (!irq_domain) {
536 dev_err(dev, "Couldn't register an IRQ domain\n");
537 clk_disable_unprepare(clk);
538 return -ENODEV;
539 }
540 }
541
542 /*
543 * Arrange gpio_to_irq() support, handling either direct IRQs or
544 * banked IRQs. Having GPIOs in the first GPIO bank use direct
545 * IRQs, while the others use banked IRQs, would need some setup
546 * tweaks to recognize hardware which can do that.
547 */
548 chips->chip.to_irq = gpio_to_irq_banked;
549 chips->irq_domain = irq_domain;
550
551 /*
552 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
553 * controller only handling trigger modes. We currently assume no
554 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
555 */
556 if (pdata->gpio_unbanked) {
557 /* pass "bank 0" GPIO IRQs to AINTC */
558 chips->chip.to_irq = gpio_to_irq_unbanked;
559 chips->gpio_unbanked = pdata->gpio_unbanked;
560 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
561
562 /* AINTC handles mask/unmask; GPIO handles triggering */
563 irq = chips->irqs[0];
564 irq_chip = gpio_get_irq_chip(irq);
565 irq_chip->name = "GPIO-AINTC";
566 irq_chip->irq_set_type = gpio_irq_type_unbanked;
567
568 /* default trigger: both edges */
569 g = chips->regs[0];
570 writel_relaxed(~0, &g->set_falling);
571 writel_relaxed(~0, &g->set_rising);
572
573 /* set the direct IRQs up to use that irqchip */
574 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
575 irq_set_chip(chips->irqs[gpio], irq_chip);
576 irq_set_handler_data(chips->irqs[gpio], chips);
577 irq_set_status_flags(chips->irqs[gpio],
578 IRQ_TYPE_EDGE_BOTH);
579 }
580
581 goto done;
582 }
583
584 /*
585 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
586 * then chain through our own handler.
587 */
588 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
589 /* disabled by default, enabled only as needed
590 * There are register sets for 32 GPIOs. 2 banks of 16
591 * GPIOs are covered by each set of registers hence divide by 2
592 */
593 g = chips->regs[bank / 2];
594 writel_relaxed(~0, &g->clr_falling);
595 writel_relaxed(~0, &g->clr_rising);
596
597 /*
598 * Each chip handles 32 gpios, and each irq bank consists of 16
599 * gpio irqs. Pass the irq bank's corresponding controller to
600 * the chained irq handler.
601 */
602 irqdata = devm_kzalloc(&pdev->dev,
603 sizeof(struct
604 davinci_gpio_irq_data),
605 GFP_KERNEL);
606 if (!irqdata) {
607 clk_disable_unprepare(clk);
608 return -ENOMEM;
609 }
610
611 irqdata->regs = g;
612 irqdata->bank_num = bank;
613 irqdata->chip = chips;
614
615 irq_set_chained_handler_and_data(chips->irqs[bank],
616 gpio_irq_handler, irqdata);
617
618 binten |= BIT(bank);
619 }
620
621done:
622 /*
623 * BINTEN -- per-bank interrupt enable. genirq would also let these
624 * bits be set/cleared dynamically.
625 */
626 writel_relaxed(binten, gpio_base + BINTEN);
627
628 return 0;
629}
630
631static const struct of_device_id davinci_gpio_ids[] = {
632 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
633 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
634 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
635 { /* sentinel */ },
636};
637MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
638
639static struct platform_driver davinci_gpio_driver = {
640 .probe = davinci_gpio_probe,
641 .driver = {
642 .name = "davinci_gpio",
643 .of_match_table = of_match_ptr(davinci_gpio_ids),
644 },
645};
646
647/**
648 * GPIO driver registration needs to be done before machine_init functions
649 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
650 */
651static int __init davinci_gpio_drv_reg(void)
652{
653 return platform_driver_register(&davinci_gpio_driver);
654}
655postcore_initcall(davinci_gpio_drv_reg);