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1/*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/gpio.h>
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18
19#include <asm/mach/irq.h>
20
21struct davinci_gpio_regs {
22 u32 dir;
23 u32 out_data;
24 u32 set_data;
25 u32 clr_data;
26 u32 in_data;
27 u32 set_rising;
28 u32 clr_rising;
29 u32 set_falling;
30 u32 clr_falling;
31 u32 intstat;
32};
33
34#define chip2controller(chip) \
35 container_of(chip, struct davinci_gpio_controller, chip)
36
37static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
38static void __iomem *gpio_base;
39
40static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
41{
42 void __iomem *ptr;
43
44 if (gpio < 32 * 1)
45 ptr = gpio_base + 0x10;
46 else if (gpio < 32 * 2)
47 ptr = gpio_base + 0x38;
48 else if (gpio < 32 * 3)
49 ptr = gpio_base + 0x60;
50 else if (gpio < 32 * 4)
51 ptr = gpio_base + 0x88;
52 else if (gpio < 32 * 5)
53 ptr = gpio_base + 0xb0;
54 else
55 ptr = NULL;
56 return ptr;
57}
58
59static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
60{
61 struct davinci_gpio_regs __iomem *g;
62
63 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
64
65 return g;
66}
67
68static int __init davinci_gpio_irq_setup(void);
69
70/*--------------------------------------------------------------------------*/
71
72/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
73static inline int __davinci_direction(struct gpio_chip *chip,
74 unsigned offset, bool out, int value)
75{
76 struct davinci_gpio_controller *d = chip2controller(chip);
77 struct davinci_gpio_regs __iomem *g = d->regs;
78 unsigned long flags;
79 u32 temp;
80 u32 mask = 1 << offset;
81
82 spin_lock_irqsave(&d->lock, flags);
83 temp = __raw_readl(&g->dir);
84 if (out) {
85 temp &= ~mask;
86 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
87 } else {
88 temp |= mask;
89 }
90 __raw_writel(temp, &g->dir);
91 spin_unlock_irqrestore(&d->lock, flags);
92
93 return 0;
94}
95
96static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
97{
98 return __davinci_direction(chip, offset, false, 0);
99}
100
101static int
102davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
103{
104 return __davinci_direction(chip, offset, true, value);
105}
106
107/*
108 * Read the pin's value (works even if it's set up as output);
109 * returns zero/nonzero.
110 *
111 * Note that changes are synched to the GPIO clock, so reading values back
112 * right after you've set them may give old values.
113 */
114static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
115{
116 struct davinci_gpio_controller *d = chip2controller(chip);
117 struct davinci_gpio_regs __iomem *g = d->regs;
118
119 return (1 << offset) & __raw_readl(&g->in_data);
120}
121
122/*
123 * Assuming the pin is muxed as a gpio output, set its output value.
124 */
125static void
126davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
127{
128 struct davinci_gpio_controller *d = chip2controller(chip);
129 struct davinci_gpio_regs __iomem *g = d->regs;
130
131 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
132}
133
134static int __init davinci_gpio_setup(void)
135{
136 int i, base;
137 unsigned ngpio;
138 struct davinci_soc_info *soc_info = &davinci_soc_info;
139 struct davinci_gpio_regs *regs;
140
141 if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
142 return 0;
143
144 /*
145 * The gpio banks conceptually expose a segmented bitmap,
146 * and "ngpio" is one more than the largest zero-based
147 * bit index that's valid.
148 */
149 ngpio = soc_info->gpio_num;
150 if (ngpio == 0) {
151 pr_err("GPIO setup: how many GPIOs?\n");
152 return -EINVAL;
153 }
154
155 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
156 ngpio = DAVINCI_N_GPIO;
157
158 gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
159 if (WARN_ON(!gpio_base))
160 return -ENOMEM;
161
162 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
163 chips[i].chip.label = "DaVinci";
164
165 chips[i].chip.direction_input = davinci_direction_in;
166 chips[i].chip.get = davinci_gpio_get;
167 chips[i].chip.direction_output = davinci_direction_out;
168 chips[i].chip.set = davinci_gpio_set;
169
170 chips[i].chip.base = base;
171 chips[i].chip.ngpio = ngpio - base;
172 if (chips[i].chip.ngpio > 32)
173 chips[i].chip.ngpio = 32;
174
175 spin_lock_init(&chips[i].lock);
176
177 regs = gpio2regs(base);
178 chips[i].regs = regs;
179 chips[i].set_data = ®s->set_data;
180 chips[i].clr_data = ®s->clr_data;
181 chips[i].in_data = ®s->in_data;
182
183 gpiochip_add(&chips[i].chip);
184 }
185
186 soc_info->gpio_ctlrs = chips;
187 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
188
189 davinci_gpio_irq_setup();
190 return 0;
191}
192pure_initcall(davinci_gpio_setup);
193
194/*--------------------------------------------------------------------------*/
195/*
196 * We expect irqs will normally be set up as input pins, but they can also be
197 * used as output pins ... which is convenient for testing.
198 *
199 * NOTE: The first few GPIOs also have direct INTC hookups in addition
200 * to their GPIOBNK0 irq, with a bit less overhead.
201 *
202 * All those INTC hookups (direct, plus several IRQ banks) can also
203 * serve as EDMA event triggers.
204 */
205
206static void gpio_irq_disable(struct irq_data *d)
207{
208 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
209 u32 mask = (u32) irq_data_get_irq_handler_data(d);
210
211 __raw_writel(mask, &g->clr_falling);
212 __raw_writel(mask, &g->clr_rising);
213}
214
215static void gpio_irq_enable(struct irq_data *d)
216{
217 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
218 u32 mask = (u32) irq_data_get_irq_handler_data(d);
219 unsigned status = irqd_get_trigger_type(d);
220
221 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
222 if (!status)
223 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
224
225 if (status & IRQ_TYPE_EDGE_FALLING)
226 __raw_writel(mask, &g->set_falling);
227 if (status & IRQ_TYPE_EDGE_RISING)
228 __raw_writel(mask, &g->set_rising);
229}
230
231static int gpio_irq_type(struct irq_data *d, unsigned trigger)
232{
233 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
234 return -EINVAL;
235
236 return 0;
237}
238
239static struct irq_chip gpio_irqchip = {
240 .name = "GPIO",
241 .irq_enable = gpio_irq_enable,
242 .irq_disable = gpio_irq_disable,
243 .irq_set_type = gpio_irq_type,
244 .flags = IRQCHIP_SET_TYPE_MASKED,
245};
246
247static void
248gpio_irq_handler(unsigned irq, struct irq_desc *desc)
249{
250 struct davinci_gpio_regs __iomem *g;
251 u32 mask = 0xffff;
252 struct davinci_gpio_controller *d;
253
254 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
255 g = (struct davinci_gpio_regs __iomem *)d->regs;
256
257 /* we only care about one bank */
258 if (irq & 1)
259 mask <<= 16;
260
261 /* temporarily mask (level sensitive) parent IRQ */
262 desc->irq_data.chip->irq_mask(&desc->irq_data);
263 desc->irq_data.chip->irq_ack(&desc->irq_data);
264 while (1) {
265 u32 status;
266 int n;
267 int res;
268
269 /* ack any irqs */
270 status = __raw_readl(&g->intstat) & mask;
271 if (!status)
272 break;
273 __raw_writel(status, &g->intstat);
274
275 /* now demux them to the right lowlevel handler */
276 n = d->irq_base;
277 if (irq & 1) {
278 n += 16;
279 status >>= 16;
280 }
281
282 while (status) {
283 res = ffs(status);
284 n += res;
285 generic_handle_irq(n - 1);
286 status >>= res;
287 }
288 }
289 desc->irq_data.chip->irq_unmask(&desc->irq_data);
290 /* now it may re-trigger */
291}
292
293static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
294{
295 struct davinci_gpio_controller *d = chip2controller(chip);
296
297 if (d->irq_base >= 0)
298 return d->irq_base + offset;
299 else
300 return -ENODEV;
301}
302
303static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
304{
305 struct davinci_soc_info *soc_info = &davinci_soc_info;
306
307 /* NOTE: we assume for now that only irqs in the first gpio_chip
308 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
309 */
310 if (offset < soc_info->gpio_unbanked)
311 return soc_info->gpio_irq + offset;
312 else
313 return -ENODEV;
314}
315
316static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
317{
318 struct davinci_gpio_controller *d;
319 struct davinci_gpio_regs __iomem *g;
320 struct davinci_soc_info *soc_info = &davinci_soc_info;
321 u32 mask;
322
323 d = (struct davinci_gpio_controller *)data->handler_data;
324 g = (struct davinci_gpio_regs __iomem *)d->regs;
325 mask = __gpio_mask(data->irq - soc_info->gpio_irq);
326
327 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
328 return -EINVAL;
329
330 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
331 ? &g->set_falling : &g->clr_falling);
332 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
333 ? &g->set_rising : &g->clr_rising);
334
335 return 0;
336}
337
338/*
339 * NOTE: for suspend/resume, probably best to make a platform_device with
340 * suspend_late/resume_resume calls hooking into results of the set_wake()
341 * calls ... so if no gpios are wakeup events the clock can be disabled,
342 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
343 * (dm6446) can be set appropriately for GPIOV33 pins.
344 */
345
346static int __init davinci_gpio_irq_setup(void)
347{
348 unsigned gpio, irq, bank;
349 struct clk *clk;
350 u32 binten = 0;
351 unsigned ngpio, bank_irq;
352 struct davinci_soc_info *soc_info = &davinci_soc_info;
353 struct davinci_gpio_regs __iomem *g;
354
355 ngpio = soc_info->gpio_num;
356
357 bank_irq = soc_info->gpio_irq;
358 if (bank_irq == 0) {
359 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
360 return -EINVAL;
361 }
362
363 clk = clk_get(NULL, "gpio");
364 if (IS_ERR(clk)) {
365 printk(KERN_ERR "Error %ld getting gpio clock?\n",
366 PTR_ERR(clk));
367 return PTR_ERR(clk);
368 }
369 clk_enable(clk);
370
371 /* Arrange gpio_to_irq() support, handling either direct IRQs or
372 * banked IRQs. Having GPIOs in the first GPIO bank use direct
373 * IRQs, while the others use banked IRQs, would need some setup
374 * tweaks to recognize hardware which can do that.
375 */
376 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
377 chips[bank].chip.to_irq = gpio_to_irq_banked;
378 chips[bank].irq_base = soc_info->gpio_unbanked
379 ? -EINVAL
380 : (soc_info->intc_irq_num + gpio);
381 }
382
383 /*
384 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
385 * controller only handling trigger modes. We currently assume no
386 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
387 */
388 if (soc_info->gpio_unbanked) {
389 static struct irq_chip_type gpio_unbanked;
390
391 /* pass "bank 0" GPIO IRQs to AINTC */
392 chips[0].chip.to_irq = gpio_to_irq_unbanked;
393 binten = BIT(0);
394
395 /* AINTC handles mask/unmask; GPIO handles triggering */
396 irq = bank_irq;
397 gpio_unbanked = *container_of(irq_get_chip(irq),
398 struct irq_chip_type, chip);
399 gpio_unbanked.chip.name = "GPIO-AINTC";
400 gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;
401
402 /* default trigger: both edges */
403 g = gpio2regs(0);
404 __raw_writel(~0, &g->set_falling);
405 __raw_writel(~0, &g->set_rising);
406
407 /* set the direct IRQs up to use that irqchip */
408 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
409 irq_set_chip(irq, &gpio_unbanked.chip);
410 irq_set_handler_data(irq, &chips[gpio / 32]);
411 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
412 }
413
414 goto done;
415 }
416
417 /*
418 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
419 * then chain through our own handler.
420 */
421 for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
422 gpio < ngpio;
423 bank++, bank_irq++) {
424 unsigned i;
425
426 /* disabled by default, enabled only as needed */
427 g = gpio2regs(gpio);
428 __raw_writel(~0, &g->clr_falling);
429 __raw_writel(~0, &g->clr_rising);
430
431 /* set up all irqs in this bank */
432 irq_set_chained_handler(bank_irq, gpio_irq_handler);
433
434 /*
435 * Each chip handles 32 gpios, and each irq bank consists of 16
436 * gpio irqs. Pass the irq bank's corresponding controller to
437 * the chained irq handler.
438 */
439 irq_set_handler_data(bank_irq, &chips[gpio / 32]);
440
441 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
442 irq_set_chip(irq, &gpio_irqchip);
443 irq_set_chip_data(irq, (__force void *)g);
444 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
445 irq_set_handler(irq, handle_simple_irq);
446 set_irq_flags(irq, IRQF_VALID);
447 }
448
449 binten |= BIT(bank);
450 }
451
452done:
453 /* BINTEN -- per-bank interrupt enable. genirq would also let these
454 * bits be set/cleared dynamically.
455 */
456 __raw_writel(binten, gpio_base + 0x08);
457
458 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
459
460 return 0;
461}
1/*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/gpio/driver.h>
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/platform_device.h>
25#include <linux/platform_data/gpio-davinci.h>
26#include <linux/irqchip/chained_irq.h>
27
28struct davinci_gpio_regs {
29 u32 dir;
30 u32 out_data;
31 u32 set_data;
32 u32 clr_data;
33 u32 in_data;
34 u32 set_rising;
35 u32 clr_rising;
36 u32 set_falling;
37 u32 clr_falling;
38 u32 intstat;
39};
40
41typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
42
43#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
44#define MAX_LABEL_SIZE 20
45
46static void __iomem *gpio_base;
47static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
48
49static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
50{
51 struct davinci_gpio_regs __iomem *g;
52
53 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
54
55 return g;
56}
57
58static int davinci_gpio_irq_setup(struct platform_device *pdev);
59
60/*--------------------------------------------------------------------------*/
61
62/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
63static inline int __davinci_direction(struct gpio_chip *chip,
64 unsigned offset, bool out, int value)
65{
66 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
67 struct davinci_gpio_regs __iomem *g;
68 unsigned long flags;
69 u32 temp;
70 int bank = offset / 32;
71 u32 mask = __gpio_mask(offset);
72
73 g = d->regs[bank];
74 spin_lock_irqsave(&d->lock, flags);
75 temp = readl_relaxed(&g->dir);
76 if (out) {
77 temp &= ~mask;
78 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
79 } else {
80 temp |= mask;
81 }
82 writel_relaxed(temp, &g->dir);
83 spin_unlock_irqrestore(&d->lock, flags);
84
85 return 0;
86}
87
88static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
89{
90 return __davinci_direction(chip, offset, false, 0);
91}
92
93static int
94davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
95{
96 return __davinci_direction(chip, offset, true, value);
97}
98
99/*
100 * Read the pin's value (works even if it's set up as output);
101 * returns zero/nonzero.
102 *
103 * Note that changes are synched to the GPIO clock, so reading values back
104 * right after you've set them may give old values.
105 */
106static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
107{
108 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
109 struct davinci_gpio_regs __iomem *g;
110 int bank = offset / 32;
111
112 g = d->regs[bank];
113
114 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
115}
116
117/*
118 * Assuming the pin is muxed as a gpio output, set its output value.
119 */
120static void
121davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
122{
123 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
124 struct davinci_gpio_regs __iomem *g;
125 int bank = offset / 32;
126
127 g = d->regs[bank];
128
129 writel_relaxed(__gpio_mask(offset),
130 value ? &g->set_data : &g->clr_data);
131}
132
133static struct davinci_gpio_platform_data *
134davinci_gpio_get_pdata(struct platform_device *pdev)
135{
136 struct device_node *dn = pdev->dev.of_node;
137 struct davinci_gpio_platform_data *pdata;
138 int ret;
139 u32 val;
140
141 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
142 return dev_get_platdata(&pdev->dev);
143
144 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
145 if (!pdata)
146 return NULL;
147
148 ret = of_property_read_u32(dn, "ti,ngpio", &val);
149 if (ret)
150 goto of_err;
151
152 pdata->ngpio = val;
153
154 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
155 if (ret)
156 goto of_err;
157
158 pdata->gpio_unbanked = val;
159
160 return pdata;
161
162of_err:
163 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
164 return NULL;
165}
166
167static int davinci_gpio_probe(struct platform_device *pdev)
168{
169 static int ctrl_num, bank_base;
170 int gpio, bank, ret = 0;
171 unsigned ngpio, nbank;
172 struct davinci_gpio_controller *chips;
173 struct davinci_gpio_platform_data *pdata;
174 struct device *dev = &pdev->dev;
175 struct resource *res;
176 char label[MAX_LABEL_SIZE];
177
178 pdata = davinci_gpio_get_pdata(pdev);
179 if (!pdata) {
180 dev_err(dev, "No platform data found\n");
181 return -EINVAL;
182 }
183
184 dev->platform_data = pdata;
185
186 /*
187 * The gpio banks conceptually expose a segmented bitmap,
188 * and "ngpio" is one more than the largest zero-based
189 * bit index that's valid.
190 */
191 ngpio = pdata->ngpio;
192 if (ngpio == 0) {
193 dev_err(dev, "How many GPIOs?\n");
194 return -EINVAL;
195 }
196
197 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
198 ngpio = ARCH_NR_GPIOS;
199
200 nbank = DIV_ROUND_UP(ngpio, 32);
201 chips = devm_kzalloc(dev,
202 nbank * sizeof(struct davinci_gpio_controller),
203 GFP_KERNEL);
204 if (!chips)
205 return -ENOMEM;
206
207 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208 gpio_base = devm_ioremap_resource(dev, res);
209 if (IS_ERR(gpio_base))
210 return PTR_ERR(gpio_base);
211
212 snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", ctrl_num++);
213 chips->chip.label = devm_kstrdup(dev, label, GFP_KERNEL);
214 if (!chips->chip.label)
215 return -ENOMEM;
216
217 chips->chip.direction_input = davinci_direction_in;
218 chips->chip.get = davinci_gpio_get;
219 chips->chip.direction_output = davinci_direction_out;
220 chips->chip.set = davinci_gpio_set;
221
222 chips->chip.ngpio = ngpio;
223 chips->chip.base = bank_base;
224
225#ifdef CONFIG_OF_GPIO
226 chips->chip.of_gpio_n_cells = 2;
227 chips->chip.parent = dev;
228 chips->chip.of_node = dev->of_node;
229
230 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
231 chips->chip.request = gpiochip_generic_request;
232 chips->chip.free = gpiochip_generic_free;
233 }
234#endif
235 spin_lock_init(&chips->lock);
236 bank_base += ngpio;
237
238 for (gpio = 0, bank = 0; gpio < ngpio; gpio += 32, bank++)
239 chips->regs[bank] = gpio_base + offset_array[bank];
240
241 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
242 if (ret)
243 goto err;
244
245 platform_set_drvdata(pdev, chips);
246 ret = davinci_gpio_irq_setup(pdev);
247 if (ret)
248 goto err;
249
250 return 0;
251
252err:
253 /* Revert the static variable increments */
254 ctrl_num--;
255 bank_base -= ngpio;
256
257 return ret;
258}
259
260/*--------------------------------------------------------------------------*/
261/*
262 * We expect irqs will normally be set up as input pins, but they can also be
263 * used as output pins ... which is convenient for testing.
264 *
265 * NOTE: The first few GPIOs also have direct INTC hookups in addition
266 * to their GPIOBNK0 irq, with a bit less overhead.
267 *
268 * All those INTC hookups (direct, plus several IRQ banks) can also
269 * serve as EDMA event triggers.
270 */
271
272static void gpio_irq_disable(struct irq_data *d)
273{
274 struct davinci_gpio_regs __iomem *g = irq2regs(d);
275 u32 mask = (u32) irq_data_get_irq_handler_data(d);
276
277 writel_relaxed(mask, &g->clr_falling);
278 writel_relaxed(mask, &g->clr_rising);
279}
280
281static void gpio_irq_enable(struct irq_data *d)
282{
283 struct davinci_gpio_regs __iomem *g = irq2regs(d);
284 u32 mask = (u32) irq_data_get_irq_handler_data(d);
285 unsigned status = irqd_get_trigger_type(d);
286
287 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
288 if (!status)
289 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
290
291 if (status & IRQ_TYPE_EDGE_FALLING)
292 writel_relaxed(mask, &g->set_falling);
293 if (status & IRQ_TYPE_EDGE_RISING)
294 writel_relaxed(mask, &g->set_rising);
295}
296
297static int gpio_irq_type(struct irq_data *d, unsigned trigger)
298{
299 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
300 return -EINVAL;
301
302 return 0;
303}
304
305static struct irq_chip gpio_irqchip = {
306 .name = "GPIO",
307 .irq_enable = gpio_irq_enable,
308 .irq_disable = gpio_irq_disable,
309 .irq_set_type = gpio_irq_type,
310 .flags = IRQCHIP_SET_TYPE_MASKED,
311};
312
313static void gpio_irq_handler(struct irq_desc *desc)
314{
315 struct davinci_gpio_regs __iomem *g;
316 u32 mask = 0xffff;
317 int bank_num;
318 struct davinci_gpio_controller *d;
319 struct davinci_gpio_irq_data *irqdata;
320
321 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
322 bank_num = irqdata->bank_num;
323 g = irqdata->regs;
324 d = irqdata->chip;
325
326 /* we only care about one bank */
327 if ((bank_num % 2) == 1)
328 mask <<= 16;
329
330 /* temporarily mask (level sensitive) parent IRQ */
331 chained_irq_enter(irq_desc_get_chip(desc), desc);
332 while (1) {
333 u32 status;
334 int bit;
335 irq_hw_number_t hw_irq;
336
337 /* ack any irqs */
338 status = readl_relaxed(&g->intstat) & mask;
339 if (!status)
340 break;
341 writel_relaxed(status, &g->intstat);
342
343 /* now demux them to the right lowlevel handler */
344
345 while (status) {
346 bit = __ffs(status);
347 status &= ~BIT(bit);
348 /* Max number of gpios per controller is 144 so
349 * hw_irq will be in [0..143]
350 */
351 hw_irq = (bank_num / 2) * 32 + bit;
352
353 generic_handle_irq(
354 irq_find_mapping(d->irq_domain, hw_irq));
355 }
356 }
357 chained_irq_exit(irq_desc_get_chip(desc), desc);
358 /* now it may re-trigger */
359}
360
361static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
362{
363 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
364
365 if (d->irq_domain)
366 return irq_create_mapping(d->irq_domain, offset);
367 else
368 return -ENXIO;
369}
370
371static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
372{
373 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
374
375 /*
376 * NOTE: we assume for now that only irqs in the first gpio_chip
377 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
378 */
379 if (offset < d->gpio_unbanked)
380 return d->base_irq + offset;
381 else
382 return -ENODEV;
383}
384
385static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
386{
387 struct davinci_gpio_controller *d;
388 struct davinci_gpio_regs __iomem *g;
389 u32 mask;
390
391 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
392 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
393 mask = __gpio_mask(data->irq - d->base_irq);
394
395 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
396 return -EINVAL;
397
398 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
399 ? &g->set_falling : &g->clr_falling);
400 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
401 ? &g->set_rising : &g->clr_rising);
402
403 return 0;
404}
405
406static int
407davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
408 irq_hw_number_t hw)
409{
410 struct davinci_gpio_controller *chips =
411 (struct davinci_gpio_controller *)d->host_data;
412 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
413
414 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
415 "davinci_gpio");
416 irq_set_irq_type(irq, IRQ_TYPE_NONE);
417 irq_set_chip_data(irq, (__force void *)g);
418 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
419
420 return 0;
421}
422
423static const struct irq_domain_ops davinci_gpio_irq_ops = {
424 .map = davinci_gpio_irq_map,
425 .xlate = irq_domain_xlate_onetwocell,
426};
427
428static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
429{
430 static struct irq_chip_type gpio_unbanked;
431
432 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
433
434 return &gpio_unbanked.chip;
435};
436
437static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
438{
439 static struct irq_chip gpio_unbanked;
440
441 gpio_unbanked = *irq_get_chip(irq);
442 return &gpio_unbanked;
443};
444
445static const struct of_device_id davinci_gpio_ids[];
446
447/*
448 * NOTE: for suspend/resume, probably best to make a platform_device with
449 * suspend_late/resume_resume calls hooking into results of the set_wake()
450 * calls ... so if no gpios are wakeup events the clock can be disabled,
451 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
452 * (dm6446) can be set appropriately for GPIOV33 pins.
453 */
454
455static int davinci_gpio_irq_setup(struct platform_device *pdev)
456{
457 unsigned gpio, bank;
458 int irq;
459 int ret;
460 struct clk *clk;
461 u32 binten = 0;
462 unsigned ngpio, bank_irq;
463 struct device *dev = &pdev->dev;
464 struct resource *res;
465 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
466 struct davinci_gpio_platform_data *pdata = dev->platform_data;
467 struct davinci_gpio_regs __iomem *g;
468 struct irq_domain *irq_domain = NULL;
469 const struct of_device_id *match;
470 struct irq_chip *irq_chip;
471 struct davinci_gpio_irq_data *irqdata;
472 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
473
474 /*
475 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
476 */
477 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
478 match = of_match_device(of_match_ptr(davinci_gpio_ids),
479 dev);
480 if (match)
481 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
482
483 ngpio = pdata->ngpio;
484 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
485 if (!res) {
486 dev_err(dev, "Invalid IRQ resource\n");
487 return -EBUSY;
488 }
489
490 bank_irq = res->start;
491
492 if (!bank_irq) {
493 dev_err(dev, "Invalid IRQ resource\n");
494 return -ENODEV;
495 }
496
497 clk = devm_clk_get(dev, "gpio");
498 if (IS_ERR(clk)) {
499 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
500 return PTR_ERR(clk);
501 }
502 ret = clk_prepare_enable(clk);
503 if (ret)
504 return ret;
505
506 if (!pdata->gpio_unbanked) {
507 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
508 if (irq < 0) {
509 dev_err(dev, "Couldn't allocate IRQ numbers\n");
510 clk_disable_unprepare(clk);
511 return irq;
512 }
513
514 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
515 &davinci_gpio_irq_ops,
516 chips);
517 if (!irq_domain) {
518 dev_err(dev, "Couldn't register an IRQ domain\n");
519 clk_disable_unprepare(clk);
520 return -ENODEV;
521 }
522 }
523
524 /*
525 * Arrange gpio_to_irq() support, handling either direct IRQs or
526 * banked IRQs. Having GPIOs in the first GPIO bank use direct
527 * IRQs, while the others use banked IRQs, would need some setup
528 * tweaks to recognize hardware which can do that.
529 */
530 chips->chip.to_irq = gpio_to_irq_banked;
531 chips->irq_domain = irq_domain;
532
533 /*
534 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
535 * controller only handling trigger modes. We currently assume no
536 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
537 */
538 if (pdata->gpio_unbanked) {
539 /* pass "bank 0" GPIO IRQs to AINTC */
540 chips->chip.to_irq = gpio_to_irq_unbanked;
541 chips->base_irq = bank_irq;
542 chips->gpio_unbanked = pdata->gpio_unbanked;
543 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
544
545 /* AINTC handles mask/unmask; GPIO handles triggering */
546 irq = bank_irq;
547 irq_chip = gpio_get_irq_chip(irq);
548 irq_chip->name = "GPIO-AINTC";
549 irq_chip->irq_set_type = gpio_irq_type_unbanked;
550
551 /* default trigger: both edges */
552 g = chips->regs[0];
553 writel_relaxed(~0, &g->set_falling);
554 writel_relaxed(~0, &g->set_rising);
555
556 /* set the direct IRQs up to use that irqchip */
557 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
558 irq_set_chip(irq, irq_chip);
559 irq_set_handler_data(irq, chips);
560 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
561 }
562
563 goto done;
564 }
565
566 /*
567 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
568 * then chain through our own handler.
569 */
570 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
571 /* disabled by default, enabled only as needed
572 * There are register sets for 32 GPIOs. 2 banks of 16
573 * GPIOs are covered by each set of registers hence divide by 2
574 */
575 g = chips->regs[bank / 2];
576 writel_relaxed(~0, &g->clr_falling);
577 writel_relaxed(~0, &g->clr_rising);
578
579 /*
580 * Each chip handles 32 gpios, and each irq bank consists of 16
581 * gpio irqs. Pass the irq bank's corresponding controller to
582 * the chained irq handler.
583 */
584 irqdata = devm_kzalloc(&pdev->dev,
585 sizeof(struct
586 davinci_gpio_irq_data),
587 GFP_KERNEL);
588 if (!irqdata) {
589 clk_disable_unprepare(clk);
590 return -ENOMEM;
591 }
592
593 irqdata->regs = g;
594 irqdata->bank_num = bank;
595 irqdata->chip = chips;
596
597 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
598 irqdata);
599
600 binten |= BIT(bank);
601 }
602
603done:
604 /*
605 * BINTEN -- per-bank interrupt enable. genirq would also let these
606 * bits be set/cleared dynamically.
607 */
608 writel_relaxed(binten, gpio_base + BINTEN);
609
610 return 0;
611}
612
613#if IS_ENABLED(CONFIG_OF)
614static const struct of_device_id davinci_gpio_ids[] = {
615 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
616 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
617 { /* sentinel */ },
618};
619MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
620#endif
621
622static struct platform_driver davinci_gpio_driver = {
623 .probe = davinci_gpio_probe,
624 .driver = {
625 .name = "davinci_gpio",
626 .of_match_table = of_match_ptr(davinci_gpio_ids),
627 },
628};
629
630/**
631 * GPIO driver registration needs to be done before machine_init functions
632 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
633 */
634static int __init davinci_gpio_drv_reg(void)
635{
636 return platform_driver_register(&davinci_gpio_driver);
637}
638postcore_initcall(davinci_gpio_drv_reg);