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1/*
2 * arch/arm/include/asm/cacheflush.h
3 *
4 * Copyright (C) 1999-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _ASMARM_CACHEFLUSH_H
11#define _ASMARM_CACHEFLUSH_H
12
13#include <linux/mm.h>
14
15#include <asm/glue-cache.h>
16#include <asm/shmparam.h>
17#include <asm/cachetype.h>
18#include <asm/outercache.h>
19
20#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
21
22/*
23 * This flag is used to indicate that the page pointed to by a pte is clean
24 * and does not require cleaning before returning it to the user.
25 */
26#define PG_dcache_clean PG_arch_1
27
28/*
29 * MM Cache Management
30 * ===================
31 *
32 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
33 * implement these methods.
34 *
35 * Start addresses are inclusive and end addresses are exclusive;
36 * start addresses should be rounded down, end addresses up.
37 *
38 * See Documentation/cachetlb.txt for more information.
39 * Please note that the implementation of these, and the required
40 * effects are cache-type (VIVT/VIPT/PIPT) specific.
41 *
42 * flush_icache_all()
43 *
44 * Unconditionally clean and invalidate the entire icache.
45 * Currently only needed for cache-v6.S and cache-v7.S, see
46 * __flush_icache_all for the generic implementation.
47 *
48 * flush_kern_all()
49 *
50 * Unconditionally clean and invalidate the entire cache.
51 *
52 * flush_user_all()
53 *
54 * Clean and invalidate all user space cache entries
55 * before a change of page tables.
56 *
57 * flush_user_range(start, end, flags)
58 *
59 * Clean and invalidate a range of cache entries in the
60 * specified address space before a change of page tables.
61 * - start - user start address (inclusive, page aligned)
62 * - end - user end address (exclusive, page aligned)
63 * - flags - vma->vm_flags field
64 *
65 * coherent_kern_range(start, end)
66 *
67 * Ensure coherency between the Icache and the Dcache in the
68 * region described by start, end. If you have non-snooping
69 * Harvard caches, you need to implement this function.
70 * - start - virtual start address
71 * - end - virtual end address
72 *
73 * coherent_user_range(start, end)
74 *
75 * Ensure coherency between the Icache and the Dcache in the
76 * region described by start, end. If you have non-snooping
77 * Harvard caches, you need to implement this function.
78 * - start - virtual start address
79 * - end - virtual end address
80 *
81 * flush_kern_dcache_area(kaddr, size)
82 *
83 * Ensure that the data held in page is written back.
84 * - kaddr - page address
85 * - size - region size
86 *
87 * DMA Cache Coherency
88 * ===================
89 *
90 * dma_flush_range(start, end)
91 *
92 * Clean and invalidate the specified virtual address range.
93 * - start - virtual start address
94 * - end - virtual end address
95 */
96
97struct cpu_cache_fns {
98 void (*flush_icache_all)(void);
99 void (*flush_kern_all)(void);
100 void (*flush_user_all)(void);
101 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
102
103 void (*coherent_kern_range)(unsigned long, unsigned long);
104 int (*coherent_user_range)(unsigned long, unsigned long);
105 void (*flush_kern_dcache_area)(void *, size_t);
106
107 void (*dma_map_area)(const void *, size_t, int);
108 void (*dma_unmap_area)(const void *, size_t, int);
109
110 void (*dma_flush_range)(const void *, const void *);
111};
112
113/*
114 * Select the calling method
115 */
116#ifdef MULTI_CACHE
117
118extern struct cpu_cache_fns cpu_cache;
119
120#define __cpuc_flush_icache_all cpu_cache.flush_icache_all
121#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
122#define __cpuc_flush_user_all cpu_cache.flush_user_all
123#define __cpuc_flush_user_range cpu_cache.flush_user_range
124#define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
125#define __cpuc_coherent_user_range cpu_cache.coherent_user_range
126#define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area
127
128/*
129 * These are private to the dma-mapping API. Do not use directly.
130 * Their sole purpose is to ensure that data held in the cache
131 * is visible to DMA, or data written by DMA to system memory is
132 * visible to the CPU.
133 */
134#define dmac_map_area cpu_cache.dma_map_area
135#define dmac_unmap_area cpu_cache.dma_unmap_area
136#define dmac_flush_range cpu_cache.dma_flush_range
137
138#else
139
140extern void __cpuc_flush_icache_all(void);
141extern void __cpuc_flush_kern_all(void);
142extern void __cpuc_flush_user_all(void);
143extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
144extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
145extern int __cpuc_coherent_user_range(unsigned long, unsigned long);
146extern void __cpuc_flush_dcache_area(void *, size_t);
147
148/*
149 * These are private to the dma-mapping API. Do not use directly.
150 * Their sole purpose is to ensure that data held in the cache
151 * is visible to DMA, or data written by DMA to system memory is
152 * visible to the CPU.
153 */
154extern void dmac_map_area(const void *, size_t, int);
155extern void dmac_unmap_area(const void *, size_t, int);
156extern void dmac_flush_range(const void *, const void *);
157
158#endif
159
160/*
161 * Copy user data from/to a page which is mapped into a different
162 * processes address space. Really, we want to allow our "user
163 * space" model to handle this.
164 */
165extern void copy_to_user_page(struct vm_area_struct *, struct page *,
166 unsigned long, void *, const void *, unsigned long);
167#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
168 do { \
169 memcpy(dst, src, len); \
170 } while (0)
171
172/*
173 * Convert calls to our calling convention.
174 */
175
176/* Invalidate I-cache */
177#define __flush_icache_all_generic() \
178 asm("mcr p15, 0, %0, c7, c5, 0" \
179 : : "r" (0));
180
181/* Invalidate I-cache inner shareable */
182#define __flush_icache_all_v7_smp() \
183 asm("mcr p15, 0, %0, c7, c1, 0" \
184 : : "r" (0));
185
186/*
187 * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
188 * will fall through to use __flush_icache_all_generic.
189 */
190#if (defined(CONFIG_CPU_V7) && \
191 (defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \
192 defined(CONFIG_SMP_ON_UP)
193#define __flush_icache_preferred __cpuc_flush_icache_all
194#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
195#define __flush_icache_preferred __flush_icache_all_v7_smp
196#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
197#define __flush_icache_preferred __cpuc_flush_icache_all
198#else
199#define __flush_icache_preferred __flush_icache_all_generic
200#endif
201
202static inline void __flush_icache_all(void)
203{
204 __flush_icache_preferred();
205}
206
207#define flush_cache_all() __cpuc_flush_kern_all()
208
209static inline void vivt_flush_cache_mm(struct mm_struct *mm)
210{
211 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
212 __cpuc_flush_user_all();
213}
214
215static inline void
216vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
217{
218 struct mm_struct *mm = vma->vm_mm;
219
220 if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
221 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
222 vma->vm_flags);
223}
224
225static inline void
226vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
227{
228 struct mm_struct *mm = vma->vm_mm;
229
230 if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
231 unsigned long addr = user_addr & PAGE_MASK;
232 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
233 }
234}
235
236#ifndef CONFIG_CPU_CACHE_VIPT
237#define flush_cache_mm(mm) \
238 vivt_flush_cache_mm(mm)
239#define flush_cache_range(vma,start,end) \
240 vivt_flush_cache_range(vma,start,end)
241#define flush_cache_page(vma,addr,pfn) \
242 vivt_flush_cache_page(vma,addr,pfn)
243#else
244extern void flush_cache_mm(struct mm_struct *mm);
245extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
246extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
247#endif
248
249#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
250
251/*
252 * flush_cache_user_range is used when we want to ensure that the
253 * Harvard caches are synchronised for the user space address range.
254 * This is used for the ARM private sys_cacheflush system call.
255 */
256#define flush_cache_user_range(start,end) \
257 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
258
259/*
260 * Perform necessary cache operations to ensure that data previously
261 * stored within this range of addresses can be executed by the CPU.
262 */
263#define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
264
265/*
266 * Perform necessary cache operations to ensure that the TLB will
267 * see data written in the specified area.
268 */
269#define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
270
271/*
272 * flush_dcache_page is used when the kernel has written to the page
273 * cache page at virtual address page->virtual.
274 *
275 * If this page isn't mapped (ie, page_mapping == NULL), or it might
276 * have userspace mappings, then we _must_ always clean + invalidate
277 * the dcache entries associated with the kernel mapping.
278 *
279 * Otherwise we can defer the operation, and clean the cache when we are
280 * about to change to user space. This is the same method as used on SPARC64.
281 * See update_mmu_cache for the user space part.
282 */
283#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
284extern void flush_dcache_page(struct page *);
285
286static inline void flush_kernel_vmap_range(void *addr, int size)
287{
288 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
289 __cpuc_flush_dcache_area(addr, (size_t)size);
290}
291static inline void invalidate_kernel_vmap_range(void *addr, int size)
292{
293 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
294 __cpuc_flush_dcache_area(addr, (size_t)size);
295}
296
297#define ARCH_HAS_FLUSH_ANON_PAGE
298static inline void flush_anon_page(struct vm_area_struct *vma,
299 struct page *page, unsigned long vmaddr)
300{
301 extern void __flush_anon_page(struct vm_area_struct *vma,
302 struct page *, unsigned long);
303 if (PageAnon(page))
304 __flush_anon_page(vma, page, vmaddr);
305}
306
307#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
308static inline void flush_kernel_dcache_page(struct page *page)
309{
310}
311
312#define flush_dcache_mmap_lock(mapping) \
313 spin_lock_irq(&(mapping)->tree_lock)
314#define flush_dcache_mmap_unlock(mapping) \
315 spin_unlock_irq(&(mapping)->tree_lock)
316
317#define flush_icache_user_range(vma,page,addr,len) \
318 flush_dcache_page(page)
319
320/*
321 * We don't appear to need to do anything here. In fact, if we did, we'd
322 * duplicate cache flushing elsewhere performed by flush_dcache_page().
323 */
324#define flush_icache_page(vma,page) do { } while (0)
325
326/*
327 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
328 * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
329 * caches, since the direct-mappings of these pages may contain cached
330 * data, we need to do a full cache flush to ensure that writebacks
331 * don't corrupt data placed into these pages via the new mappings.
332 */
333static inline void flush_cache_vmap(unsigned long start, unsigned long end)
334{
335 if (!cache_is_vipt_nonaliasing())
336 flush_cache_all();
337 else
338 /*
339 * set_pte_at() called from vmap_pte_range() does not
340 * have a DSB after cleaning the cache line.
341 */
342 dsb();
343}
344
345static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
346{
347 if (!cache_is_vipt_nonaliasing())
348 flush_cache_all();
349}
350
351#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/include/asm/cacheflush.h
4 *
5 * Copyright (C) 1999-2002 Russell King
6 */
7#ifndef _ASMARM_CACHEFLUSH_H
8#define _ASMARM_CACHEFLUSH_H
9
10#include <linux/mm.h>
11
12#include <asm/glue-cache.h>
13#include <asm/shmparam.h>
14#include <asm/cachetype.h>
15#include <asm/outercache.h>
16
17#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
18
19/*
20 * This flag is used to indicate that the page pointed to by a pte is clean
21 * and does not require cleaning before returning it to the user.
22 */
23#define PG_dcache_clean PG_arch_1
24
25/*
26 * MM Cache Management
27 * ===================
28 *
29 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
30 * implement these methods.
31 *
32 * Start addresses are inclusive and end addresses are exclusive;
33 * start addresses should be rounded down, end addresses up.
34 *
35 * See Documentation/core-api/cachetlb.rst for more information.
36 * Please note that the implementation of these, and the required
37 * effects are cache-type (VIVT/VIPT/PIPT) specific.
38 *
39 * flush_icache_all()
40 *
41 * Unconditionally clean and invalidate the entire icache.
42 * Currently only needed for cache-v6.S and cache-v7.S, see
43 * __flush_icache_all for the generic implementation.
44 *
45 * flush_kern_all()
46 *
47 * Unconditionally clean and invalidate the entire cache.
48 *
49 * flush_kern_louis()
50 *
51 * Flush data cache levels up to the level of unification
52 * inner shareable and invalidate the I-cache.
53 * Only needed from v7 onwards, falls back to flush_cache_all()
54 * for all other processor versions.
55 *
56 * flush_user_all()
57 *
58 * Clean and invalidate all user space cache entries
59 * before a change of page tables.
60 *
61 * flush_user_range(start, end, flags)
62 *
63 * Clean and invalidate a range of cache entries in the
64 * specified address space before a change of page tables.
65 * - start - user start address (inclusive, page aligned)
66 * - end - user end address (exclusive, page aligned)
67 * - flags - vma->vm_flags field
68 *
69 * coherent_kern_range(start, end)
70 *
71 * Ensure coherency between the Icache and the Dcache in the
72 * region described by start, end. If you have non-snooping
73 * Harvard caches, you need to implement this function.
74 * - start - virtual start address
75 * - end - virtual end address
76 *
77 * coherent_user_range(start, end)
78 *
79 * Ensure coherency between the Icache and the Dcache in the
80 * region described by start, end. If you have non-snooping
81 * Harvard caches, you need to implement this function.
82 * - start - virtual start address
83 * - end - virtual end address
84 *
85 * flush_kern_dcache_area(kaddr, size)
86 *
87 * Ensure that the data held in page is written back.
88 * - kaddr - page address
89 * - size - region size
90 *
91 * DMA Cache Coherency
92 * ===================
93 *
94 * dma_flush_range(start, end)
95 *
96 * Clean and invalidate the specified virtual address range.
97 * - start - virtual start address
98 * - end - virtual end address
99 */
100
101struct cpu_cache_fns {
102 void (*flush_icache_all)(void);
103 void (*flush_kern_all)(void);
104 void (*flush_kern_louis)(void);
105 void (*flush_user_all)(void);
106 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
107
108 void (*coherent_kern_range)(unsigned long, unsigned long);
109 int (*coherent_user_range)(unsigned long, unsigned long);
110 void (*flush_kern_dcache_area)(void *, size_t);
111
112 void (*dma_map_area)(const void *, size_t, int);
113 void (*dma_unmap_area)(const void *, size_t, int);
114
115 void (*dma_flush_range)(const void *, const void *);
116} __no_randomize_layout;
117
118/*
119 * Select the calling method
120 */
121#ifdef MULTI_CACHE
122
123extern struct cpu_cache_fns cpu_cache;
124
125#define __cpuc_flush_icache_all cpu_cache.flush_icache_all
126#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
127#define __cpuc_flush_kern_louis cpu_cache.flush_kern_louis
128#define __cpuc_flush_user_all cpu_cache.flush_user_all
129#define __cpuc_flush_user_range cpu_cache.flush_user_range
130#define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
131#define __cpuc_coherent_user_range cpu_cache.coherent_user_range
132#define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area
133
134/*
135 * These are private to the dma-mapping API. Do not use directly.
136 * Their sole purpose is to ensure that data held in the cache
137 * is visible to DMA, or data written by DMA to system memory is
138 * visible to the CPU.
139 */
140#define dmac_flush_range cpu_cache.dma_flush_range
141
142#else
143
144extern void __cpuc_flush_icache_all(void);
145extern void __cpuc_flush_kern_all(void);
146extern void __cpuc_flush_kern_louis(void);
147extern void __cpuc_flush_user_all(void);
148extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
149extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
150extern int __cpuc_coherent_user_range(unsigned long, unsigned long);
151extern void __cpuc_flush_dcache_area(void *, size_t);
152
153/*
154 * These are private to the dma-mapping API. Do not use directly.
155 * Their sole purpose is to ensure that data held in the cache
156 * is visible to DMA, or data written by DMA to system memory is
157 * visible to the CPU.
158 */
159extern void dmac_flush_range(const void *, const void *);
160
161#endif
162
163/*
164 * Copy user data from/to a page which is mapped into a different
165 * processes address space. Really, we want to allow our "user
166 * space" model to handle this.
167 */
168extern void copy_to_user_page(struct vm_area_struct *, struct page *,
169 unsigned long, void *, const void *, unsigned long);
170#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
171 do { \
172 memcpy(dst, src, len); \
173 } while (0)
174
175/*
176 * Convert calls to our calling convention.
177 */
178
179/* Invalidate I-cache */
180#define __flush_icache_all_generic() \
181 asm("mcr p15, 0, %0, c7, c5, 0" \
182 : : "r" (0));
183
184/* Invalidate I-cache inner shareable */
185#define __flush_icache_all_v7_smp() \
186 asm("mcr p15, 0, %0, c7, c1, 0" \
187 : : "r" (0));
188
189/*
190 * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
191 * will fall through to use __flush_icache_all_generic.
192 */
193#if (defined(CONFIG_CPU_V7) && \
194 (defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \
195 defined(CONFIG_SMP_ON_UP)
196#define __flush_icache_preferred __cpuc_flush_icache_all
197#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
198#define __flush_icache_preferred __flush_icache_all_v7_smp
199#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
200#define __flush_icache_preferred __cpuc_flush_icache_all
201#else
202#define __flush_icache_preferred __flush_icache_all_generic
203#endif
204
205static inline void __flush_icache_all(void)
206{
207 __flush_icache_preferred();
208 dsb(ishst);
209}
210
211/*
212 * Flush caches up to Level of Unification Inner Shareable
213 */
214#define flush_cache_louis() __cpuc_flush_kern_louis()
215
216#define flush_cache_all() __cpuc_flush_kern_all()
217
218static inline void vivt_flush_cache_mm(struct mm_struct *mm)
219{
220 if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
221 __cpuc_flush_user_all();
222}
223
224static inline void
225vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
226{
227 struct mm_struct *mm = vma->vm_mm;
228
229 if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
230 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
231 vma->vm_flags);
232}
233
234static inline void
235vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
236{
237 struct mm_struct *mm = vma->vm_mm;
238
239 if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
240 unsigned long addr = user_addr & PAGE_MASK;
241 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
242 }
243}
244
245#ifndef CONFIG_CPU_CACHE_VIPT
246#define flush_cache_mm(mm) \
247 vivt_flush_cache_mm(mm)
248#define flush_cache_range(vma,start,end) \
249 vivt_flush_cache_range(vma,start,end)
250#define flush_cache_page(vma,addr,pfn) \
251 vivt_flush_cache_page(vma,addr,pfn)
252#else
253extern void flush_cache_mm(struct mm_struct *mm);
254extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
255extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
256#endif
257
258#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
259
260/*
261 * flush_icache_user_range is used when we want to ensure that the
262 * Harvard caches are synchronised for the user space address range.
263 * This is used for the ARM private sys_cacheflush system call.
264 */
265#define flush_icache_user_range(s,e) __cpuc_coherent_user_range(s,e)
266
267/*
268 * Perform necessary cache operations to ensure that data previously
269 * stored within this range of addresses can be executed by the CPU.
270 */
271#define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
272
273/*
274 * Perform necessary cache operations to ensure that the TLB will
275 * see data written in the specified area.
276 */
277#define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
278
279/*
280 * flush_dcache_page is used when the kernel has written to the page
281 * cache page at virtual address page->virtual.
282 *
283 * If this page isn't mapped (ie, page_mapping == NULL), or it might
284 * have userspace mappings, then we _must_ always clean + invalidate
285 * the dcache entries associated with the kernel mapping.
286 *
287 * Otherwise we can defer the operation, and clean the cache when we are
288 * about to change to user space. This is the same method as used on SPARC64.
289 * See update_mmu_cache for the user space part.
290 */
291#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
292extern void flush_dcache_page(struct page *);
293
294static inline void flush_kernel_vmap_range(void *addr, int size)
295{
296 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
297 __cpuc_flush_dcache_area(addr, (size_t)size);
298}
299static inline void invalidate_kernel_vmap_range(void *addr, int size)
300{
301 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
302 __cpuc_flush_dcache_area(addr, (size_t)size);
303}
304
305#define ARCH_HAS_FLUSH_ANON_PAGE
306static inline void flush_anon_page(struct vm_area_struct *vma,
307 struct page *page, unsigned long vmaddr)
308{
309 extern void __flush_anon_page(struct vm_area_struct *vma,
310 struct page *, unsigned long);
311 if (PageAnon(page))
312 __flush_anon_page(vma, page, vmaddr);
313}
314
315#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
316extern void flush_kernel_dcache_page(struct page *);
317
318#define flush_dcache_mmap_lock(mapping) xa_lock_irq(&mapping->i_pages)
319#define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&mapping->i_pages)
320
321/*
322 * We don't appear to need to do anything here. In fact, if we did, we'd
323 * duplicate cache flushing elsewhere performed by flush_dcache_page().
324 */
325#define flush_icache_page(vma,page) do { } while (0)
326
327/*
328 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
329 * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT
330 * caches, since the direct-mappings of these pages may contain cached
331 * data, we need to do a full cache flush to ensure that writebacks
332 * don't corrupt data placed into these pages via the new mappings.
333 */
334static inline void flush_cache_vmap(unsigned long start, unsigned long end)
335{
336 if (!cache_is_vipt_nonaliasing())
337 flush_cache_all();
338 else
339 /*
340 * set_pte_at() called from vmap_pte_range() does not
341 * have a DSB after cleaning the cache line.
342 */
343 dsb(ishst);
344}
345
346static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
347{
348 if (!cache_is_vipt_nonaliasing())
349 flush_cache_all();
350}
351
352/*
353 * Memory synchronization helpers for mixed cached vs non cached accesses.
354 *
355 * Some synchronization algorithms have to set states in memory with the
356 * cache enabled or disabled depending on the code path. It is crucial
357 * to always ensure proper cache maintenance to update main memory right
358 * away in that case.
359 *
360 * Any cached write must be followed by a cache clean operation.
361 * Any cached read must be preceded by a cache invalidate operation.
362 * Yet, in the read case, a cache flush i.e. atomic clean+invalidate
363 * operation is needed to avoid discarding possible concurrent writes to the
364 * accessed memory.
365 *
366 * Also, in order to prevent a cached writer from interfering with an
367 * adjacent non-cached writer, each state variable must be located to
368 * a separate cache line.
369 */
370
371/*
372 * This needs to be >= the max cache writeback size of all
373 * supported platforms included in the current kernel configuration.
374 * This is used to align state variables to their own cache lines.
375 */
376#define __CACHE_WRITEBACK_ORDER 6 /* guessed from existing platforms */
377#define __CACHE_WRITEBACK_GRANULE (1 << __CACHE_WRITEBACK_ORDER)
378
379/*
380 * There is no __cpuc_clean_dcache_area but we use it anyway for
381 * code intent clarity, and alias it to __cpuc_flush_dcache_area.
382 */
383#define __cpuc_clean_dcache_area __cpuc_flush_dcache_area
384
385/*
386 * Ensure preceding writes to *p by this CPU are visible to
387 * subsequent reads by other CPUs:
388 */
389static inline void __sync_cache_range_w(volatile void *p, size_t size)
390{
391 char *_p = (char *)p;
392
393 __cpuc_clean_dcache_area(_p, size);
394 outer_clean_range(__pa(_p), __pa(_p + size));
395}
396
397/*
398 * Ensure preceding writes to *p by other CPUs are visible to
399 * subsequent reads by this CPU. We must be careful not to
400 * discard data simultaneously written by another CPU, hence the
401 * usage of flush rather than invalidate operations.
402 */
403static inline void __sync_cache_range_r(volatile void *p, size_t size)
404{
405 char *_p = (char *)p;
406
407#ifdef CONFIG_OUTER_CACHE
408 if (outer_cache.flush_range) {
409 /*
410 * Ensure dirty data migrated from other CPUs into our cache
411 * are cleaned out safely before the outer cache is cleaned:
412 */
413 __cpuc_clean_dcache_area(_p, size);
414
415 /* Clean and invalidate stale data for *p from outer ... */
416 outer_flush_range(__pa(_p), __pa(_p + size));
417 }
418#endif
419
420 /* ... and inner cache: */
421 __cpuc_flush_dcache_area(_p, size);
422}
423
424#define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr))
425#define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr))
426
427/*
428 * Disabling cache access for one CPU in an ARMv7 SMP system is tricky.
429 * To do so we must:
430 *
431 * - Clear the SCTLR.C bit to prevent further cache allocations
432 * - Flush the desired level of cache
433 * - Clear the ACTLR "SMP" bit to disable local coherency
434 *
435 * ... and so without any intervening memory access in between those steps,
436 * not even to the stack.
437 *
438 * WARNING -- After this has been called:
439 *
440 * - No ldrex/strex (and similar) instructions must be used.
441 * - The CPU is obviously no longer coherent with the other CPUs.
442 * - This is unlikely to work as expected if Linux is running non-secure.
443 *
444 * Note:
445 *
446 * - This is known to apply to several ARMv7 processor implementations,
447 * however some exceptions may exist. Caveat emptor.
448 *
449 * - The clobber list is dictated by the call to v7_flush_dcache_*.
450 * fp is preserved to the stack explicitly prior disabling the cache
451 * since adding it to the clobber list is incompatible with having
452 * CONFIG_FRAME_POINTER=y. ip is saved as well if ever r12-clobbering
453 * trampoline are inserted by the linker and to keep sp 64-bit aligned.
454 */
455#define v7_exit_coherency_flush(level) \
456 asm volatile( \
457 ".arch armv7-a \n\t" \
458 "stmfd sp!, {fp, ip} \n\t" \
459 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \
460 "bic r0, r0, #"__stringify(CR_C)" \n\t" \
461 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \
462 "isb \n\t" \
463 "bl v7_flush_dcache_"__stringify(level)" \n\t" \
464 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
465 "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
466 "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
467 "isb \n\t" \
468 "dsb \n\t" \
469 "ldmfd sp!, {fp, ip}" \
470 : : : "r0","r1","r2","r3","r4","r5","r6","r7", \
471 "r9","r10","lr","memory" )
472
473void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
474 void *kaddr, unsigned long len);
475
476
477#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
478void check_cpu_icache_size(int cpuid);
479#else
480static inline void check_cpu_icache_size(int cpuid) { }
481#endif
482
483#endif