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1/*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 */
8
9#include <linux/err.h>
10#include <linux/mm.h>
11#include <linux/irq.h>
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/export.h>
15#include <linux/ioport.h>
16#include <linux/pci.h>
17#include <linux/proc_fs.h>
18#include <linux/msi.h>
19#include <linux/smp.h>
20#include <linux/errno.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23
24#include "pci.h"
25#include "msi.h"
26
27static int pci_msi_enable = 1;
28
29/* Arch hooks */
30
31#ifndef arch_msi_check_device
32int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
33{
34 return 0;
35}
36#endif
37
38#ifndef arch_setup_msi_irqs
39# define arch_setup_msi_irqs default_setup_msi_irqs
40# define HAVE_DEFAULT_MSI_SETUP_IRQS
41#endif
42
43#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
44int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
45{
46 struct msi_desc *entry;
47 int ret;
48
49 /*
50 * If an architecture wants to support multiple MSI, it needs to
51 * override arch_setup_msi_irqs()
52 */
53 if (type == PCI_CAP_ID_MSI && nvec > 1)
54 return 1;
55
56 list_for_each_entry(entry, &dev->msi_list, list) {
57 ret = arch_setup_msi_irq(dev, entry);
58 if (ret < 0)
59 return ret;
60 if (ret > 0)
61 return -ENOSPC;
62 }
63
64 return 0;
65}
66#endif
67
68#ifndef arch_teardown_msi_irqs
69# define arch_teardown_msi_irqs default_teardown_msi_irqs
70# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
71#endif
72
73#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
74void default_teardown_msi_irqs(struct pci_dev *dev)
75{
76 struct msi_desc *entry;
77
78 list_for_each_entry(entry, &dev->msi_list, list) {
79 int i, nvec;
80 if (entry->irq == 0)
81 continue;
82 nvec = 1 << entry->msi_attrib.multiple;
83 for (i = 0; i < nvec; i++)
84 arch_teardown_msi_irq(entry->irq + i);
85 }
86}
87#endif
88
89#ifndef arch_restore_msi_irqs
90# define arch_restore_msi_irqs default_restore_msi_irqs
91# define HAVE_DEFAULT_MSI_RESTORE_IRQS
92#endif
93
94#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
95void default_restore_msi_irqs(struct pci_dev *dev, int irq)
96{
97 struct msi_desc *entry;
98
99 entry = NULL;
100 if (dev->msix_enabled) {
101 list_for_each_entry(entry, &dev->msi_list, list) {
102 if (irq == entry->irq)
103 break;
104 }
105 } else if (dev->msi_enabled) {
106 entry = irq_get_msi_desc(irq);
107 }
108
109 if (entry)
110 write_msi_msg(irq, &entry->msg);
111}
112#endif
113
114static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
115{
116 u16 control;
117
118 BUG_ON(!pos);
119
120 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
121 control &= ~PCI_MSI_FLAGS_ENABLE;
122 if (enable)
123 control |= PCI_MSI_FLAGS_ENABLE;
124 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
125}
126
127static void msix_set_enable(struct pci_dev *dev, int enable)
128{
129 int pos;
130 u16 control;
131
132 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
133 if (pos) {
134 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
135 control &= ~PCI_MSIX_FLAGS_ENABLE;
136 if (enable)
137 control |= PCI_MSIX_FLAGS_ENABLE;
138 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
139 }
140}
141
142static inline __attribute_const__ u32 msi_mask(unsigned x)
143{
144 /* Don't shift by >= width of type */
145 if (x >= 5)
146 return 0xffffffff;
147 return (1 << (1 << x)) - 1;
148}
149
150static inline __attribute_const__ u32 msi_capable_mask(u16 control)
151{
152 return msi_mask((control >> 1) & 7);
153}
154
155static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
156{
157 return msi_mask((control >> 4) & 7);
158}
159
160/*
161 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
162 * mask all MSI interrupts by clearing the MSI enable bit does not work
163 * reliably as devices without an INTx disable bit will then generate a
164 * level IRQ which will never be cleared.
165 */
166static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
167{
168 u32 mask_bits = desc->masked;
169
170 if (!desc->msi_attrib.maskbit)
171 return 0;
172
173 mask_bits &= ~mask;
174 mask_bits |= flag;
175 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
176
177 return mask_bits;
178}
179
180static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
181{
182 desc->masked = __msi_mask_irq(desc, mask, flag);
183}
184
185/*
186 * This internal function does not flush PCI writes to the device.
187 * All users must ensure that they read from the device before either
188 * assuming that the device state is up to date, or returning out of this
189 * file. This saves a few milliseconds when initialising devices with lots
190 * of MSI-X interrupts.
191 */
192static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
193{
194 u32 mask_bits = desc->masked;
195 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
196 PCI_MSIX_ENTRY_VECTOR_CTRL;
197 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
198 if (flag)
199 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
200 writel(mask_bits, desc->mask_base + offset);
201
202 return mask_bits;
203}
204
205static void msix_mask_irq(struct msi_desc *desc, u32 flag)
206{
207 desc->masked = __msix_mask_irq(desc, flag);
208}
209
210static void msi_set_mask_bit(struct irq_data *data, u32 flag)
211{
212 struct msi_desc *desc = irq_data_get_msi(data);
213
214 if (desc->msi_attrib.is_msix) {
215 msix_mask_irq(desc, flag);
216 readl(desc->mask_base); /* Flush write to device */
217 } else {
218 unsigned offset = data->irq - desc->dev->irq;
219 msi_mask_irq(desc, 1 << offset, flag << offset);
220 }
221}
222
223void mask_msi_irq(struct irq_data *data)
224{
225 msi_set_mask_bit(data, 1);
226}
227
228void unmask_msi_irq(struct irq_data *data)
229{
230 msi_set_mask_bit(data, 0);
231}
232
233void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
234{
235 BUG_ON(entry->dev->current_state != PCI_D0);
236
237 if (entry->msi_attrib.is_msix) {
238 void __iomem *base = entry->mask_base +
239 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
240
241 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
242 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
243 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
244 } else {
245 struct pci_dev *dev = entry->dev;
246 int pos = entry->msi_attrib.pos;
247 u16 data;
248
249 pci_read_config_dword(dev, msi_lower_address_reg(pos),
250 &msg->address_lo);
251 if (entry->msi_attrib.is_64) {
252 pci_read_config_dword(dev, msi_upper_address_reg(pos),
253 &msg->address_hi);
254 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
255 } else {
256 msg->address_hi = 0;
257 pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
258 }
259 msg->data = data;
260 }
261}
262
263void read_msi_msg(unsigned int irq, struct msi_msg *msg)
264{
265 struct msi_desc *entry = irq_get_msi_desc(irq);
266
267 __read_msi_msg(entry, msg);
268}
269
270void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
271{
272 /* Assert that the cache is valid, assuming that
273 * valid messages are not all-zeroes. */
274 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
275 entry->msg.data));
276
277 *msg = entry->msg;
278}
279
280void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
281{
282 struct msi_desc *entry = irq_get_msi_desc(irq);
283
284 __get_cached_msi_msg(entry, msg);
285}
286
287void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
288{
289 if (entry->dev->current_state != PCI_D0) {
290 /* Don't touch the hardware now */
291 } else if (entry->msi_attrib.is_msix) {
292 void __iomem *base;
293 base = entry->mask_base +
294 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
295
296 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
297 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
298 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
299 } else {
300 struct pci_dev *dev = entry->dev;
301 int pos = entry->msi_attrib.pos;
302 u16 msgctl;
303
304 pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
305 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
306 msgctl |= entry->msi_attrib.multiple << 4;
307 pci_write_config_word(dev, msi_control_reg(pos), msgctl);
308
309 pci_write_config_dword(dev, msi_lower_address_reg(pos),
310 msg->address_lo);
311 if (entry->msi_attrib.is_64) {
312 pci_write_config_dword(dev, msi_upper_address_reg(pos),
313 msg->address_hi);
314 pci_write_config_word(dev, msi_data_reg(pos, 1),
315 msg->data);
316 } else {
317 pci_write_config_word(dev, msi_data_reg(pos, 0),
318 msg->data);
319 }
320 }
321 entry->msg = *msg;
322}
323
324void write_msi_msg(unsigned int irq, struct msi_msg *msg)
325{
326 struct msi_desc *entry = irq_get_msi_desc(irq);
327
328 __write_msi_msg(entry, msg);
329}
330
331static void free_msi_irqs(struct pci_dev *dev)
332{
333 struct msi_desc *entry, *tmp;
334
335 list_for_each_entry(entry, &dev->msi_list, list) {
336 int i, nvec;
337 if (!entry->irq)
338 continue;
339 nvec = 1 << entry->msi_attrib.multiple;
340 for (i = 0; i < nvec; i++)
341 BUG_ON(irq_has_action(entry->irq + i));
342 }
343
344 arch_teardown_msi_irqs(dev);
345
346 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
347 if (entry->msi_attrib.is_msix) {
348 if (list_is_last(&entry->list, &dev->msi_list))
349 iounmap(entry->mask_base);
350 }
351
352 /*
353 * Its possible that we get into this path
354 * When populate_msi_sysfs fails, which means the entries
355 * were not registered with sysfs. In that case don't
356 * unregister them.
357 */
358 if (entry->kobj.parent) {
359 kobject_del(&entry->kobj);
360 kobject_put(&entry->kobj);
361 }
362
363 list_del(&entry->list);
364 kfree(entry);
365 }
366}
367
368static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
369{
370 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
371 if (!desc)
372 return NULL;
373
374 INIT_LIST_HEAD(&desc->list);
375 desc->dev = dev;
376
377 return desc;
378}
379
380static void pci_intx_for_msi(struct pci_dev *dev, int enable)
381{
382 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
383 pci_intx(dev, enable);
384}
385
386static void __pci_restore_msi_state(struct pci_dev *dev)
387{
388 int pos;
389 u16 control;
390 struct msi_desc *entry;
391
392 if (!dev->msi_enabled)
393 return;
394
395 entry = irq_get_msi_desc(dev->irq);
396 pos = entry->msi_attrib.pos;
397
398 pci_intx_for_msi(dev, 0);
399 msi_set_enable(dev, pos, 0);
400 arch_restore_msi_irqs(dev, dev->irq);
401
402 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
403 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
404 control &= ~PCI_MSI_FLAGS_QSIZE;
405 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
406 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
407}
408
409static void __pci_restore_msix_state(struct pci_dev *dev)
410{
411 int pos;
412 struct msi_desc *entry;
413 u16 control;
414
415 if (!dev->msix_enabled)
416 return;
417 BUG_ON(list_empty(&dev->msi_list));
418 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
419 pos = entry->msi_attrib.pos;
420 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
421
422 /* route the table */
423 pci_intx_for_msi(dev, 0);
424 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
425 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
426
427 list_for_each_entry(entry, &dev->msi_list, list) {
428 arch_restore_msi_irqs(dev, entry->irq);
429 msix_mask_irq(entry, entry->masked);
430 }
431
432 control &= ~PCI_MSIX_FLAGS_MASKALL;
433 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
434}
435
436void pci_restore_msi_state(struct pci_dev *dev)
437{
438 __pci_restore_msi_state(dev);
439 __pci_restore_msix_state(dev);
440}
441EXPORT_SYMBOL_GPL(pci_restore_msi_state);
442
443
444#define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
445#define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
446
447struct msi_attribute {
448 struct attribute attr;
449 ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr,
450 char *buf);
451 ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr,
452 const char *buf, size_t count);
453};
454
455static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr,
456 char *buf)
457{
458 return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");
459}
460
461static ssize_t msi_irq_attr_show(struct kobject *kobj,
462 struct attribute *attr, char *buf)
463{
464 struct msi_attribute *attribute = to_msi_attr(attr);
465 struct msi_desc *entry = to_msi_desc(kobj);
466
467 if (!attribute->show)
468 return -EIO;
469
470 return attribute->show(entry, attribute, buf);
471}
472
473static const struct sysfs_ops msi_irq_sysfs_ops = {
474 .show = msi_irq_attr_show,
475};
476
477static struct msi_attribute mode_attribute =
478 __ATTR(mode, S_IRUGO, show_msi_mode, NULL);
479
480
481struct attribute *msi_irq_default_attrs[] = {
482 &mode_attribute.attr,
483 NULL
484};
485
486void msi_kobj_release(struct kobject *kobj)
487{
488 struct msi_desc *entry = to_msi_desc(kobj);
489
490 pci_dev_put(entry->dev);
491}
492
493static struct kobj_type msi_irq_ktype = {
494 .release = msi_kobj_release,
495 .sysfs_ops = &msi_irq_sysfs_ops,
496 .default_attrs = msi_irq_default_attrs,
497};
498
499static int populate_msi_sysfs(struct pci_dev *pdev)
500{
501 struct msi_desc *entry;
502 struct kobject *kobj;
503 int ret;
504 int count = 0;
505
506 pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);
507 if (!pdev->msi_kset)
508 return -ENOMEM;
509
510 list_for_each_entry(entry, &pdev->msi_list, list) {
511 kobj = &entry->kobj;
512 kobj->kset = pdev->msi_kset;
513 pci_dev_get(pdev);
514 ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,
515 "%u", entry->irq);
516 if (ret)
517 goto out_unroll;
518
519 count++;
520 }
521
522 return 0;
523
524out_unroll:
525 list_for_each_entry(entry, &pdev->msi_list, list) {
526 if (!count)
527 break;
528 kobject_del(&entry->kobj);
529 kobject_put(&entry->kobj);
530 count--;
531 }
532 return ret;
533}
534
535/**
536 * msi_capability_init - configure device's MSI capability structure
537 * @dev: pointer to the pci_dev data structure of MSI device function
538 * @nvec: number of interrupts to allocate
539 *
540 * Setup the MSI capability structure of the device with the requested
541 * number of interrupts. A return value of zero indicates the successful
542 * setup of an entry with the new MSI irq. A negative return value indicates
543 * an error, and a positive return value indicates the number of interrupts
544 * which could have been allocated.
545 */
546static int msi_capability_init(struct pci_dev *dev, int nvec)
547{
548 struct msi_desc *entry;
549 int pos, ret;
550 u16 control;
551 unsigned mask;
552
553 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
554 msi_set_enable(dev, pos, 0); /* Disable MSI during set up */
555
556 pci_read_config_word(dev, msi_control_reg(pos), &control);
557 /* MSI Entry Initialization */
558 entry = alloc_msi_entry(dev);
559 if (!entry)
560 return -ENOMEM;
561
562 entry->msi_attrib.is_msix = 0;
563 entry->msi_attrib.is_64 = is_64bit_address(control);
564 entry->msi_attrib.entry_nr = 0;
565 entry->msi_attrib.maskbit = is_mask_bit_support(control);
566 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
567 entry->msi_attrib.pos = pos;
568
569 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
570 /* All MSIs are unmasked by default, Mask them all */
571 if (entry->msi_attrib.maskbit)
572 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
573 mask = msi_capable_mask(control);
574 msi_mask_irq(entry, mask, mask);
575
576 list_add_tail(&entry->list, &dev->msi_list);
577
578 /* Configure MSI capability structure */
579 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
580 if (ret) {
581 msi_mask_irq(entry, mask, ~mask);
582 free_msi_irqs(dev);
583 return ret;
584 }
585
586 ret = populate_msi_sysfs(dev);
587 if (ret) {
588 msi_mask_irq(entry, mask, ~mask);
589 free_msi_irqs(dev);
590 return ret;
591 }
592
593 /* Set MSI enabled bits */
594 pci_intx_for_msi(dev, 0);
595 msi_set_enable(dev, pos, 1);
596 dev->msi_enabled = 1;
597
598 dev->irq = entry->irq;
599 return 0;
600}
601
602static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
603 unsigned nr_entries)
604{
605 resource_size_t phys_addr;
606 u32 table_offset;
607 u8 bir;
608
609 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
610 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
611 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
612 phys_addr = pci_resource_start(dev, bir) + table_offset;
613
614 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
615}
616
617static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
618 void __iomem *base, struct msix_entry *entries,
619 int nvec)
620{
621 struct msi_desc *entry;
622 int i;
623
624 for (i = 0; i < nvec; i++) {
625 entry = alloc_msi_entry(dev);
626 if (!entry) {
627 if (!i)
628 iounmap(base);
629 else
630 free_msi_irqs(dev);
631 /* No enough memory. Don't try again */
632 return -ENOMEM;
633 }
634
635 entry->msi_attrib.is_msix = 1;
636 entry->msi_attrib.is_64 = 1;
637 entry->msi_attrib.entry_nr = entries[i].entry;
638 entry->msi_attrib.default_irq = dev->irq;
639 entry->msi_attrib.pos = pos;
640 entry->mask_base = base;
641
642 list_add_tail(&entry->list, &dev->msi_list);
643 }
644
645 return 0;
646}
647
648static void msix_program_entries(struct pci_dev *dev,
649 struct msix_entry *entries)
650{
651 struct msi_desc *entry;
652 int i = 0;
653
654 list_for_each_entry(entry, &dev->msi_list, list) {
655 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
656 PCI_MSIX_ENTRY_VECTOR_CTRL;
657
658 entries[i].vector = entry->irq;
659 irq_set_msi_desc(entry->irq, entry);
660 entry->masked = readl(entry->mask_base + offset);
661 msix_mask_irq(entry, 1);
662 i++;
663 }
664}
665
666/**
667 * msix_capability_init - configure device's MSI-X capability
668 * @dev: pointer to the pci_dev data structure of MSI-X device function
669 * @entries: pointer to an array of struct msix_entry entries
670 * @nvec: number of @entries
671 *
672 * Setup the MSI-X capability structure of device function with a
673 * single MSI-X irq. A return of zero indicates the successful setup of
674 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
675 **/
676static int msix_capability_init(struct pci_dev *dev,
677 struct msix_entry *entries, int nvec)
678{
679 int pos, ret;
680 u16 control;
681 void __iomem *base;
682
683 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
684 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
685
686 /* Ensure MSI-X is disabled while it is set up */
687 control &= ~PCI_MSIX_FLAGS_ENABLE;
688 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
689
690 /* Request & Map MSI-X table region */
691 base = msix_map_region(dev, pos, multi_msix_capable(control));
692 if (!base)
693 return -ENOMEM;
694
695 ret = msix_setup_entries(dev, pos, base, entries, nvec);
696 if (ret)
697 return ret;
698
699 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
700 if (ret)
701 goto error;
702
703 /*
704 * Some devices require MSI-X to be enabled before we can touch the
705 * MSI-X registers. We need to mask all the vectors to prevent
706 * interrupts coming in before they're fully set up.
707 */
708 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
709 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
710
711 msix_program_entries(dev, entries);
712
713 ret = populate_msi_sysfs(dev);
714 if (ret) {
715 ret = 0;
716 goto error;
717 }
718
719 /* Set MSI-X enabled bits and unmask the function */
720 pci_intx_for_msi(dev, 0);
721 dev->msix_enabled = 1;
722
723 control &= ~PCI_MSIX_FLAGS_MASKALL;
724 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
725
726 return 0;
727
728error:
729 if (ret < 0) {
730 /*
731 * If we had some success, report the number of irqs
732 * we succeeded in setting up.
733 */
734 struct msi_desc *entry;
735 int avail = 0;
736
737 list_for_each_entry(entry, &dev->msi_list, list) {
738 if (entry->irq != 0)
739 avail++;
740 }
741 if (avail != 0)
742 ret = avail;
743 }
744
745 free_msi_irqs(dev);
746
747 return ret;
748}
749
750/**
751 * pci_msi_check_device - check whether MSI may be enabled on a device
752 * @dev: pointer to the pci_dev data structure of MSI device function
753 * @nvec: how many MSIs have been requested ?
754 * @type: are we checking for MSI or MSI-X ?
755 *
756 * Look at global flags, the device itself, and its parent busses
757 * to determine if MSI/-X are supported for the device. If MSI/-X is
758 * supported return 0, else return an error code.
759 **/
760static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
761{
762 struct pci_bus *bus;
763 int ret;
764
765 /* MSI must be globally enabled and supported by the device */
766 if (!pci_msi_enable || !dev || dev->no_msi)
767 return -EINVAL;
768
769 /*
770 * You can't ask to have 0 or less MSIs configured.
771 * a) it's stupid ..
772 * b) the list manipulation code assumes nvec >= 1.
773 */
774 if (nvec < 1)
775 return -ERANGE;
776
777 /*
778 * Any bridge which does NOT route MSI transactions from its
779 * secondary bus to its primary bus must set NO_MSI flag on
780 * the secondary pci_bus.
781 * We expect only arch-specific PCI host bus controller driver
782 * or quirks for specific PCI bridges to be setting NO_MSI.
783 */
784 for (bus = dev->bus; bus; bus = bus->parent)
785 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
786 return -EINVAL;
787
788 ret = arch_msi_check_device(dev, nvec, type);
789 if (ret)
790 return ret;
791
792 if (!pci_find_capability(dev, type))
793 return -EINVAL;
794
795 return 0;
796}
797
798/**
799 * pci_enable_msi_block - configure device's MSI capability structure
800 * @dev: device to configure
801 * @nvec: number of interrupts to configure
802 *
803 * Allocate IRQs for a device with the MSI capability.
804 * This function returns a negative errno if an error occurs. If it
805 * is unable to allocate the number of interrupts requested, it returns
806 * the number of interrupts it might be able to allocate. If it successfully
807 * allocates at least the number of interrupts requested, it returns 0 and
808 * updates the @dev's irq member to the lowest new interrupt number; the
809 * other interrupt numbers allocated to this device are consecutive.
810 */
811int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
812{
813 int status, pos, maxvec;
814 u16 msgctl;
815
816 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
817 if (!pos)
818 return -EINVAL;
819 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
820 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
821 if (nvec > maxvec)
822 return maxvec;
823
824 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
825 if (status)
826 return status;
827
828 WARN_ON(!!dev->msi_enabled);
829
830 /* Check whether driver already requested MSI-X irqs */
831 if (dev->msix_enabled) {
832 dev_info(&dev->dev, "can't enable MSI "
833 "(MSI-X already enabled)\n");
834 return -EINVAL;
835 }
836
837 status = msi_capability_init(dev, nvec);
838 return status;
839}
840EXPORT_SYMBOL(pci_enable_msi_block);
841
842void pci_msi_shutdown(struct pci_dev *dev)
843{
844 struct msi_desc *desc;
845 u32 mask;
846 u16 ctrl;
847 unsigned pos;
848
849 if (!pci_msi_enable || !dev || !dev->msi_enabled)
850 return;
851
852 BUG_ON(list_empty(&dev->msi_list));
853 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
854 pos = desc->msi_attrib.pos;
855
856 msi_set_enable(dev, pos, 0);
857 pci_intx_for_msi(dev, 1);
858 dev->msi_enabled = 0;
859
860 /* Return the device with MSI unmasked as initial states */
861 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
862 mask = msi_capable_mask(ctrl);
863 /* Keep cached state to be restored */
864 __msi_mask_irq(desc, mask, ~mask);
865
866 /* Restore dev->irq to its default pin-assertion irq */
867 dev->irq = desc->msi_attrib.default_irq;
868}
869
870void pci_disable_msi(struct pci_dev *dev)
871{
872 if (!pci_msi_enable || !dev || !dev->msi_enabled)
873 return;
874
875 pci_msi_shutdown(dev);
876 free_msi_irqs(dev);
877 kset_unregister(dev->msi_kset);
878 dev->msi_kset = NULL;
879}
880EXPORT_SYMBOL(pci_disable_msi);
881
882/**
883 * pci_msix_table_size - return the number of device's MSI-X table entries
884 * @dev: pointer to the pci_dev data structure of MSI-X device function
885 */
886int pci_msix_table_size(struct pci_dev *dev)
887{
888 int pos;
889 u16 control;
890
891 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
892 if (!pos)
893 return 0;
894
895 pci_read_config_word(dev, msi_control_reg(pos), &control);
896 return multi_msix_capable(control);
897}
898
899/**
900 * pci_enable_msix - configure device's MSI-X capability structure
901 * @dev: pointer to the pci_dev data structure of MSI-X device function
902 * @entries: pointer to an array of MSI-X entries
903 * @nvec: number of MSI-X irqs requested for allocation by device driver
904 *
905 * Setup the MSI-X capability structure of device function with the number
906 * of requested irqs upon its software driver call to request for
907 * MSI-X mode enabled on its hardware device function. A return of zero
908 * indicates the successful configuration of MSI-X capability structure
909 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
910 * Or a return of > 0 indicates that driver request is exceeding the number
911 * of irqs or MSI-X vectors available. Driver should use the returned value to
912 * re-send its request.
913 **/
914int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
915{
916 int status, nr_entries;
917 int i, j;
918
919 if (!entries)
920 return -EINVAL;
921
922 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
923 if (status)
924 return status;
925
926 nr_entries = pci_msix_table_size(dev);
927 if (nvec > nr_entries)
928 return nr_entries;
929
930 /* Check for any invalid entries */
931 for (i = 0; i < nvec; i++) {
932 if (entries[i].entry >= nr_entries)
933 return -EINVAL; /* invalid entry */
934 for (j = i + 1; j < nvec; j++) {
935 if (entries[i].entry == entries[j].entry)
936 return -EINVAL; /* duplicate entry */
937 }
938 }
939 WARN_ON(!!dev->msix_enabled);
940
941 /* Check whether driver already requested for MSI irq */
942 if (dev->msi_enabled) {
943 dev_info(&dev->dev, "can't enable MSI-X "
944 "(MSI IRQ already assigned)\n");
945 return -EINVAL;
946 }
947 status = msix_capability_init(dev, entries, nvec);
948 return status;
949}
950EXPORT_SYMBOL(pci_enable_msix);
951
952void pci_msix_shutdown(struct pci_dev *dev)
953{
954 struct msi_desc *entry;
955
956 if (!pci_msi_enable || !dev || !dev->msix_enabled)
957 return;
958
959 /* Return the device with MSI-X masked as initial states */
960 list_for_each_entry(entry, &dev->msi_list, list) {
961 /* Keep cached states to be restored */
962 __msix_mask_irq(entry, 1);
963 }
964
965 msix_set_enable(dev, 0);
966 pci_intx_for_msi(dev, 1);
967 dev->msix_enabled = 0;
968}
969
970void pci_disable_msix(struct pci_dev *dev)
971{
972 if (!pci_msi_enable || !dev || !dev->msix_enabled)
973 return;
974
975 pci_msix_shutdown(dev);
976 free_msi_irqs(dev);
977 kset_unregister(dev->msi_kset);
978 dev->msi_kset = NULL;
979}
980EXPORT_SYMBOL(pci_disable_msix);
981
982/**
983 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
984 * @dev: pointer to the pci_dev data structure of MSI(X) device function
985 *
986 * Being called during hotplug remove, from which the device function
987 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
988 * allocated for this device function, are reclaimed to unused state,
989 * which may be used later on.
990 **/
991void msi_remove_pci_irq_vectors(struct pci_dev *dev)
992{
993 if (!pci_msi_enable || !dev)
994 return;
995
996 if (dev->msi_enabled || dev->msix_enabled)
997 free_msi_irqs(dev);
998}
999
1000void pci_no_msi(void)
1001{
1002 pci_msi_enable = 0;
1003}
1004
1005/**
1006 * pci_msi_enabled - is MSI enabled?
1007 *
1008 * Returns true if MSI has not been disabled by the command-line option
1009 * pci=nomsi.
1010 **/
1011int pci_msi_enabled(void)
1012{
1013 return pci_msi_enable;
1014}
1015EXPORT_SYMBOL(pci_msi_enabled);
1016
1017void pci_msi_init_pci_dev(struct pci_dev *dev)
1018{
1019 int pos;
1020 INIT_LIST_HEAD(&dev->msi_list);
1021
1022 /* Disable the msi hardware to avoid screaming interrupts
1023 * during boot. This is the power on reset default so
1024 * usually this should be a noop.
1025 */
1026 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1027 if (pos)
1028 msi_set_enable(dev, pos, 0);
1029 msix_set_enable(dev, 0);
1030}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
8 */
9
10#include <linux/err.h>
11#include <linux/mm.h>
12#include <linux/irq.h>
13#include <linux/interrupt.h>
14#include <linux/export.h>
15#include <linux/ioport.h>
16#include <linux/pci.h>
17#include <linux/proc_fs.h>
18#include <linux/msi.h>
19#include <linux/smp.h>
20#include <linux/errno.h>
21#include <linux/io.h>
22#include <linux/acpi_iort.h>
23#include <linux/slab.h>
24#include <linux/irqdomain.h>
25#include <linux/of_irq.h>
26
27#include "pci.h"
28
29static int pci_msi_enable = 1;
30int pci_msi_ignore_mask;
31
32#define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33
34#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
35static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
36{
37 struct irq_domain *domain;
38
39 domain = dev_get_msi_domain(&dev->dev);
40 if (domain && irq_domain_is_hierarchy(domain))
41 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
42
43 return arch_setup_msi_irqs(dev, nvec, type);
44}
45
46static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
47{
48 struct irq_domain *domain;
49
50 domain = dev_get_msi_domain(&dev->dev);
51 if (domain && irq_domain_is_hierarchy(domain))
52 msi_domain_free_irqs(domain, &dev->dev);
53 else
54 arch_teardown_msi_irqs(dev);
55}
56#else
57#define pci_msi_setup_msi_irqs arch_setup_msi_irqs
58#define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
59#endif
60
61/* Arch hooks */
62
63int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
64{
65 struct msi_controller *chip = dev->bus->msi;
66 int err;
67
68 if (!chip || !chip->setup_irq)
69 return -EINVAL;
70
71 err = chip->setup_irq(chip, dev, desc);
72 if (err < 0)
73 return err;
74
75 irq_set_chip_data(desc->irq, chip);
76
77 return 0;
78}
79
80void __weak arch_teardown_msi_irq(unsigned int irq)
81{
82 struct msi_controller *chip = irq_get_chip_data(irq);
83
84 if (!chip || !chip->teardown_irq)
85 return;
86
87 chip->teardown_irq(chip, irq);
88}
89
90int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
91{
92 struct msi_controller *chip = dev->bus->msi;
93 struct msi_desc *entry;
94 int ret;
95
96 if (chip && chip->setup_irqs)
97 return chip->setup_irqs(chip, dev, nvec, type);
98 /*
99 * If an architecture wants to support multiple MSI, it needs to
100 * override arch_setup_msi_irqs()
101 */
102 if (type == PCI_CAP_ID_MSI && nvec > 1)
103 return 1;
104
105 for_each_pci_msi_entry(entry, dev) {
106 ret = arch_setup_msi_irq(dev, entry);
107 if (ret < 0)
108 return ret;
109 if (ret > 0)
110 return -ENOSPC;
111 }
112
113 return 0;
114}
115
116/*
117 * We have a default implementation available as a separate non-weak
118 * function, as it is used by the Xen x86 PCI code
119 */
120void default_teardown_msi_irqs(struct pci_dev *dev)
121{
122 int i;
123 struct msi_desc *entry;
124
125 for_each_pci_msi_entry(entry, dev)
126 if (entry->irq)
127 for (i = 0; i < entry->nvec_used; i++)
128 arch_teardown_msi_irq(entry->irq + i);
129}
130
131void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
132{
133 return default_teardown_msi_irqs(dev);
134}
135
136static void default_restore_msi_irq(struct pci_dev *dev, int irq)
137{
138 struct msi_desc *entry;
139
140 entry = NULL;
141 if (dev->msix_enabled) {
142 for_each_pci_msi_entry(entry, dev) {
143 if (irq == entry->irq)
144 break;
145 }
146 } else if (dev->msi_enabled) {
147 entry = irq_get_msi_desc(irq);
148 }
149
150 if (entry)
151 __pci_write_msi_msg(entry, &entry->msg);
152}
153
154void __weak arch_restore_msi_irqs(struct pci_dev *dev)
155{
156 return default_restore_msi_irqs(dev);
157}
158
159static inline __attribute_const__ u32 msi_mask(unsigned x)
160{
161 /* Don't shift by >= width of type */
162 if (x >= 5)
163 return 0xffffffff;
164 return (1 << (1 << x)) - 1;
165}
166
167/*
168 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
169 * mask all MSI interrupts by clearing the MSI enable bit does not work
170 * reliably as devices without an INTx disable bit will then generate a
171 * level IRQ which will never be cleared.
172 */
173u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
174{
175 u32 mask_bits = desc->masked;
176
177 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
178 return 0;
179
180 mask_bits &= ~mask;
181 mask_bits |= flag;
182 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
183 mask_bits);
184
185 return mask_bits;
186}
187
188static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
189{
190 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
191}
192
193static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
194{
195 if (desc->msi_attrib.is_virtual)
196 return NULL;
197
198 return desc->mask_base +
199 desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
200}
201
202/*
203 * This internal function does not flush PCI writes to the device.
204 * All users must ensure that they read from the device before either
205 * assuming that the device state is up to date, or returning out of this
206 * file. This saves a few milliseconds when initialising devices with lots
207 * of MSI-X interrupts.
208 */
209u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
210{
211 u32 mask_bits = desc->masked;
212 void __iomem *desc_addr;
213
214 if (pci_msi_ignore_mask)
215 return 0;
216
217 desc_addr = pci_msix_desc_addr(desc);
218 if (!desc_addr)
219 return 0;
220
221 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
222 if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
223 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
224
225 writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
226
227 return mask_bits;
228}
229
230static void msix_mask_irq(struct msi_desc *desc, u32 flag)
231{
232 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
233}
234
235static void msi_set_mask_bit(struct irq_data *data, u32 flag)
236{
237 struct msi_desc *desc = irq_data_get_msi_desc(data);
238
239 if (desc->msi_attrib.is_msix) {
240 msix_mask_irq(desc, flag);
241 readl(desc->mask_base); /* Flush write to device */
242 } else {
243 unsigned offset = data->irq - desc->irq;
244 msi_mask_irq(desc, 1 << offset, flag << offset);
245 }
246}
247
248/**
249 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
250 * @data: pointer to irqdata associated to that interrupt
251 */
252void pci_msi_mask_irq(struct irq_data *data)
253{
254 msi_set_mask_bit(data, 1);
255}
256EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
257
258/**
259 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
260 * @data: pointer to irqdata associated to that interrupt
261 */
262void pci_msi_unmask_irq(struct irq_data *data)
263{
264 msi_set_mask_bit(data, 0);
265}
266EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
267
268void default_restore_msi_irqs(struct pci_dev *dev)
269{
270 struct msi_desc *entry;
271
272 for_each_pci_msi_entry(entry, dev)
273 default_restore_msi_irq(dev, entry->irq);
274}
275
276void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
277{
278 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
279
280 BUG_ON(dev->current_state != PCI_D0);
281
282 if (entry->msi_attrib.is_msix) {
283 void __iomem *base = pci_msix_desc_addr(entry);
284
285 if (!base) {
286 WARN_ON(1);
287 return;
288 }
289
290 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
291 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
292 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
293 } else {
294 int pos = dev->msi_cap;
295 u16 data;
296
297 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
298 &msg->address_lo);
299 if (entry->msi_attrib.is_64) {
300 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
301 &msg->address_hi);
302 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
303 } else {
304 msg->address_hi = 0;
305 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
306 }
307 msg->data = data;
308 }
309}
310
311void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
312{
313 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
314
315 if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
316 /* Don't touch the hardware now */
317 } else if (entry->msi_attrib.is_msix) {
318 void __iomem *base = pci_msix_desc_addr(entry);
319
320 if (!base)
321 goto skip;
322
323 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
324 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
325 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
326 } else {
327 int pos = dev->msi_cap;
328 u16 msgctl;
329
330 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
331 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
332 msgctl |= entry->msi_attrib.multiple << 4;
333 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
334
335 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
336 msg->address_lo);
337 if (entry->msi_attrib.is_64) {
338 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
339 msg->address_hi);
340 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
341 msg->data);
342 } else {
343 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
344 msg->data);
345 }
346 }
347
348skip:
349 entry->msg = *msg;
350
351 if (entry->write_msi_msg)
352 entry->write_msi_msg(entry, entry->write_msi_msg_data);
353
354}
355
356void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
357{
358 struct msi_desc *entry = irq_get_msi_desc(irq);
359
360 __pci_write_msi_msg(entry, msg);
361}
362EXPORT_SYMBOL_GPL(pci_write_msi_msg);
363
364static void free_msi_irqs(struct pci_dev *dev)
365{
366 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
367 struct msi_desc *entry, *tmp;
368 struct attribute **msi_attrs;
369 struct device_attribute *dev_attr;
370 int i, count = 0;
371
372 for_each_pci_msi_entry(entry, dev)
373 if (entry->irq)
374 for (i = 0; i < entry->nvec_used; i++)
375 BUG_ON(irq_has_action(entry->irq + i));
376
377 pci_msi_teardown_msi_irqs(dev);
378
379 list_for_each_entry_safe(entry, tmp, msi_list, list) {
380 if (entry->msi_attrib.is_msix) {
381 if (list_is_last(&entry->list, msi_list))
382 iounmap(entry->mask_base);
383 }
384
385 list_del(&entry->list);
386 free_msi_entry(entry);
387 }
388
389 if (dev->msi_irq_groups) {
390 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
391 msi_attrs = dev->msi_irq_groups[0]->attrs;
392 while (msi_attrs[count]) {
393 dev_attr = container_of(msi_attrs[count],
394 struct device_attribute, attr);
395 kfree(dev_attr->attr.name);
396 kfree(dev_attr);
397 ++count;
398 }
399 kfree(msi_attrs);
400 kfree(dev->msi_irq_groups[0]);
401 kfree(dev->msi_irq_groups);
402 dev->msi_irq_groups = NULL;
403 }
404}
405
406static void pci_intx_for_msi(struct pci_dev *dev, int enable)
407{
408 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
409 pci_intx(dev, enable);
410}
411
412static void __pci_restore_msi_state(struct pci_dev *dev)
413{
414 u16 control;
415 struct msi_desc *entry;
416
417 if (!dev->msi_enabled)
418 return;
419
420 entry = irq_get_msi_desc(dev->irq);
421
422 pci_intx_for_msi(dev, 0);
423 pci_msi_set_enable(dev, 0);
424 arch_restore_msi_irqs(dev);
425
426 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
427 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
428 entry->masked);
429 control &= ~PCI_MSI_FLAGS_QSIZE;
430 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
431 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
432}
433
434static void __pci_restore_msix_state(struct pci_dev *dev)
435{
436 struct msi_desc *entry;
437
438 if (!dev->msix_enabled)
439 return;
440 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
441
442 /* route the table */
443 pci_intx_for_msi(dev, 0);
444 pci_msix_clear_and_set_ctrl(dev, 0,
445 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
446
447 arch_restore_msi_irqs(dev);
448 for_each_pci_msi_entry(entry, dev)
449 msix_mask_irq(entry, entry->masked);
450
451 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
452}
453
454void pci_restore_msi_state(struct pci_dev *dev)
455{
456 __pci_restore_msi_state(dev);
457 __pci_restore_msix_state(dev);
458}
459EXPORT_SYMBOL_GPL(pci_restore_msi_state);
460
461static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
462 char *buf)
463{
464 struct msi_desc *entry;
465 unsigned long irq;
466 int retval;
467
468 retval = kstrtoul(attr->attr.name, 10, &irq);
469 if (retval)
470 return retval;
471
472 entry = irq_get_msi_desc(irq);
473 if (entry)
474 return sprintf(buf, "%s\n",
475 entry->msi_attrib.is_msix ? "msix" : "msi");
476
477 return -ENODEV;
478}
479
480static int populate_msi_sysfs(struct pci_dev *pdev)
481{
482 struct attribute **msi_attrs;
483 struct attribute *msi_attr;
484 struct device_attribute *msi_dev_attr;
485 struct attribute_group *msi_irq_group;
486 const struct attribute_group **msi_irq_groups;
487 struct msi_desc *entry;
488 int ret = -ENOMEM;
489 int num_msi = 0;
490 int count = 0;
491 int i;
492
493 /* Determine how many msi entries we have */
494 for_each_pci_msi_entry(entry, pdev)
495 num_msi += entry->nvec_used;
496 if (!num_msi)
497 return 0;
498
499 /* Dynamically create the MSI attributes for the PCI device */
500 msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL);
501 if (!msi_attrs)
502 return -ENOMEM;
503 for_each_pci_msi_entry(entry, pdev) {
504 for (i = 0; i < entry->nvec_used; i++) {
505 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
506 if (!msi_dev_attr)
507 goto error_attrs;
508 msi_attrs[count] = &msi_dev_attr->attr;
509
510 sysfs_attr_init(&msi_dev_attr->attr);
511 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
512 entry->irq + i);
513 if (!msi_dev_attr->attr.name)
514 goto error_attrs;
515 msi_dev_attr->attr.mode = S_IRUGO;
516 msi_dev_attr->show = msi_mode_show;
517 ++count;
518 }
519 }
520
521 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
522 if (!msi_irq_group)
523 goto error_attrs;
524 msi_irq_group->name = "msi_irqs";
525 msi_irq_group->attrs = msi_attrs;
526
527 msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL);
528 if (!msi_irq_groups)
529 goto error_irq_group;
530 msi_irq_groups[0] = msi_irq_group;
531
532 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
533 if (ret)
534 goto error_irq_groups;
535 pdev->msi_irq_groups = msi_irq_groups;
536
537 return 0;
538
539error_irq_groups:
540 kfree(msi_irq_groups);
541error_irq_group:
542 kfree(msi_irq_group);
543error_attrs:
544 count = 0;
545 msi_attr = msi_attrs[count];
546 while (msi_attr) {
547 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
548 kfree(msi_attr->name);
549 kfree(msi_dev_attr);
550 ++count;
551 msi_attr = msi_attrs[count];
552 }
553 kfree(msi_attrs);
554 return ret;
555}
556
557static struct msi_desc *
558msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
559{
560 struct irq_affinity_desc *masks = NULL;
561 struct msi_desc *entry;
562 u16 control;
563
564 if (affd)
565 masks = irq_create_affinity_masks(nvec, affd);
566
567 /* MSI Entry Initialization */
568 entry = alloc_msi_entry(&dev->dev, nvec, masks);
569 if (!entry)
570 goto out;
571
572 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
573
574 entry->msi_attrib.is_msix = 0;
575 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
576 entry->msi_attrib.is_virtual = 0;
577 entry->msi_attrib.entry_nr = 0;
578 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
579 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
580 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
581 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
582
583 if (control & PCI_MSI_FLAGS_64BIT)
584 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
585 else
586 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
587
588 /* Save the initial mask status */
589 if (entry->msi_attrib.maskbit)
590 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
591
592out:
593 kfree(masks);
594 return entry;
595}
596
597static int msi_verify_entries(struct pci_dev *dev)
598{
599 struct msi_desc *entry;
600
601 for_each_pci_msi_entry(entry, dev) {
602 if (!dev->no_64bit_msi || !entry->msg.address_hi)
603 continue;
604 pci_err(dev, "Device has broken 64-bit MSI but arch"
605 " tried to assign one above 4G\n");
606 return -EIO;
607 }
608 return 0;
609}
610
611/**
612 * msi_capability_init - configure device's MSI capability structure
613 * @dev: pointer to the pci_dev data structure of MSI device function
614 * @nvec: number of interrupts to allocate
615 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
616 *
617 * Setup the MSI capability structure of the device with the requested
618 * number of interrupts. A return value of zero indicates the successful
619 * setup of an entry with the new MSI IRQ. A negative return value indicates
620 * an error, and a positive return value indicates the number of interrupts
621 * which could have been allocated.
622 */
623static int msi_capability_init(struct pci_dev *dev, int nvec,
624 struct irq_affinity *affd)
625{
626 struct msi_desc *entry;
627 int ret;
628 unsigned mask;
629
630 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
631
632 entry = msi_setup_entry(dev, nvec, affd);
633 if (!entry)
634 return -ENOMEM;
635
636 /* All MSIs are unmasked by default; mask them all */
637 mask = msi_mask(entry->msi_attrib.multi_cap);
638 msi_mask_irq(entry, mask, mask);
639
640 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
641
642 /* Configure MSI capability structure */
643 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
644 if (ret) {
645 msi_mask_irq(entry, mask, ~mask);
646 free_msi_irqs(dev);
647 return ret;
648 }
649
650 ret = msi_verify_entries(dev);
651 if (ret) {
652 msi_mask_irq(entry, mask, ~mask);
653 free_msi_irqs(dev);
654 return ret;
655 }
656
657 ret = populate_msi_sysfs(dev);
658 if (ret) {
659 msi_mask_irq(entry, mask, ~mask);
660 free_msi_irqs(dev);
661 return ret;
662 }
663
664 /* Set MSI enabled bits */
665 pci_intx_for_msi(dev, 0);
666 pci_msi_set_enable(dev, 1);
667 dev->msi_enabled = 1;
668
669 pcibios_free_irq(dev);
670 dev->irq = entry->irq;
671 return 0;
672}
673
674static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
675{
676 resource_size_t phys_addr;
677 u32 table_offset;
678 unsigned long flags;
679 u8 bir;
680
681 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
682 &table_offset);
683 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
684 flags = pci_resource_flags(dev, bir);
685 if (!flags || (flags & IORESOURCE_UNSET))
686 return NULL;
687
688 table_offset &= PCI_MSIX_TABLE_OFFSET;
689 phys_addr = pci_resource_start(dev, bir) + table_offset;
690
691 return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
692}
693
694static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
695 struct msix_entry *entries, int nvec,
696 struct irq_affinity *affd)
697{
698 struct irq_affinity_desc *curmsk, *masks = NULL;
699 struct msi_desc *entry;
700 int ret, i;
701 int vec_count = pci_msix_vec_count(dev);
702
703 if (affd)
704 masks = irq_create_affinity_masks(nvec, affd);
705
706 for (i = 0, curmsk = masks; i < nvec; i++) {
707 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
708 if (!entry) {
709 if (!i)
710 iounmap(base);
711 else
712 free_msi_irqs(dev);
713 /* No enough memory. Don't try again */
714 ret = -ENOMEM;
715 goto out;
716 }
717
718 entry->msi_attrib.is_msix = 1;
719 entry->msi_attrib.is_64 = 1;
720 if (entries)
721 entry->msi_attrib.entry_nr = entries[i].entry;
722 else
723 entry->msi_attrib.entry_nr = i;
724
725 entry->msi_attrib.is_virtual =
726 entry->msi_attrib.entry_nr >= vec_count;
727
728 entry->msi_attrib.default_irq = dev->irq;
729 entry->mask_base = base;
730
731 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
732 if (masks)
733 curmsk++;
734 }
735 ret = 0;
736out:
737 kfree(masks);
738 return ret;
739}
740
741static void msix_program_entries(struct pci_dev *dev,
742 struct msix_entry *entries)
743{
744 struct msi_desc *entry;
745 int i = 0;
746 void __iomem *desc_addr;
747
748 for_each_pci_msi_entry(entry, dev) {
749 if (entries)
750 entries[i++].vector = entry->irq;
751
752 desc_addr = pci_msix_desc_addr(entry);
753 if (desc_addr)
754 entry->masked = readl(desc_addr +
755 PCI_MSIX_ENTRY_VECTOR_CTRL);
756 else
757 entry->masked = 0;
758
759 msix_mask_irq(entry, 1);
760 }
761}
762
763/**
764 * msix_capability_init - configure device's MSI-X capability
765 * @dev: pointer to the pci_dev data structure of MSI-X device function
766 * @entries: pointer to an array of struct msix_entry entries
767 * @nvec: number of @entries
768 * @affd: Optional pointer to enable automatic affinity assignment
769 *
770 * Setup the MSI-X capability structure of device function with a
771 * single MSI-X IRQ. A return of zero indicates the successful setup of
772 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
773 **/
774static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
775 int nvec, struct irq_affinity *affd)
776{
777 int ret;
778 u16 control;
779 void __iomem *base;
780
781 /* Ensure MSI-X is disabled while it is set up */
782 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
783
784 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
785 /* Request & Map MSI-X table region */
786 base = msix_map_region(dev, msix_table_size(control));
787 if (!base)
788 return -ENOMEM;
789
790 ret = msix_setup_entries(dev, base, entries, nvec, affd);
791 if (ret)
792 return ret;
793
794 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
795 if (ret)
796 goto out_avail;
797
798 /* Check if all MSI entries honor device restrictions */
799 ret = msi_verify_entries(dev);
800 if (ret)
801 goto out_free;
802
803 /*
804 * Some devices require MSI-X to be enabled before we can touch the
805 * MSI-X registers. We need to mask all the vectors to prevent
806 * interrupts coming in before they're fully set up.
807 */
808 pci_msix_clear_and_set_ctrl(dev, 0,
809 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
810
811 msix_program_entries(dev, entries);
812
813 ret = populate_msi_sysfs(dev);
814 if (ret)
815 goto out_free;
816
817 /* Set MSI-X enabled bits and unmask the function */
818 pci_intx_for_msi(dev, 0);
819 dev->msix_enabled = 1;
820 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
821
822 pcibios_free_irq(dev);
823 return 0;
824
825out_avail:
826 if (ret < 0) {
827 /*
828 * If we had some success, report the number of IRQs
829 * we succeeded in setting up.
830 */
831 struct msi_desc *entry;
832 int avail = 0;
833
834 for_each_pci_msi_entry(entry, dev) {
835 if (entry->irq != 0)
836 avail++;
837 }
838 if (avail != 0)
839 ret = avail;
840 }
841
842out_free:
843 free_msi_irqs(dev);
844
845 return ret;
846}
847
848/**
849 * pci_msi_supported - check whether MSI may be enabled on a device
850 * @dev: pointer to the pci_dev data structure of MSI device function
851 * @nvec: how many MSIs have been requested?
852 *
853 * Look at global flags, the device itself, and its parent buses
854 * to determine if MSI/-X are supported for the device. If MSI/-X is
855 * supported return 1, else return 0.
856 **/
857static int pci_msi_supported(struct pci_dev *dev, int nvec)
858{
859 struct pci_bus *bus;
860
861 /* MSI must be globally enabled and supported by the device */
862 if (!pci_msi_enable)
863 return 0;
864
865 if (!dev || dev->no_msi)
866 return 0;
867
868 /*
869 * You can't ask to have 0 or less MSIs configured.
870 * a) it's stupid ..
871 * b) the list manipulation code assumes nvec >= 1.
872 */
873 if (nvec < 1)
874 return 0;
875
876 /*
877 * Any bridge which does NOT route MSI transactions from its
878 * secondary bus to its primary bus must set NO_MSI flag on
879 * the secondary pci_bus.
880 * We expect only arch-specific PCI host bus controller driver
881 * or quirks for specific PCI bridges to be setting NO_MSI.
882 */
883 for (bus = dev->bus; bus; bus = bus->parent)
884 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
885 return 0;
886
887 return 1;
888}
889
890/**
891 * pci_msi_vec_count - Return the number of MSI vectors a device can send
892 * @dev: device to report about
893 *
894 * This function returns the number of MSI vectors a device requested via
895 * Multiple Message Capable register. It returns a negative errno if the
896 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
897 * and returns a power of two, up to a maximum of 2^5 (32), according to the
898 * MSI specification.
899 **/
900int pci_msi_vec_count(struct pci_dev *dev)
901{
902 int ret;
903 u16 msgctl;
904
905 if (!dev->msi_cap)
906 return -EINVAL;
907
908 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
909 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
910
911 return ret;
912}
913EXPORT_SYMBOL(pci_msi_vec_count);
914
915static void pci_msi_shutdown(struct pci_dev *dev)
916{
917 struct msi_desc *desc;
918 u32 mask;
919
920 if (!pci_msi_enable || !dev || !dev->msi_enabled)
921 return;
922
923 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
924 desc = first_pci_msi_entry(dev);
925
926 pci_msi_set_enable(dev, 0);
927 pci_intx_for_msi(dev, 1);
928 dev->msi_enabled = 0;
929
930 /* Return the device with MSI unmasked as initial states */
931 mask = msi_mask(desc->msi_attrib.multi_cap);
932 /* Keep cached state to be restored */
933 __pci_msi_desc_mask_irq(desc, mask, ~mask);
934
935 /* Restore dev->irq to its default pin-assertion IRQ */
936 dev->irq = desc->msi_attrib.default_irq;
937 pcibios_alloc_irq(dev);
938}
939
940void pci_disable_msi(struct pci_dev *dev)
941{
942 if (!pci_msi_enable || !dev || !dev->msi_enabled)
943 return;
944
945 pci_msi_shutdown(dev);
946 free_msi_irqs(dev);
947}
948EXPORT_SYMBOL(pci_disable_msi);
949
950/**
951 * pci_msix_vec_count - return the number of device's MSI-X table entries
952 * @dev: pointer to the pci_dev data structure of MSI-X device function
953 * This function returns the number of device's MSI-X table entries and
954 * therefore the number of MSI-X vectors device is capable of sending.
955 * It returns a negative errno if the device is not capable of sending MSI-X
956 * interrupts.
957 **/
958int pci_msix_vec_count(struct pci_dev *dev)
959{
960 u16 control;
961
962 if (!dev->msix_cap)
963 return -EINVAL;
964
965 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
966 return msix_table_size(control);
967}
968EXPORT_SYMBOL(pci_msix_vec_count);
969
970static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
971 int nvec, struct irq_affinity *affd, int flags)
972{
973 int nr_entries;
974 int i, j;
975
976 if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0)
977 return -EINVAL;
978
979 nr_entries = pci_msix_vec_count(dev);
980 if (nr_entries < 0)
981 return nr_entries;
982 if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
983 return nr_entries;
984
985 if (entries) {
986 /* Check for any invalid entries */
987 for (i = 0; i < nvec; i++) {
988 if (entries[i].entry >= nr_entries)
989 return -EINVAL; /* invalid entry */
990 for (j = i + 1; j < nvec; j++) {
991 if (entries[i].entry == entries[j].entry)
992 return -EINVAL; /* duplicate entry */
993 }
994 }
995 }
996
997 /* Check whether driver already requested for MSI IRQ */
998 if (dev->msi_enabled) {
999 pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
1000 return -EINVAL;
1001 }
1002 return msix_capability_init(dev, entries, nvec, affd);
1003}
1004
1005static void pci_msix_shutdown(struct pci_dev *dev)
1006{
1007 struct msi_desc *entry;
1008
1009 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1010 return;
1011
1012 if (pci_dev_is_disconnected(dev)) {
1013 dev->msix_enabled = 0;
1014 return;
1015 }
1016
1017 /* Return the device with MSI-X masked as initial states */
1018 for_each_pci_msi_entry(entry, dev) {
1019 /* Keep cached states to be restored */
1020 __pci_msix_desc_mask_irq(entry, 1);
1021 }
1022
1023 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1024 pci_intx_for_msi(dev, 1);
1025 dev->msix_enabled = 0;
1026 pcibios_alloc_irq(dev);
1027}
1028
1029void pci_disable_msix(struct pci_dev *dev)
1030{
1031 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1032 return;
1033
1034 pci_msix_shutdown(dev);
1035 free_msi_irqs(dev);
1036}
1037EXPORT_SYMBOL(pci_disable_msix);
1038
1039void pci_no_msi(void)
1040{
1041 pci_msi_enable = 0;
1042}
1043
1044/**
1045 * pci_msi_enabled - is MSI enabled?
1046 *
1047 * Returns true if MSI has not been disabled by the command-line option
1048 * pci=nomsi.
1049 **/
1050int pci_msi_enabled(void)
1051{
1052 return pci_msi_enable;
1053}
1054EXPORT_SYMBOL(pci_msi_enabled);
1055
1056static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1057 struct irq_affinity *affd)
1058{
1059 int nvec;
1060 int rc;
1061
1062 if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
1063 return -EINVAL;
1064
1065 /* Check whether driver already requested MSI-X IRQs */
1066 if (dev->msix_enabled) {
1067 pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
1068 return -EINVAL;
1069 }
1070
1071 if (maxvec < minvec)
1072 return -ERANGE;
1073
1074 if (WARN_ON_ONCE(dev->msi_enabled))
1075 return -EINVAL;
1076
1077 nvec = pci_msi_vec_count(dev);
1078 if (nvec < 0)
1079 return nvec;
1080 if (nvec < minvec)
1081 return -ENOSPC;
1082
1083 if (nvec > maxvec)
1084 nvec = maxvec;
1085
1086 for (;;) {
1087 if (affd) {
1088 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1089 if (nvec < minvec)
1090 return -ENOSPC;
1091 }
1092
1093 rc = msi_capability_init(dev, nvec, affd);
1094 if (rc == 0)
1095 return nvec;
1096
1097 if (rc < 0)
1098 return rc;
1099 if (rc < minvec)
1100 return -ENOSPC;
1101
1102 nvec = rc;
1103 }
1104}
1105
1106/* deprecated, don't use */
1107int pci_enable_msi(struct pci_dev *dev)
1108{
1109 int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
1110 if (rc < 0)
1111 return rc;
1112 return 0;
1113}
1114EXPORT_SYMBOL(pci_enable_msi);
1115
1116static int __pci_enable_msix_range(struct pci_dev *dev,
1117 struct msix_entry *entries, int minvec,
1118 int maxvec, struct irq_affinity *affd,
1119 int flags)
1120{
1121 int rc, nvec = maxvec;
1122
1123 if (maxvec < minvec)
1124 return -ERANGE;
1125
1126 if (WARN_ON_ONCE(dev->msix_enabled))
1127 return -EINVAL;
1128
1129 for (;;) {
1130 if (affd) {
1131 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1132 if (nvec < minvec)
1133 return -ENOSPC;
1134 }
1135
1136 rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
1137 if (rc == 0)
1138 return nvec;
1139
1140 if (rc < 0)
1141 return rc;
1142 if (rc < minvec)
1143 return -ENOSPC;
1144
1145 nvec = rc;
1146 }
1147}
1148
1149/**
1150 * pci_enable_msix_range - configure device's MSI-X capability structure
1151 * @dev: pointer to the pci_dev data structure of MSI-X device function
1152 * @entries: pointer to an array of MSI-X entries
1153 * @minvec: minimum number of MSI-X IRQs requested
1154 * @maxvec: maximum number of MSI-X IRQs requested
1155 *
1156 * Setup the MSI-X capability structure of device function with a maximum
1157 * possible number of interrupts in the range between @minvec and @maxvec
1158 * upon its software driver call to request for MSI-X mode enabled on its
1159 * hardware device function. It returns a negative errno if an error occurs.
1160 * If it succeeds, it returns the actual number of interrupts allocated and
1161 * indicates the successful configuration of MSI-X capability structure
1162 * with new allocated MSI-X interrupts.
1163 **/
1164int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1165 int minvec, int maxvec)
1166{
1167 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
1168}
1169EXPORT_SYMBOL(pci_enable_msix_range);
1170
1171/**
1172 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1173 * @dev: PCI device to operate on
1174 * @min_vecs: minimum number of vectors required (must be >= 1)
1175 * @max_vecs: maximum (desired) number of vectors
1176 * @flags: flags or quirks for the allocation
1177 * @affd: optional description of the affinity requirements
1178 *
1179 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1180 * vectors if available, and fall back to a single legacy vector
1181 * if neither is available. Return the number of vectors allocated,
1182 * (which might be smaller than @max_vecs) if successful, or a negative
1183 * error code on error. If less than @min_vecs interrupt vectors are
1184 * available for @dev the function will fail with -ENOSPC.
1185 *
1186 * To get the Linux IRQ number used for a vector that can be passed to
1187 * request_irq() use the pci_irq_vector() helper.
1188 */
1189int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1190 unsigned int max_vecs, unsigned int flags,
1191 struct irq_affinity *affd)
1192{
1193 struct irq_affinity msi_default_affd = {0};
1194 int nvecs = -ENOSPC;
1195
1196 if (flags & PCI_IRQ_AFFINITY) {
1197 if (!affd)
1198 affd = &msi_default_affd;
1199 } else {
1200 if (WARN_ON(affd))
1201 affd = NULL;
1202 }
1203
1204 if (flags & PCI_IRQ_MSIX) {
1205 nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1206 affd, flags);
1207 if (nvecs > 0)
1208 return nvecs;
1209 }
1210
1211 if (flags & PCI_IRQ_MSI) {
1212 nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
1213 if (nvecs > 0)
1214 return nvecs;
1215 }
1216
1217 /* use legacy IRQ if allowed */
1218 if (flags & PCI_IRQ_LEGACY) {
1219 if (min_vecs == 1 && dev->irq) {
1220 /*
1221 * Invoke the affinity spreading logic to ensure that
1222 * the device driver can adjust queue configuration
1223 * for the single interrupt case.
1224 */
1225 if (affd)
1226 irq_create_affinity_masks(1, affd);
1227 pci_intx(dev, 1);
1228 return 1;
1229 }
1230 }
1231
1232 return nvecs;
1233}
1234EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1235
1236/**
1237 * pci_free_irq_vectors - free previously allocated IRQs for a device
1238 * @dev: PCI device to operate on
1239 *
1240 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1241 */
1242void pci_free_irq_vectors(struct pci_dev *dev)
1243{
1244 pci_disable_msix(dev);
1245 pci_disable_msi(dev);
1246}
1247EXPORT_SYMBOL(pci_free_irq_vectors);
1248
1249/**
1250 * pci_irq_vector - return Linux IRQ number of a device vector
1251 * @dev: PCI device to operate on
1252 * @nr: device-relative interrupt vector index (0-based).
1253 */
1254int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1255{
1256 if (dev->msix_enabled) {
1257 struct msi_desc *entry;
1258 int i = 0;
1259
1260 for_each_pci_msi_entry(entry, dev) {
1261 if (i == nr)
1262 return entry->irq;
1263 i++;
1264 }
1265 WARN_ON_ONCE(1);
1266 return -EINVAL;
1267 }
1268
1269 if (dev->msi_enabled) {
1270 struct msi_desc *entry = first_pci_msi_entry(dev);
1271
1272 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1273 return -EINVAL;
1274 } else {
1275 if (WARN_ON_ONCE(nr > 0))
1276 return -EINVAL;
1277 }
1278
1279 return dev->irq + nr;
1280}
1281EXPORT_SYMBOL(pci_irq_vector);
1282
1283/**
1284 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1285 * @dev: PCI device to operate on
1286 * @nr: device-relative interrupt vector index (0-based).
1287 */
1288const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1289{
1290 if (dev->msix_enabled) {
1291 struct msi_desc *entry;
1292 int i = 0;
1293
1294 for_each_pci_msi_entry(entry, dev) {
1295 if (i == nr)
1296 return &entry->affinity->mask;
1297 i++;
1298 }
1299 WARN_ON_ONCE(1);
1300 return NULL;
1301 } else if (dev->msi_enabled) {
1302 struct msi_desc *entry = first_pci_msi_entry(dev);
1303
1304 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1305 nr >= entry->nvec_used))
1306 return NULL;
1307
1308 return &entry->affinity[nr].mask;
1309 } else {
1310 return cpu_possible_mask;
1311 }
1312}
1313EXPORT_SYMBOL(pci_irq_get_affinity);
1314
1315struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1316{
1317 return to_pci_dev(desc->dev);
1318}
1319EXPORT_SYMBOL(msi_desc_to_pci_dev);
1320
1321void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1322{
1323 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1324
1325 return dev->bus->sysdata;
1326}
1327EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1328
1329#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1330/**
1331 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1332 * @irq_data: Pointer to interrupt data of the MSI interrupt
1333 * @msg: Pointer to the message
1334 */
1335void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1336{
1337 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1338
1339 /*
1340 * For MSI-X desc->irq is always equal to irq_data->irq. For
1341 * MSI only the first interrupt of MULTI MSI passes the test.
1342 */
1343 if (desc->irq == irq_data->irq)
1344 __pci_write_msi_msg(desc, msg);
1345}
1346
1347/**
1348 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1349 * @dev: Pointer to the PCI device
1350 * @desc: Pointer to the MSI descriptor
1351 *
1352 * The ID number is only used within the irqdomain.
1353 */
1354irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1355 struct msi_desc *desc)
1356{
1357 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1358 pci_dev_id(dev) << 11 |
1359 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1360}
1361
1362static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1363{
1364 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1365}
1366
1367/**
1368 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
1369 * for @dev
1370 * @domain: The interrupt domain to check
1371 * @info: The domain info for verification
1372 * @dev: The device to check
1373 *
1374 * Returns:
1375 * 0 if the functionality is supported
1376 * 1 if Multi MSI is requested, but the domain does not support it
1377 * -ENOTSUPP otherwise
1378 */
1379int pci_msi_domain_check_cap(struct irq_domain *domain,
1380 struct msi_domain_info *info, struct device *dev)
1381{
1382 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1383
1384 /* Special handling to support __pci_enable_msi_range() */
1385 if (pci_msi_desc_is_multi_msi(desc) &&
1386 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1387 return 1;
1388 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1389 return -ENOTSUPP;
1390
1391 return 0;
1392}
1393
1394static int pci_msi_domain_handle_error(struct irq_domain *domain,
1395 struct msi_desc *desc, int error)
1396{
1397 /* Special handling to support __pci_enable_msi_range() */
1398 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1399 return 1;
1400
1401 return error;
1402}
1403
1404#ifdef GENERIC_MSI_DOMAIN_OPS
1405static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1406 struct msi_desc *desc)
1407{
1408 arg->desc = desc;
1409 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1410 desc);
1411}
1412#else
1413#define pci_msi_domain_set_desc NULL
1414#endif
1415
1416static struct msi_domain_ops pci_msi_domain_ops_default = {
1417 .set_desc = pci_msi_domain_set_desc,
1418 .msi_check = pci_msi_domain_check_cap,
1419 .handle_error = pci_msi_domain_handle_error,
1420};
1421
1422static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1423{
1424 struct msi_domain_ops *ops = info->ops;
1425
1426 if (ops == NULL) {
1427 info->ops = &pci_msi_domain_ops_default;
1428 } else {
1429 if (ops->set_desc == NULL)
1430 ops->set_desc = pci_msi_domain_set_desc;
1431 if (ops->msi_check == NULL)
1432 ops->msi_check = pci_msi_domain_check_cap;
1433 if (ops->handle_error == NULL)
1434 ops->handle_error = pci_msi_domain_handle_error;
1435 }
1436}
1437
1438static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1439{
1440 struct irq_chip *chip = info->chip;
1441
1442 BUG_ON(!chip);
1443 if (!chip->irq_write_msi_msg)
1444 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1445 if (!chip->irq_mask)
1446 chip->irq_mask = pci_msi_mask_irq;
1447 if (!chip->irq_unmask)
1448 chip->irq_unmask = pci_msi_unmask_irq;
1449}
1450
1451/**
1452 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1453 * @fwnode: Optional fwnode of the interrupt controller
1454 * @info: MSI domain info
1455 * @parent: Parent irq domain
1456 *
1457 * Updates the domain and chip ops and creates a MSI interrupt domain.
1458 *
1459 * Returns:
1460 * A domain pointer or NULL in case of failure.
1461 */
1462struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1463 struct msi_domain_info *info,
1464 struct irq_domain *parent)
1465{
1466 struct irq_domain *domain;
1467
1468 if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE))
1469 info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
1470
1471 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1472 pci_msi_domain_update_dom_ops(info);
1473 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1474 pci_msi_domain_update_chip_ops(info);
1475
1476 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1477 if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE))
1478 info->flags |= MSI_FLAG_MUST_REACTIVATE;
1479
1480 /* PCI-MSI is oneshot-safe */
1481 info->chip->flags |= IRQCHIP_ONESHOT_SAFE;
1482
1483 domain = msi_create_irq_domain(fwnode, info, parent);
1484 if (!domain)
1485 return NULL;
1486
1487 irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI);
1488 return domain;
1489}
1490EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1491
1492/*
1493 * Users of the generic MSI infrastructure expect a device to have a single ID,
1494 * so with DMA aliases we have to pick the least-worst compromise. Devices with
1495 * DMA phantom functions tend to still emit MSIs from the real function number,
1496 * so we ignore those and only consider topological aliases where either the
1497 * alias device or RID appears on a different bus number. We also make the
1498 * reasonable assumption that bridges are walked in an upstream direction (so
1499 * the last one seen wins), and the much braver assumption that the most likely
1500 * case is that of PCI->PCIe so we should always use the alias RID. This echoes
1501 * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
1502 * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
1503 * for taking ownership all we can really do is close our eyes and hope...
1504 */
1505static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1506{
1507 u32 *pa = data;
1508 u8 bus = PCI_BUS_NUM(*pa);
1509
1510 if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus)
1511 *pa = alias;
1512
1513 return 0;
1514}
1515
1516/**
1517 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1518 * @domain: The interrupt domain
1519 * @pdev: The PCI device.
1520 *
1521 * The RID for a device is formed from the alias, with a firmware
1522 * supplied mapping applied
1523 *
1524 * Returns: The RID.
1525 */
1526u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1527{
1528 struct device_node *of_node;
1529 u32 rid = pci_dev_id(pdev);
1530
1531 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1532
1533 of_node = irq_domain_get_of_node(domain);
1534 rid = of_node ? of_msi_map_id(&pdev->dev, of_node, rid) :
1535 iort_msi_map_id(&pdev->dev, rid);
1536
1537 return rid;
1538}
1539
1540/**
1541 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1542 * @pdev: The PCI device
1543 *
1544 * Use the firmware data to find a device-specific MSI domain
1545 * (i.e. not one that is set as a default).
1546 *
1547 * Returns: The corresponding MSI domain or NULL if none has been found.
1548 */
1549struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1550{
1551 struct irq_domain *dom;
1552 u32 rid = pci_dev_id(pdev);
1553
1554 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1555 dom = of_msi_map_get_device_domain(&pdev->dev, rid, DOMAIN_BUS_PCI_MSI);
1556 if (!dom)
1557 dom = iort_get_device_domain(&pdev->dev, rid,
1558 DOMAIN_BUS_PCI_MSI);
1559 return dom;
1560}
1561#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */