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1/*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 */
8
9#include <linux/err.h>
10#include <linux/mm.h>
11#include <linux/irq.h>
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/export.h>
15#include <linux/ioport.h>
16#include <linux/pci.h>
17#include <linux/proc_fs.h>
18#include <linux/msi.h>
19#include <linux/smp.h>
20#include <linux/errno.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23
24#include "pci.h"
25#include "msi.h"
26
27static int pci_msi_enable = 1;
28
29/* Arch hooks */
30
31#ifndef arch_msi_check_device
32int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
33{
34 return 0;
35}
36#endif
37
38#ifndef arch_setup_msi_irqs
39# define arch_setup_msi_irqs default_setup_msi_irqs
40# define HAVE_DEFAULT_MSI_SETUP_IRQS
41#endif
42
43#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
44int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
45{
46 struct msi_desc *entry;
47 int ret;
48
49 /*
50 * If an architecture wants to support multiple MSI, it needs to
51 * override arch_setup_msi_irqs()
52 */
53 if (type == PCI_CAP_ID_MSI && nvec > 1)
54 return 1;
55
56 list_for_each_entry(entry, &dev->msi_list, list) {
57 ret = arch_setup_msi_irq(dev, entry);
58 if (ret < 0)
59 return ret;
60 if (ret > 0)
61 return -ENOSPC;
62 }
63
64 return 0;
65}
66#endif
67
68#ifndef arch_teardown_msi_irqs
69# define arch_teardown_msi_irqs default_teardown_msi_irqs
70# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
71#endif
72
73#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
74void default_teardown_msi_irqs(struct pci_dev *dev)
75{
76 struct msi_desc *entry;
77
78 list_for_each_entry(entry, &dev->msi_list, list) {
79 int i, nvec;
80 if (entry->irq == 0)
81 continue;
82 nvec = 1 << entry->msi_attrib.multiple;
83 for (i = 0; i < nvec; i++)
84 arch_teardown_msi_irq(entry->irq + i);
85 }
86}
87#endif
88
89#ifndef arch_restore_msi_irqs
90# define arch_restore_msi_irqs default_restore_msi_irqs
91# define HAVE_DEFAULT_MSI_RESTORE_IRQS
92#endif
93
94#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
95void default_restore_msi_irqs(struct pci_dev *dev, int irq)
96{
97 struct msi_desc *entry;
98
99 entry = NULL;
100 if (dev->msix_enabled) {
101 list_for_each_entry(entry, &dev->msi_list, list) {
102 if (irq == entry->irq)
103 break;
104 }
105 } else if (dev->msi_enabled) {
106 entry = irq_get_msi_desc(irq);
107 }
108
109 if (entry)
110 write_msi_msg(irq, &entry->msg);
111}
112#endif
113
114static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
115{
116 u16 control;
117
118 BUG_ON(!pos);
119
120 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
121 control &= ~PCI_MSI_FLAGS_ENABLE;
122 if (enable)
123 control |= PCI_MSI_FLAGS_ENABLE;
124 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
125}
126
127static void msix_set_enable(struct pci_dev *dev, int enable)
128{
129 int pos;
130 u16 control;
131
132 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
133 if (pos) {
134 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
135 control &= ~PCI_MSIX_FLAGS_ENABLE;
136 if (enable)
137 control |= PCI_MSIX_FLAGS_ENABLE;
138 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
139 }
140}
141
142static inline __attribute_const__ u32 msi_mask(unsigned x)
143{
144 /* Don't shift by >= width of type */
145 if (x >= 5)
146 return 0xffffffff;
147 return (1 << (1 << x)) - 1;
148}
149
150static inline __attribute_const__ u32 msi_capable_mask(u16 control)
151{
152 return msi_mask((control >> 1) & 7);
153}
154
155static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
156{
157 return msi_mask((control >> 4) & 7);
158}
159
160/*
161 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
162 * mask all MSI interrupts by clearing the MSI enable bit does not work
163 * reliably as devices without an INTx disable bit will then generate a
164 * level IRQ which will never be cleared.
165 */
166static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
167{
168 u32 mask_bits = desc->masked;
169
170 if (!desc->msi_attrib.maskbit)
171 return 0;
172
173 mask_bits &= ~mask;
174 mask_bits |= flag;
175 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
176
177 return mask_bits;
178}
179
180static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
181{
182 desc->masked = __msi_mask_irq(desc, mask, flag);
183}
184
185/*
186 * This internal function does not flush PCI writes to the device.
187 * All users must ensure that they read from the device before either
188 * assuming that the device state is up to date, or returning out of this
189 * file. This saves a few milliseconds when initialising devices with lots
190 * of MSI-X interrupts.
191 */
192static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
193{
194 u32 mask_bits = desc->masked;
195 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
196 PCI_MSIX_ENTRY_VECTOR_CTRL;
197 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
198 if (flag)
199 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
200 writel(mask_bits, desc->mask_base + offset);
201
202 return mask_bits;
203}
204
205static void msix_mask_irq(struct msi_desc *desc, u32 flag)
206{
207 desc->masked = __msix_mask_irq(desc, flag);
208}
209
210static void msi_set_mask_bit(struct irq_data *data, u32 flag)
211{
212 struct msi_desc *desc = irq_data_get_msi(data);
213
214 if (desc->msi_attrib.is_msix) {
215 msix_mask_irq(desc, flag);
216 readl(desc->mask_base); /* Flush write to device */
217 } else {
218 unsigned offset = data->irq - desc->dev->irq;
219 msi_mask_irq(desc, 1 << offset, flag << offset);
220 }
221}
222
223void mask_msi_irq(struct irq_data *data)
224{
225 msi_set_mask_bit(data, 1);
226}
227
228void unmask_msi_irq(struct irq_data *data)
229{
230 msi_set_mask_bit(data, 0);
231}
232
233void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
234{
235 BUG_ON(entry->dev->current_state != PCI_D0);
236
237 if (entry->msi_attrib.is_msix) {
238 void __iomem *base = entry->mask_base +
239 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
240
241 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
242 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
243 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
244 } else {
245 struct pci_dev *dev = entry->dev;
246 int pos = entry->msi_attrib.pos;
247 u16 data;
248
249 pci_read_config_dword(dev, msi_lower_address_reg(pos),
250 &msg->address_lo);
251 if (entry->msi_attrib.is_64) {
252 pci_read_config_dword(dev, msi_upper_address_reg(pos),
253 &msg->address_hi);
254 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
255 } else {
256 msg->address_hi = 0;
257 pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
258 }
259 msg->data = data;
260 }
261}
262
263void read_msi_msg(unsigned int irq, struct msi_msg *msg)
264{
265 struct msi_desc *entry = irq_get_msi_desc(irq);
266
267 __read_msi_msg(entry, msg);
268}
269
270void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
271{
272 /* Assert that the cache is valid, assuming that
273 * valid messages are not all-zeroes. */
274 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
275 entry->msg.data));
276
277 *msg = entry->msg;
278}
279
280void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
281{
282 struct msi_desc *entry = irq_get_msi_desc(irq);
283
284 __get_cached_msi_msg(entry, msg);
285}
286
287void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
288{
289 if (entry->dev->current_state != PCI_D0) {
290 /* Don't touch the hardware now */
291 } else if (entry->msi_attrib.is_msix) {
292 void __iomem *base;
293 base = entry->mask_base +
294 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
295
296 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
297 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
298 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
299 } else {
300 struct pci_dev *dev = entry->dev;
301 int pos = entry->msi_attrib.pos;
302 u16 msgctl;
303
304 pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
305 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
306 msgctl |= entry->msi_attrib.multiple << 4;
307 pci_write_config_word(dev, msi_control_reg(pos), msgctl);
308
309 pci_write_config_dword(dev, msi_lower_address_reg(pos),
310 msg->address_lo);
311 if (entry->msi_attrib.is_64) {
312 pci_write_config_dword(dev, msi_upper_address_reg(pos),
313 msg->address_hi);
314 pci_write_config_word(dev, msi_data_reg(pos, 1),
315 msg->data);
316 } else {
317 pci_write_config_word(dev, msi_data_reg(pos, 0),
318 msg->data);
319 }
320 }
321 entry->msg = *msg;
322}
323
324void write_msi_msg(unsigned int irq, struct msi_msg *msg)
325{
326 struct msi_desc *entry = irq_get_msi_desc(irq);
327
328 __write_msi_msg(entry, msg);
329}
330
331static void free_msi_irqs(struct pci_dev *dev)
332{
333 struct msi_desc *entry, *tmp;
334
335 list_for_each_entry(entry, &dev->msi_list, list) {
336 int i, nvec;
337 if (!entry->irq)
338 continue;
339 nvec = 1 << entry->msi_attrib.multiple;
340 for (i = 0; i < nvec; i++)
341 BUG_ON(irq_has_action(entry->irq + i));
342 }
343
344 arch_teardown_msi_irqs(dev);
345
346 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
347 if (entry->msi_attrib.is_msix) {
348 if (list_is_last(&entry->list, &dev->msi_list))
349 iounmap(entry->mask_base);
350 }
351
352 /*
353 * Its possible that we get into this path
354 * When populate_msi_sysfs fails, which means the entries
355 * were not registered with sysfs. In that case don't
356 * unregister them.
357 */
358 if (entry->kobj.parent) {
359 kobject_del(&entry->kobj);
360 kobject_put(&entry->kobj);
361 }
362
363 list_del(&entry->list);
364 kfree(entry);
365 }
366}
367
368static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
369{
370 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
371 if (!desc)
372 return NULL;
373
374 INIT_LIST_HEAD(&desc->list);
375 desc->dev = dev;
376
377 return desc;
378}
379
380static void pci_intx_for_msi(struct pci_dev *dev, int enable)
381{
382 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
383 pci_intx(dev, enable);
384}
385
386static void __pci_restore_msi_state(struct pci_dev *dev)
387{
388 int pos;
389 u16 control;
390 struct msi_desc *entry;
391
392 if (!dev->msi_enabled)
393 return;
394
395 entry = irq_get_msi_desc(dev->irq);
396 pos = entry->msi_attrib.pos;
397
398 pci_intx_for_msi(dev, 0);
399 msi_set_enable(dev, pos, 0);
400 arch_restore_msi_irqs(dev, dev->irq);
401
402 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
403 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
404 control &= ~PCI_MSI_FLAGS_QSIZE;
405 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
406 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
407}
408
409static void __pci_restore_msix_state(struct pci_dev *dev)
410{
411 int pos;
412 struct msi_desc *entry;
413 u16 control;
414
415 if (!dev->msix_enabled)
416 return;
417 BUG_ON(list_empty(&dev->msi_list));
418 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
419 pos = entry->msi_attrib.pos;
420 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
421
422 /* route the table */
423 pci_intx_for_msi(dev, 0);
424 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
425 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
426
427 list_for_each_entry(entry, &dev->msi_list, list) {
428 arch_restore_msi_irqs(dev, entry->irq);
429 msix_mask_irq(entry, entry->masked);
430 }
431
432 control &= ~PCI_MSIX_FLAGS_MASKALL;
433 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
434}
435
436void pci_restore_msi_state(struct pci_dev *dev)
437{
438 __pci_restore_msi_state(dev);
439 __pci_restore_msix_state(dev);
440}
441EXPORT_SYMBOL_GPL(pci_restore_msi_state);
442
443
444#define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
445#define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
446
447struct msi_attribute {
448 struct attribute attr;
449 ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr,
450 char *buf);
451 ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr,
452 const char *buf, size_t count);
453};
454
455static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr,
456 char *buf)
457{
458 return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");
459}
460
461static ssize_t msi_irq_attr_show(struct kobject *kobj,
462 struct attribute *attr, char *buf)
463{
464 struct msi_attribute *attribute = to_msi_attr(attr);
465 struct msi_desc *entry = to_msi_desc(kobj);
466
467 if (!attribute->show)
468 return -EIO;
469
470 return attribute->show(entry, attribute, buf);
471}
472
473static const struct sysfs_ops msi_irq_sysfs_ops = {
474 .show = msi_irq_attr_show,
475};
476
477static struct msi_attribute mode_attribute =
478 __ATTR(mode, S_IRUGO, show_msi_mode, NULL);
479
480
481struct attribute *msi_irq_default_attrs[] = {
482 &mode_attribute.attr,
483 NULL
484};
485
486void msi_kobj_release(struct kobject *kobj)
487{
488 struct msi_desc *entry = to_msi_desc(kobj);
489
490 pci_dev_put(entry->dev);
491}
492
493static struct kobj_type msi_irq_ktype = {
494 .release = msi_kobj_release,
495 .sysfs_ops = &msi_irq_sysfs_ops,
496 .default_attrs = msi_irq_default_attrs,
497};
498
499static int populate_msi_sysfs(struct pci_dev *pdev)
500{
501 struct msi_desc *entry;
502 struct kobject *kobj;
503 int ret;
504 int count = 0;
505
506 pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);
507 if (!pdev->msi_kset)
508 return -ENOMEM;
509
510 list_for_each_entry(entry, &pdev->msi_list, list) {
511 kobj = &entry->kobj;
512 kobj->kset = pdev->msi_kset;
513 pci_dev_get(pdev);
514 ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,
515 "%u", entry->irq);
516 if (ret)
517 goto out_unroll;
518
519 count++;
520 }
521
522 return 0;
523
524out_unroll:
525 list_for_each_entry(entry, &pdev->msi_list, list) {
526 if (!count)
527 break;
528 kobject_del(&entry->kobj);
529 kobject_put(&entry->kobj);
530 count--;
531 }
532 return ret;
533}
534
535/**
536 * msi_capability_init - configure device's MSI capability structure
537 * @dev: pointer to the pci_dev data structure of MSI device function
538 * @nvec: number of interrupts to allocate
539 *
540 * Setup the MSI capability structure of the device with the requested
541 * number of interrupts. A return value of zero indicates the successful
542 * setup of an entry with the new MSI irq. A negative return value indicates
543 * an error, and a positive return value indicates the number of interrupts
544 * which could have been allocated.
545 */
546static int msi_capability_init(struct pci_dev *dev, int nvec)
547{
548 struct msi_desc *entry;
549 int pos, ret;
550 u16 control;
551 unsigned mask;
552
553 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
554 msi_set_enable(dev, pos, 0); /* Disable MSI during set up */
555
556 pci_read_config_word(dev, msi_control_reg(pos), &control);
557 /* MSI Entry Initialization */
558 entry = alloc_msi_entry(dev);
559 if (!entry)
560 return -ENOMEM;
561
562 entry->msi_attrib.is_msix = 0;
563 entry->msi_attrib.is_64 = is_64bit_address(control);
564 entry->msi_attrib.entry_nr = 0;
565 entry->msi_attrib.maskbit = is_mask_bit_support(control);
566 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
567 entry->msi_attrib.pos = pos;
568
569 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
570 /* All MSIs are unmasked by default, Mask them all */
571 if (entry->msi_attrib.maskbit)
572 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
573 mask = msi_capable_mask(control);
574 msi_mask_irq(entry, mask, mask);
575
576 list_add_tail(&entry->list, &dev->msi_list);
577
578 /* Configure MSI capability structure */
579 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
580 if (ret) {
581 msi_mask_irq(entry, mask, ~mask);
582 free_msi_irqs(dev);
583 return ret;
584 }
585
586 ret = populate_msi_sysfs(dev);
587 if (ret) {
588 msi_mask_irq(entry, mask, ~mask);
589 free_msi_irqs(dev);
590 return ret;
591 }
592
593 /* Set MSI enabled bits */
594 pci_intx_for_msi(dev, 0);
595 msi_set_enable(dev, pos, 1);
596 dev->msi_enabled = 1;
597
598 dev->irq = entry->irq;
599 return 0;
600}
601
602static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
603 unsigned nr_entries)
604{
605 resource_size_t phys_addr;
606 u32 table_offset;
607 u8 bir;
608
609 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
610 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
611 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
612 phys_addr = pci_resource_start(dev, bir) + table_offset;
613
614 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
615}
616
617static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
618 void __iomem *base, struct msix_entry *entries,
619 int nvec)
620{
621 struct msi_desc *entry;
622 int i;
623
624 for (i = 0; i < nvec; i++) {
625 entry = alloc_msi_entry(dev);
626 if (!entry) {
627 if (!i)
628 iounmap(base);
629 else
630 free_msi_irqs(dev);
631 /* No enough memory. Don't try again */
632 return -ENOMEM;
633 }
634
635 entry->msi_attrib.is_msix = 1;
636 entry->msi_attrib.is_64 = 1;
637 entry->msi_attrib.entry_nr = entries[i].entry;
638 entry->msi_attrib.default_irq = dev->irq;
639 entry->msi_attrib.pos = pos;
640 entry->mask_base = base;
641
642 list_add_tail(&entry->list, &dev->msi_list);
643 }
644
645 return 0;
646}
647
648static void msix_program_entries(struct pci_dev *dev,
649 struct msix_entry *entries)
650{
651 struct msi_desc *entry;
652 int i = 0;
653
654 list_for_each_entry(entry, &dev->msi_list, list) {
655 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
656 PCI_MSIX_ENTRY_VECTOR_CTRL;
657
658 entries[i].vector = entry->irq;
659 irq_set_msi_desc(entry->irq, entry);
660 entry->masked = readl(entry->mask_base + offset);
661 msix_mask_irq(entry, 1);
662 i++;
663 }
664}
665
666/**
667 * msix_capability_init - configure device's MSI-X capability
668 * @dev: pointer to the pci_dev data structure of MSI-X device function
669 * @entries: pointer to an array of struct msix_entry entries
670 * @nvec: number of @entries
671 *
672 * Setup the MSI-X capability structure of device function with a
673 * single MSI-X irq. A return of zero indicates the successful setup of
674 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
675 **/
676static int msix_capability_init(struct pci_dev *dev,
677 struct msix_entry *entries, int nvec)
678{
679 int pos, ret;
680 u16 control;
681 void __iomem *base;
682
683 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
684 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
685
686 /* Ensure MSI-X is disabled while it is set up */
687 control &= ~PCI_MSIX_FLAGS_ENABLE;
688 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
689
690 /* Request & Map MSI-X table region */
691 base = msix_map_region(dev, pos, multi_msix_capable(control));
692 if (!base)
693 return -ENOMEM;
694
695 ret = msix_setup_entries(dev, pos, base, entries, nvec);
696 if (ret)
697 return ret;
698
699 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
700 if (ret)
701 goto error;
702
703 /*
704 * Some devices require MSI-X to be enabled before we can touch the
705 * MSI-X registers. We need to mask all the vectors to prevent
706 * interrupts coming in before they're fully set up.
707 */
708 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
709 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
710
711 msix_program_entries(dev, entries);
712
713 ret = populate_msi_sysfs(dev);
714 if (ret) {
715 ret = 0;
716 goto error;
717 }
718
719 /* Set MSI-X enabled bits and unmask the function */
720 pci_intx_for_msi(dev, 0);
721 dev->msix_enabled = 1;
722
723 control &= ~PCI_MSIX_FLAGS_MASKALL;
724 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
725
726 return 0;
727
728error:
729 if (ret < 0) {
730 /*
731 * If we had some success, report the number of irqs
732 * we succeeded in setting up.
733 */
734 struct msi_desc *entry;
735 int avail = 0;
736
737 list_for_each_entry(entry, &dev->msi_list, list) {
738 if (entry->irq != 0)
739 avail++;
740 }
741 if (avail != 0)
742 ret = avail;
743 }
744
745 free_msi_irqs(dev);
746
747 return ret;
748}
749
750/**
751 * pci_msi_check_device - check whether MSI may be enabled on a device
752 * @dev: pointer to the pci_dev data structure of MSI device function
753 * @nvec: how many MSIs have been requested ?
754 * @type: are we checking for MSI or MSI-X ?
755 *
756 * Look at global flags, the device itself, and its parent busses
757 * to determine if MSI/-X are supported for the device. If MSI/-X is
758 * supported return 0, else return an error code.
759 **/
760static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
761{
762 struct pci_bus *bus;
763 int ret;
764
765 /* MSI must be globally enabled and supported by the device */
766 if (!pci_msi_enable || !dev || dev->no_msi)
767 return -EINVAL;
768
769 /*
770 * You can't ask to have 0 or less MSIs configured.
771 * a) it's stupid ..
772 * b) the list manipulation code assumes nvec >= 1.
773 */
774 if (nvec < 1)
775 return -ERANGE;
776
777 /*
778 * Any bridge which does NOT route MSI transactions from its
779 * secondary bus to its primary bus must set NO_MSI flag on
780 * the secondary pci_bus.
781 * We expect only arch-specific PCI host bus controller driver
782 * or quirks for specific PCI bridges to be setting NO_MSI.
783 */
784 for (bus = dev->bus; bus; bus = bus->parent)
785 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
786 return -EINVAL;
787
788 ret = arch_msi_check_device(dev, nvec, type);
789 if (ret)
790 return ret;
791
792 if (!pci_find_capability(dev, type))
793 return -EINVAL;
794
795 return 0;
796}
797
798/**
799 * pci_enable_msi_block - configure device's MSI capability structure
800 * @dev: device to configure
801 * @nvec: number of interrupts to configure
802 *
803 * Allocate IRQs for a device with the MSI capability.
804 * This function returns a negative errno if an error occurs. If it
805 * is unable to allocate the number of interrupts requested, it returns
806 * the number of interrupts it might be able to allocate. If it successfully
807 * allocates at least the number of interrupts requested, it returns 0 and
808 * updates the @dev's irq member to the lowest new interrupt number; the
809 * other interrupt numbers allocated to this device are consecutive.
810 */
811int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
812{
813 int status, pos, maxvec;
814 u16 msgctl;
815
816 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
817 if (!pos)
818 return -EINVAL;
819 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
820 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
821 if (nvec > maxvec)
822 return maxvec;
823
824 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
825 if (status)
826 return status;
827
828 WARN_ON(!!dev->msi_enabled);
829
830 /* Check whether driver already requested MSI-X irqs */
831 if (dev->msix_enabled) {
832 dev_info(&dev->dev, "can't enable MSI "
833 "(MSI-X already enabled)\n");
834 return -EINVAL;
835 }
836
837 status = msi_capability_init(dev, nvec);
838 return status;
839}
840EXPORT_SYMBOL(pci_enable_msi_block);
841
842void pci_msi_shutdown(struct pci_dev *dev)
843{
844 struct msi_desc *desc;
845 u32 mask;
846 u16 ctrl;
847 unsigned pos;
848
849 if (!pci_msi_enable || !dev || !dev->msi_enabled)
850 return;
851
852 BUG_ON(list_empty(&dev->msi_list));
853 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
854 pos = desc->msi_attrib.pos;
855
856 msi_set_enable(dev, pos, 0);
857 pci_intx_for_msi(dev, 1);
858 dev->msi_enabled = 0;
859
860 /* Return the device with MSI unmasked as initial states */
861 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
862 mask = msi_capable_mask(ctrl);
863 /* Keep cached state to be restored */
864 __msi_mask_irq(desc, mask, ~mask);
865
866 /* Restore dev->irq to its default pin-assertion irq */
867 dev->irq = desc->msi_attrib.default_irq;
868}
869
870void pci_disable_msi(struct pci_dev *dev)
871{
872 if (!pci_msi_enable || !dev || !dev->msi_enabled)
873 return;
874
875 pci_msi_shutdown(dev);
876 free_msi_irqs(dev);
877 kset_unregister(dev->msi_kset);
878 dev->msi_kset = NULL;
879}
880EXPORT_SYMBOL(pci_disable_msi);
881
882/**
883 * pci_msix_table_size - return the number of device's MSI-X table entries
884 * @dev: pointer to the pci_dev data structure of MSI-X device function
885 */
886int pci_msix_table_size(struct pci_dev *dev)
887{
888 int pos;
889 u16 control;
890
891 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
892 if (!pos)
893 return 0;
894
895 pci_read_config_word(dev, msi_control_reg(pos), &control);
896 return multi_msix_capable(control);
897}
898
899/**
900 * pci_enable_msix - configure device's MSI-X capability structure
901 * @dev: pointer to the pci_dev data structure of MSI-X device function
902 * @entries: pointer to an array of MSI-X entries
903 * @nvec: number of MSI-X irqs requested for allocation by device driver
904 *
905 * Setup the MSI-X capability structure of device function with the number
906 * of requested irqs upon its software driver call to request for
907 * MSI-X mode enabled on its hardware device function. A return of zero
908 * indicates the successful configuration of MSI-X capability structure
909 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
910 * Or a return of > 0 indicates that driver request is exceeding the number
911 * of irqs or MSI-X vectors available. Driver should use the returned value to
912 * re-send its request.
913 **/
914int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
915{
916 int status, nr_entries;
917 int i, j;
918
919 if (!entries)
920 return -EINVAL;
921
922 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
923 if (status)
924 return status;
925
926 nr_entries = pci_msix_table_size(dev);
927 if (nvec > nr_entries)
928 return nr_entries;
929
930 /* Check for any invalid entries */
931 for (i = 0; i < nvec; i++) {
932 if (entries[i].entry >= nr_entries)
933 return -EINVAL; /* invalid entry */
934 for (j = i + 1; j < nvec; j++) {
935 if (entries[i].entry == entries[j].entry)
936 return -EINVAL; /* duplicate entry */
937 }
938 }
939 WARN_ON(!!dev->msix_enabled);
940
941 /* Check whether driver already requested for MSI irq */
942 if (dev->msi_enabled) {
943 dev_info(&dev->dev, "can't enable MSI-X "
944 "(MSI IRQ already assigned)\n");
945 return -EINVAL;
946 }
947 status = msix_capability_init(dev, entries, nvec);
948 return status;
949}
950EXPORT_SYMBOL(pci_enable_msix);
951
952void pci_msix_shutdown(struct pci_dev *dev)
953{
954 struct msi_desc *entry;
955
956 if (!pci_msi_enable || !dev || !dev->msix_enabled)
957 return;
958
959 /* Return the device with MSI-X masked as initial states */
960 list_for_each_entry(entry, &dev->msi_list, list) {
961 /* Keep cached states to be restored */
962 __msix_mask_irq(entry, 1);
963 }
964
965 msix_set_enable(dev, 0);
966 pci_intx_for_msi(dev, 1);
967 dev->msix_enabled = 0;
968}
969
970void pci_disable_msix(struct pci_dev *dev)
971{
972 if (!pci_msi_enable || !dev || !dev->msix_enabled)
973 return;
974
975 pci_msix_shutdown(dev);
976 free_msi_irqs(dev);
977 kset_unregister(dev->msi_kset);
978 dev->msi_kset = NULL;
979}
980EXPORT_SYMBOL(pci_disable_msix);
981
982/**
983 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
984 * @dev: pointer to the pci_dev data structure of MSI(X) device function
985 *
986 * Being called during hotplug remove, from which the device function
987 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
988 * allocated for this device function, are reclaimed to unused state,
989 * which may be used later on.
990 **/
991void msi_remove_pci_irq_vectors(struct pci_dev *dev)
992{
993 if (!pci_msi_enable || !dev)
994 return;
995
996 if (dev->msi_enabled || dev->msix_enabled)
997 free_msi_irqs(dev);
998}
999
1000void pci_no_msi(void)
1001{
1002 pci_msi_enable = 0;
1003}
1004
1005/**
1006 * pci_msi_enabled - is MSI enabled?
1007 *
1008 * Returns true if MSI has not been disabled by the command-line option
1009 * pci=nomsi.
1010 **/
1011int pci_msi_enabled(void)
1012{
1013 return pci_msi_enable;
1014}
1015EXPORT_SYMBOL(pci_msi_enabled);
1016
1017void pci_msi_init_pci_dev(struct pci_dev *dev)
1018{
1019 int pos;
1020 INIT_LIST_HEAD(&dev->msi_list);
1021
1022 /* Disable the msi hardware to avoid screaming interrupts
1023 * during boot. This is the power on reset default so
1024 * usually this should be a noop.
1025 */
1026 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1027 if (pos)
1028 msi_set_enable(dev, pos, 0);
1029 msix_set_enable(dev, 0);
1030}
1/*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 */
8
9#include <linux/err.h>
10#include <linux/mm.h>
11#include <linux/irq.h>
12#include <linux/interrupt.h>
13#include <linux/export.h>
14#include <linux/ioport.h>
15#include <linux/pci.h>
16#include <linux/proc_fs.h>
17#include <linux/msi.h>
18#include <linux/smp.h>
19#include <linux/errno.h>
20#include <linux/io.h>
21#include <linux/slab.h>
22#include <linux/irqdomain.h>
23#include <linux/of_irq.h>
24
25#include "pci.h"
26
27static int pci_msi_enable = 1;
28int pci_msi_ignore_mask;
29
30#define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
31
32#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
33static struct irq_domain *pci_msi_default_domain;
34static DEFINE_MUTEX(pci_msi_domain_lock);
35
36struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
37{
38 return pci_msi_default_domain;
39}
40
41static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev)
42{
43 struct irq_domain *domain;
44
45 domain = dev_get_msi_domain(&dev->dev);
46 if (domain)
47 return domain;
48
49 return arch_get_pci_msi_domain(dev);
50}
51
52static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
53{
54 struct irq_domain *domain;
55
56 domain = pci_msi_get_domain(dev);
57 if (domain && irq_domain_is_hierarchy(domain))
58 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
59
60 return arch_setup_msi_irqs(dev, nvec, type);
61}
62
63static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
64{
65 struct irq_domain *domain;
66
67 domain = pci_msi_get_domain(dev);
68 if (domain && irq_domain_is_hierarchy(domain))
69 pci_msi_domain_free_irqs(domain, dev);
70 else
71 arch_teardown_msi_irqs(dev);
72}
73#else
74#define pci_msi_setup_msi_irqs arch_setup_msi_irqs
75#define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
76#endif
77
78/* Arch hooks */
79
80int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
81{
82 struct msi_controller *chip = dev->bus->msi;
83 int err;
84
85 if (!chip || !chip->setup_irq)
86 return -EINVAL;
87
88 err = chip->setup_irq(chip, dev, desc);
89 if (err < 0)
90 return err;
91
92 irq_set_chip_data(desc->irq, chip);
93
94 return 0;
95}
96
97void __weak arch_teardown_msi_irq(unsigned int irq)
98{
99 struct msi_controller *chip = irq_get_chip_data(irq);
100
101 if (!chip || !chip->teardown_irq)
102 return;
103
104 chip->teardown_irq(chip, irq);
105}
106
107int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
108{
109 struct msi_controller *chip = dev->bus->msi;
110 struct msi_desc *entry;
111 int ret;
112
113 if (chip && chip->setup_irqs)
114 return chip->setup_irqs(chip, dev, nvec, type);
115 /*
116 * If an architecture wants to support multiple MSI, it needs to
117 * override arch_setup_msi_irqs()
118 */
119 if (type == PCI_CAP_ID_MSI && nvec > 1)
120 return 1;
121
122 for_each_pci_msi_entry(entry, dev) {
123 ret = arch_setup_msi_irq(dev, entry);
124 if (ret < 0)
125 return ret;
126 if (ret > 0)
127 return -ENOSPC;
128 }
129
130 return 0;
131}
132
133/*
134 * We have a default implementation available as a separate non-weak
135 * function, as it is used by the Xen x86 PCI code
136 */
137void default_teardown_msi_irqs(struct pci_dev *dev)
138{
139 int i;
140 struct msi_desc *entry;
141
142 for_each_pci_msi_entry(entry, dev)
143 if (entry->irq)
144 for (i = 0; i < entry->nvec_used; i++)
145 arch_teardown_msi_irq(entry->irq + i);
146}
147
148void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
149{
150 return default_teardown_msi_irqs(dev);
151}
152
153static void default_restore_msi_irq(struct pci_dev *dev, int irq)
154{
155 struct msi_desc *entry;
156
157 entry = NULL;
158 if (dev->msix_enabled) {
159 for_each_pci_msi_entry(entry, dev) {
160 if (irq == entry->irq)
161 break;
162 }
163 } else if (dev->msi_enabled) {
164 entry = irq_get_msi_desc(irq);
165 }
166
167 if (entry)
168 __pci_write_msi_msg(entry, &entry->msg);
169}
170
171void __weak arch_restore_msi_irqs(struct pci_dev *dev)
172{
173 return default_restore_msi_irqs(dev);
174}
175
176static inline __attribute_const__ u32 msi_mask(unsigned x)
177{
178 /* Don't shift by >= width of type */
179 if (x >= 5)
180 return 0xffffffff;
181 return (1 << (1 << x)) - 1;
182}
183
184/*
185 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
186 * mask all MSI interrupts by clearing the MSI enable bit does not work
187 * reliably as devices without an INTx disable bit will then generate a
188 * level IRQ which will never be cleared.
189 */
190u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
191{
192 u32 mask_bits = desc->masked;
193
194 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
195 return 0;
196
197 mask_bits &= ~mask;
198 mask_bits |= flag;
199 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
200 mask_bits);
201
202 return mask_bits;
203}
204
205static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
206{
207 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
208}
209
210/*
211 * This internal function does not flush PCI writes to the device.
212 * All users must ensure that they read from the device before either
213 * assuming that the device state is up to date, or returning out of this
214 * file. This saves a few milliseconds when initialising devices with lots
215 * of MSI-X interrupts.
216 */
217u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
218{
219 u32 mask_bits = desc->masked;
220 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
221 PCI_MSIX_ENTRY_VECTOR_CTRL;
222
223 if (pci_msi_ignore_mask)
224 return 0;
225
226 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
227 if (flag)
228 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
229 writel(mask_bits, desc->mask_base + offset);
230
231 return mask_bits;
232}
233
234static void msix_mask_irq(struct msi_desc *desc, u32 flag)
235{
236 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
237}
238
239static void msi_set_mask_bit(struct irq_data *data, u32 flag)
240{
241 struct msi_desc *desc = irq_data_get_msi_desc(data);
242
243 if (desc->msi_attrib.is_msix) {
244 msix_mask_irq(desc, flag);
245 readl(desc->mask_base); /* Flush write to device */
246 } else {
247 unsigned offset = data->irq - desc->irq;
248 msi_mask_irq(desc, 1 << offset, flag << offset);
249 }
250}
251
252/**
253 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
254 * @data: pointer to irqdata associated to that interrupt
255 */
256void pci_msi_mask_irq(struct irq_data *data)
257{
258 msi_set_mask_bit(data, 1);
259}
260EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
261
262/**
263 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
264 * @data: pointer to irqdata associated to that interrupt
265 */
266void pci_msi_unmask_irq(struct irq_data *data)
267{
268 msi_set_mask_bit(data, 0);
269}
270EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
271
272void default_restore_msi_irqs(struct pci_dev *dev)
273{
274 struct msi_desc *entry;
275
276 for_each_pci_msi_entry(entry, dev)
277 default_restore_msi_irq(dev, entry->irq);
278}
279
280void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
281{
282 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
283
284 BUG_ON(dev->current_state != PCI_D0);
285
286 if (entry->msi_attrib.is_msix) {
287 void __iomem *base = entry->mask_base +
288 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
289
290 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
291 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
292 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
293 } else {
294 int pos = dev->msi_cap;
295 u16 data;
296
297 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
298 &msg->address_lo);
299 if (entry->msi_attrib.is_64) {
300 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
301 &msg->address_hi);
302 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
303 } else {
304 msg->address_hi = 0;
305 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
306 }
307 msg->data = data;
308 }
309}
310
311void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
312{
313 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
314
315 if (dev->current_state != PCI_D0) {
316 /* Don't touch the hardware now */
317 } else if (entry->msi_attrib.is_msix) {
318 void __iomem *base;
319 base = entry->mask_base +
320 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
321
322 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
323 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
324 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
325 } else {
326 int pos = dev->msi_cap;
327 u16 msgctl;
328
329 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
330 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
331 msgctl |= entry->msi_attrib.multiple << 4;
332 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
333
334 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
335 msg->address_lo);
336 if (entry->msi_attrib.is_64) {
337 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
338 msg->address_hi);
339 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
340 msg->data);
341 } else {
342 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
343 msg->data);
344 }
345 }
346 entry->msg = *msg;
347}
348
349void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
350{
351 struct msi_desc *entry = irq_get_msi_desc(irq);
352
353 __pci_write_msi_msg(entry, msg);
354}
355EXPORT_SYMBOL_GPL(pci_write_msi_msg);
356
357static void free_msi_irqs(struct pci_dev *dev)
358{
359 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
360 struct msi_desc *entry, *tmp;
361 struct attribute **msi_attrs;
362 struct device_attribute *dev_attr;
363 int i, count = 0;
364
365 for_each_pci_msi_entry(entry, dev)
366 if (entry->irq)
367 for (i = 0; i < entry->nvec_used; i++)
368 BUG_ON(irq_has_action(entry->irq + i));
369
370 pci_msi_teardown_msi_irqs(dev);
371
372 list_for_each_entry_safe(entry, tmp, msi_list, list) {
373 if (entry->msi_attrib.is_msix) {
374 if (list_is_last(&entry->list, msi_list))
375 iounmap(entry->mask_base);
376 }
377
378 list_del(&entry->list);
379 kfree(entry);
380 }
381
382 if (dev->msi_irq_groups) {
383 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
384 msi_attrs = dev->msi_irq_groups[0]->attrs;
385 while (msi_attrs[count]) {
386 dev_attr = container_of(msi_attrs[count],
387 struct device_attribute, attr);
388 kfree(dev_attr->attr.name);
389 kfree(dev_attr);
390 ++count;
391 }
392 kfree(msi_attrs);
393 kfree(dev->msi_irq_groups[0]);
394 kfree(dev->msi_irq_groups);
395 dev->msi_irq_groups = NULL;
396 }
397}
398
399static void pci_intx_for_msi(struct pci_dev *dev, int enable)
400{
401 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
402 pci_intx(dev, enable);
403}
404
405static void __pci_restore_msi_state(struct pci_dev *dev)
406{
407 u16 control;
408 struct msi_desc *entry;
409
410 if (!dev->msi_enabled)
411 return;
412
413 entry = irq_get_msi_desc(dev->irq);
414
415 pci_intx_for_msi(dev, 0);
416 pci_msi_set_enable(dev, 0);
417 arch_restore_msi_irqs(dev);
418
419 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
420 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
421 entry->masked);
422 control &= ~PCI_MSI_FLAGS_QSIZE;
423 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
424 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
425}
426
427static void __pci_restore_msix_state(struct pci_dev *dev)
428{
429 struct msi_desc *entry;
430
431 if (!dev->msix_enabled)
432 return;
433 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
434
435 /* route the table */
436 pci_intx_for_msi(dev, 0);
437 pci_msix_clear_and_set_ctrl(dev, 0,
438 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
439
440 arch_restore_msi_irqs(dev);
441 for_each_pci_msi_entry(entry, dev)
442 msix_mask_irq(entry, entry->masked);
443
444 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
445}
446
447void pci_restore_msi_state(struct pci_dev *dev)
448{
449 __pci_restore_msi_state(dev);
450 __pci_restore_msix_state(dev);
451}
452EXPORT_SYMBOL_GPL(pci_restore_msi_state);
453
454static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
455 char *buf)
456{
457 struct msi_desc *entry;
458 unsigned long irq;
459 int retval;
460
461 retval = kstrtoul(attr->attr.name, 10, &irq);
462 if (retval)
463 return retval;
464
465 entry = irq_get_msi_desc(irq);
466 if (entry)
467 return sprintf(buf, "%s\n",
468 entry->msi_attrib.is_msix ? "msix" : "msi");
469
470 return -ENODEV;
471}
472
473static int populate_msi_sysfs(struct pci_dev *pdev)
474{
475 struct attribute **msi_attrs;
476 struct attribute *msi_attr;
477 struct device_attribute *msi_dev_attr;
478 struct attribute_group *msi_irq_group;
479 const struct attribute_group **msi_irq_groups;
480 struct msi_desc *entry;
481 int ret = -ENOMEM;
482 int num_msi = 0;
483 int count = 0;
484 int i;
485
486 /* Determine how many msi entries we have */
487 for_each_pci_msi_entry(entry, pdev)
488 num_msi += entry->nvec_used;
489 if (!num_msi)
490 return 0;
491
492 /* Dynamically create the MSI attributes for the PCI device */
493 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
494 if (!msi_attrs)
495 return -ENOMEM;
496 for_each_pci_msi_entry(entry, pdev) {
497 for (i = 0; i < entry->nvec_used; i++) {
498 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
499 if (!msi_dev_attr)
500 goto error_attrs;
501 msi_attrs[count] = &msi_dev_attr->attr;
502
503 sysfs_attr_init(&msi_dev_attr->attr);
504 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
505 entry->irq + i);
506 if (!msi_dev_attr->attr.name)
507 goto error_attrs;
508 msi_dev_attr->attr.mode = S_IRUGO;
509 msi_dev_attr->show = msi_mode_show;
510 ++count;
511 }
512 }
513
514 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
515 if (!msi_irq_group)
516 goto error_attrs;
517 msi_irq_group->name = "msi_irqs";
518 msi_irq_group->attrs = msi_attrs;
519
520 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
521 if (!msi_irq_groups)
522 goto error_irq_group;
523 msi_irq_groups[0] = msi_irq_group;
524
525 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
526 if (ret)
527 goto error_irq_groups;
528 pdev->msi_irq_groups = msi_irq_groups;
529
530 return 0;
531
532error_irq_groups:
533 kfree(msi_irq_groups);
534error_irq_group:
535 kfree(msi_irq_group);
536error_attrs:
537 count = 0;
538 msi_attr = msi_attrs[count];
539 while (msi_attr) {
540 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
541 kfree(msi_attr->name);
542 kfree(msi_dev_attr);
543 ++count;
544 msi_attr = msi_attrs[count];
545 }
546 kfree(msi_attrs);
547 return ret;
548}
549
550static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
551{
552 u16 control;
553 struct msi_desc *entry;
554
555 /* MSI Entry Initialization */
556 entry = alloc_msi_entry(&dev->dev);
557 if (!entry)
558 return NULL;
559
560 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
561
562 entry->msi_attrib.is_msix = 0;
563 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
564 entry->msi_attrib.entry_nr = 0;
565 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
566 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
567 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
568 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
569 entry->nvec_used = nvec;
570
571 if (control & PCI_MSI_FLAGS_64BIT)
572 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
573 else
574 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
575
576 /* Save the initial mask status */
577 if (entry->msi_attrib.maskbit)
578 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
579
580 return entry;
581}
582
583static int msi_verify_entries(struct pci_dev *dev)
584{
585 struct msi_desc *entry;
586
587 for_each_pci_msi_entry(entry, dev) {
588 if (!dev->no_64bit_msi || !entry->msg.address_hi)
589 continue;
590 dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
591 " tried to assign one above 4G\n");
592 return -EIO;
593 }
594 return 0;
595}
596
597/**
598 * msi_capability_init - configure device's MSI capability structure
599 * @dev: pointer to the pci_dev data structure of MSI device function
600 * @nvec: number of interrupts to allocate
601 *
602 * Setup the MSI capability structure of the device with the requested
603 * number of interrupts. A return value of zero indicates the successful
604 * setup of an entry with the new MSI irq. A negative return value indicates
605 * an error, and a positive return value indicates the number of interrupts
606 * which could have been allocated.
607 */
608static int msi_capability_init(struct pci_dev *dev, int nvec)
609{
610 struct msi_desc *entry;
611 int ret;
612 unsigned mask;
613
614 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
615
616 entry = msi_setup_entry(dev, nvec);
617 if (!entry)
618 return -ENOMEM;
619
620 /* All MSIs are unmasked by default, Mask them all */
621 mask = msi_mask(entry->msi_attrib.multi_cap);
622 msi_mask_irq(entry, mask, mask);
623
624 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
625
626 /* Configure MSI capability structure */
627 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
628 if (ret) {
629 msi_mask_irq(entry, mask, ~mask);
630 free_msi_irqs(dev);
631 return ret;
632 }
633
634 ret = msi_verify_entries(dev);
635 if (ret) {
636 msi_mask_irq(entry, mask, ~mask);
637 free_msi_irqs(dev);
638 return ret;
639 }
640
641 ret = populate_msi_sysfs(dev);
642 if (ret) {
643 msi_mask_irq(entry, mask, ~mask);
644 free_msi_irqs(dev);
645 return ret;
646 }
647
648 /* Set MSI enabled bits */
649 pci_intx_for_msi(dev, 0);
650 pci_msi_set_enable(dev, 1);
651 dev->msi_enabled = 1;
652
653 pcibios_free_irq(dev);
654 dev->irq = entry->irq;
655 return 0;
656}
657
658static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
659{
660 resource_size_t phys_addr;
661 u32 table_offset;
662 unsigned long flags;
663 u8 bir;
664
665 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
666 &table_offset);
667 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
668 flags = pci_resource_flags(dev, bir);
669 if (!flags || (flags & IORESOURCE_UNSET))
670 return NULL;
671
672 table_offset &= PCI_MSIX_TABLE_OFFSET;
673 phys_addr = pci_resource_start(dev, bir) + table_offset;
674
675 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
676}
677
678static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
679 struct msix_entry *entries, int nvec)
680{
681 struct msi_desc *entry;
682 int i;
683
684 for (i = 0; i < nvec; i++) {
685 entry = alloc_msi_entry(&dev->dev);
686 if (!entry) {
687 if (!i)
688 iounmap(base);
689 else
690 free_msi_irqs(dev);
691 /* No enough memory. Don't try again */
692 return -ENOMEM;
693 }
694
695 entry->msi_attrib.is_msix = 1;
696 entry->msi_attrib.is_64 = 1;
697 entry->msi_attrib.entry_nr = entries[i].entry;
698 entry->msi_attrib.default_irq = dev->irq;
699 entry->mask_base = base;
700 entry->nvec_used = 1;
701
702 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
703 }
704
705 return 0;
706}
707
708static void msix_program_entries(struct pci_dev *dev,
709 struct msix_entry *entries)
710{
711 struct msi_desc *entry;
712 int i = 0;
713
714 for_each_pci_msi_entry(entry, dev) {
715 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
716 PCI_MSIX_ENTRY_VECTOR_CTRL;
717
718 entries[i].vector = entry->irq;
719 entry->masked = readl(entry->mask_base + offset);
720 msix_mask_irq(entry, 1);
721 i++;
722 }
723}
724
725/**
726 * msix_capability_init - configure device's MSI-X capability
727 * @dev: pointer to the pci_dev data structure of MSI-X device function
728 * @entries: pointer to an array of struct msix_entry entries
729 * @nvec: number of @entries
730 *
731 * Setup the MSI-X capability structure of device function with a
732 * single MSI-X irq. A return of zero indicates the successful setup of
733 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
734 **/
735static int msix_capability_init(struct pci_dev *dev,
736 struct msix_entry *entries, int nvec)
737{
738 int ret;
739 u16 control;
740 void __iomem *base;
741
742 /* Ensure MSI-X is disabled while it is set up */
743 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
744
745 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
746 /* Request & Map MSI-X table region */
747 base = msix_map_region(dev, msix_table_size(control));
748 if (!base)
749 return -ENOMEM;
750
751 ret = msix_setup_entries(dev, base, entries, nvec);
752 if (ret)
753 return ret;
754
755 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
756 if (ret)
757 goto out_avail;
758
759 /* Check if all MSI entries honor device restrictions */
760 ret = msi_verify_entries(dev);
761 if (ret)
762 goto out_free;
763
764 /*
765 * Some devices require MSI-X to be enabled before we can touch the
766 * MSI-X registers. We need to mask all the vectors to prevent
767 * interrupts coming in before they're fully set up.
768 */
769 pci_msix_clear_and_set_ctrl(dev, 0,
770 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
771
772 msix_program_entries(dev, entries);
773
774 ret = populate_msi_sysfs(dev);
775 if (ret)
776 goto out_free;
777
778 /* Set MSI-X enabled bits and unmask the function */
779 pci_intx_for_msi(dev, 0);
780 dev->msix_enabled = 1;
781 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
782
783 pcibios_free_irq(dev);
784 return 0;
785
786out_avail:
787 if (ret < 0) {
788 /*
789 * If we had some success, report the number of irqs
790 * we succeeded in setting up.
791 */
792 struct msi_desc *entry;
793 int avail = 0;
794
795 for_each_pci_msi_entry(entry, dev) {
796 if (entry->irq != 0)
797 avail++;
798 }
799 if (avail != 0)
800 ret = avail;
801 }
802
803out_free:
804 free_msi_irqs(dev);
805
806 return ret;
807}
808
809/**
810 * pci_msi_supported - check whether MSI may be enabled on a device
811 * @dev: pointer to the pci_dev data structure of MSI device function
812 * @nvec: how many MSIs have been requested ?
813 *
814 * Look at global flags, the device itself, and its parent buses
815 * to determine if MSI/-X are supported for the device. If MSI/-X is
816 * supported return 1, else return 0.
817 **/
818static int pci_msi_supported(struct pci_dev *dev, int nvec)
819{
820 struct pci_bus *bus;
821
822 /* MSI must be globally enabled and supported by the device */
823 if (!pci_msi_enable)
824 return 0;
825
826 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
827 return 0;
828
829 /*
830 * You can't ask to have 0 or less MSIs configured.
831 * a) it's stupid ..
832 * b) the list manipulation code assumes nvec >= 1.
833 */
834 if (nvec < 1)
835 return 0;
836
837 /*
838 * Any bridge which does NOT route MSI transactions from its
839 * secondary bus to its primary bus must set NO_MSI flag on
840 * the secondary pci_bus.
841 * We expect only arch-specific PCI host bus controller driver
842 * or quirks for specific PCI bridges to be setting NO_MSI.
843 */
844 for (bus = dev->bus; bus; bus = bus->parent)
845 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
846 return 0;
847
848 return 1;
849}
850
851/**
852 * pci_msi_vec_count - Return the number of MSI vectors a device can send
853 * @dev: device to report about
854 *
855 * This function returns the number of MSI vectors a device requested via
856 * Multiple Message Capable register. It returns a negative errno if the
857 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
858 * and returns a power of two, up to a maximum of 2^5 (32), according to the
859 * MSI specification.
860 **/
861int pci_msi_vec_count(struct pci_dev *dev)
862{
863 int ret;
864 u16 msgctl;
865
866 if (!dev->msi_cap)
867 return -EINVAL;
868
869 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
870 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
871
872 return ret;
873}
874EXPORT_SYMBOL(pci_msi_vec_count);
875
876void pci_msi_shutdown(struct pci_dev *dev)
877{
878 struct msi_desc *desc;
879 u32 mask;
880
881 if (!pci_msi_enable || !dev || !dev->msi_enabled)
882 return;
883
884 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
885 desc = first_pci_msi_entry(dev);
886
887 pci_msi_set_enable(dev, 0);
888 pci_intx_for_msi(dev, 1);
889 dev->msi_enabled = 0;
890
891 /* Return the device with MSI unmasked as initial states */
892 mask = msi_mask(desc->msi_attrib.multi_cap);
893 /* Keep cached state to be restored */
894 __pci_msi_desc_mask_irq(desc, mask, ~mask);
895
896 /* Restore dev->irq to its default pin-assertion irq */
897 dev->irq = desc->msi_attrib.default_irq;
898 pcibios_alloc_irq(dev);
899}
900
901void pci_disable_msi(struct pci_dev *dev)
902{
903 if (!pci_msi_enable || !dev || !dev->msi_enabled)
904 return;
905
906 pci_msi_shutdown(dev);
907 free_msi_irqs(dev);
908}
909EXPORT_SYMBOL(pci_disable_msi);
910
911/**
912 * pci_msix_vec_count - return the number of device's MSI-X table entries
913 * @dev: pointer to the pci_dev data structure of MSI-X device function
914 * This function returns the number of device's MSI-X table entries and
915 * therefore the number of MSI-X vectors device is capable of sending.
916 * It returns a negative errno if the device is not capable of sending MSI-X
917 * interrupts.
918 **/
919int pci_msix_vec_count(struct pci_dev *dev)
920{
921 u16 control;
922
923 if (!dev->msix_cap)
924 return -EINVAL;
925
926 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
927 return msix_table_size(control);
928}
929EXPORT_SYMBOL(pci_msix_vec_count);
930
931/**
932 * pci_enable_msix - configure device's MSI-X capability structure
933 * @dev: pointer to the pci_dev data structure of MSI-X device function
934 * @entries: pointer to an array of MSI-X entries
935 * @nvec: number of MSI-X irqs requested for allocation by device driver
936 *
937 * Setup the MSI-X capability structure of device function with the number
938 * of requested irqs upon its software driver call to request for
939 * MSI-X mode enabled on its hardware device function. A return of zero
940 * indicates the successful configuration of MSI-X capability structure
941 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
942 * Or a return of > 0 indicates that driver request is exceeding the number
943 * of irqs or MSI-X vectors available. Driver should use the returned value to
944 * re-send its request.
945 **/
946int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
947{
948 int nr_entries;
949 int i, j;
950
951 if (!pci_msi_supported(dev, nvec))
952 return -EINVAL;
953
954 if (!entries)
955 return -EINVAL;
956
957 nr_entries = pci_msix_vec_count(dev);
958 if (nr_entries < 0)
959 return nr_entries;
960 if (nvec > nr_entries)
961 return nr_entries;
962
963 /* Check for any invalid entries */
964 for (i = 0; i < nvec; i++) {
965 if (entries[i].entry >= nr_entries)
966 return -EINVAL; /* invalid entry */
967 for (j = i + 1; j < nvec; j++) {
968 if (entries[i].entry == entries[j].entry)
969 return -EINVAL; /* duplicate entry */
970 }
971 }
972 WARN_ON(!!dev->msix_enabled);
973
974 /* Check whether driver already requested for MSI irq */
975 if (dev->msi_enabled) {
976 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
977 return -EINVAL;
978 }
979 return msix_capability_init(dev, entries, nvec);
980}
981EXPORT_SYMBOL(pci_enable_msix);
982
983void pci_msix_shutdown(struct pci_dev *dev)
984{
985 struct msi_desc *entry;
986
987 if (!pci_msi_enable || !dev || !dev->msix_enabled)
988 return;
989
990 /* Return the device with MSI-X masked as initial states */
991 for_each_pci_msi_entry(entry, dev) {
992 /* Keep cached states to be restored */
993 __pci_msix_desc_mask_irq(entry, 1);
994 }
995
996 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
997 pci_intx_for_msi(dev, 1);
998 dev->msix_enabled = 0;
999 pcibios_alloc_irq(dev);
1000}
1001
1002void pci_disable_msix(struct pci_dev *dev)
1003{
1004 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1005 return;
1006
1007 pci_msix_shutdown(dev);
1008 free_msi_irqs(dev);
1009}
1010EXPORT_SYMBOL(pci_disable_msix);
1011
1012void pci_no_msi(void)
1013{
1014 pci_msi_enable = 0;
1015}
1016
1017/**
1018 * pci_msi_enabled - is MSI enabled?
1019 *
1020 * Returns true if MSI has not been disabled by the command-line option
1021 * pci=nomsi.
1022 **/
1023int pci_msi_enabled(void)
1024{
1025 return pci_msi_enable;
1026}
1027EXPORT_SYMBOL(pci_msi_enabled);
1028
1029/**
1030 * pci_enable_msi_range - configure device's MSI capability structure
1031 * @dev: device to configure
1032 * @minvec: minimal number of interrupts to configure
1033 * @maxvec: maximum number of interrupts to configure
1034 *
1035 * This function tries to allocate a maximum possible number of interrupts in a
1036 * range between @minvec and @maxvec. It returns a negative errno if an error
1037 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1038 * and updates the @dev's irq member to the lowest new interrupt number;
1039 * the other interrupt numbers allocated to this device are consecutive.
1040 **/
1041int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1042{
1043 int nvec;
1044 int rc;
1045
1046 if (!pci_msi_supported(dev, minvec))
1047 return -EINVAL;
1048
1049 WARN_ON(!!dev->msi_enabled);
1050
1051 /* Check whether driver already requested MSI-X irqs */
1052 if (dev->msix_enabled) {
1053 dev_info(&dev->dev,
1054 "can't enable MSI (MSI-X already enabled)\n");
1055 return -EINVAL;
1056 }
1057
1058 if (maxvec < minvec)
1059 return -ERANGE;
1060
1061 nvec = pci_msi_vec_count(dev);
1062 if (nvec < 0)
1063 return nvec;
1064 else if (nvec < minvec)
1065 return -EINVAL;
1066 else if (nvec > maxvec)
1067 nvec = maxvec;
1068
1069 do {
1070 rc = msi_capability_init(dev, nvec);
1071 if (rc < 0) {
1072 return rc;
1073 } else if (rc > 0) {
1074 if (rc < minvec)
1075 return -ENOSPC;
1076 nvec = rc;
1077 }
1078 } while (rc);
1079
1080 return nvec;
1081}
1082EXPORT_SYMBOL(pci_enable_msi_range);
1083
1084/**
1085 * pci_enable_msix_range - configure device's MSI-X capability structure
1086 * @dev: pointer to the pci_dev data structure of MSI-X device function
1087 * @entries: pointer to an array of MSI-X entries
1088 * @minvec: minimum number of MSI-X irqs requested
1089 * @maxvec: maximum number of MSI-X irqs requested
1090 *
1091 * Setup the MSI-X capability structure of device function with a maximum
1092 * possible number of interrupts in the range between @minvec and @maxvec
1093 * upon its software driver call to request for MSI-X mode enabled on its
1094 * hardware device function. It returns a negative errno if an error occurs.
1095 * If it succeeds, it returns the actual number of interrupts allocated and
1096 * indicates the successful configuration of MSI-X capability structure
1097 * with new allocated MSI-X interrupts.
1098 **/
1099int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1100 int minvec, int maxvec)
1101{
1102 int nvec = maxvec;
1103 int rc;
1104
1105 if (maxvec < minvec)
1106 return -ERANGE;
1107
1108 do {
1109 rc = pci_enable_msix(dev, entries, nvec);
1110 if (rc < 0) {
1111 return rc;
1112 } else if (rc > 0) {
1113 if (rc < minvec)
1114 return -ENOSPC;
1115 nvec = rc;
1116 }
1117 } while (rc);
1118
1119 return nvec;
1120}
1121EXPORT_SYMBOL(pci_enable_msix_range);
1122
1123struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1124{
1125 return to_pci_dev(desc->dev);
1126}
1127EXPORT_SYMBOL(msi_desc_to_pci_dev);
1128
1129void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1130{
1131 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1132
1133 return dev->bus->sysdata;
1134}
1135EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1136
1137#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1138/**
1139 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1140 * @irq_data: Pointer to interrupt data of the MSI interrupt
1141 * @msg: Pointer to the message
1142 */
1143void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1144{
1145 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1146
1147 /*
1148 * For MSI-X desc->irq is always equal to irq_data->irq. For
1149 * MSI only the first interrupt of MULTI MSI passes the test.
1150 */
1151 if (desc->irq == irq_data->irq)
1152 __pci_write_msi_msg(desc, msg);
1153}
1154
1155/**
1156 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1157 * @dev: Pointer to the PCI device
1158 * @desc: Pointer to the msi descriptor
1159 *
1160 * The ID number is only used within the irqdomain.
1161 */
1162irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1163 struct msi_desc *desc)
1164{
1165 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1166 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1167 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1168}
1169
1170static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1171{
1172 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1173}
1174
1175/**
1176 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1177 * @domain: The interrupt domain to check
1178 * @info: The domain info for verification
1179 * @dev: The device to check
1180 *
1181 * Returns:
1182 * 0 if the functionality is supported
1183 * 1 if Multi MSI is requested, but the domain does not support it
1184 * -ENOTSUPP otherwise
1185 */
1186int pci_msi_domain_check_cap(struct irq_domain *domain,
1187 struct msi_domain_info *info, struct device *dev)
1188{
1189 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1190
1191 /* Special handling to support pci_enable_msi_range() */
1192 if (pci_msi_desc_is_multi_msi(desc) &&
1193 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1194 return 1;
1195 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1196 return -ENOTSUPP;
1197
1198 return 0;
1199}
1200
1201static int pci_msi_domain_handle_error(struct irq_domain *domain,
1202 struct msi_desc *desc, int error)
1203{
1204 /* Special handling to support pci_enable_msi_range() */
1205 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1206 return 1;
1207
1208 return error;
1209}
1210
1211#ifdef GENERIC_MSI_DOMAIN_OPS
1212static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1213 struct msi_desc *desc)
1214{
1215 arg->desc = desc;
1216 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1217 desc);
1218}
1219#else
1220#define pci_msi_domain_set_desc NULL
1221#endif
1222
1223static struct msi_domain_ops pci_msi_domain_ops_default = {
1224 .set_desc = pci_msi_domain_set_desc,
1225 .msi_check = pci_msi_domain_check_cap,
1226 .handle_error = pci_msi_domain_handle_error,
1227};
1228
1229static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1230{
1231 struct msi_domain_ops *ops = info->ops;
1232
1233 if (ops == NULL) {
1234 info->ops = &pci_msi_domain_ops_default;
1235 } else {
1236 if (ops->set_desc == NULL)
1237 ops->set_desc = pci_msi_domain_set_desc;
1238 if (ops->msi_check == NULL)
1239 ops->msi_check = pci_msi_domain_check_cap;
1240 if (ops->handle_error == NULL)
1241 ops->handle_error = pci_msi_domain_handle_error;
1242 }
1243}
1244
1245static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1246{
1247 struct irq_chip *chip = info->chip;
1248
1249 BUG_ON(!chip);
1250 if (!chip->irq_write_msi_msg)
1251 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1252 if (!chip->irq_mask)
1253 chip->irq_mask = pci_msi_mask_irq;
1254 if (!chip->irq_unmask)
1255 chip->irq_unmask = pci_msi_unmask_irq;
1256}
1257
1258/**
1259 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1260 * @fwnode: Optional fwnode of the interrupt controller
1261 * @info: MSI domain info
1262 * @parent: Parent irq domain
1263 *
1264 * Updates the domain and chip ops and creates a MSI interrupt domain.
1265 *
1266 * Returns:
1267 * A domain pointer or NULL in case of failure.
1268 */
1269struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1270 struct msi_domain_info *info,
1271 struct irq_domain *parent)
1272{
1273 struct irq_domain *domain;
1274
1275 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1276 pci_msi_domain_update_dom_ops(info);
1277 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1278 pci_msi_domain_update_chip_ops(info);
1279
1280 domain = msi_create_irq_domain(fwnode, info, parent);
1281 if (!domain)
1282 return NULL;
1283
1284 domain->bus_token = DOMAIN_BUS_PCI_MSI;
1285 return domain;
1286}
1287EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1288
1289/**
1290 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1291 * @domain: The interrupt domain to allocate from
1292 * @dev: The device for which to allocate
1293 * @nvec: The number of interrupts to allocate
1294 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1295 *
1296 * Returns:
1297 * A virtual interrupt number or an error code in case of failure
1298 */
1299int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
1300 int nvec, int type)
1301{
1302 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
1303}
1304
1305/**
1306 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1307 * @domain: The interrupt domain
1308 * @dev: The device for which to free interrupts
1309 */
1310void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
1311{
1312 msi_domain_free_irqs(domain, &dev->dev);
1313}
1314
1315/**
1316 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1317 * @fwnode: Optional fwnode of the interrupt controller
1318 * @info: MSI domain info
1319 * @parent: Parent irq domain
1320 *
1321 * Returns: A domain pointer or NULL in case of failure. If successful
1322 * the default PCI/MSI irqdomain pointer is updated.
1323 */
1324struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode,
1325 struct msi_domain_info *info, struct irq_domain *parent)
1326{
1327 struct irq_domain *domain;
1328
1329 mutex_lock(&pci_msi_domain_lock);
1330 if (pci_msi_default_domain) {
1331 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1332 domain = NULL;
1333 } else {
1334 domain = pci_msi_create_irq_domain(fwnode, info, parent);
1335 pci_msi_default_domain = domain;
1336 }
1337 mutex_unlock(&pci_msi_domain_lock);
1338
1339 return domain;
1340}
1341
1342static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1343{
1344 u32 *pa = data;
1345
1346 *pa = alias;
1347 return 0;
1348}
1349/**
1350 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1351 * @domain: The interrupt domain
1352 * @pdev: The PCI device.
1353 *
1354 * The RID for a device is formed from the alias, with a firmware
1355 * supplied mapping applied
1356 *
1357 * Returns: The RID.
1358 */
1359u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1360{
1361 struct device_node *of_node;
1362 u32 rid = 0;
1363
1364 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1365
1366 of_node = irq_domain_get_of_node(domain);
1367 if (of_node)
1368 rid = of_msi_map_rid(&pdev->dev, of_node, rid);
1369
1370 return rid;
1371}
1372
1373/**
1374 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1375 * @pdev: The PCI device
1376 *
1377 * Use the firmware data to find a device-specific MSI domain
1378 * (i.e. not one that is ste as a default).
1379 *
1380 * Returns: The coresponding MSI domain or NULL if none has been found.
1381 */
1382struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1383{
1384 u32 rid = 0;
1385
1386 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1387 return of_msi_map_get_device_domain(&pdev->dev, rid);
1388}
1389#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */