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1/*
2 * check TSC synchronization.
3 *
4 * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar
5 *
6 * We check whether all boot CPUs have their TSC's synchronized,
7 * print a warning if not and turn off the TSC clock-source.
8 *
9 * The warp-check is point-to-point between two CPUs, the CPU
10 * initiating the bootup is the 'source CPU', the freshly booting
11 * CPU is the 'target CPU'.
12 *
13 * Only two CPUs may participate - they can enter in any order.
14 * ( The serial nature of the boot logic and the CPU hotplug lock
15 * protects against more than 2 CPUs entering this code. )
16 */
17#include <linux/spinlock.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/smp.h>
21#include <linux/nmi.h>
22#include <asm/tsc.h>
23
24/*
25 * Entry/exit counters that make sure that both CPUs
26 * run the measurement code at once:
27 */
28static __cpuinitdata atomic_t start_count;
29static __cpuinitdata atomic_t stop_count;
30
31/*
32 * We use a raw spinlock in this exceptional case, because
33 * we want to have the fastest, inlined, non-debug version
34 * of a critical section, to be able to prove TSC time-warps:
35 */
36static __cpuinitdata arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED;
37
38static __cpuinitdata cycles_t last_tsc;
39static __cpuinitdata cycles_t max_warp;
40static __cpuinitdata int nr_warps;
41
42/*
43 * TSC-warp measurement loop running on both CPUs:
44 */
45static __cpuinit void check_tsc_warp(unsigned int timeout)
46{
47 cycles_t start, now, prev, end;
48 int i;
49
50 rdtsc_barrier();
51 start = get_cycles();
52 rdtsc_barrier();
53 /*
54 * The measurement runs for 'timeout' msecs:
55 */
56 end = start + (cycles_t) tsc_khz * timeout;
57 now = start;
58
59 for (i = 0; ; i++) {
60 /*
61 * We take the global lock, measure TSC, save the
62 * previous TSC that was measured (possibly on
63 * another CPU) and update the previous TSC timestamp.
64 */
65 arch_spin_lock(&sync_lock);
66 prev = last_tsc;
67 rdtsc_barrier();
68 now = get_cycles();
69 rdtsc_barrier();
70 last_tsc = now;
71 arch_spin_unlock(&sync_lock);
72
73 /*
74 * Be nice every now and then (and also check whether
75 * measurement is done [we also insert a 10 million
76 * loops safety exit, so we dont lock up in case the
77 * TSC readout is totally broken]):
78 */
79 if (unlikely(!(i & 7))) {
80 if (now > end || i > 10000000)
81 break;
82 cpu_relax();
83 touch_nmi_watchdog();
84 }
85 /*
86 * Outside the critical section we can now see whether
87 * we saw a time-warp of the TSC going backwards:
88 */
89 if (unlikely(prev > now)) {
90 arch_spin_lock(&sync_lock);
91 max_warp = max(max_warp, prev - now);
92 nr_warps++;
93 arch_spin_unlock(&sync_lock);
94 }
95 }
96 WARN(!(now-start),
97 "Warning: zero tsc calibration delta: %Ld [max: %Ld]\n",
98 now-start, end-start);
99}
100
101/*
102 * If the target CPU coming online doesn't have any of its core-siblings
103 * online, a timeout of 20msec will be used for the TSC-warp measurement
104 * loop. Otherwise a smaller timeout of 2msec will be used, as we have some
105 * information about this socket already (and this information grows as we
106 * have more and more logical-siblings in that socket).
107 *
108 * Ideally we should be able to skip the TSC sync check on the other
109 * core-siblings, if the first logical CPU in a socket passed the sync test.
110 * But as the TSC is per-logical CPU and can potentially be modified wrongly
111 * by the bios, TSC sync test for smaller duration should be able
112 * to catch such errors. Also this will catch the condition where all the
113 * cores in the socket doesn't get reset at the same time.
114 */
115static inline unsigned int loop_timeout(int cpu)
116{
117 return (cpumask_weight(cpu_core_mask(cpu)) > 1) ? 2 : 20;
118}
119
120/*
121 * Source CPU calls into this - it waits for the freshly booted
122 * target CPU to arrive and then starts the measurement:
123 */
124void __cpuinit check_tsc_sync_source(int cpu)
125{
126 int cpus = 2;
127
128 /*
129 * No need to check if we already know that the TSC is not
130 * synchronized:
131 */
132 if (unsynchronized_tsc())
133 return;
134
135 if (tsc_clocksource_reliable) {
136 if (cpu == (nr_cpu_ids-1) || system_state != SYSTEM_BOOTING)
137 pr_info(
138 "Skipped synchronization checks as TSC is reliable.\n");
139 return;
140 }
141
142 /*
143 * Reset it - in case this is a second bootup:
144 */
145 atomic_set(&stop_count, 0);
146
147 /*
148 * Wait for the target to arrive:
149 */
150 while (atomic_read(&start_count) != cpus-1)
151 cpu_relax();
152 /*
153 * Trigger the target to continue into the measurement too:
154 */
155 atomic_inc(&start_count);
156
157 check_tsc_warp(loop_timeout(cpu));
158
159 while (atomic_read(&stop_count) != cpus-1)
160 cpu_relax();
161
162 if (nr_warps) {
163 pr_warning("TSC synchronization [CPU#%d -> CPU#%d]:\n",
164 smp_processor_id(), cpu);
165 pr_warning("Measured %Ld cycles TSC warp between CPUs, "
166 "turning off TSC clock.\n", max_warp);
167 mark_tsc_unstable("check_tsc_sync_source failed");
168 } else {
169 pr_debug("TSC synchronization [CPU#%d -> CPU#%d]: passed\n",
170 smp_processor_id(), cpu);
171 }
172
173 /*
174 * Reset it - just in case we boot another CPU later:
175 */
176 atomic_set(&start_count, 0);
177 nr_warps = 0;
178 max_warp = 0;
179 last_tsc = 0;
180
181 /*
182 * Let the target continue with the bootup:
183 */
184 atomic_inc(&stop_count);
185}
186
187/*
188 * Freshly booted CPUs call into this:
189 */
190void __cpuinit check_tsc_sync_target(void)
191{
192 int cpus = 2;
193
194 if (unsynchronized_tsc() || tsc_clocksource_reliable)
195 return;
196
197 /*
198 * Register this CPU's participation and wait for the
199 * source CPU to start the measurement:
200 */
201 atomic_inc(&start_count);
202 while (atomic_read(&start_count) != cpus)
203 cpu_relax();
204
205 check_tsc_warp(loop_timeout(smp_processor_id()));
206
207 /*
208 * Ok, we are done:
209 */
210 atomic_inc(&stop_count);
211
212 /*
213 * Wait for the source CPU to print stuff:
214 */
215 while (atomic_read(&stop_count) != cpus)
216 cpu_relax();
217}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * check TSC synchronization.
4 *
5 * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar
6 *
7 * We check whether all boot CPUs have their TSC's synchronized,
8 * print a warning if not and turn off the TSC clock-source.
9 *
10 * The warp-check is point-to-point between two CPUs, the CPU
11 * initiating the bootup is the 'source CPU', the freshly booting
12 * CPU is the 'target CPU'.
13 *
14 * Only two CPUs may participate - they can enter in any order.
15 * ( The serial nature of the boot logic and the CPU hotplug lock
16 * protects against more than 2 CPUs entering this code. )
17 */
18#include <linux/topology.h>
19#include <linux/spinlock.h>
20#include <linux/kernel.h>
21#include <linux/smp.h>
22#include <linux/nmi.h>
23#include <asm/tsc.h>
24
25struct tsc_adjust {
26 s64 bootval;
27 s64 adjusted;
28 unsigned long nextcheck;
29 bool warned;
30};
31
32static DEFINE_PER_CPU(struct tsc_adjust, tsc_adjust);
33
34/*
35 * TSC's on different sockets may be reset asynchronously.
36 * This may cause the TSC ADJUST value on socket 0 to be NOT 0.
37 */
38bool __read_mostly tsc_async_resets;
39
40void mark_tsc_async_resets(char *reason)
41{
42 if (tsc_async_resets)
43 return;
44 tsc_async_resets = true;
45 pr_info("tsc: Marking TSC async resets true due to %s\n", reason);
46}
47
48void tsc_verify_tsc_adjust(bool resume)
49{
50 struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust);
51 s64 curval;
52
53 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
54 return;
55
56 /* Skip unnecessary error messages if TSC already unstable */
57 if (check_tsc_unstable())
58 return;
59
60 /* Rate limit the MSR check */
61 if (!resume && time_before(jiffies, adj->nextcheck))
62 return;
63
64 adj->nextcheck = jiffies + HZ;
65
66 rdmsrl(MSR_IA32_TSC_ADJUST, curval);
67 if (adj->adjusted == curval)
68 return;
69
70 /* Restore the original value */
71 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted);
72
73 if (!adj->warned || resume) {
74 pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",
75 smp_processor_id(), adj->adjusted, curval);
76 adj->warned = true;
77 }
78}
79
80static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval,
81 unsigned int cpu, bool bootcpu)
82{
83 /*
84 * First online CPU in a package stores the boot value in the
85 * adjustment value. This value might change later via the sync
86 * mechanism. If that fails we still can yell about boot values not
87 * being consistent.
88 *
89 * On the boot cpu we just force set the ADJUST value to 0 if it's
90 * non zero. We don't do that on non boot cpus because physical
91 * hotplug should have set the ADJUST register to a value > 0 so
92 * the TSC is in sync with the already running cpus.
93 *
94 * Also don't force the ADJUST value to zero if that is a valid value
95 * for socket 0 as determined by the system arch. This is required
96 * when multiple sockets are reset asynchronously with each other
97 * and socket 0 may not have an TSC ADJUST value of 0.
98 */
99 if (bootcpu && bootval != 0) {
100 if (likely(!tsc_async_resets)) {
101 pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n",
102 cpu, bootval);
103 wrmsrl(MSR_IA32_TSC_ADJUST, 0);
104 bootval = 0;
105 } else {
106 pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n",
107 cpu, bootval);
108 }
109 }
110 cur->adjusted = bootval;
111}
112
113#ifndef CONFIG_SMP
114bool __init tsc_store_and_check_tsc_adjust(bool bootcpu)
115{
116 struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
117 s64 bootval;
118
119 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
120 return false;
121
122 /* Skip unnecessary error messages if TSC already unstable */
123 if (check_tsc_unstable())
124 return false;
125
126 rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
127 cur->bootval = bootval;
128 cur->nextcheck = jiffies + HZ;
129 tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu);
130 return false;
131}
132
133#else /* !CONFIG_SMP */
134
135/*
136 * Store and check the TSC ADJUST MSR if available
137 */
138bool tsc_store_and_check_tsc_adjust(bool bootcpu)
139{
140 struct tsc_adjust *ref, *cur = this_cpu_ptr(&tsc_adjust);
141 unsigned int refcpu, cpu = smp_processor_id();
142 struct cpumask *mask;
143 s64 bootval;
144
145 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
146 return false;
147
148 rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
149 cur->bootval = bootval;
150 cur->nextcheck = jiffies + HZ;
151 cur->warned = false;
152
153 /*
154 * If a non-zero TSC value for socket 0 may be valid then the default
155 * adjusted value cannot assumed to be zero either.
156 */
157 if (tsc_async_resets)
158 cur->adjusted = bootval;
159
160 /*
161 * Check whether this CPU is the first in a package to come up. In
162 * this case do not check the boot value against another package
163 * because the new package might have been physically hotplugged,
164 * where TSC_ADJUST is expected to be different. When called on the
165 * boot CPU topology_core_cpumask() might not be available yet.
166 */
167 mask = topology_core_cpumask(cpu);
168 refcpu = mask ? cpumask_any_but(mask, cpu) : nr_cpu_ids;
169
170 if (refcpu >= nr_cpu_ids) {
171 tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(),
172 bootcpu);
173 return false;
174 }
175
176 ref = per_cpu_ptr(&tsc_adjust, refcpu);
177 /*
178 * Compare the boot value and complain if it differs in the
179 * package.
180 */
181 if (bootval != ref->bootval)
182 printk_once(FW_BUG "TSC ADJUST differs within socket(s), fixing all errors\n");
183
184 /*
185 * The TSC_ADJUST values in a package must be the same. If the boot
186 * value on this newly upcoming CPU differs from the adjustment
187 * value of the already online CPU in this package, set it to that
188 * adjusted value.
189 */
190 if (bootval != ref->adjusted) {
191 cur->adjusted = ref->adjusted;
192 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted);
193 }
194 /*
195 * We have the TSCs forced to be in sync on this package. Skip sync
196 * test:
197 */
198 return true;
199}
200
201/*
202 * Entry/exit counters that make sure that both CPUs
203 * run the measurement code at once:
204 */
205static atomic_t start_count;
206static atomic_t stop_count;
207static atomic_t skip_test;
208static atomic_t test_runs;
209
210/*
211 * We use a raw spinlock in this exceptional case, because
212 * we want to have the fastest, inlined, non-debug version
213 * of a critical section, to be able to prove TSC time-warps:
214 */
215static arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED;
216
217static cycles_t last_tsc;
218static cycles_t max_warp;
219static int nr_warps;
220static int random_warps;
221
222/*
223 * TSC-warp measurement loop running on both CPUs. This is not called
224 * if there is no TSC.
225 */
226static cycles_t check_tsc_warp(unsigned int timeout)
227{
228 cycles_t start, now, prev, end, cur_max_warp = 0;
229 int i, cur_warps = 0;
230
231 start = rdtsc_ordered();
232 /*
233 * The measurement runs for 'timeout' msecs:
234 */
235 end = start + (cycles_t) tsc_khz * timeout;
236
237 for (i = 0; ; i++) {
238 /*
239 * We take the global lock, measure TSC, save the
240 * previous TSC that was measured (possibly on
241 * another CPU) and update the previous TSC timestamp.
242 */
243 arch_spin_lock(&sync_lock);
244 prev = last_tsc;
245 now = rdtsc_ordered();
246 last_tsc = now;
247 arch_spin_unlock(&sync_lock);
248
249 /*
250 * Be nice every now and then (and also check whether
251 * measurement is done [we also insert a 10 million
252 * loops safety exit, so we dont lock up in case the
253 * TSC readout is totally broken]):
254 */
255 if (unlikely(!(i & 7))) {
256 if (now > end || i > 10000000)
257 break;
258 cpu_relax();
259 touch_nmi_watchdog();
260 }
261 /*
262 * Outside the critical section we can now see whether
263 * we saw a time-warp of the TSC going backwards:
264 */
265 if (unlikely(prev > now)) {
266 arch_spin_lock(&sync_lock);
267 max_warp = max(max_warp, prev - now);
268 cur_max_warp = max_warp;
269 /*
270 * Check whether this bounces back and forth. Only
271 * one CPU should observe time going backwards.
272 */
273 if (cur_warps != nr_warps)
274 random_warps++;
275 nr_warps++;
276 cur_warps = nr_warps;
277 arch_spin_unlock(&sync_lock);
278 }
279 }
280 WARN(!(now-start),
281 "Warning: zero tsc calibration delta: %Ld [max: %Ld]\n",
282 now-start, end-start);
283 return cur_max_warp;
284}
285
286/*
287 * If the target CPU coming online doesn't have any of its core-siblings
288 * online, a timeout of 20msec will be used for the TSC-warp measurement
289 * loop. Otherwise a smaller timeout of 2msec will be used, as we have some
290 * information about this socket already (and this information grows as we
291 * have more and more logical-siblings in that socket).
292 *
293 * Ideally we should be able to skip the TSC sync check on the other
294 * core-siblings, if the first logical CPU in a socket passed the sync test.
295 * But as the TSC is per-logical CPU and can potentially be modified wrongly
296 * by the bios, TSC sync test for smaller duration should be able
297 * to catch such errors. Also this will catch the condition where all the
298 * cores in the socket don't get reset at the same time.
299 */
300static inline unsigned int loop_timeout(int cpu)
301{
302 return (cpumask_weight(topology_core_cpumask(cpu)) > 1) ? 2 : 20;
303}
304
305/*
306 * Source CPU calls into this - it waits for the freshly booted
307 * target CPU to arrive and then starts the measurement:
308 */
309void check_tsc_sync_source(int cpu)
310{
311 int cpus = 2;
312
313 /*
314 * No need to check if we already know that the TSC is not
315 * synchronized or if we have no TSC.
316 */
317 if (unsynchronized_tsc())
318 return;
319
320 /*
321 * Set the maximum number of test runs to
322 * 1 if the CPU does not provide the TSC_ADJUST MSR
323 * 3 if the MSR is available, so the target can try to adjust
324 */
325 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
326 atomic_set(&test_runs, 1);
327 else
328 atomic_set(&test_runs, 3);
329retry:
330 /*
331 * Wait for the target to start or to skip the test:
332 */
333 while (atomic_read(&start_count) != cpus - 1) {
334 if (atomic_read(&skip_test) > 0) {
335 atomic_set(&skip_test, 0);
336 return;
337 }
338 cpu_relax();
339 }
340
341 /*
342 * Trigger the target to continue into the measurement too:
343 */
344 atomic_inc(&start_count);
345
346 check_tsc_warp(loop_timeout(cpu));
347
348 while (atomic_read(&stop_count) != cpus-1)
349 cpu_relax();
350
351 /*
352 * If the test was successful set the number of runs to zero and
353 * stop. If not, decrement the number of runs an check if we can
354 * retry. In case of random warps no retry is attempted.
355 */
356 if (!nr_warps) {
357 atomic_set(&test_runs, 0);
358
359 pr_debug("TSC synchronization [CPU#%d -> CPU#%d]: passed\n",
360 smp_processor_id(), cpu);
361
362 } else if (atomic_dec_and_test(&test_runs) || random_warps) {
363 /* Force it to 0 if random warps brought us here */
364 atomic_set(&test_runs, 0);
365
366 pr_warn("TSC synchronization [CPU#%d -> CPU#%d]:\n",
367 smp_processor_id(), cpu);
368 pr_warn("Measured %Ld cycles TSC warp between CPUs, "
369 "turning off TSC clock.\n", max_warp);
370 if (random_warps)
371 pr_warn("TSC warped randomly between CPUs\n");
372 mark_tsc_unstable("check_tsc_sync_source failed");
373 }
374
375 /*
376 * Reset it - just in case we boot another CPU later:
377 */
378 atomic_set(&start_count, 0);
379 random_warps = 0;
380 nr_warps = 0;
381 max_warp = 0;
382 last_tsc = 0;
383
384 /*
385 * Let the target continue with the bootup:
386 */
387 atomic_inc(&stop_count);
388
389 /*
390 * Retry, if there is a chance to do so.
391 */
392 if (atomic_read(&test_runs) > 0)
393 goto retry;
394}
395
396/*
397 * Freshly booted CPUs call into this:
398 */
399void check_tsc_sync_target(void)
400{
401 struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
402 unsigned int cpu = smp_processor_id();
403 cycles_t cur_max_warp, gbl_max_warp;
404 int cpus = 2;
405
406 /* Also aborts if there is no TSC. */
407 if (unsynchronized_tsc())
408 return;
409
410 /*
411 * Store, verify and sanitize the TSC adjust register. If
412 * successful skip the test.
413 *
414 * The test is also skipped when the TSC is marked reliable. This
415 * is true for SoCs which have no fallback clocksource. On these
416 * SoCs the TSC is frequency synchronized, but still the TSC ADJUST
417 * register might have been wreckaged by the BIOS..
418 */
419 if (tsc_store_and_check_tsc_adjust(false) || tsc_clocksource_reliable) {
420 atomic_inc(&skip_test);
421 return;
422 }
423
424retry:
425 /*
426 * Register this CPU's participation and wait for the
427 * source CPU to start the measurement:
428 */
429 atomic_inc(&start_count);
430 while (atomic_read(&start_count) != cpus)
431 cpu_relax();
432
433 cur_max_warp = check_tsc_warp(loop_timeout(cpu));
434
435 /*
436 * Store the maximum observed warp value for a potential retry:
437 */
438 gbl_max_warp = max_warp;
439
440 /*
441 * Ok, we are done:
442 */
443 atomic_inc(&stop_count);
444
445 /*
446 * Wait for the source CPU to print stuff:
447 */
448 while (atomic_read(&stop_count) != cpus)
449 cpu_relax();
450
451 /*
452 * Reset it for the next sync test:
453 */
454 atomic_set(&stop_count, 0);
455
456 /*
457 * Check the number of remaining test runs. If not zero, the test
458 * failed and a retry with adjusted TSC is possible. If zero the
459 * test was either successful or failed terminally.
460 */
461 if (!atomic_read(&test_runs))
462 return;
463
464 /*
465 * If the warp value of this CPU is 0, then the other CPU
466 * observed time going backwards so this TSC was ahead and
467 * needs to move backwards.
468 */
469 if (!cur_max_warp)
470 cur_max_warp = -gbl_max_warp;
471
472 /*
473 * Add the result to the previous adjustment value.
474 *
475 * The adjustement value is slightly off by the overhead of the
476 * sync mechanism (observed values are ~200 TSC cycles), but this
477 * really depends on CPU, node distance and frequency. So
478 * compensating for this is hard to get right. Experiments show
479 * that the warp is not longer detectable when the observed warp
480 * value is used. In the worst case the adjustment needs to go
481 * through a 3rd run for fine tuning.
482 */
483 cur->adjusted += cur_max_warp;
484
485 pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n",
486 cpu, cur_max_warp, cur->adjusted);
487
488 wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted);
489 goto retry;
490
491}
492
493#endif /* CONFIG_SMP */