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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Interrupt descriptor table related code
4 */
5#include <linux/interrupt.h>
6
7#include <asm/cpu_entry_area.h>
8#include <asm/set_memory.h>
9#include <asm/traps.h>
10#include <asm/proto.h>
11#include <asm/desc.h>
12#include <asm/hw_irq.h>
13
14struct idt_data {
15 unsigned int vector;
16 unsigned int segment;
17 struct idt_bits bits;
18 const void *addr;
19};
20
21#define DPL0 0x0
22#define DPL3 0x3
23
24#define DEFAULT_STACK 0
25
26#define G(_vector, _addr, _ist, _type, _dpl, _segment) \
27 { \
28 .vector = _vector, \
29 .bits.ist = _ist, \
30 .bits.type = _type, \
31 .bits.dpl = _dpl, \
32 .bits.p = 1, \
33 .addr = _addr, \
34 .segment = _segment, \
35 }
36
37/* Interrupt gate */
38#define INTG(_vector, _addr) \
39 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
40
41/* System interrupt gate */
42#define SYSG(_vector, _addr) \
43 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
44
45/*
46 * Interrupt gate with interrupt stack. The _ist index is the index in
47 * the tss.ist[] array, but for the descriptor it needs to start at 1.
48 */
49#define ISTG(_vector, _addr, _ist) \
50 G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS)
51
52/* Task gate */
53#define TSKG(_vector, _gdt) \
54 G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
55
56#define IDT_TABLE_SIZE (IDT_ENTRIES * sizeof(gate_desc))
57
58static bool idt_setup_done __initdata;
59
60/*
61 * Early traps running on the DEFAULT_STACK because the other interrupt
62 * stacks work only after cpu_init().
63 */
64static const __initconst struct idt_data early_idts[] = {
65 INTG(X86_TRAP_DB, asm_exc_debug),
66 SYSG(X86_TRAP_BP, asm_exc_int3),
67
68#ifdef CONFIG_X86_32
69 /*
70 * Not possible on 64-bit. See idt_setup_early_pf() for details.
71 */
72 INTG(X86_TRAP_PF, asm_exc_page_fault),
73#endif
74};
75
76/*
77 * The default IDT entries which are set up in trap_init() before
78 * cpu_init() is invoked. Interrupt stacks cannot be used at that point and
79 * the traps which use them are reinitialized with IST after cpu_init() has
80 * set up TSS.
81 */
82static const __initconst struct idt_data def_idts[] = {
83 INTG(X86_TRAP_DE, asm_exc_divide_error),
84 INTG(X86_TRAP_NMI, asm_exc_nmi),
85 INTG(X86_TRAP_BR, asm_exc_bounds),
86 INTG(X86_TRAP_UD, asm_exc_invalid_op),
87 INTG(X86_TRAP_NM, asm_exc_device_not_available),
88 INTG(X86_TRAP_OLD_MF, asm_exc_coproc_segment_overrun),
89 INTG(X86_TRAP_TS, asm_exc_invalid_tss),
90 INTG(X86_TRAP_NP, asm_exc_segment_not_present),
91 INTG(X86_TRAP_SS, asm_exc_stack_segment),
92 INTG(X86_TRAP_GP, asm_exc_general_protection),
93 INTG(X86_TRAP_SPURIOUS, asm_exc_spurious_interrupt_bug),
94 INTG(X86_TRAP_MF, asm_exc_coprocessor_error),
95 INTG(X86_TRAP_AC, asm_exc_alignment_check),
96 INTG(X86_TRAP_XF, asm_exc_simd_coprocessor_error),
97
98#ifdef CONFIG_X86_32
99 TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS),
100#else
101 INTG(X86_TRAP_DF, asm_exc_double_fault),
102#endif
103 INTG(X86_TRAP_DB, asm_exc_debug),
104
105#ifdef CONFIG_X86_MCE
106 INTG(X86_TRAP_MC, asm_exc_machine_check),
107#endif
108
109 SYSG(X86_TRAP_OF, asm_exc_overflow),
110#if defined(CONFIG_IA32_EMULATION)
111 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat),
112#elif defined(CONFIG_X86_32)
113 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32),
114#endif
115};
116
117/*
118 * The APIC and SMP idt entries
119 */
120static const __initconst struct idt_data apic_idts[] = {
121#ifdef CONFIG_SMP
122 INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi),
123 INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function),
124 INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single),
125 INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup),
126 INTG(REBOOT_VECTOR, asm_sysvec_reboot),
127#endif
128
129#ifdef CONFIG_X86_THERMAL_VECTOR
130 INTG(THERMAL_APIC_VECTOR, asm_sysvec_thermal),
131#endif
132
133#ifdef CONFIG_X86_MCE_THRESHOLD
134 INTG(THRESHOLD_APIC_VECTOR, asm_sysvec_threshold),
135#endif
136
137#ifdef CONFIG_X86_MCE_AMD
138 INTG(DEFERRED_ERROR_VECTOR, asm_sysvec_deferred_error),
139#endif
140
141#ifdef CONFIG_X86_LOCAL_APIC
142 INTG(LOCAL_TIMER_VECTOR, asm_sysvec_apic_timer_interrupt),
143 INTG(X86_PLATFORM_IPI_VECTOR, asm_sysvec_x86_platform_ipi),
144# ifdef CONFIG_HAVE_KVM
145 INTG(POSTED_INTR_VECTOR, asm_sysvec_kvm_posted_intr_ipi),
146 INTG(POSTED_INTR_WAKEUP_VECTOR, asm_sysvec_kvm_posted_intr_wakeup_ipi),
147 INTG(POSTED_INTR_NESTED_VECTOR, asm_sysvec_kvm_posted_intr_nested_ipi),
148# endif
149# ifdef CONFIG_IRQ_WORK
150 INTG(IRQ_WORK_VECTOR, asm_sysvec_irq_work),
151# endif
152# ifdef CONFIG_X86_UV
153 INTG(UV_BAU_MESSAGE, asm_sysvec_uv_bau_message),
154# endif
155 INTG(SPURIOUS_APIC_VECTOR, asm_sysvec_spurious_apic_interrupt),
156 INTG(ERROR_APIC_VECTOR, asm_sysvec_error_interrupt),
157#endif
158};
159
160/* Must be page-aligned because the real IDT is used in the cpu entry area */
161static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;
162
163static struct desc_ptr idt_descr __ro_after_init = {
164 .size = IDT_TABLE_SIZE - 1,
165 .address = (unsigned long) idt_table,
166};
167
168void load_current_idt(void)
169{
170 lockdep_assert_irqs_disabled();
171 load_idt(&idt_descr);
172}
173
174#ifdef CONFIG_X86_F00F_BUG
175bool idt_is_f00f_address(unsigned long address)
176{
177 return ((address - idt_descr.address) >> 3) == 6;
178}
179#endif
180
181static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d)
182{
183 unsigned long addr = (unsigned long) d->addr;
184
185 gate->offset_low = (u16) addr;
186 gate->segment = (u16) d->segment;
187 gate->bits = d->bits;
188 gate->offset_middle = (u16) (addr >> 16);
189#ifdef CONFIG_X86_64
190 gate->offset_high = (u32) (addr >> 32);
191 gate->reserved = 0;
192#endif
193}
194
195static __init void
196idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys)
197{
198 gate_desc desc;
199
200 for (; size > 0; t++, size--) {
201 idt_init_desc(&desc, t);
202 write_idt_entry(idt, t->vector, &desc);
203 if (sys)
204 set_bit(t->vector, system_vectors);
205 }
206}
207
208static __init void set_intr_gate(unsigned int n, const void *addr)
209{
210 struct idt_data data;
211
212 BUG_ON(n > 0xFF);
213
214 memset(&data, 0, sizeof(data));
215 data.vector = n;
216 data.addr = addr;
217 data.segment = __KERNEL_CS;
218 data.bits.type = GATE_INTERRUPT;
219 data.bits.p = 1;
220
221 idt_setup_from_table(idt_table, &data, 1, false);
222}
223
224/**
225 * idt_setup_early_traps - Initialize the idt table with early traps
226 *
227 * On X8664 these traps do not use interrupt stacks as they can't work
228 * before cpu_init() is invoked and sets up TSS. The IST variants are
229 * installed after that.
230 */
231void __init idt_setup_early_traps(void)
232{
233 idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts),
234 true);
235 load_idt(&idt_descr);
236}
237
238/**
239 * idt_setup_traps - Initialize the idt table with default traps
240 */
241void __init idt_setup_traps(void)
242{
243 idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true);
244}
245
246#ifdef CONFIG_X86_64
247/*
248 * Early traps running on the DEFAULT_STACK because the other interrupt
249 * stacks work only after cpu_init().
250 */
251static const __initconst struct idt_data early_pf_idts[] = {
252 INTG(X86_TRAP_PF, asm_exc_page_fault),
253};
254
255/*
256 * The exceptions which use Interrupt stacks. They are setup after
257 * cpu_init() when the TSS has been initialized.
258 */
259static const __initconst struct idt_data ist_idts[] = {
260 ISTG(X86_TRAP_DB, asm_exc_debug, IST_INDEX_DB),
261 ISTG(X86_TRAP_NMI, asm_exc_nmi, IST_INDEX_NMI),
262 ISTG(X86_TRAP_DF, asm_exc_double_fault, IST_INDEX_DF),
263#ifdef CONFIG_X86_MCE
264 ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE),
265#endif
266};
267
268/**
269 * idt_setup_early_pf - Initialize the idt table with early pagefault handler
270 *
271 * On X8664 this does not use interrupt stacks as they can't work before
272 * cpu_init() is invoked and sets up TSS. The IST variant is installed
273 * after that.
274 *
275 * Note, that X86_64 cannot install the real #PF handler in
276 * idt_setup_early_traps() because the memory intialization needs the #PF
277 * handler from the early_idt_handler_array to initialize the early page
278 * tables.
279 */
280void __init idt_setup_early_pf(void)
281{
282 idt_setup_from_table(idt_table, early_pf_idts,
283 ARRAY_SIZE(early_pf_idts), true);
284}
285
286/**
287 * idt_setup_ist_traps - Initialize the idt table with traps using IST
288 */
289void __init idt_setup_ist_traps(void)
290{
291 idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts), true);
292}
293#endif
294
295static void __init idt_map_in_cea(void)
296{
297 /*
298 * Set the IDT descriptor to a fixed read-only location in the cpu
299 * entry area, so that the "sidt" instruction will not leak the
300 * location of the kernel, and to defend the IDT against arbitrary
301 * memory write vulnerabilities.
302 */
303 cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
304 PAGE_KERNEL_RO);
305 idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
306}
307
308/**
309 * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates
310 */
311void __init idt_setup_apic_and_irq_gates(void)
312{
313 int i = FIRST_EXTERNAL_VECTOR;
314 void *entry;
315
316 idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true);
317
318 for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) {
319 entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR);
320 set_intr_gate(i, entry);
321 }
322
323#ifdef CONFIG_X86_LOCAL_APIC
324 for_each_clear_bit_from(i, system_vectors, NR_VECTORS) {
325 /*
326 * Don't set the non assigned system vectors in the
327 * system_vectors bitmap. Otherwise they show up in
328 * /proc/interrupts.
329 */
330 entry = spurious_entries_start + 8 * (i - FIRST_SYSTEM_VECTOR);
331 set_intr_gate(i, entry);
332 }
333#endif
334 /* Map IDT into CPU entry area and reload it. */
335 idt_map_in_cea();
336 load_idt(&idt_descr);
337
338 /* Make the IDT table read only */
339 set_memory_ro((unsigned long)&idt_table, 1);
340
341 idt_setup_done = true;
342}
343
344/**
345 * idt_setup_early_handler - Initializes the idt table with early handlers
346 */
347void __init idt_setup_early_handler(void)
348{
349 int i;
350
351 for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
352 set_intr_gate(i, early_idt_handler_array[i]);
353#ifdef CONFIG_X86_32
354 for ( ; i < NR_VECTORS; i++)
355 set_intr_gate(i, early_ignore_irq);
356#endif
357 load_idt(&idt_descr);
358}
359
360/**
361 * idt_invalidate - Invalidate interrupt descriptor table
362 * @addr: The virtual address of the 'invalid' IDT
363 */
364void idt_invalidate(void *addr)
365{
366 struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 };
367
368 load_idt(&idt);
369}
370
371void __init alloc_intr_gate(unsigned int n, const void *addr)
372{
373 if (WARN_ON(n < FIRST_SYSTEM_VECTOR))
374 return;
375
376 if (WARN_ON(idt_setup_done))
377 return;
378
379 if (!WARN_ON(test_and_set_bit(n, system_vectors)))
380 set_intr_gate(n, addr);
381}