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1/*
2 * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
3 * JZ4740 Watchdog driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/miscdevice.h>
21#include <linux/watchdog.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25#include <linux/device.h>
26#include <linux/clk.h>
27#include <linux/slab.h>
28#include <linux/err.h>
29
30#include <asm/mach-jz4740/timer.h>
31
32#define JZ_REG_WDT_TIMER_DATA 0x0
33#define JZ_REG_WDT_COUNTER_ENABLE 0x4
34#define JZ_REG_WDT_TIMER_COUNTER 0x8
35#define JZ_REG_WDT_TIMER_CONTROL 0xC
36
37#define JZ_WDT_CLOCK_PCLK 0x1
38#define JZ_WDT_CLOCK_RTC 0x2
39#define JZ_WDT_CLOCK_EXT 0x4
40
41#define JZ_WDT_CLOCK_DIV_SHIFT 3
42
43#define JZ_WDT_CLOCK_DIV_1 (0 << JZ_WDT_CLOCK_DIV_SHIFT)
44#define JZ_WDT_CLOCK_DIV_4 (1 << JZ_WDT_CLOCK_DIV_SHIFT)
45#define JZ_WDT_CLOCK_DIV_16 (2 << JZ_WDT_CLOCK_DIV_SHIFT)
46#define JZ_WDT_CLOCK_DIV_64 (3 << JZ_WDT_CLOCK_DIV_SHIFT)
47#define JZ_WDT_CLOCK_DIV_256 (4 << JZ_WDT_CLOCK_DIV_SHIFT)
48#define JZ_WDT_CLOCK_DIV_1024 (5 << JZ_WDT_CLOCK_DIV_SHIFT)
49
50#define DEFAULT_HEARTBEAT 5
51#define MAX_HEARTBEAT 2048
52
53static bool nowayout = WATCHDOG_NOWAYOUT;
54module_param(nowayout, bool, 0);
55MODULE_PARM_DESC(nowayout,
56 "Watchdog cannot be stopped once started (default="
57 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
58
59static unsigned int heartbeat = DEFAULT_HEARTBEAT;
60module_param(heartbeat, uint, 0);
61MODULE_PARM_DESC(heartbeat,
62 "Watchdog heartbeat period in seconds from 1 to "
63 __MODULE_STRING(MAX_HEARTBEAT) ", default "
64 __MODULE_STRING(DEFAULT_HEARTBEAT));
65
66struct jz4740_wdt_drvdata {
67 struct watchdog_device wdt;
68 void __iomem *base;
69 struct clk *rtc_clk;
70};
71
72static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
73{
74 struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
75
76 writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
77 return 0;
78}
79
80static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
81 unsigned int new_timeout)
82{
83 struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
84 unsigned int rtc_clk_rate;
85 unsigned int timeout_value;
86 unsigned short clock_div = JZ_WDT_CLOCK_DIV_1;
87
88 rtc_clk_rate = clk_get_rate(drvdata->rtc_clk);
89
90 timeout_value = rtc_clk_rate * new_timeout;
91 while (timeout_value > 0xffff) {
92 if (clock_div == JZ_WDT_CLOCK_DIV_1024) {
93 /* Requested timeout too high;
94 * use highest possible value. */
95 timeout_value = 0xffff;
96 break;
97 }
98 timeout_value >>= 2;
99 clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT);
100 }
101
102 writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
103 writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
104
105 writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA);
106 writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
107 writew(clock_div | JZ_WDT_CLOCK_RTC,
108 drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
109
110 writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
111
112 wdt_dev->timeout = new_timeout;
113 return 0;
114}
115
116static int jz4740_wdt_start(struct watchdog_device *wdt_dev)
117{
118 jz4740_timer_enable_watchdog();
119 jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
120
121 return 0;
122}
123
124static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
125{
126 struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
127
128 jz4740_timer_disable_watchdog();
129 writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
130
131 return 0;
132}
133
134static const struct watchdog_info jz4740_wdt_info = {
135 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
136 .identity = "jz4740 Watchdog",
137};
138
139static const struct watchdog_ops jz4740_wdt_ops = {
140 .owner = THIS_MODULE,
141 .start = jz4740_wdt_start,
142 .stop = jz4740_wdt_stop,
143 .ping = jz4740_wdt_ping,
144 .set_timeout = jz4740_wdt_set_timeout,
145};
146
147static int __devinit jz4740_wdt_probe(struct platform_device *pdev)
148{
149 struct jz4740_wdt_drvdata *drvdata;
150 struct watchdog_device *jz4740_wdt;
151 struct resource *res;
152 int ret;
153
154 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct jz4740_wdt_drvdata),
155 GFP_KERNEL);
156 if (!drvdata) {
157 dev_err(&pdev->dev, "Unable to alloacate watchdog device\n");
158 return -ENOMEM;
159 }
160
161 if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
162 heartbeat = DEFAULT_HEARTBEAT;
163
164 jz4740_wdt = &drvdata->wdt;
165 jz4740_wdt->info = &jz4740_wdt_info;
166 jz4740_wdt->ops = &jz4740_wdt_ops;
167 jz4740_wdt->timeout = heartbeat;
168 jz4740_wdt->min_timeout = 1;
169 jz4740_wdt->max_timeout = MAX_HEARTBEAT;
170 watchdog_set_nowayout(jz4740_wdt, nowayout);
171 watchdog_set_drvdata(jz4740_wdt, drvdata);
172
173 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
174 drvdata->base = devm_request_and_ioremap(&pdev->dev, res);
175 if (drvdata->base == NULL) {
176 ret = -EBUSY;
177 goto err_out;
178 }
179
180 drvdata->rtc_clk = clk_get(NULL, "rtc");
181 if (IS_ERR(drvdata->rtc_clk)) {
182 dev_err(&pdev->dev, "cannot find RTC clock\n");
183 ret = PTR_ERR(drvdata->rtc_clk);
184 goto err_out;
185 }
186
187 ret = watchdog_register_device(&drvdata->wdt);
188 if (ret < 0)
189 goto err_disable_clk;
190
191 platform_set_drvdata(pdev, drvdata);
192 return 0;
193
194err_disable_clk:
195 clk_put(drvdata->rtc_clk);
196err_out:
197 return ret;
198}
199
200static int __devexit jz4740_wdt_remove(struct platform_device *pdev)
201{
202 struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
203
204 jz4740_wdt_stop(&drvdata->wdt);
205 watchdog_unregister_device(&drvdata->wdt);
206 clk_put(drvdata->rtc_clk);
207
208 return 0;
209}
210
211static struct platform_driver jz4740_wdt_driver = {
212 .probe = jz4740_wdt_probe,
213 .remove = __devexit_p(jz4740_wdt_remove),
214 .driver = {
215 .name = "jz4740-wdt",
216 .owner = THIS_MODULE,
217 },
218};
219
220module_platform_driver(jz4740_wdt_driver);
221
222MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
223MODULE_DESCRIPTION("jz4740 Watchdog Driver");
224MODULE_LICENSE("GPL");
225MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
226MODULE_ALIAS("platform:jz4740-wdt");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
4 * JZ4740 Watchdog driver
5 */
6
7#include <linux/mfd/ingenic-tcu.h>
8#include <linux/module.h>
9#include <linux/moduleparam.h>
10#include <linux/types.h>
11#include <linux/kernel.h>
12#include <linux/watchdog.h>
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/device.h>
16#include <linux/clk.h>
17#include <linux/slab.h>
18#include <linux/err.h>
19#include <linux/of.h>
20
21#include <asm/mach-jz4740/timer.h>
22
23#define JZ_WDT_CLOCK_PCLK 0x1
24#define JZ_WDT_CLOCK_RTC 0x2
25#define JZ_WDT_CLOCK_EXT 0x4
26
27#define JZ_WDT_CLOCK_DIV_1 (0 << TCU_TCSR_PRESCALE_LSB)
28#define JZ_WDT_CLOCK_DIV_4 (1 << TCU_TCSR_PRESCALE_LSB)
29#define JZ_WDT_CLOCK_DIV_16 (2 << TCU_TCSR_PRESCALE_LSB)
30#define JZ_WDT_CLOCK_DIV_64 (3 << TCU_TCSR_PRESCALE_LSB)
31#define JZ_WDT_CLOCK_DIV_256 (4 << TCU_TCSR_PRESCALE_LSB)
32#define JZ_WDT_CLOCK_DIV_1024 (5 << TCU_TCSR_PRESCALE_LSB)
33
34#define DEFAULT_HEARTBEAT 5
35#define MAX_HEARTBEAT 2048
36
37static bool nowayout = WATCHDOG_NOWAYOUT;
38module_param(nowayout, bool, 0);
39MODULE_PARM_DESC(nowayout,
40 "Watchdog cannot be stopped once started (default="
41 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
42
43static unsigned int heartbeat = DEFAULT_HEARTBEAT;
44module_param(heartbeat, uint, 0);
45MODULE_PARM_DESC(heartbeat,
46 "Watchdog heartbeat period in seconds from 1 to "
47 __MODULE_STRING(MAX_HEARTBEAT) ", default "
48 __MODULE_STRING(DEFAULT_HEARTBEAT));
49
50struct jz4740_wdt_drvdata {
51 struct watchdog_device wdt;
52 void __iomem *base;
53 struct clk *rtc_clk;
54};
55
56static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
57{
58 struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
59
60 writew(0x0, drvdata->base + TCU_REG_WDT_TCNT);
61 return 0;
62}
63
64static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
65 unsigned int new_timeout)
66{
67 struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
68 unsigned int rtc_clk_rate;
69 unsigned int timeout_value;
70 unsigned short clock_div = JZ_WDT_CLOCK_DIV_1;
71 u8 tcer;
72
73 rtc_clk_rate = clk_get_rate(drvdata->rtc_clk);
74
75 timeout_value = rtc_clk_rate * new_timeout;
76 while (timeout_value > 0xffff) {
77 if (clock_div == JZ_WDT_CLOCK_DIV_1024) {
78 /* Requested timeout too high;
79 * use highest possible value. */
80 timeout_value = 0xffff;
81 break;
82 }
83 timeout_value >>= 2;
84 clock_div += (1 << TCU_TCSR_PRESCALE_LSB);
85 }
86
87 tcer = readb(drvdata->base + TCU_REG_WDT_TCER);
88 writeb(0x0, drvdata->base + TCU_REG_WDT_TCER);
89 writew(clock_div, drvdata->base + TCU_REG_WDT_TCSR);
90
91 writew((u16)timeout_value, drvdata->base + TCU_REG_WDT_TDR);
92 writew(0x0, drvdata->base + TCU_REG_WDT_TCNT);
93 writew(clock_div | JZ_WDT_CLOCK_RTC, drvdata->base + TCU_REG_WDT_TCSR);
94
95 if (tcer & TCU_WDT_TCER_TCEN)
96 writeb(TCU_WDT_TCER_TCEN, drvdata->base + TCU_REG_WDT_TCER);
97
98 wdt_dev->timeout = new_timeout;
99 return 0;
100}
101
102static int jz4740_wdt_start(struct watchdog_device *wdt_dev)
103{
104 struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
105 u8 tcer;
106
107 tcer = readb(drvdata->base + TCU_REG_WDT_TCER);
108
109 jz4740_timer_enable_watchdog();
110 jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
111
112 /* Start watchdog if it wasn't started already */
113 if (!(tcer & TCU_WDT_TCER_TCEN))
114 writeb(TCU_WDT_TCER_TCEN, drvdata->base + TCU_REG_WDT_TCER);
115
116 return 0;
117}
118
119static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
120{
121 struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
122
123 writeb(0x0, drvdata->base + TCU_REG_WDT_TCER);
124 jz4740_timer_disable_watchdog();
125
126 return 0;
127}
128
129static int jz4740_wdt_restart(struct watchdog_device *wdt_dev,
130 unsigned long action, void *data)
131{
132 wdt_dev->timeout = 0;
133 jz4740_wdt_start(wdt_dev);
134 return 0;
135}
136
137static const struct watchdog_info jz4740_wdt_info = {
138 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
139 .identity = "jz4740 Watchdog",
140};
141
142static const struct watchdog_ops jz4740_wdt_ops = {
143 .owner = THIS_MODULE,
144 .start = jz4740_wdt_start,
145 .stop = jz4740_wdt_stop,
146 .ping = jz4740_wdt_ping,
147 .set_timeout = jz4740_wdt_set_timeout,
148 .restart = jz4740_wdt_restart,
149};
150
151#ifdef CONFIG_OF
152static const struct of_device_id jz4740_wdt_of_matches[] = {
153 { .compatible = "ingenic,jz4740-watchdog", },
154 { .compatible = "ingenic,jz4780-watchdog", },
155 { /* sentinel */ }
156};
157MODULE_DEVICE_TABLE(of, jz4740_wdt_of_matches);
158#endif
159
160static int jz4740_wdt_probe(struct platform_device *pdev)
161{
162 struct device *dev = &pdev->dev;
163 struct jz4740_wdt_drvdata *drvdata;
164 struct watchdog_device *jz4740_wdt;
165
166 drvdata = devm_kzalloc(dev, sizeof(struct jz4740_wdt_drvdata),
167 GFP_KERNEL);
168 if (!drvdata)
169 return -ENOMEM;
170
171 if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
172 heartbeat = DEFAULT_HEARTBEAT;
173
174 jz4740_wdt = &drvdata->wdt;
175 jz4740_wdt->info = &jz4740_wdt_info;
176 jz4740_wdt->ops = &jz4740_wdt_ops;
177 jz4740_wdt->timeout = heartbeat;
178 jz4740_wdt->min_timeout = 1;
179 jz4740_wdt->max_timeout = MAX_HEARTBEAT;
180 jz4740_wdt->parent = dev;
181 watchdog_set_nowayout(jz4740_wdt, nowayout);
182 watchdog_set_drvdata(jz4740_wdt, drvdata);
183
184 drvdata->base = devm_platform_ioremap_resource(pdev, 0);
185 if (IS_ERR(drvdata->base))
186 return PTR_ERR(drvdata->base);
187
188 drvdata->rtc_clk = devm_clk_get(dev, "rtc");
189 if (IS_ERR(drvdata->rtc_clk)) {
190 dev_err(dev, "cannot find RTC clock\n");
191 return PTR_ERR(drvdata->rtc_clk);
192 }
193
194 return devm_watchdog_register_device(dev, &drvdata->wdt);
195}
196
197static struct platform_driver jz4740_wdt_driver = {
198 .probe = jz4740_wdt_probe,
199 .driver = {
200 .name = "jz4740-wdt",
201 .of_match_table = of_match_ptr(jz4740_wdt_of_matches),
202 },
203};
204
205module_platform_driver(jz4740_wdt_driver);
206
207MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
208MODULE_DESCRIPTION("jz4740 Watchdog Driver");
209MODULE_LICENSE("GPL");
210MODULE_ALIAS("platform:jz4740-wdt");