1/*
  2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
  3 *
  4 * (C) Copyright 2008-2010 Intel Corporation
  5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
  6 *
  7 * This program is free software; you can redistribute it and/or
  8 * modify it under the terms of the GNU General Public License
  9 * as published by the Free Software Foundation; version 2
 10 * of the License.
 11 *
 12 * SCU running in ARC processor communicates with other entity running in IA
 13 * core through IPC mechanism which in turn messaging between IA core ad SCU.
 14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
 15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
 16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
 17 * along with other APIs.
 18 */
 
 19#include <linux/delay.h>
 
 20#include <linux/errno.h>
 21#include <linux/init.h>
 22#include <linux/device.h>
 23#include <linux/pm.h>
 24#include <linux/pci.h>
 25#include <linux/interrupt.h>
 
 
 26#include <linux/sfi.h>
 27#include <linux/module.h>
 28#include <asm/mrst.h>
 29#include <asm/intel_scu_ipc.h>
 30
 31/* IPC defines the following message types */
 32#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
 33#define IPCMSG_BATTERY        0xEF /* Coulomb Counter Accumulator */
 34#define IPCMSG_FW_UPDATE      0xFE /* Firmware update */
 35#define IPCMSG_PCNTRL         0xFF /* Power controller unit read/write */
 36#define IPCMSG_FW_REVISION    0xF4 /* Get firmware revision */
 37
 38/* Command id associated with message IPCMSG_PCNTRL */
 39#define IPC_CMD_PCNTRL_W      0 /* Register write */
 40#define IPC_CMD_PCNTRL_R      1 /* Register read */
 41#define IPC_CMD_PCNTRL_M      2 /* Register read-modify-write */
 42
 43/*
 44 * IPC register summary
 45 *
 46 * IPC register blocks are memory mapped at fixed address of 0xFF11C000
 47 * To read or write information to the SCU, driver writes to IPC-1 memory
 48 * mapped registers (base address 0xFF11C000). The following is the IPC
 49 * mechanism
 50 *
 51 * 1. IA core cDMI interface claims this transaction and converts it to a
 52 *    Transaction Layer Packet (TLP) message which is sent across the cDMI.
 53 *
 54 * 2. South Complex cDMI block receives this message and writes it to
 55 *    the IPC-1 register block, causing an interrupt to the SCU
 56 *
 57 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
 58 *    message handler is called within firmware.
 59 */
 60
 61#define IPC_BASE_ADDR     0xFF11C000	/* IPC1 base register address */
 62#define IPC_MAX_ADDR      0x100		/* Maximum IPC regisers */
 63#define IPC_WWBUF_SIZE    20		/* IPC Write buffer Size */
 64#define IPC_RWBUF_SIZE    20		/* IPC Read buffer Size */
 65#define IPC_I2C_BASE      0xFF12B000	/* I2C control register base address */
 66#define IPC_I2C_MAX_ADDR  0x10		/* Maximum I2C regisers */
 
 
 
 
 
 
 
 
 
 
 
 67
 68static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
 69static void ipc_remove(struct pci_dev *pdev);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 70
 71struct intel_scu_ipc_dev {
 72	struct pci_dev *pdev;
 73	void __iomem *ipc_base;
 74	void __iomem *i2c_base;
 
 
 75};
 76
 77static struct intel_scu_ipc_dev  ipcdev; /* Only one for now */
 78
 79static int platform;		/* Platform type */
 80
 81/*
 82 * IPC Read Buffer (Read Only):
 83 * 16 byte buffer for receiving data from SCU, if IPC command
 84 * processing results in response data
 85 */
 86#define IPC_READ_BUFFER		0x90
 87
 88#define IPC_I2C_CNTRL_ADDR	0
 89#define I2C_DATA_ADDR		0x04
 90
 91static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
 92
 93/*
 
 94 * Command Register (Write Only):
 95 * A write to this register results in an interrupt to the SCU core processor
 96 * Format:
 97 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
 98 */
 99static inline void ipc_command(u32 cmd) /* Send ipc command */
100{
101	writel(cmd, ipcdev.ipc_base);
 
 
 
 
102}
103
104/*
 
105 * IPC Write Buffer (Write Only):
106 * 16-byte buffer for sending data associated with IPC command to
107 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
108 */
109static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
110{
111	writel(data, ipcdev.ipc_base + 0x80 + offset);
112}
113
114/*
115 * Status Register (Read Only):
116 * Driver will read this register to get the ready/busy status of the IPC
117 * block and error status of the IPC command that was just processed by SCU
118 * Format:
119 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
120 */
121
122static inline u8 ipc_read_status(void)
123{
124	return __raw_readl(ipcdev.ipc_base + 0x04);
125}
126
127static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
 
128{
129	return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
130}
131
132static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */
 
133{
134	return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
135}
136
137static inline int busy_loop(void) /* Wait till scu status is busy */
 
138{
139	u32 status = 0;
140	u32 loop_count = 0;
141
142	status = ipc_read_status();
143	while (status & 1) {
144		udelay(1); /* scu processing time is in few u secods */
145		status = ipc_read_status();
146		loop_count++;
147		/* break if scu doesn't reset busy bit after huge retry */
148		if (loop_count > 100000) {
149			dev_err(&ipcdev.pdev->dev, "IPC timed out");
150			return -ETIMEDOUT;
151		}
152	}
153	if ((status >> 1) & 1)
 
 
 
 
 
 
154		return -EIO;
155
156	return 0;
157}
158
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
159/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
160static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
161{
 
162	int nc;
163	u32 offset = 0;
164	int err;
165	u8 cbuf[IPC_WWBUF_SIZE] = { };
166	u32 *wbuf = (u32 *)&cbuf;
167
168	mutex_lock(&ipclock);
169
170	memset(cbuf, 0, sizeof(cbuf));
171
172	if (ipcdev.pdev == NULL) {
 
 
173		mutex_unlock(&ipclock);
174		return -ENODEV;
175	}
176
177	for (nc = 0; nc < count; nc++, offset += 2) {
178		cbuf[offset] = addr[nc];
179		cbuf[offset + 1] = addr[nc] >> 8;
180	}
181
182	if (id == IPC_CMD_PCNTRL_R) {
183		for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
184			ipc_data_writel(wbuf[nc], offset);
185		ipc_command((count*2) << 16 |  id << 12 | 0 << 8 | op);
186	} else if (id == IPC_CMD_PCNTRL_W) {
187		for (nc = 0; nc < count; nc++, offset += 1)
188			cbuf[offset] = data[nc];
189		for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
190			ipc_data_writel(wbuf[nc], offset);
191		ipc_command((count*3) << 16 |  id << 12 | 0 << 8 | op);
192	} else if (id == IPC_CMD_PCNTRL_M) {
193		cbuf[offset] = data[0];
194		cbuf[offset + 1] = data[1];
195		ipc_data_writel(wbuf[0], 0); /* Write wbuff */
196		ipc_command(4 << 16 |  id << 12 | 0 << 8 | op);
197	}
198
199	err = busy_loop();
200	if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
201		/* Workaround: values are read as 0 without memcpy_fromio */
202		memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
203		for (nc = 0; nc < count; nc++)
204			data[nc] = ipc_data_readb(nc);
205	}
206	mutex_unlock(&ipclock);
207	return err;
208}
209
210/**
211 *	intel_scu_ipc_ioread8		-	read a word via the SCU
212 *	@addr: register on SCU
213 *	@data: return pointer for read byte
214 *
215 *	Read a single register. Returns 0 on success or an error code. All
216 *	locking between SCU accesses is handled for the caller.
217 *
218 *	This function may sleep.
219 */
220int intel_scu_ipc_ioread8(u16 addr, u8 *data)
221{
222	return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
223}
224EXPORT_SYMBOL(intel_scu_ipc_ioread8);
225
226/**
227 *	intel_scu_ipc_ioread16		-	read a word via the SCU
228 *	@addr: register on SCU
229 *	@data: return pointer for read word
230 *
231 *	Read a register pair. Returns 0 on success or an error code. All
232 *	locking between SCU accesses is handled for the caller.
233 *
234 *	This function may sleep.
235 */
236int intel_scu_ipc_ioread16(u16 addr, u16 *data)
237{
238	u16 x[2] = {addr, addr + 1 };
239	return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
240}
241EXPORT_SYMBOL(intel_scu_ipc_ioread16);
242
243/**
244 *	intel_scu_ipc_ioread32		-	read a dword via the SCU
245 *	@addr: register on SCU
246 *	@data: return pointer for read dword
247 *
248 *	Read four registers. Returns 0 on success or an error code. All
249 *	locking between SCU accesses is handled for the caller.
250 *
251 *	This function may sleep.
252 */
253int intel_scu_ipc_ioread32(u16 addr, u32 *data)
254{
255	u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
256	return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
257}
258EXPORT_SYMBOL(intel_scu_ipc_ioread32);
259
260/**
261 *	intel_scu_ipc_iowrite8		-	write a byte via the SCU
262 *	@addr: register on SCU
263 *	@data: byte to write
264 *
265 *	Write a single register. Returns 0 on success or an error code. All
266 *	locking between SCU accesses is handled for the caller.
267 *
268 *	This function may sleep.
269 */
270int intel_scu_ipc_iowrite8(u16 addr, u8 data)
271{
272	return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
273}
274EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
275
276/**
277 *	intel_scu_ipc_iowrite16		-	write a word via the SCU
278 *	@addr: register on SCU
279 *	@data: word to write
280 *
281 *	Write two registers. Returns 0 on success or an error code. All
282 *	locking between SCU accesses is handled for the caller.
283 *
284 *	This function may sleep.
285 */
286int intel_scu_ipc_iowrite16(u16 addr, u16 data)
287{
288	u16 x[2] = {addr, addr + 1 };
289	return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
290}
291EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
292
293/**
294 *	intel_scu_ipc_iowrite32		-	write a dword via the SCU
295 *	@addr: register on SCU
296 *	@data: dword to write
297 *
298 *	Write four registers. Returns 0 on success or an error code. All
299 *	locking between SCU accesses is handled for the caller.
300 *
301 *	This function may sleep.
302 */
303int intel_scu_ipc_iowrite32(u16 addr, u32 data)
304{
305	u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
306	return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
307}
308EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
309
310/**
311 *	intel_scu_ipc_readvv		-	read a set of registers
312 *	@addr: register list
313 *	@data: bytes to return
314 *	@len: length of array
315 *
316 *	Read registers. Returns 0 on success or an error code. All
317 *	locking between SCU accesses is handled for the caller.
318 *
319 *	The largest array length permitted by the hardware is 5 items.
320 *
321 *	This function may sleep.
322 */
323int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
324{
325	return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
326}
327EXPORT_SYMBOL(intel_scu_ipc_readv);
328
329/**
330 *	intel_scu_ipc_writev		-	write a set of registers
331 *	@addr: register list
332 *	@data: bytes to write
333 *	@len: length of array
334 *
335 *	Write registers. Returns 0 on success or an error code. All
336 *	locking between SCU accesses is handled for the caller.
337 *
338 *	The largest array length permitted by the hardware is 5 items.
339 *
340 *	This function may sleep.
341 *
342 */
343int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
344{
345	return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
346}
347EXPORT_SYMBOL(intel_scu_ipc_writev);
348
349
350/**
351 *	intel_scu_ipc_update_register	-	r/m/w a register
352 *	@addr: register address
353 *	@bits: bits to update
354 *	@mask: mask of bits to update
355 *
356 *	Read-modify-write power control unit register. The first data argument
357 *	must be register value and second is mask value
358 *	mask is a bitmap that indicates which bits to update.
359 *	0 = masked. Don't modify this bit, 1 = modify this bit.
360 *	returns 0 on success or an error code.
361 *
362 *	This function may sleep. Locking between SCU accesses is handled
363 *	for the caller.
364 */
365int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
366{
367	u8 data[2] = { bits, mask };
368	return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
369}
370EXPORT_SYMBOL(intel_scu_ipc_update_register);
371
372/**
373 *	intel_scu_ipc_simple_command	-	send a simple command
374 *	@cmd: command
375 *	@sub: sub type
376 *
377 *	Issue a simple command to the SCU. Do not use this interface if
378 *	you must then access data as any data values may be overwritten
379 *	by another SCU access by the time this function returns.
380 *
381 *	This function may sleep. Locking for SCU accesses is handled for
382 *	the caller.
383 */
384int intel_scu_ipc_simple_command(int cmd, int sub)
385{
 
386	int err;
387
388	mutex_lock(&ipclock);
389	if (ipcdev.pdev == NULL) {
390		mutex_unlock(&ipclock);
391		return -ENODEV;
392	}
393	ipc_command(sub << 12 | cmd);
394	err = busy_loop();
395	mutex_unlock(&ipclock);
396	return err;
397}
398EXPORT_SYMBOL(intel_scu_ipc_simple_command);
399
400/**
401 *	intel_scu_ipc_command	-	command with data
402 *	@cmd: command
403 *	@sub: sub type
404 *	@in: input data
405 *	@inlen: input length in dwords
406 *	@out: output data
407 *	@outlein: output length in dwords
408 *
409 *	Issue a command to the SCU which involves data transfers. Do the
410 *	data copies under the lock but leave it for the caller to interpret
411 */
412
413int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
414							u32 *out, int outlen)
415{
 
416	int i, err;
417
418	mutex_lock(&ipclock);
419	if (ipcdev.pdev == NULL) {
420		mutex_unlock(&ipclock);
421		return -ENODEV;
422	}
423
424	for (i = 0; i < inlen; i++)
425		ipc_data_writel(*in++, 4 * i);
426
427	ipc_command((inlen << 16) | (sub << 12) | cmd);
428	err = busy_loop();
429
430	for (i = 0; i < outlen; i++)
431		*out++ = ipc_data_readl(4 * i);
 
 
432
433	mutex_unlock(&ipclock);
434	return err;
435}
436EXPORT_SYMBOL(intel_scu_ipc_command);
437
438/*I2C commands */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
439#define IPC_I2C_WRITE 1 /* I2C Write command */
440#define IPC_I2C_READ  2 /* I2C Read command */
441
442/**
443 *	intel_scu_ipc_i2c_cntrl		-	I2C read/write operations
444 *	@addr: I2C address + command bits
445 *	@data: data to read/write
446 *
447 *	Perform an an I2C read/write operation via the SCU. All locking is
448 *	handled for the caller. This function may sleep.
449 *
450 *	Returns an error code or 0 on success.
451 *
452 *	This has to be in the IPC driver for the locking.
453 */
454int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
455{
 
456	u32 cmd = 0;
457
458	mutex_lock(&ipclock);
459	if (ipcdev.pdev == NULL) {
460		mutex_unlock(&ipclock);
461		return -ENODEV;
462	}
463	cmd = (addr >> 24) & 0xFF;
464	if (cmd == IPC_I2C_READ) {
465		writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
466		/* Write not getting updated without delay */
467		mdelay(1);
468		*data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
469	} else if (cmd == IPC_I2C_WRITE) {
470		writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR);
471		mdelay(1);
472		writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
473	} else {
474		dev_err(&ipcdev.pdev->dev,
475			"intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
476
477		mutex_unlock(&ipclock);
478		return -EIO;
479	}
480	mutex_unlock(&ipclock);
481	return 0;
482}
483EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
484
485/*
486 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
487 * When ioc bit is set to 1, caller api must wait for interrupt handler called
488 * which in turn unlocks the caller api. Currently this is not used
489 *
490 * This is edge triggered so we need take no action to clear anything
491 */
492static irqreturn_t ioc(int irq, void *dev_id)
493{
 
 
 
 
 
494	return IRQ_HANDLED;
495}
496
497/**
498 *	ipc_probe	-	probe an Intel SCU IPC
499 *	@dev: the PCI device matching
500 *	@id: entry in the match table
501 *
502 *	Enable and install an intel SCU IPC. This appears in the PCI space
503 *	but uses some hard coded addresses as well.
504 */
505static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
506{
507	int err;
508	resource_size_t pci_resource;
 
509
510	if (ipcdev.pdev)		/* We support only one SCU */
511		return -EBUSY;
512
513	ipcdev.pdev = pci_dev_get(dev);
 
 
 
 
514
515	err = pci_enable_device(dev);
516	if (err)
517		return err;
518
519	err = pci_request_regions(dev, "intel_scu_ipc");
520	if (err)
521		return err;
522
523	pci_resource = pci_resource_start(dev, 0);
524	if (!pci_resource)
525		return -ENOMEM;
526
527	if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
528		return -EBUSY;
529
530	ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR);
531	if (!ipcdev.ipc_base)
532		return -ENOMEM;
533
534	ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR);
535	if (!ipcdev.i2c_base) {
536		iounmap(ipcdev.ipc_base);
537		return -ENOMEM;
538	}
 
 
539
540	intel_scu_devices_create();
541
 
542	return 0;
543}
544
545/**
546 *	ipc_remove	-	remove a bound IPC device
547 *	@pdev: PCI device
548 *
549 *	In practice the SCU is not removable but this function is also
550 *	called for each device on a module unload or cleanup which is the
551 *	path that will get used.
552 *
553 *	Free up the mappings and release the PCI resources
554 */
555static void ipc_remove(struct pci_dev *pdev)
556{
557	free_irq(pdev->irq, &ipcdev);
558	pci_release_regions(pdev);
559	pci_dev_put(ipcdev.pdev);
560	iounmap(ipcdev.ipc_base);
561	iounmap(ipcdev.i2c_base);
562	ipcdev.pdev = NULL;
563	intel_scu_devices_destroy();
564}
565
566static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
567	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)},
568	{ 0,}
 
 
 
569};
570MODULE_DEVICE_TABLE(pci, pci_ids);
571
572static struct pci_driver ipc_driver = {
 
 
 
573	.name = "intel_scu_ipc",
574	.id_table = pci_ids,
575	.probe = ipc_probe,
576	.remove = ipc_remove,
577};
578
579
580static int __init intel_scu_ipc_init(void)
581{
582	platform = mrst_identify_cpu();
583	if (platform == 0)
584		return -ENODEV;
585	return  pci_register_driver(&ipc_driver);
586}
587
588static void __exit intel_scu_ipc_exit(void)
589{
590	pci_unregister_driver(&ipc_driver);
591}
592
593MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
594MODULE_DESCRIPTION("Intel SCU IPC driver");
595MODULE_LICENSE("GPL");
596
597module_init(intel_scu_ipc_init);
598module_exit(intel_scu_ipc_exit);

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Driver for the Intel SCU IPC mechanism
  4 *
  5 * (C) Copyright 2008-2010,2015 Intel Corporation
  6 * Author: Sreedhara DS (sreedhara.ds@intel.com)
  7 *
 
 
 
 
 
  8 * SCU running in ARC processor communicates with other entity running in IA
  9 * core through IPC mechanism which in turn messaging between IA core ad SCU.
 10 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
 11 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
 12 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
 13 * along with other APIs.
 14 */
 15
 16#include <linux/delay.h>
 17#include <linux/device.h>
 18#include <linux/errno.h>
 19#include <linux/init.h>
 
 
 
 20#include <linux/interrupt.h>
 21#include <linux/pci.h>
 22#include <linux/pm.h>
 23#include <linux/sfi.h>
 24
 25#include <asm/intel-mid.h>
 26#include <asm/intel_scu_ipc.h>
 27
 28/* IPC defines the following message types */
 29#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
 30#define IPCMSG_BATTERY        0xEF /* Coulomb Counter Accumulator */
 31#define IPCMSG_FW_UPDATE      0xFE /* Firmware update */
 32#define IPCMSG_PCNTRL         0xFF /* Power controller unit read/write */
 33#define IPCMSG_FW_REVISION    0xF4 /* Get firmware revision */
 34
 35/* Command id associated with message IPCMSG_PCNTRL */
 36#define IPC_CMD_PCNTRL_W      0 /* Register write */
 37#define IPC_CMD_PCNTRL_R      1 /* Register read */
 38#define IPC_CMD_PCNTRL_M      2 /* Register read-modify-write */
 39
 40/*
 41 * IPC register summary
 42 *
 43 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
 44 * To read or write information to the SCU, driver writes to IPC-1 memory
 45 * mapped registers. The following is the IPC mechanism
 
 46 *
 47 * 1. IA core cDMI interface claims this transaction and converts it to a
 48 *    Transaction Layer Packet (TLP) message which is sent across the cDMI.
 49 *
 50 * 2. South Complex cDMI block receives this message and writes it to
 51 *    the IPC-1 register block, causing an interrupt to the SCU
 52 *
 53 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
 54 *    message handler is called within firmware.
 55 */
 56
 
 
 57#define IPC_WWBUF_SIZE    20		/* IPC Write buffer Size */
 58#define IPC_RWBUF_SIZE    20		/* IPC Read buffer Size */
 59#define IPC_IOC	          0x100		/* IPC command register IOC bit */
 60
 61#define PCI_DEVICE_ID_LINCROFT		0x082a
 62#define PCI_DEVICE_ID_PENWELL		0x080e
 63#define PCI_DEVICE_ID_CLOVERVIEW	0x08ea
 64#define PCI_DEVICE_ID_TANGIER		0x11a0
 65
 66/* intel scu ipc driver data */
 67struct intel_scu_ipc_pdata_t {
 68	u32 i2c_base;
 69	u32 i2c_len;
 70	u8 irq_mode;
 71};
 72
 73static const struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
 74	.i2c_base = 0xff12b000,
 75	.i2c_len = 0x10,
 76	.irq_mode = 0,
 77};
 78
 79/* Penwell and Cloverview */
 80static const struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
 81	.i2c_base = 0xff12b000,
 82	.i2c_len = 0x10,
 83	.irq_mode = 1,
 84};
 85
 86static const struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
 87	.i2c_base  = 0xff00d000,
 88	.i2c_len = 0x10,
 89	.irq_mode = 0,
 90};
 91
 92struct intel_scu_ipc_dev {
 93	struct device *dev;
 94	void __iomem *ipc_base;
 95	void __iomem *i2c_base;
 96	struct completion cmd_complete;
 97	u8 irq_mode;
 98};
 99
100static struct intel_scu_ipc_dev  ipcdev; /* Only one for now */
101
 
 
102/*
103 * IPC Read Buffer (Read Only):
104 * 16 byte buffer for receiving data from SCU, if IPC command
105 * processing results in response data
106 */
107#define IPC_READ_BUFFER		0x90
108
109#define IPC_I2C_CNTRL_ADDR	0
110#define I2C_DATA_ADDR		0x04
111
112static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
113
114/*
115 * Send ipc command
116 * Command Register (Write Only):
117 * A write to this register results in an interrupt to the SCU core processor
118 * Format:
119 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
120 */
121static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
122{
123	if (scu->irq_mode) {
124		reinit_completion(&scu->cmd_complete);
125		writel(cmd | IPC_IOC, scu->ipc_base);
126	}
127	writel(cmd, scu->ipc_base);
128}
129
130/*
131 * Write ipc data
132 * IPC Write Buffer (Write Only):
133 * 16-byte buffer for sending data associated with IPC command to
134 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
135 */
136static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
137{
138	writel(data, scu->ipc_base + 0x80 + offset);
139}
140
141/*
142 * Status Register (Read Only):
143 * Driver will read this register to get the ready/busy status of the IPC
144 * block and error status of the IPC command that was just processed by SCU
145 * Format:
146 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
147 */
148static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
 
149{
150	return __raw_readl(scu->ipc_base + 0x04);
151}
152
153/* Read ipc byte data */
154static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
155{
156	return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
157}
158
159/* Read ipc u32 data */
160static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
161{
162	return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
163}
164
165/* Wait till scu status is busy */
166static inline int busy_loop(struct intel_scu_ipc_dev *scu)
167{
168	u32 status = ipc_read_status(scu);
169	u32 loop_count = 100000;
170
171	/* break if scu doesn't reset busy bit after huge retry */
172	while ((status & BIT(0)) && --loop_count) {
173		udelay(1); /* scu processing time is in few u secods */
174		status = ipc_read_status(scu);
 
 
 
 
 
 
175	}
176
177	if (status & BIT(0)) {
178		dev_err(scu->dev, "IPC timed out");
179		return -ETIMEDOUT;
180	}
181
182	if (status & BIT(1))
183		return -EIO;
184
185	return 0;
186}
187
188/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
189static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
190{
191	int status;
192
193	if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
194		dev_err(scu->dev, "IPC timed out\n");
195		return -ETIMEDOUT;
196	}
197
198	status = ipc_read_status(scu);
199	if (status & BIT(1))
200		return -EIO;
201
202	return 0;
203}
204
205static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
206{
207	return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
208}
209
210/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
211static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
212{
213	struct intel_scu_ipc_dev *scu = &ipcdev;
214	int nc;
215	u32 offset = 0;
216	int err;
217	u8 cbuf[IPC_WWBUF_SIZE];
218	u32 *wbuf = (u32 *)&cbuf;
219
 
 
220	memset(cbuf, 0, sizeof(cbuf));
221
222	mutex_lock(&ipclock);
223
224	if (scu->dev == NULL) {
225		mutex_unlock(&ipclock);
226		return -ENODEV;
227	}
228
229	for (nc = 0; nc < count; nc++, offset += 2) {
230		cbuf[offset] = addr[nc];
231		cbuf[offset + 1] = addr[nc] >> 8;
232	}
233
234	if (id == IPC_CMD_PCNTRL_R) {
235		for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
236			ipc_data_writel(scu, wbuf[nc], offset);
237		ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
238	} else if (id == IPC_CMD_PCNTRL_W) {
239		for (nc = 0; nc < count; nc++, offset += 1)
240			cbuf[offset] = data[nc];
241		for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
242			ipc_data_writel(scu, wbuf[nc], offset);
243		ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
244	} else if (id == IPC_CMD_PCNTRL_M) {
245		cbuf[offset] = data[0];
246		cbuf[offset + 1] = data[1];
247		ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
248		ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
249	}
250
251	err = intel_scu_ipc_check_status(scu);
252	if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
253		/* Workaround: values are read as 0 without memcpy_fromio */
254		memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
255		for (nc = 0; nc < count; nc++)
256			data[nc] = ipc_data_readb(scu, nc);
257	}
258	mutex_unlock(&ipclock);
259	return err;
260}
261
262/**
263 *	intel_scu_ipc_ioread8		-	read a word via the SCU
264 *	@addr: register on SCU
265 *	@data: return pointer for read byte
266 *
267 *	Read a single register. Returns 0 on success or an error code. All
268 *	locking between SCU accesses is handled for the caller.
269 *
270 *	This function may sleep.
271 */
272int intel_scu_ipc_ioread8(u16 addr, u8 *data)
273{
274	return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
275}
276EXPORT_SYMBOL(intel_scu_ipc_ioread8);
277
278/**
279 *	intel_scu_ipc_ioread16		-	read a word via the SCU
280 *	@addr: register on SCU
281 *	@data: return pointer for read word
282 *
283 *	Read a register pair. Returns 0 on success or an error code. All
284 *	locking between SCU accesses is handled for the caller.
285 *
286 *	This function may sleep.
287 */
288int intel_scu_ipc_ioread16(u16 addr, u16 *data)
289{
290	u16 x[2] = {addr, addr + 1};
291	return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
292}
293EXPORT_SYMBOL(intel_scu_ipc_ioread16);
294
295/**
296 *	intel_scu_ipc_ioread32		-	read a dword via the SCU
297 *	@addr: register on SCU
298 *	@data: return pointer for read dword
299 *
300 *	Read four registers. Returns 0 on success or an error code. All
301 *	locking between SCU accesses is handled for the caller.
302 *
303 *	This function may sleep.
304 */
305int intel_scu_ipc_ioread32(u16 addr, u32 *data)
306{
307	u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
308	return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
309}
310EXPORT_SYMBOL(intel_scu_ipc_ioread32);
311
312/**
313 *	intel_scu_ipc_iowrite8		-	write a byte via the SCU
314 *	@addr: register on SCU
315 *	@data: byte to write
316 *
317 *	Write a single register. Returns 0 on success or an error code. All
318 *	locking between SCU accesses is handled for the caller.
319 *
320 *	This function may sleep.
321 */
322int intel_scu_ipc_iowrite8(u16 addr, u8 data)
323{
324	return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
325}
326EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
327
328/**
329 *	intel_scu_ipc_iowrite16		-	write a word via the SCU
330 *	@addr: register on SCU
331 *	@data: word to write
332 *
333 *	Write two registers. Returns 0 on success or an error code. All
334 *	locking between SCU accesses is handled for the caller.
335 *
336 *	This function may sleep.
337 */
338int intel_scu_ipc_iowrite16(u16 addr, u16 data)
339{
340	u16 x[2] = {addr, addr + 1};
341	return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
342}
343EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
344
345/**
346 *	intel_scu_ipc_iowrite32		-	write a dword via the SCU
347 *	@addr: register on SCU
348 *	@data: dword to write
349 *
350 *	Write four registers. Returns 0 on success or an error code. All
351 *	locking between SCU accesses is handled for the caller.
352 *
353 *	This function may sleep.
354 */
355int intel_scu_ipc_iowrite32(u16 addr, u32 data)
356{
357	u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
358	return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
359}
360EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
361
362/**
363 *	intel_scu_ipc_readvv		-	read a set of registers
364 *	@addr: register list
365 *	@data: bytes to return
366 *	@len: length of array
367 *
368 *	Read registers. Returns 0 on success or an error code. All
369 *	locking between SCU accesses is handled for the caller.
370 *
371 *	The largest array length permitted by the hardware is 5 items.
372 *
373 *	This function may sleep.
374 */
375int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
376{
377	return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
378}
379EXPORT_SYMBOL(intel_scu_ipc_readv);
380
381/**
382 *	intel_scu_ipc_writev		-	write a set of registers
383 *	@addr: register list
384 *	@data: bytes to write
385 *	@len: length of array
386 *
387 *	Write registers. Returns 0 on success or an error code. All
388 *	locking between SCU accesses is handled for the caller.
389 *
390 *	The largest array length permitted by the hardware is 5 items.
391 *
392 *	This function may sleep.
393 *
394 */
395int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
396{
397	return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
398}
399EXPORT_SYMBOL(intel_scu_ipc_writev);
400
 
401/**
402 *	intel_scu_ipc_update_register	-	r/m/w a register
403 *	@addr: register address
404 *	@bits: bits to update
405 *	@mask: mask of bits to update
406 *
407 *	Read-modify-write power control unit register. The first data argument
408 *	must be register value and second is mask value
409 *	mask is a bitmap that indicates which bits to update.
410 *	0 = masked. Don't modify this bit, 1 = modify this bit.
411 *	returns 0 on success or an error code.
412 *
413 *	This function may sleep. Locking between SCU accesses is handled
414 *	for the caller.
415 */
416int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
417{
418	u8 data[2] = { bits, mask };
419	return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
420}
421EXPORT_SYMBOL(intel_scu_ipc_update_register);
422
423/**
424 *	intel_scu_ipc_simple_command	-	send a simple command
425 *	@cmd: command
426 *	@sub: sub type
427 *
428 *	Issue a simple command to the SCU. Do not use this interface if
429 *	you must then access data as any data values may be overwritten
430 *	by another SCU access by the time this function returns.
431 *
432 *	This function may sleep. Locking for SCU accesses is handled for
433 *	the caller.
434 */
435int intel_scu_ipc_simple_command(int cmd, int sub)
436{
437	struct intel_scu_ipc_dev *scu = &ipcdev;
438	int err;
439
440	mutex_lock(&ipclock);
441	if (scu->dev == NULL) {
442		mutex_unlock(&ipclock);
443		return -ENODEV;
444	}
445	ipc_command(scu, sub << 12 | cmd);
446	err = intel_scu_ipc_check_status(scu);
447	mutex_unlock(&ipclock);
448	return err;
449}
450EXPORT_SYMBOL(intel_scu_ipc_simple_command);
451
452/**
453 *	intel_scu_ipc_command	-	command with data
454 *	@cmd: command
455 *	@sub: sub type
456 *	@in: input data
457 *	@inlen: input length in dwords
458 *	@out: output data
459 *	@outlein: output length in dwords
460 *
461 *	Issue a command to the SCU which involves data transfers. Do the
462 *	data copies under the lock but leave it for the caller to interpret
463 */
 
464int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
465			  u32 *out, int outlen)
466{
467	struct intel_scu_ipc_dev *scu = &ipcdev;
468	int i, err;
469
470	mutex_lock(&ipclock);
471	if (scu->dev == NULL) {
472		mutex_unlock(&ipclock);
473		return -ENODEV;
474	}
475
476	for (i = 0; i < inlen; i++)
477		ipc_data_writel(scu, *in++, 4 * i);
478
479	ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
480	err = intel_scu_ipc_check_status(scu);
481
482	if (!err) {
483		for (i = 0; i < outlen; i++)
484			*out++ = ipc_data_readl(scu, 4 * i);
485	}
486
487	mutex_unlock(&ipclock);
488	return err;
489}
490EXPORT_SYMBOL(intel_scu_ipc_command);
491
492#define IPC_SPTR		0x08
493#define IPC_DPTR		0x0C
494
495/**
496 * intel_scu_ipc_raw_command() - IPC command with data and pointers
497 * @cmd:	IPC command code.
498 * @sub:	IPC command sub type.
499 * @in:		input data of this IPC command.
500 * @inlen:	input data length in dwords.
501 * @out:	output data of this IPC command.
502 * @outlen:	output data length in dwords.
503 * @sptr:	data writing to SPTR register.
504 * @dptr:	data writing to DPTR register.
505 *
506 * Send an IPC command to SCU with input/output data and source/dest pointers.
507 *
508 * Return:	an IPC error code or 0 on success.
509 */
510int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,
511			      u32 *out, int outlen, u32 dptr, u32 sptr)
512{
513	struct intel_scu_ipc_dev *scu = &ipcdev;
514	int inbuflen = DIV_ROUND_UP(inlen, 4);
515	u32 inbuf[4];
516	int i, err;
517
518	/* Up to 16 bytes */
519	if (inbuflen > 4)
520		return -EINVAL;
521
522	mutex_lock(&ipclock);
523	if (scu->dev == NULL) {
524		mutex_unlock(&ipclock);
525		return -ENODEV;
526	}
527
528	writel(dptr, scu->ipc_base + IPC_DPTR);
529	writel(sptr, scu->ipc_base + IPC_SPTR);
530
531	/*
532	 * SRAM controller doesn't support 8-bit writes, it only
533	 * supports 32-bit writes, so we have to copy input data into
534	 * the temporary buffer, and SCU FW will use the inlen to
535	 * determine the actual input data length in the temporary
536	 * buffer.
537	 */
538	memcpy(inbuf, in, inlen);
539
540	for (i = 0; i < inbuflen; i++)
541		ipc_data_writel(scu, inbuf[i], 4 * i);
542
543	ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
544	err = intel_scu_ipc_check_status(scu);
545	if (!err) {
546		for (i = 0; i < outlen; i++)
547			*out++ = ipc_data_readl(scu, 4 * i);
548	}
549
550	mutex_unlock(&ipclock);
551	return err;
552}
553EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command);
554
555/* I2C commands */
556#define IPC_I2C_WRITE 1 /* I2C Write command */
557#define IPC_I2C_READ  2 /* I2C Read command */
558
559/**
560 *	intel_scu_ipc_i2c_cntrl		-	I2C read/write operations
561 *	@addr: I2C address + command bits
562 *	@data: data to read/write
563 *
564 *	Perform an an I2C read/write operation via the SCU. All locking is
565 *	handled for the caller. This function may sleep.
566 *
567 *	Returns an error code or 0 on success.
568 *
569 *	This has to be in the IPC driver for the locking.
570 */
571int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
572{
573	struct intel_scu_ipc_dev *scu = &ipcdev;
574	u32 cmd = 0;
575
576	mutex_lock(&ipclock);
577	if (scu->dev == NULL) {
578		mutex_unlock(&ipclock);
579		return -ENODEV;
580	}
581	cmd = (addr >> 24) & 0xFF;
582	if (cmd == IPC_I2C_READ) {
583		writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
584		/* Write not getting updated without delay */
585		usleep_range(1000, 2000);
586		*data = readl(scu->i2c_base + I2C_DATA_ADDR);
587	} else if (cmd == IPC_I2C_WRITE) {
588		writel(*data, scu->i2c_base + I2C_DATA_ADDR);
589		usleep_range(1000, 2000);
590		writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
591	} else {
592		dev_err(scu->dev,
593			"intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
594
595		mutex_unlock(&ipclock);
596		return -EIO;
597	}
598	mutex_unlock(&ipclock);
599	return 0;
600}
601EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
602
603/*
604 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
605 * When ioc bit is set to 1, caller api must wait for interrupt handler called
606 * which in turn unlocks the caller api. Currently this is not used
607 *
608 * This is edge triggered so we need take no action to clear anything
609 */
610static irqreturn_t ioc(int irq, void *dev_id)
611{
612	struct intel_scu_ipc_dev *scu = dev_id;
613
614	if (scu->irq_mode)
615		complete(&scu->cmd_complete);
616
617	return IRQ_HANDLED;
618}
619
620/**
621 *	ipc_probe	-	probe an Intel SCU IPC
622 *	@pdev: the PCI device matching
623 *	@id: entry in the match table
624 *
625 *	Enable and install an intel SCU IPC. This appears in the PCI space
626 *	but uses some hard coded addresses as well.
627 */
628static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)
629{
630	int err;
631	struct intel_scu_ipc_dev *scu = &ipcdev;
632	struct intel_scu_ipc_pdata_t *pdata;
633
634	if (scu->dev)		/* We support only one SCU */
635		return -EBUSY;
636
637	pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
638	if (!pdata)
639		return -ENODEV;
640
641	scu->irq_mode = pdata->irq_mode;
642
643	err = pcim_enable_device(pdev);
644	if (err)
645		return err;
646
647	err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
648	if (err)
649		return err;
650
651	init_completion(&scu->cmd_complete);
 
 
652
653	scu->ipc_base = pcim_iomap_table(pdev)[0];
 
654
655	scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
656	if (!scu->i2c_base)
657		return -ENOMEM;
658
659	err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_scu_ipc",
660			       scu);
661	if (err)
662		return err;
663
664	/* Assign device at last */
665	scu->dev = &pdev->dev;
666
667	intel_scu_devices_create();
668
669	pci_set_drvdata(pdev, scu);
670	return 0;
671}
672
673#define SCU_DEVICE(id, pdata)	{PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&pdata}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
674
675static const struct pci_device_id pci_ids[] = {
676	SCU_DEVICE(PCI_DEVICE_ID_LINCROFT,	intel_scu_ipc_lincroft_pdata),
677	SCU_DEVICE(PCI_DEVICE_ID_PENWELL,	intel_scu_ipc_penwell_pdata),
678	SCU_DEVICE(PCI_DEVICE_ID_CLOVERVIEW,	intel_scu_ipc_penwell_pdata),
679	SCU_DEVICE(PCI_DEVICE_ID_TANGIER,	intel_scu_ipc_tangier_pdata),
680	{}
681};
 
682
683static struct pci_driver ipc_driver = {
684	.driver = {
685		.suppress_bind_attrs = true,
686	},
687	.name = "intel_scu_ipc",
688	.id_table = pci_ids,
689	.probe = ipc_probe,
 
690};
691builtin_pci_driver(ipc_driver);