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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2010,2015 Broadcom
4 * Copyright (C) 2012 Stephen Warren
5 */
6
7/**
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
9 *
10 * The clock tree on the 2835 has several levels. There's a root
11 * oscillator running at 19.2Mhz. After the oscillator there are 5
12 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
13 * and "HDMI displays". Those 5 PLLs each can divide their output to
14 * produce up to 4 channels. Finally, there is the level of clocks to
15 * be consumed by other hardware components (like "H264" or "HDMI
16 * state machine"), which divide off of some subset of the PLL
17 * channels.
18 *
19 * All of the clocks in the tree are exposed in the DT, because the DT
20 * may want to make assignments of the final layer of clocks to the
21 * PLL channels, and some components of the hardware will actually
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
24 * generator).
25 */
26
27#include <linux/clk-provider.h>
28#include <linux/clkdev.h>
29#include <linux/clk.h>
30#include <linux/debugfs.h>
31#include <linux/delay.h>
32#include <linux/io.h>
33#include <linux/module.h>
34#include <linux/of_device.h>
35#include <linux/platform_device.h>
36#include <linux/slab.h>
37#include <dt-bindings/clock/bcm2835.h>
38
39#define CM_PASSWORD 0x5a000000
40
41#define CM_GNRICCTL 0x000
42#define CM_GNRICDIV 0x004
43# define CM_DIV_FRAC_BITS 12
44# define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
45
46#define CM_VPUCTL 0x008
47#define CM_VPUDIV 0x00c
48#define CM_SYSCTL 0x010
49#define CM_SYSDIV 0x014
50#define CM_PERIACTL 0x018
51#define CM_PERIADIV 0x01c
52#define CM_PERIICTL 0x020
53#define CM_PERIIDIV 0x024
54#define CM_H264CTL 0x028
55#define CM_H264DIV 0x02c
56#define CM_ISPCTL 0x030
57#define CM_ISPDIV 0x034
58#define CM_V3DCTL 0x038
59#define CM_V3DDIV 0x03c
60#define CM_CAM0CTL 0x040
61#define CM_CAM0DIV 0x044
62#define CM_CAM1CTL 0x048
63#define CM_CAM1DIV 0x04c
64#define CM_CCP2CTL 0x050
65#define CM_CCP2DIV 0x054
66#define CM_DSI0ECTL 0x058
67#define CM_DSI0EDIV 0x05c
68#define CM_DSI0PCTL 0x060
69#define CM_DSI0PDIV 0x064
70#define CM_DPICTL 0x068
71#define CM_DPIDIV 0x06c
72#define CM_GP0CTL 0x070
73#define CM_GP0DIV 0x074
74#define CM_GP1CTL 0x078
75#define CM_GP1DIV 0x07c
76#define CM_GP2CTL 0x080
77#define CM_GP2DIV 0x084
78#define CM_HSMCTL 0x088
79#define CM_HSMDIV 0x08c
80#define CM_OTPCTL 0x090
81#define CM_OTPDIV 0x094
82#define CM_PCMCTL 0x098
83#define CM_PCMDIV 0x09c
84#define CM_PWMCTL 0x0a0
85#define CM_PWMDIV 0x0a4
86#define CM_SLIMCTL 0x0a8
87#define CM_SLIMDIV 0x0ac
88#define CM_SMICTL 0x0b0
89#define CM_SMIDIV 0x0b4
90/* no definition for 0x0b8 and 0x0bc */
91#define CM_TCNTCTL 0x0c0
92# define CM_TCNT_SRC1_SHIFT 12
93#define CM_TCNTCNT 0x0c4
94#define CM_TECCTL 0x0c8
95#define CM_TECDIV 0x0cc
96#define CM_TD0CTL 0x0d0
97#define CM_TD0DIV 0x0d4
98#define CM_TD1CTL 0x0d8
99#define CM_TD1DIV 0x0dc
100#define CM_TSENSCTL 0x0e0
101#define CM_TSENSDIV 0x0e4
102#define CM_TIMERCTL 0x0e8
103#define CM_TIMERDIV 0x0ec
104#define CM_UARTCTL 0x0f0
105#define CM_UARTDIV 0x0f4
106#define CM_VECCTL 0x0f8
107#define CM_VECDIV 0x0fc
108#define CM_PULSECTL 0x190
109#define CM_PULSEDIV 0x194
110#define CM_SDCCTL 0x1a8
111#define CM_SDCDIV 0x1ac
112#define CM_ARMCTL 0x1b0
113#define CM_AVEOCTL 0x1b8
114#define CM_AVEODIV 0x1bc
115#define CM_EMMCCTL 0x1c0
116#define CM_EMMCDIV 0x1c4
117#define CM_EMMC2CTL 0x1d0
118#define CM_EMMC2DIV 0x1d4
119
120/* General bits for the CM_*CTL regs */
121# define CM_ENABLE BIT(4)
122# define CM_KILL BIT(5)
123# define CM_GATE_BIT 6
124# define CM_GATE BIT(CM_GATE_BIT)
125# define CM_BUSY BIT(7)
126# define CM_BUSYD BIT(8)
127# define CM_FRAC BIT(9)
128# define CM_SRC_SHIFT 0
129# define CM_SRC_BITS 4
130# define CM_SRC_MASK 0xf
131# define CM_SRC_GND 0
132# define CM_SRC_OSC 1
133# define CM_SRC_TESTDEBUG0 2
134# define CM_SRC_TESTDEBUG1 3
135# define CM_SRC_PLLA_CORE 4
136# define CM_SRC_PLLA_PER 4
137# define CM_SRC_PLLC_CORE0 5
138# define CM_SRC_PLLC_PER 5
139# define CM_SRC_PLLC_CORE1 8
140# define CM_SRC_PLLD_CORE 6
141# define CM_SRC_PLLD_PER 6
142# define CM_SRC_PLLH_AUX 7
143# define CM_SRC_PLLC_CORE1 8
144# define CM_SRC_PLLC_CORE2 9
145
146#define CM_OSCCOUNT 0x100
147
148#define CM_PLLA 0x104
149# define CM_PLL_ANARST BIT(8)
150# define CM_PLLA_HOLDPER BIT(7)
151# define CM_PLLA_LOADPER BIT(6)
152# define CM_PLLA_HOLDCORE BIT(5)
153# define CM_PLLA_LOADCORE BIT(4)
154# define CM_PLLA_HOLDCCP2 BIT(3)
155# define CM_PLLA_LOADCCP2 BIT(2)
156# define CM_PLLA_HOLDDSI0 BIT(1)
157# define CM_PLLA_LOADDSI0 BIT(0)
158
159#define CM_PLLC 0x108
160# define CM_PLLC_HOLDPER BIT(7)
161# define CM_PLLC_LOADPER BIT(6)
162# define CM_PLLC_HOLDCORE2 BIT(5)
163# define CM_PLLC_LOADCORE2 BIT(4)
164# define CM_PLLC_HOLDCORE1 BIT(3)
165# define CM_PLLC_LOADCORE1 BIT(2)
166# define CM_PLLC_HOLDCORE0 BIT(1)
167# define CM_PLLC_LOADCORE0 BIT(0)
168
169#define CM_PLLD 0x10c
170# define CM_PLLD_HOLDPER BIT(7)
171# define CM_PLLD_LOADPER BIT(6)
172# define CM_PLLD_HOLDCORE BIT(5)
173# define CM_PLLD_LOADCORE BIT(4)
174# define CM_PLLD_HOLDDSI1 BIT(3)
175# define CM_PLLD_LOADDSI1 BIT(2)
176# define CM_PLLD_HOLDDSI0 BIT(1)
177# define CM_PLLD_LOADDSI0 BIT(0)
178
179#define CM_PLLH 0x110
180# define CM_PLLH_LOADRCAL BIT(2)
181# define CM_PLLH_LOADAUX BIT(1)
182# define CM_PLLH_LOADPIX BIT(0)
183
184#define CM_LOCK 0x114
185# define CM_LOCK_FLOCKH BIT(12)
186# define CM_LOCK_FLOCKD BIT(11)
187# define CM_LOCK_FLOCKC BIT(10)
188# define CM_LOCK_FLOCKB BIT(9)
189# define CM_LOCK_FLOCKA BIT(8)
190
191#define CM_EVENT 0x118
192#define CM_DSI1ECTL 0x158
193#define CM_DSI1EDIV 0x15c
194#define CM_DSI1PCTL 0x160
195#define CM_DSI1PDIV 0x164
196#define CM_DFTCTL 0x168
197#define CM_DFTDIV 0x16c
198
199#define CM_PLLB 0x170
200# define CM_PLLB_HOLDARM BIT(1)
201# define CM_PLLB_LOADARM BIT(0)
202
203#define A2W_PLLA_CTRL 0x1100
204#define A2W_PLLC_CTRL 0x1120
205#define A2W_PLLD_CTRL 0x1140
206#define A2W_PLLH_CTRL 0x1160
207#define A2W_PLLB_CTRL 0x11e0
208# define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
209# define A2W_PLL_CTRL_PWRDN BIT(16)
210# define A2W_PLL_CTRL_PDIV_MASK 0x000007000
211# define A2W_PLL_CTRL_PDIV_SHIFT 12
212# define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
213# define A2W_PLL_CTRL_NDIV_SHIFT 0
214
215#define A2W_PLLA_ANA0 0x1010
216#define A2W_PLLC_ANA0 0x1030
217#define A2W_PLLD_ANA0 0x1050
218#define A2W_PLLH_ANA0 0x1070
219#define A2W_PLLB_ANA0 0x10f0
220
221#define A2W_PLL_KA_SHIFT 7
222#define A2W_PLL_KA_MASK GENMASK(9, 7)
223#define A2W_PLL_KI_SHIFT 19
224#define A2W_PLL_KI_MASK GENMASK(21, 19)
225#define A2W_PLL_KP_SHIFT 15
226#define A2W_PLL_KP_MASK GENMASK(18, 15)
227
228#define A2W_PLLH_KA_SHIFT 19
229#define A2W_PLLH_KA_MASK GENMASK(21, 19)
230#define A2W_PLLH_KI_LOW_SHIFT 22
231#define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
232#define A2W_PLLH_KI_HIGH_SHIFT 0
233#define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
234#define A2W_PLLH_KP_SHIFT 1
235#define A2W_PLLH_KP_MASK GENMASK(4, 1)
236
237#define A2W_XOSC_CTRL 0x1190
238# define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
239# define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
240# define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
241# define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
242# define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
243# define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
244# define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
245# define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
246
247#define A2W_PLLA_FRAC 0x1200
248#define A2W_PLLC_FRAC 0x1220
249#define A2W_PLLD_FRAC 0x1240
250#define A2W_PLLH_FRAC 0x1260
251#define A2W_PLLB_FRAC 0x12e0
252# define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
253# define A2W_PLL_FRAC_BITS 20
254
255#define A2W_PLL_CHANNEL_DISABLE BIT(8)
256#define A2W_PLL_DIV_BITS 8
257#define A2W_PLL_DIV_SHIFT 0
258
259#define A2W_PLLA_DSI0 0x1300
260#define A2W_PLLA_CORE 0x1400
261#define A2W_PLLA_PER 0x1500
262#define A2W_PLLA_CCP2 0x1600
263
264#define A2W_PLLC_CORE2 0x1320
265#define A2W_PLLC_CORE1 0x1420
266#define A2W_PLLC_PER 0x1520
267#define A2W_PLLC_CORE0 0x1620
268
269#define A2W_PLLD_DSI0 0x1340
270#define A2W_PLLD_CORE 0x1440
271#define A2W_PLLD_PER 0x1540
272#define A2W_PLLD_DSI1 0x1640
273
274#define A2W_PLLH_AUX 0x1360
275#define A2W_PLLH_RCAL 0x1460
276#define A2W_PLLH_PIX 0x1560
277#define A2W_PLLH_STS 0x1660
278
279#define A2W_PLLH_CTRLR 0x1960
280#define A2W_PLLH_FRACR 0x1a60
281#define A2W_PLLH_AUXR 0x1b60
282#define A2W_PLLH_RCALR 0x1c60
283#define A2W_PLLH_PIXR 0x1d60
284#define A2W_PLLH_STSR 0x1e60
285
286#define A2W_PLLB_ARM 0x13e0
287#define A2W_PLLB_SP0 0x14e0
288#define A2W_PLLB_SP1 0x15e0
289#define A2W_PLLB_SP2 0x16e0
290
291#define LOCK_TIMEOUT_NS 100000000
292#define BCM2835_MAX_FB_RATE 1750000000u
293
294#define SOC_BCM2835 BIT(0)
295#define SOC_BCM2711 BIT(1)
296#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
297
298/*
299 * Names of clocks used within the driver that need to be replaced
300 * with an external parent's name. This array is in the order that
301 * the clocks node in the DT references external clocks.
302 */
303static const char *const cprman_parent_names[] = {
304 "xosc",
305 "dsi0_byte",
306 "dsi0_ddr2",
307 "dsi0_ddr",
308 "dsi1_byte",
309 "dsi1_ddr2",
310 "dsi1_ddr",
311};
312
313struct bcm2835_cprman {
314 struct device *dev;
315 void __iomem *regs;
316 spinlock_t regs_lock; /* spinlock for all clocks */
317
318 /*
319 * Real names of cprman clock parents looked up through
320 * of_clk_get_parent_name(), which will be used in the
321 * parent_names[] arrays for clock registration.
322 */
323 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
324
325 /* Must be last */
326 struct clk_hw_onecell_data onecell;
327};
328
329struct cprman_plat_data {
330 unsigned int soc;
331};
332
333static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
334{
335 writel(CM_PASSWORD | val, cprman->regs + reg);
336}
337
338static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
339{
340 return readl(cprman->regs + reg);
341}
342
343/* Does a cycle of measuring a clock through the TCNT clock, which may
344 * source from many other clocks in the system.
345 */
346static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
347 u32 tcnt_mux)
348{
349 u32 osccount = 19200; /* 1ms */
350 u32 count;
351 ktime_t timeout;
352
353 spin_lock(&cprman->regs_lock);
354
355 cprman_write(cprman, CM_TCNTCTL, CM_KILL);
356
357 cprman_write(cprman, CM_TCNTCTL,
358 (tcnt_mux & CM_SRC_MASK) |
359 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
360
361 cprman_write(cprman, CM_OSCCOUNT, osccount);
362
363 /* do a kind delay at the start */
364 mdelay(1);
365
366 /* Finish off whatever is left of OSCCOUNT */
367 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
368 while (cprman_read(cprman, CM_OSCCOUNT)) {
369 if (ktime_after(ktime_get(), timeout)) {
370 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
371 count = 0;
372 goto out;
373 }
374 cpu_relax();
375 }
376
377 /* Wait for BUSY to clear. */
378 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
379 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
380 if (ktime_after(ktime_get(), timeout)) {
381 dev_err(cprman->dev, "timeout waiting for !BUSY\n");
382 count = 0;
383 goto out;
384 }
385 cpu_relax();
386 }
387
388 count = cprman_read(cprman, CM_TCNTCNT);
389
390 cprman_write(cprman, CM_TCNTCTL, 0);
391
392out:
393 spin_unlock(&cprman->regs_lock);
394
395 return count * 1000;
396}
397
398static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
399 struct debugfs_reg32 *regs, size_t nregs,
400 struct dentry *dentry)
401{
402 struct debugfs_regset32 *regset;
403
404 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
405 if (!regset)
406 return;
407
408 regset->regs = regs;
409 regset->nregs = nregs;
410 regset->base = cprman->regs + base;
411
412 debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
413}
414
415struct bcm2835_pll_data {
416 const char *name;
417 u32 cm_ctrl_reg;
418 u32 a2w_ctrl_reg;
419 u32 frac_reg;
420 u32 ana_reg_base;
421 u32 reference_enable_mask;
422 /* Bit in CM_LOCK to indicate when the PLL has locked. */
423 u32 lock_mask;
424
425 const struct bcm2835_pll_ana_bits *ana;
426
427 unsigned long min_rate;
428 unsigned long max_rate;
429 /*
430 * Highest rate for the VCO before we have to use the
431 * pre-divide-by-2.
432 */
433 unsigned long max_fb_rate;
434};
435
436struct bcm2835_pll_ana_bits {
437 u32 mask0;
438 u32 set0;
439 u32 mask1;
440 u32 set1;
441 u32 mask3;
442 u32 set3;
443 u32 fb_prediv_mask;
444};
445
446static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
447 .mask0 = 0,
448 .set0 = 0,
449 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
450 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
451 .mask3 = A2W_PLL_KA_MASK,
452 .set3 = (2 << A2W_PLL_KA_SHIFT),
453 .fb_prediv_mask = BIT(14),
454};
455
456static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
457 .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,
458 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
459 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
460 .set1 = (6 << A2W_PLLH_KP_SHIFT),
461 .mask3 = 0,
462 .set3 = 0,
463 .fb_prediv_mask = BIT(11),
464};
465
466struct bcm2835_pll_divider_data {
467 const char *name;
468 const char *source_pll;
469
470 u32 cm_reg;
471 u32 a2w_reg;
472
473 u32 load_mask;
474 u32 hold_mask;
475 u32 fixed_divider;
476 u32 flags;
477};
478
479struct bcm2835_clock_data {
480 const char *name;
481
482 const char *const *parents;
483 int num_mux_parents;
484
485 /* Bitmap encoding which parents accept rate change propagation. */
486 unsigned int set_rate_parent;
487
488 u32 ctl_reg;
489 u32 div_reg;
490
491 /* Number of integer bits in the divider */
492 u32 int_bits;
493 /* Number of fractional bits in the divider */
494 u32 frac_bits;
495
496 u32 flags;
497
498 bool is_vpu_clock;
499 bool is_mash_clock;
500 bool low_jitter;
501
502 u32 tcnt_mux;
503};
504
505struct bcm2835_gate_data {
506 const char *name;
507 const char *parent;
508
509 u32 ctl_reg;
510};
511
512struct bcm2835_pll {
513 struct clk_hw hw;
514 struct bcm2835_cprman *cprman;
515 const struct bcm2835_pll_data *data;
516};
517
518static int bcm2835_pll_is_on(struct clk_hw *hw)
519{
520 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
521 struct bcm2835_cprman *cprman = pll->cprman;
522 const struct bcm2835_pll_data *data = pll->data;
523
524 return cprman_read(cprman, data->a2w_ctrl_reg) &
525 A2W_PLL_CTRL_PRST_DISABLE;
526}
527
528static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
529 unsigned long parent_rate,
530 u32 *ndiv, u32 *fdiv)
531{
532 u64 div;
533
534 div = (u64)rate << A2W_PLL_FRAC_BITS;
535 do_div(div, parent_rate);
536
537 *ndiv = div >> A2W_PLL_FRAC_BITS;
538 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
539}
540
541static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
542 u32 ndiv, u32 fdiv, u32 pdiv)
543{
544 u64 rate;
545
546 if (pdiv == 0)
547 return 0;
548
549 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
550 do_div(rate, pdiv);
551 return rate >> A2W_PLL_FRAC_BITS;
552}
553
554static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
555 unsigned long *parent_rate)
556{
557 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
558 const struct bcm2835_pll_data *data = pll->data;
559 u32 ndiv, fdiv;
560
561 rate = clamp(rate, data->min_rate, data->max_rate);
562
563 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
564
565 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
566}
567
568static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
569 unsigned long parent_rate)
570{
571 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
572 struct bcm2835_cprman *cprman = pll->cprman;
573 const struct bcm2835_pll_data *data = pll->data;
574 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
575 u32 ndiv, pdiv, fdiv;
576 bool using_prediv;
577
578 if (parent_rate == 0)
579 return 0;
580
581 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
582 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
583 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
584 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
585 data->ana->fb_prediv_mask;
586
587 if (using_prediv) {
588 ndiv *= 2;
589 fdiv *= 2;
590 }
591
592 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
593}
594
595static void bcm2835_pll_off(struct clk_hw *hw)
596{
597 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
598 struct bcm2835_cprman *cprman = pll->cprman;
599 const struct bcm2835_pll_data *data = pll->data;
600
601 spin_lock(&cprman->regs_lock);
602 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
603 cprman_write(cprman, data->a2w_ctrl_reg,
604 cprman_read(cprman, data->a2w_ctrl_reg) |
605 A2W_PLL_CTRL_PWRDN);
606 spin_unlock(&cprman->regs_lock);
607}
608
609static int bcm2835_pll_on(struct clk_hw *hw)
610{
611 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
612 struct bcm2835_cprman *cprman = pll->cprman;
613 const struct bcm2835_pll_data *data = pll->data;
614 ktime_t timeout;
615
616 cprman_write(cprman, data->a2w_ctrl_reg,
617 cprman_read(cprman, data->a2w_ctrl_reg) &
618 ~A2W_PLL_CTRL_PWRDN);
619
620 /* Take the PLL out of reset. */
621 spin_lock(&cprman->regs_lock);
622 cprman_write(cprman, data->cm_ctrl_reg,
623 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
624 spin_unlock(&cprman->regs_lock);
625
626 /* Wait for the PLL to lock. */
627 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
628 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
629 if (ktime_after(ktime_get(), timeout)) {
630 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
631 clk_hw_get_name(hw));
632 return -ETIMEDOUT;
633 }
634
635 cpu_relax();
636 }
637
638 cprman_write(cprman, data->a2w_ctrl_reg,
639 cprman_read(cprman, data->a2w_ctrl_reg) |
640 A2W_PLL_CTRL_PRST_DISABLE);
641
642 return 0;
643}
644
645static void
646bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
647{
648 int i;
649
650 /*
651 * ANA register setup is done as a series of writes to
652 * ANA3-ANA0, in that order. This lets us write all 4
653 * registers as a single cycle of the serdes interface (taking
654 * 100 xosc clocks), whereas if we were to update ana0, 1, and
655 * 3 individually through their partial-write registers, each
656 * would be their own serdes cycle.
657 */
658 for (i = 3; i >= 0; i--)
659 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
660}
661
662static int bcm2835_pll_set_rate(struct clk_hw *hw,
663 unsigned long rate, unsigned long parent_rate)
664{
665 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
666 struct bcm2835_cprman *cprman = pll->cprman;
667 const struct bcm2835_pll_data *data = pll->data;
668 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
669 u32 ndiv, fdiv, a2w_ctl;
670 u32 ana[4];
671 int i;
672
673 if (rate > data->max_fb_rate) {
674 use_fb_prediv = true;
675 rate /= 2;
676 } else {
677 use_fb_prediv = false;
678 }
679
680 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
681
682 for (i = 3; i >= 0; i--)
683 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
684
685 was_using_prediv = ana[1] & data->ana->fb_prediv_mask;
686
687 ana[0] &= ~data->ana->mask0;
688 ana[0] |= data->ana->set0;
689 ana[1] &= ~data->ana->mask1;
690 ana[1] |= data->ana->set1;
691 ana[3] &= ~data->ana->mask3;
692 ana[3] |= data->ana->set3;
693
694 if (was_using_prediv && !use_fb_prediv) {
695 ana[1] &= ~data->ana->fb_prediv_mask;
696 do_ana_setup_first = true;
697 } else if (!was_using_prediv && use_fb_prediv) {
698 ana[1] |= data->ana->fb_prediv_mask;
699 do_ana_setup_first = false;
700 } else {
701 do_ana_setup_first = true;
702 }
703
704 /* Unmask the reference clock from the oscillator. */
705 spin_lock(&cprman->regs_lock);
706 cprman_write(cprman, A2W_XOSC_CTRL,
707 cprman_read(cprman, A2W_XOSC_CTRL) |
708 data->reference_enable_mask);
709 spin_unlock(&cprman->regs_lock);
710
711 if (do_ana_setup_first)
712 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
713
714 /* Set the PLL multiplier from the oscillator. */
715 cprman_write(cprman, data->frac_reg, fdiv);
716
717 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
718 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
719 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
720 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
721 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
722 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
723
724 if (!do_ana_setup_first)
725 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
726
727 return 0;
728}
729
730static void bcm2835_pll_debug_init(struct clk_hw *hw,
731 struct dentry *dentry)
732{
733 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
734 struct bcm2835_cprman *cprman = pll->cprman;
735 const struct bcm2835_pll_data *data = pll->data;
736 struct debugfs_reg32 *regs;
737
738 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
739 if (!regs)
740 return;
741
742 regs[0].name = "cm_ctrl";
743 regs[0].offset = data->cm_ctrl_reg;
744 regs[1].name = "a2w_ctrl";
745 regs[1].offset = data->a2w_ctrl_reg;
746 regs[2].name = "frac";
747 regs[2].offset = data->frac_reg;
748 regs[3].name = "ana0";
749 regs[3].offset = data->ana_reg_base + 0 * 4;
750 regs[4].name = "ana1";
751 regs[4].offset = data->ana_reg_base + 1 * 4;
752 regs[5].name = "ana2";
753 regs[5].offset = data->ana_reg_base + 2 * 4;
754 regs[6].name = "ana3";
755 regs[6].offset = data->ana_reg_base + 3 * 4;
756
757 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
758}
759
760static const struct clk_ops bcm2835_pll_clk_ops = {
761 .is_prepared = bcm2835_pll_is_on,
762 .prepare = bcm2835_pll_on,
763 .unprepare = bcm2835_pll_off,
764 .recalc_rate = bcm2835_pll_get_rate,
765 .set_rate = bcm2835_pll_set_rate,
766 .round_rate = bcm2835_pll_round_rate,
767 .debug_init = bcm2835_pll_debug_init,
768};
769
770struct bcm2835_pll_divider {
771 struct clk_divider div;
772 struct bcm2835_cprman *cprman;
773 const struct bcm2835_pll_divider_data *data;
774};
775
776static struct bcm2835_pll_divider *
777bcm2835_pll_divider_from_hw(struct clk_hw *hw)
778{
779 return container_of(hw, struct bcm2835_pll_divider, div.hw);
780}
781
782static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
783{
784 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
785 struct bcm2835_cprman *cprman = divider->cprman;
786 const struct bcm2835_pll_divider_data *data = divider->data;
787
788 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
789}
790
791static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
792 unsigned long rate,
793 unsigned long *parent_rate)
794{
795 return clk_divider_ops.round_rate(hw, rate, parent_rate);
796}
797
798static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
799 unsigned long parent_rate)
800{
801 return clk_divider_ops.recalc_rate(hw, parent_rate);
802}
803
804static void bcm2835_pll_divider_off(struct clk_hw *hw)
805{
806 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
807 struct bcm2835_cprman *cprman = divider->cprman;
808 const struct bcm2835_pll_divider_data *data = divider->data;
809
810 spin_lock(&cprman->regs_lock);
811 cprman_write(cprman, data->cm_reg,
812 (cprman_read(cprman, data->cm_reg) &
813 ~data->load_mask) | data->hold_mask);
814 cprman_write(cprman, data->a2w_reg,
815 cprman_read(cprman, data->a2w_reg) |
816 A2W_PLL_CHANNEL_DISABLE);
817 spin_unlock(&cprman->regs_lock);
818}
819
820static int bcm2835_pll_divider_on(struct clk_hw *hw)
821{
822 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
823 struct bcm2835_cprman *cprman = divider->cprman;
824 const struct bcm2835_pll_divider_data *data = divider->data;
825
826 spin_lock(&cprman->regs_lock);
827 cprman_write(cprman, data->a2w_reg,
828 cprman_read(cprman, data->a2w_reg) &
829 ~A2W_PLL_CHANNEL_DISABLE);
830
831 cprman_write(cprman, data->cm_reg,
832 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
833 spin_unlock(&cprman->regs_lock);
834
835 return 0;
836}
837
838static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
839 unsigned long rate,
840 unsigned long parent_rate)
841{
842 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
843 struct bcm2835_cprman *cprman = divider->cprman;
844 const struct bcm2835_pll_divider_data *data = divider->data;
845 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
846
847 div = DIV_ROUND_UP_ULL(parent_rate, rate);
848
849 div = min(div, max_div);
850 if (div == max_div)
851 div = 0;
852
853 cprman_write(cprman, data->a2w_reg, div);
854 cm = cprman_read(cprman, data->cm_reg);
855 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
856 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
857
858 return 0;
859}
860
861static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
862 struct dentry *dentry)
863{
864 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
865 struct bcm2835_cprman *cprman = divider->cprman;
866 const struct bcm2835_pll_divider_data *data = divider->data;
867 struct debugfs_reg32 *regs;
868
869 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
870 if (!regs)
871 return;
872
873 regs[0].name = "cm";
874 regs[0].offset = data->cm_reg;
875 regs[1].name = "a2w";
876 regs[1].offset = data->a2w_reg;
877
878 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
879}
880
881static const struct clk_ops bcm2835_pll_divider_clk_ops = {
882 .is_prepared = bcm2835_pll_divider_is_on,
883 .prepare = bcm2835_pll_divider_on,
884 .unprepare = bcm2835_pll_divider_off,
885 .recalc_rate = bcm2835_pll_divider_get_rate,
886 .set_rate = bcm2835_pll_divider_set_rate,
887 .round_rate = bcm2835_pll_divider_round_rate,
888 .debug_init = bcm2835_pll_divider_debug_init,
889};
890
891/*
892 * The CM dividers do fixed-point division, so we can't use the
893 * generic integer divider code like the PLL dividers do (and we can't
894 * fake it by having some fixed shifts preceding it in the clock tree,
895 * because we'd run out of bits in a 32-bit unsigned long).
896 */
897struct bcm2835_clock {
898 struct clk_hw hw;
899 struct bcm2835_cprman *cprman;
900 const struct bcm2835_clock_data *data;
901};
902
903static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
904{
905 return container_of(hw, struct bcm2835_clock, hw);
906}
907
908static int bcm2835_clock_is_on(struct clk_hw *hw)
909{
910 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
911 struct bcm2835_cprman *cprman = clock->cprman;
912 const struct bcm2835_clock_data *data = clock->data;
913
914 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
915}
916
917static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
918 unsigned long rate,
919 unsigned long parent_rate,
920 bool round_up)
921{
922 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
923 const struct bcm2835_clock_data *data = clock->data;
924 u32 unused_frac_mask =
925 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
926 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
927 u64 rem;
928 u32 div, mindiv, maxdiv;
929
930 rem = do_div(temp, rate);
931 div = temp;
932
933 /* Round up and mask off the unused bits */
934 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0))
935 div += unused_frac_mask + 1;
936 div &= ~unused_frac_mask;
937
938 /* different clamping limits apply for a mash clock */
939 if (data->is_mash_clock) {
940 /* clamp to min divider of 2 */
941 mindiv = 2 << CM_DIV_FRAC_BITS;
942 /* clamp to the highest possible integer divider */
943 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
944 } else {
945 /* clamp to min divider of 1 */
946 mindiv = 1 << CM_DIV_FRAC_BITS;
947 /* clamp to the highest possible fractional divider */
948 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
949 CM_DIV_FRAC_BITS - data->frac_bits);
950 }
951
952 /* apply the clamping limits */
953 div = max_t(u32, div, mindiv);
954 div = min_t(u32, div, maxdiv);
955
956 return div;
957}
958
959static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
960 unsigned long parent_rate,
961 u32 div)
962{
963 const struct bcm2835_clock_data *data = clock->data;
964 u64 temp;
965
966 if (data->int_bits == 0 && data->frac_bits == 0)
967 return parent_rate;
968
969 /*
970 * The divisor is a 12.12 fixed point field, but only some of
971 * the bits are populated in any given clock.
972 */
973 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
974 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
975
976 if (div == 0)
977 return 0;
978
979 temp = (u64)parent_rate << data->frac_bits;
980
981 do_div(temp, div);
982
983 return temp;
984}
985
986static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
987 unsigned long parent_rate)
988{
989 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
990 struct bcm2835_cprman *cprman = clock->cprman;
991 const struct bcm2835_clock_data *data = clock->data;
992 u32 div;
993
994 if (data->int_bits == 0 && data->frac_bits == 0)
995 return parent_rate;
996
997 div = cprman_read(cprman, data->div_reg);
998
999 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1000}
1001
1002static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1003{
1004 struct bcm2835_cprman *cprman = clock->cprman;
1005 const struct bcm2835_clock_data *data = clock->data;
1006 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1007
1008 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1009 if (ktime_after(ktime_get(), timeout)) {
1010 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1011 clk_hw_get_name(&clock->hw));
1012 return;
1013 }
1014 cpu_relax();
1015 }
1016}
1017
1018static void bcm2835_clock_off(struct clk_hw *hw)
1019{
1020 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1021 struct bcm2835_cprman *cprman = clock->cprman;
1022 const struct bcm2835_clock_data *data = clock->data;
1023
1024 spin_lock(&cprman->regs_lock);
1025 cprman_write(cprman, data->ctl_reg,
1026 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1027 spin_unlock(&cprman->regs_lock);
1028
1029 /* BUSY will remain high until the divider completes its cycle. */
1030 bcm2835_clock_wait_busy(clock);
1031}
1032
1033static int bcm2835_clock_on(struct clk_hw *hw)
1034{
1035 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1036 struct bcm2835_cprman *cprman = clock->cprman;
1037 const struct bcm2835_clock_data *data = clock->data;
1038
1039 spin_lock(&cprman->regs_lock);
1040 cprman_write(cprman, data->ctl_reg,
1041 cprman_read(cprman, data->ctl_reg) |
1042 CM_ENABLE |
1043 CM_GATE);
1044 spin_unlock(&cprman->regs_lock);
1045
1046 /* Debug code to measure the clock once it's turned on to see
1047 * if it's ticking at the rate we expect.
1048 */
1049 if (data->tcnt_mux && false) {
1050 dev_info(cprman->dev,
1051 "clk %s: rate %ld, measure %ld\n",
1052 data->name,
1053 clk_hw_get_rate(hw),
1054 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
1055 }
1056
1057 return 0;
1058}
1059
1060static int bcm2835_clock_set_rate(struct clk_hw *hw,
1061 unsigned long rate, unsigned long parent_rate)
1062{
1063 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1064 struct bcm2835_cprman *cprman = clock->cprman;
1065 const struct bcm2835_clock_data *data = clock->data;
1066 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
1067 u32 ctl;
1068
1069 spin_lock(&cprman->regs_lock);
1070
1071 /*
1072 * Setting up frac support
1073 *
1074 * In principle it is recommended to stop/start the clock first,
1075 * but as we set CLK_SET_RATE_GATE during registration of the
1076 * clock this requirement should be take care of by the
1077 * clk-framework.
1078 */
1079 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
1080 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
1081 cprman_write(cprman, data->ctl_reg, ctl);
1082
1083 cprman_write(cprman, data->div_reg, div);
1084
1085 spin_unlock(&cprman->regs_lock);
1086
1087 return 0;
1088}
1089
1090static bool
1091bcm2835_clk_is_pllc(struct clk_hw *hw)
1092{
1093 if (!hw)
1094 return false;
1095
1096 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
1097}
1098
1099static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
1100 int parent_idx,
1101 unsigned long rate,
1102 u32 *div,
1103 unsigned long *prate,
1104 unsigned long *avgrate)
1105{
1106 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1107 struct bcm2835_cprman *cprman = clock->cprman;
1108 const struct bcm2835_clock_data *data = clock->data;
1109 unsigned long best_rate = 0;
1110 u32 curdiv, mindiv, maxdiv;
1111 struct clk_hw *parent;
1112
1113 parent = clk_hw_get_parent_by_index(hw, parent_idx);
1114
1115 if (!(BIT(parent_idx) & data->set_rate_parent)) {
1116 *prate = clk_hw_get_rate(parent);
1117 *div = bcm2835_clock_choose_div(hw, rate, *prate, true);
1118
1119 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1120
1121 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
1122 unsigned long high, low;
1123 u32 int_div = *div & ~CM_DIV_FRAC_MASK;
1124
1125 high = bcm2835_clock_rate_from_divisor(clock, *prate,
1126 int_div);
1127 int_div += CM_DIV_FRAC_MASK + 1;
1128 low = bcm2835_clock_rate_from_divisor(clock, *prate,
1129 int_div);
1130
1131 /*
1132 * Return a value which is the maximum deviation
1133 * below the ideal rate, for use as a metric.
1134 */
1135 return *avgrate - max(*avgrate - low, high - *avgrate);
1136 }
1137 return *avgrate;
1138 }
1139
1140 if (data->frac_bits)
1141 dev_warn(cprman->dev,
1142 "frac bits are not used when propagating rate change");
1143
1144 /* clamp to min divider of 2 if we're dealing with a mash clock */
1145 mindiv = data->is_mash_clock ? 2 : 1;
1146 maxdiv = BIT(data->int_bits) - 1;
1147
1148 /* TODO: Be smart, and only test a subset of the available divisors. */
1149 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
1150 unsigned long tmp_rate;
1151
1152 tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
1153 tmp_rate /= curdiv;
1154 if (curdiv == mindiv ||
1155 (tmp_rate > best_rate && tmp_rate <= rate))
1156 best_rate = tmp_rate;
1157
1158 if (best_rate == rate)
1159 break;
1160 }
1161
1162 *div = curdiv << CM_DIV_FRAC_BITS;
1163 *prate = curdiv * best_rate;
1164 *avgrate = best_rate;
1165
1166 return best_rate;
1167}
1168
1169static int bcm2835_clock_determine_rate(struct clk_hw *hw,
1170 struct clk_rate_request *req)
1171{
1172 struct clk_hw *parent, *best_parent = NULL;
1173 bool current_parent_is_pllc;
1174 unsigned long rate, best_rate = 0;
1175 unsigned long prate, best_prate = 0;
1176 unsigned long avgrate, best_avgrate = 0;
1177 size_t i;
1178 u32 div;
1179
1180 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
1181
1182 /*
1183 * Select parent clock that results in the closest but lower rate
1184 */
1185 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
1186 parent = clk_hw_get_parent_by_index(hw, i);
1187 if (!parent)
1188 continue;
1189
1190 /*
1191 * Don't choose a PLLC-derived clock as our parent
1192 * unless it had been manually set that way. PLLC's
1193 * frequency gets adjusted by the firmware due to
1194 * over-temp or under-voltage conditions, without
1195 * prior notification to our clock consumer.
1196 */
1197 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
1198 continue;
1199
1200 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
1201 &div, &prate,
1202 &avgrate);
1203 if (rate > best_rate && rate <= req->rate) {
1204 best_parent = parent;
1205 best_prate = prate;
1206 best_rate = rate;
1207 best_avgrate = avgrate;
1208 }
1209 }
1210
1211 if (!best_parent)
1212 return -EINVAL;
1213
1214 req->best_parent_hw = best_parent;
1215 req->best_parent_rate = best_prate;
1216
1217 req->rate = best_avgrate;
1218
1219 return 0;
1220}
1221
1222static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
1223{
1224 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1225 struct bcm2835_cprman *cprman = clock->cprman;
1226 const struct bcm2835_clock_data *data = clock->data;
1227 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
1228
1229 cprman_write(cprman, data->ctl_reg, src);
1230 return 0;
1231}
1232
1233static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1234{
1235 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1236 struct bcm2835_cprman *cprman = clock->cprman;
1237 const struct bcm2835_clock_data *data = clock->data;
1238 u32 src = cprman_read(cprman, data->ctl_reg);
1239
1240 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1241}
1242
1243static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1244 {
1245 .name = "ctl",
1246 .offset = 0,
1247 },
1248 {
1249 .name = "div",
1250 .offset = 4,
1251 },
1252};
1253
1254static void bcm2835_clock_debug_init(struct clk_hw *hw,
1255 struct dentry *dentry)
1256{
1257 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1258 struct bcm2835_cprman *cprman = clock->cprman;
1259 const struct bcm2835_clock_data *data = clock->data;
1260
1261 bcm2835_debugfs_regset(cprman, data->ctl_reg,
1262 bcm2835_debugfs_clock_reg32,
1263 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1264 dentry);
1265}
1266
1267static const struct clk_ops bcm2835_clock_clk_ops = {
1268 .is_prepared = bcm2835_clock_is_on,
1269 .prepare = bcm2835_clock_on,
1270 .unprepare = bcm2835_clock_off,
1271 .recalc_rate = bcm2835_clock_get_rate,
1272 .set_rate = bcm2835_clock_set_rate,
1273 .determine_rate = bcm2835_clock_determine_rate,
1274 .set_parent = bcm2835_clock_set_parent,
1275 .get_parent = bcm2835_clock_get_parent,
1276 .debug_init = bcm2835_clock_debug_init,
1277};
1278
1279static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1280{
1281 return true;
1282}
1283
1284/*
1285 * The VPU clock can never be disabled (it doesn't have an ENABLE
1286 * bit), so it gets its own set of clock ops.
1287 */
1288static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1289 .is_prepared = bcm2835_vpu_clock_is_on,
1290 .recalc_rate = bcm2835_clock_get_rate,
1291 .set_rate = bcm2835_clock_set_rate,
1292 .determine_rate = bcm2835_clock_determine_rate,
1293 .set_parent = bcm2835_clock_set_parent,
1294 .get_parent = bcm2835_clock_get_parent,
1295 .debug_init = bcm2835_clock_debug_init,
1296};
1297
1298static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1299 const struct bcm2835_pll_data *data)
1300{
1301 struct bcm2835_pll *pll;
1302 struct clk_init_data init;
1303 int ret;
1304
1305 memset(&init, 0, sizeof(init));
1306
1307 /* All of the PLLs derive from the external oscillator. */
1308 init.parent_names = &cprman->real_parent_names[0];
1309 init.num_parents = 1;
1310 init.name = data->name;
1311 init.ops = &bcm2835_pll_clk_ops;
1312 init.flags = CLK_IGNORE_UNUSED;
1313
1314 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1315 if (!pll)
1316 return NULL;
1317
1318 pll->cprman = cprman;
1319 pll->data = data;
1320 pll->hw.init = &init;
1321
1322 ret = devm_clk_hw_register(cprman->dev, &pll->hw);
1323 if (ret)
1324 return NULL;
1325 return &pll->hw;
1326}
1327
1328static struct clk_hw *
1329bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1330 const struct bcm2835_pll_divider_data *data)
1331{
1332 struct bcm2835_pll_divider *divider;
1333 struct clk_init_data init;
1334 const char *divider_name;
1335 int ret;
1336
1337 if (data->fixed_divider != 1) {
1338 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1339 "%s_prediv", data->name);
1340 if (!divider_name)
1341 return NULL;
1342 } else {
1343 divider_name = data->name;
1344 }
1345
1346 memset(&init, 0, sizeof(init));
1347
1348 init.parent_names = &data->source_pll;
1349 init.num_parents = 1;
1350 init.name = divider_name;
1351 init.ops = &bcm2835_pll_divider_clk_ops;
1352 init.flags = data->flags | CLK_IGNORE_UNUSED;
1353
1354 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1355 if (!divider)
1356 return NULL;
1357
1358 divider->div.reg = cprman->regs + data->a2w_reg;
1359 divider->div.shift = A2W_PLL_DIV_SHIFT;
1360 divider->div.width = A2W_PLL_DIV_BITS;
1361 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
1362 divider->div.lock = &cprman->regs_lock;
1363 divider->div.hw.init = &init;
1364 divider->div.table = NULL;
1365
1366 divider->cprman = cprman;
1367 divider->data = data;
1368
1369 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw);
1370 if (ret)
1371 return ERR_PTR(ret);
1372
1373 /*
1374 * PLLH's channels have a fixed divide by 10 afterwards, which
1375 * is what our consumers are actually using.
1376 */
1377 if (data->fixed_divider != 1) {
1378 return clk_hw_register_fixed_factor(cprman->dev, data->name,
1379 divider_name,
1380 CLK_SET_RATE_PARENT,
1381 1,
1382 data->fixed_divider);
1383 }
1384
1385 return ÷r->div.hw;
1386}
1387
1388static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1389 const struct bcm2835_clock_data *data)
1390{
1391 struct bcm2835_clock *clock;
1392 struct clk_init_data init;
1393 const char *parents[1 << CM_SRC_BITS];
1394 size_t i;
1395 int ret;
1396
1397 /*
1398 * Replace our strings referencing parent clocks with the
1399 * actual clock-output-name of the parent.
1400 */
1401 for (i = 0; i < data->num_mux_parents; i++) {
1402 parents[i] = data->parents[i];
1403
1404 ret = match_string(cprman_parent_names,
1405 ARRAY_SIZE(cprman_parent_names),
1406 parents[i]);
1407 if (ret >= 0)
1408 parents[i] = cprman->real_parent_names[ret];
1409 }
1410
1411 memset(&init, 0, sizeof(init));
1412 init.parent_names = parents;
1413 init.num_parents = data->num_mux_parents;
1414 init.name = data->name;
1415 init.flags = data->flags | CLK_IGNORE_UNUSED;
1416
1417 /*
1418 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
1419 * rate changes on at least of the parents.
1420 */
1421 if (data->set_rate_parent)
1422 init.flags |= CLK_SET_RATE_PARENT;
1423
1424 if (data->is_vpu_clock) {
1425 init.ops = &bcm2835_vpu_clock_clk_ops;
1426 } else {
1427 init.ops = &bcm2835_clock_clk_ops;
1428 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1429
1430 /* If the clock wasn't actually enabled at boot, it's not
1431 * critical.
1432 */
1433 if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE))
1434 init.flags &= ~CLK_IS_CRITICAL;
1435 }
1436
1437 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1438 if (!clock)
1439 return NULL;
1440
1441 clock->cprman = cprman;
1442 clock->data = data;
1443 clock->hw.init = &init;
1444
1445 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1446 if (ret)
1447 return ERR_PTR(ret);
1448 return &clock->hw;
1449}
1450
1451static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1452 const struct bcm2835_gate_data *data)
1453{
1454 return clk_register_gate(cprman->dev, data->name, data->parent,
1455 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1456 cprman->regs + data->ctl_reg,
1457 CM_GATE_BIT, 0, &cprman->regs_lock);
1458}
1459
1460typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
1461 const void *data);
1462struct bcm2835_clk_desc {
1463 bcm2835_clk_register clk_register;
1464 unsigned int supported;
1465 const void *data;
1466};
1467
1468/* assignment helper macros for different clock types */
1469#define _REGISTER(f, s, ...) { .clk_register = (bcm2835_clk_register)f, \
1470 .supported = s, \
1471 .data = __VA_ARGS__ }
1472#define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \
1473 s, \
1474 &(struct bcm2835_pll_data) \
1475 {__VA_ARGS__})
1476#define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
1477 s, \
1478 &(struct bcm2835_pll_divider_data) \
1479 {__VA_ARGS__})
1480#define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \
1481 s, \
1482 &(struct bcm2835_clock_data) \
1483 {__VA_ARGS__})
1484#define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \
1485 s, \
1486 &(struct bcm2835_gate_data) \
1487 {__VA_ARGS__})
1488
1489/* parent mux arrays plus helper macros */
1490
1491/* main oscillator parent mux */
1492static const char *const bcm2835_clock_osc_parents[] = {
1493 "gnd",
1494 "xosc",
1495 "testdebug0",
1496 "testdebug1"
1497};
1498
1499#define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \
1500 s, \
1501 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1502 .parents = bcm2835_clock_osc_parents, \
1503 __VA_ARGS__)
1504
1505/* main peripherial parent mux */
1506static const char *const bcm2835_clock_per_parents[] = {
1507 "gnd",
1508 "xosc",
1509 "testdebug0",
1510 "testdebug1",
1511 "plla_per",
1512 "pllc_per",
1513 "plld_per",
1514 "pllh_aux",
1515};
1516
1517#define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \
1518 s, \
1519 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1520 .parents = bcm2835_clock_per_parents, \
1521 __VA_ARGS__)
1522
1523/*
1524 * Restrict clock sources for the PCM peripheral to the oscillator and
1525 * PLLD_PER because other source may have varying rates or be switched
1526 * off.
1527 *
1528 * Prevent other sources from being selected by replacing their names in
1529 * the list of potential parents with dummy entries (entry index is
1530 * significant).
1531 */
1532static const char *const bcm2835_pcm_per_parents[] = {
1533 "-",
1534 "xosc",
1535 "-",
1536 "-",
1537 "-",
1538 "-",
1539 "plld_per",
1540 "-",
1541};
1542
1543#define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \
1544 s, \
1545 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
1546 .parents = bcm2835_pcm_per_parents, \
1547 __VA_ARGS__)
1548
1549/* main vpu parent mux */
1550static const char *const bcm2835_clock_vpu_parents[] = {
1551 "gnd",
1552 "xosc",
1553 "testdebug0",
1554 "testdebug1",
1555 "plla_core",
1556 "pllc_core0",
1557 "plld_core",
1558 "pllh_aux",
1559 "pllc_core1",
1560 "pllc_core2",
1561};
1562
1563#define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \
1564 s, \
1565 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1566 .parents = bcm2835_clock_vpu_parents, \
1567 __VA_ARGS__)
1568
1569/*
1570 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI
1571 * analog PHY. The _inv variants are generated internally to cprman,
1572 * but we don't use them so they aren't hooked up.
1573 */
1574static const char *const bcm2835_clock_dsi0_parents[] = {
1575 "gnd",
1576 "xosc",
1577 "testdebug0",
1578 "testdebug1",
1579 "dsi0_ddr",
1580 "dsi0_ddr_inv",
1581 "dsi0_ddr2",
1582 "dsi0_ddr2_inv",
1583 "dsi0_byte",
1584 "dsi0_byte_inv",
1585};
1586
1587static const char *const bcm2835_clock_dsi1_parents[] = {
1588 "gnd",
1589 "xosc",
1590 "testdebug0",
1591 "testdebug1",
1592 "dsi1_ddr",
1593 "dsi1_ddr_inv",
1594 "dsi1_ddr2",
1595 "dsi1_ddr2_inv",
1596 "dsi1_byte",
1597 "dsi1_byte_inv",
1598};
1599
1600#define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \
1601 s, \
1602 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
1603 .parents = bcm2835_clock_dsi0_parents, \
1604 __VA_ARGS__)
1605
1606#define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \
1607 s, \
1608 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
1609 .parents = bcm2835_clock_dsi1_parents, \
1610 __VA_ARGS__)
1611
1612/*
1613 * the real definition of all the pll, pll_dividers and clocks
1614 * these make use of the above REGISTER_* macros
1615 */
1616static const struct bcm2835_clk_desc clk_desc_array[] = {
1617 /* the PLL + PLL dividers */
1618
1619 /*
1620 * PLLA is the auxiliary PLL, used to drive the CCP2
1621 * (Compact Camera Port 2) transmitter clock.
1622 *
1623 * It is in the PX LDO power domain, which is on when the
1624 * AUDIO domain is on.
1625 */
1626 [BCM2835_PLLA] = REGISTER_PLL(
1627 SOC_ALL,
1628 .name = "plla",
1629 .cm_ctrl_reg = CM_PLLA,
1630 .a2w_ctrl_reg = A2W_PLLA_CTRL,
1631 .frac_reg = A2W_PLLA_FRAC,
1632 .ana_reg_base = A2W_PLLA_ANA0,
1633 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
1634 .lock_mask = CM_LOCK_FLOCKA,
1635
1636 .ana = &bcm2835_ana_default,
1637
1638 .min_rate = 600000000u,
1639 .max_rate = 2400000000u,
1640 .max_fb_rate = BCM2835_MAX_FB_RATE),
1641 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
1642 SOC_ALL,
1643 .name = "plla_core",
1644 .source_pll = "plla",
1645 .cm_reg = CM_PLLA,
1646 .a2w_reg = A2W_PLLA_CORE,
1647 .load_mask = CM_PLLA_LOADCORE,
1648 .hold_mask = CM_PLLA_HOLDCORE,
1649 .fixed_divider = 1,
1650 .flags = CLK_SET_RATE_PARENT),
1651 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1652 SOC_ALL,
1653 .name = "plla_per",
1654 .source_pll = "plla",
1655 .cm_reg = CM_PLLA,
1656 .a2w_reg = A2W_PLLA_PER,
1657 .load_mask = CM_PLLA_LOADPER,
1658 .hold_mask = CM_PLLA_HOLDPER,
1659 .fixed_divider = 1,
1660 .flags = CLK_SET_RATE_PARENT),
1661 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
1662 SOC_ALL,
1663 .name = "plla_dsi0",
1664 .source_pll = "plla",
1665 .cm_reg = CM_PLLA,
1666 .a2w_reg = A2W_PLLA_DSI0,
1667 .load_mask = CM_PLLA_LOADDSI0,
1668 .hold_mask = CM_PLLA_HOLDDSI0,
1669 .fixed_divider = 1),
1670 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
1671 SOC_ALL,
1672 .name = "plla_ccp2",
1673 .source_pll = "plla",
1674 .cm_reg = CM_PLLA,
1675 .a2w_reg = A2W_PLLA_CCP2,
1676 .load_mask = CM_PLLA_LOADCCP2,
1677 .hold_mask = CM_PLLA_HOLDCCP2,
1678 .fixed_divider = 1,
1679 .flags = CLK_SET_RATE_PARENT),
1680
1681 /*
1682 * PLLB is used for the ARM's clock. Controlled by firmware, see
1683 * clk-raspberrypi.c.
1684 */
1685
1686 /*
1687 * PLLC is the core PLL, used to drive the core VPU clock.
1688 *
1689 * It is in the PX LDO power domain, which is on when the
1690 * AUDIO domain is on.
1691 */
1692 [BCM2835_PLLC] = REGISTER_PLL(
1693 SOC_ALL,
1694 .name = "pllc",
1695 .cm_ctrl_reg = CM_PLLC,
1696 .a2w_ctrl_reg = A2W_PLLC_CTRL,
1697 .frac_reg = A2W_PLLC_FRAC,
1698 .ana_reg_base = A2W_PLLC_ANA0,
1699 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1700 .lock_mask = CM_LOCK_FLOCKC,
1701
1702 .ana = &bcm2835_ana_default,
1703
1704 .min_rate = 600000000u,
1705 .max_rate = 3000000000u,
1706 .max_fb_rate = BCM2835_MAX_FB_RATE),
1707 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
1708 SOC_ALL,
1709 .name = "pllc_core0",
1710 .source_pll = "pllc",
1711 .cm_reg = CM_PLLC,
1712 .a2w_reg = A2W_PLLC_CORE0,
1713 .load_mask = CM_PLLC_LOADCORE0,
1714 .hold_mask = CM_PLLC_HOLDCORE0,
1715 .fixed_divider = 1,
1716 .flags = CLK_SET_RATE_PARENT),
1717 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
1718 SOC_ALL,
1719 .name = "pllc_core1",
1720 .source_pll = "pllc",
1721 .cm_reg = CM_PLLC,
1722 .a2w_reg = A2W_PLLC_CORE1,
1723 .load_mask = CM_PLLC_LOADCORE1,
1724 .hold_mask = CM_PLLC_HOLDCORE1,
1725 .fixed_divider = 1,
1726 .flags = CLK_SET_RATE_PARENT),
1727 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
1728 SOC_ALL,
1729 .name = "pllc_core2",
1730 .source_pll = "pllc",
1731 .cm_reg = CM_PLLC,
1732 .a2w_reg = A2W_PLLC_CORE2,
1733 .load_mask = CM_PLLC_LOADCORE2,
1734 .hold_mask = CM_PLLC_HOLDCORE2,
1735 .fixed_divider = 1,
1736 .flags = CLK_SET_RATE_PARENT),
1737 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
1738 SOC_ALL,
1739 .name = "pllc_per",
1740 .source_pll = "pllc",
1741 .cm_reg = CM_PLLC,
1742 .a2w_reg = A2W_PLLC_PER,
1743 .load_mask = CM_PLLC_LOADPER,
1744 .hold_mask = CM_PLLC_HOLDPER,
1745 .fixed_divider = 1,
1746 .flags = CLK_SET_RATE_PARENT),
1747
1748 /*
1749 * PLLD is the display PLL, used to drive DSI display panels.
1750 *
1751 * It is in the PX LDO power domain, which is on when the
1752 * AUDIO domain is on.
1753 */
1754 [BCM2835_PLLD] = REGISTER_PLL(
1755 SOC_ALL,
1756 .name = "plld",
1757 .cm_ctrl_reg = CM_PLLD,
1758 .a2w_ctrl_reg = A2W_PLLD_CTRL,
1759 .frac_reg = A2W_PLLD_FRAC,
1760 .ana_reg_base = A2W_PLLD_ANA0,
1761 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
1762 .lock_mask = CM_LOCK_FLOCKD,
1763
1764 .ana = &bcm2835_ana_default,
1765
1766 .min_rate = 600000000u,
1767 .max_rate = 2400000000u,
1768 .max_fb_rate = BCM2835_MAX_FB_RATE),
1769 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
1770 SOC_ALL,
1771 .name = "plld_core",
1772 .source_pll = "plld",
1773 .cm_reg = CM_PLLD,
1774 .a2w_reg = A2W_PLLD_CORE,
1775 .load_mask = CM_PLLD_LOADCORE,
1776 .hold_mask = CM_PLLD_HOLDCORE,
1777 .fixed_divider = 1,
1778 .flags = CLK_SET_RATE_PARENT),
1779 /*
1780 * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core.
1781 * Otherwise this could cause firmware lookups. That's why we mark
1782 * it as critical.
1783 */
1784 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
1785 SOC_ALL,
1786 .name = "plld_per",
1787 .source_pll = "plld",
1788 .cm_reg = CM_PLLD,
1789 .a2w_reg = A2W_PLLD_PER,
1790 .load_mask = CM_PLLD_LOADPER,
1791 .hold_mask = CM_PLLD_HOLDPER,
1792 .fixed_divider = 1,
1793 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1794 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
1795 SOC_ALL,
1796 .name = "plld_dsi0",
1797 .source_pll = "plld",
1798 .cm_reg = CM_PLLD,
1799 .a2w_reg = A2W_PLLD_DSI0,
1800 .load_mask = CM_PLLD_LOADDSI0,
1801 .hold_mask = CM_PLLD_HOLDDSI0,
1802 .fixed_divider = 1),
1803 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
1804 SOC_ALL,
1805 .name = "plld_dsi1",
1806 .source_pll = "plld",
1807 .cm_reg = CM_PLLD,
1808 .a2w_reg = A2W_PLLD_DSI1,
1809 .load_mask = CM_PLLD_LOADDSI1,
1810 .hold_mask = CM_PLLD_HOLDDSI1,
1811 .fixed_divider = 1),
1812
1813 /*
1814 * PLLH is used to supply the pixel clock or the AUX clock for the
1815 * TV encoder.
1816 *
1817 * It is in the HDMI power domain.
1818 */
1819 [BCM2835_PLLH] = REGISTER_PLL(
1820 SOC_BCM2835,
1821 "pllh",
1822 .cm_ctrl_reg = CM_PLLH,
1823 .a2w_ctrl_reg = A2W_PLLH_CTRL,
1824 .frac_reg = A2W_PLLH_FRAC,
1825 .ana_reg_base = A2W_PLLH_ANA0,
1826 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1827 .lock_mask = CM_LOCK_FLOCKH,
1828
1829 .ana = &bcm2835_ana_pllh,
1830
1831 .min_rate = 600000000u,
1832 .max_rate = 3000000000u,
1833 .max_fb_rate = BCM2835_MAX_FB_RATE),
1834 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
1835 SOC_BCM2835,
1836 .name = "pllh_rcal",
1837 .source_pll = "pllh",
1838 .cm_reg = CM_PLLH,
1839 .a2w_reg = A2W_PLLH_RCAL,
1840 .load_mask = CM_PLLH_LOADRCAL,
1841 .hold_mask = 0,
1842 .fixed_divider = 10,
1843 .flags = CLK_SET_RATE_PARENT),
1844 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
1845 SOC_BCM2835,
1846 .name = "pllh_aux",
1847 .source_pll = "pllh",
1848 .cm_reg = CM_PLLH,
1849 .a2w_reg = A2W_PLLH_AUX,
1850 .load_mask = CM_PLLH_LOADAUX,
1851 .hold_mask = 0,
1852 .fixed_divider = 1,
1853 .flags = CLK_SET_RATE_PARENT),
1854 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
1855 SOC_BCM2835,
1856 .name = "pllh_pix",
1857 .source_pll = "pllh",
1858 .cm_reg = CM_PLLH,
1859 .a2w_reg = A2W_PLLH_PIX,
1860 .load_mask = CM_PLLH_LOADPIX,
1861 .hold_mask = 0,
1862 .fixed_divider = 10,
1863 .flags = CLK_SET_RATE_PARENT),
1864
1865 /* the clocks */
1866
1867 /* clocks with oscillator parent mux */
1868
1869 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1870 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
1871 SOC_ALL,
1872 .name = "otp",
1873 .ctl_reg = CM_OTPCTL,
1874 .div_reg = CM_OTPDIV,
1875 .int_bits = 4,
1876 .frac_bits = 0,
1877 .tcnt_mux = 6),
1878 /*
1879 * Used for a 1Mhz clock for the system clocksource, and also used
1880 * bythe watchdog timer and the camera pulse generator.
1881 */
1882 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
1883 SOC_ALL,
1884 .name = "timer",
1885 .ctl_reg = CM_TIMERCTL,
1886 .div_reg = CM_TIMERDIV,
1887 .int_bits = 6,
1888 .frac_bits = 12),
1889 /*
1890 * Clock for the temperature sensor.
1891 * Generally run at 2Mhz, max 5Mhz.
1892 */
1893 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
1894 SOC_ALL,
1895 .name = "tsens",
1896 .ctl_reg = CM_TSENSCTL,
1897 .div_reg = CM_TSENSDIV,
1898 .int_bits = 5,
1899 .frac_bits = 0),
1900 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
1901 SOC_ALL,
1902 .name = "tec",
1903 .ctl_reg = CM_TECCTL,
1904 .div_reg = CM_TECDIV,
1905 .int_bits = 6,
1906 .frac_bits = 0),
1907
1908 /* clocks with vpu parent mux */
1909 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
1910 SOC_ALL,
1911 .name = "h264",
1912 .ctl_reg = CM_H264CTL,
1913 .div_reg = CM_H264DIV,
1914 .int_bits = 4,
1915 .frac_bits = 8,
1916 .tcnt_mux = 1),
1917 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
1918 SOC_ALL,
1919 .name = "isp",
1920 .ctl_reg = CM_ISPCTL,
1921 .div_reg = CM_ISPDIV,
1922 .int_bits = 4,
1923 .frac_bits = 8,
1924 .tcnt_mux = 2),
1925
1926 /*
1927 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1928 * in the SDRAM controller can't be used.
1929 */
1930 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
1931 SOC_ALL,
1932 .name = "sdram",
1933 .ctl_reg = CM_SDCCTL,
1934 .div_reg = CM_SDCDIV,
1935 .int_bits = 6,
1936 .frac_bits = 0,
1937 .tcnt_mux = 3),
1938 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
1939 SOC_ALL,
1940 .name = "v3d",
1941 .ctl_reg = CM_V3DCTL,
1942 .div_reg = CM_V3DDIV,
1943 .int_bits = 4,
1944 .frac_bits = 8,
1945 .tcnt_mux = 4),
1946 /*
1947 * VPU clock. This doesn't have an enable bit, since it drives
1948 * the bus for everything else, and is special so it doesn't need
1949 * to be gated for rate changes. It is also known as "clk_audio"
1950 * in various hardware documentation.
1951 */
1952 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
1953 SOC_ALL,
1954 .name = "vpu",
1955 .ctl_reg = CM_VPUCTL,
1956 .div_reg = CM_VPUDIV,
1957 .int_bits = 12,
1958 .frac_bits = 8,
1959 .flags = CLK_IS_CRITICAL,
1960 .is_vpu_clock = true,
1961 .tcnt_mux = 5),
1962
1963 /* clocks with per parent mux */
1964 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
1965 SOC_ALL,
1966 .name = "aveo",
1967 .ctl_reg = CM_AVEOCTL,
1968 .div_reg = CM_AVEODIV,
1969 .int_bits = 4,
1970 .frac_bits = 0,
1971 .tcnt_mux = 38),
1972 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
1973 SOC_ALL,
1974 .name = "cam0",
1975 .ctl_reg = CM_CAM0CTL,
1976 .div_reg = CM_CAM0DIV,
1977 .int_bits = 4,
1978 .frac_bits = 8,
1979 .tcnt_mux = 14),
1980 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
1981 SOC_ALL,
1982 .name = "cam1",
1983 .ctl_reg = CM_CAM1CTL,
1984 .div_reg = CM_CAM1DIV,
1985 .int_bits = 4,
1986 .frac_bits = 8,
1987 .tcnt_mux = 15),
1988 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
1989 SOC_ALL,
1990 .name = "dft",
1991 .ctl_reg = CM_DFTCTL,
1992 .div_reg = CM_DFTDIV,
1993 .int_bits = 5,
1994 .frac_bits = 0),
1995 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
1996 SOC_ALL,
1997 .name = "dpi",
1998 .ctl_reg = CM_DPICTL,
1999 .div_reg = CM_DPIDIV,
2000 .int_bits = 4,
2001 .frac_bits = 8,
2002 .tcnt_mux = 17),
2003
2004 /* Arasan EMMC clock */
2005 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
2006 SOC_ALL,
2007 .name = "emmc",
2008 .ctl_reg = CM_EMMCCTL,
2009 .div_reg = CM_EMMCDIV,
2010 .int_bits = 4,
2011 .frac_bits = 8,
2012 .tcnt_mux = 39),
2013
2014 /* EMMC2 clock (only available for BCM2711) */
2015 [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
2016 SOC_BCM2711,
2017 .name = "emmc2",
2018 .ctl_reg = CM_EMMC2CTL,
2019 .div_reg = CM_EMMC2DIV,
2020 .int_bits = 4,
2021 .frac_bits = 8,
2022 .tcnt_mux = 42),
2023
2024 /* General purpose (GPIO) clocks */
2025 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
2026 SOC_ALL,
2027 .name = "gp0",
2028 .ctl_reg = CM_GP0CTL,
2029 .div_reg = CM_GP0DIV,
2030 .int_bits = 12,
2031 .frac_bits = 12,
2032 .is_mash_clock = true,
2033 .tcnt_mux = 20),
2034 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
2035 SOC_ALL,
2036 .name = "gp1",
2037 .ctl_reg = CM_GP1CTL,
2038 .div_reg = CM_GP1DIV,
2039 .int_bits = 12,
2040 .frac_bits = 12,
2041 .flags = CLK_IS_CRITICAL,
2042 .is_mash_clock = true,
2043 .tcnt_mux = 21),
2044 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
2045 SOC_ALL,
2046 .name = "gp2",
2047 .ctl_reg = CM_GP2CTL,
2048 .div_reg = CM_GP2DIV,
2049 .int_bits = 12,
2050 .frac_bits = 12,
2051 .flags = CLK_IS_CRITICAL),
2052
2053 /* HDMI state machine */
2054 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
2055 SOC_ALL,
2056 .name = "hsm",
2057 .ctl_reg = CM_HSMCTL,
2058 .div_reg = CM_HSMDIV,
2059 .int_bits = 4,
2060 .frac_bits = 8,
2061 .tcnt_mux = 22),
2062 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
2063 SOC_ALL,
2064 .name = "pcm",
2065 .ctl_reg = CM_PCMCTL,
2066 .div_reg = CM_PCMDIV,
2067 .int_bits = 12,
2068 .frac_bits = 12,
2069 .is_mash_clock = true,
2070 .low_jitter = true,
2071 .tcnt_mux = 23),
2072 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
2073 SOC_ALL,
2074 .name = "pwm",
2075 .ctl_reg = CM_PWMCTL,
2076 .div_reg = CM_PWMDIV,
2077 .int_bits = 12,
2078 .frac_bits = 12,
2079 .is_mash_clock = true,
2080 .tcnt_mux = 24),
2081 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
2082 SOC_ALL,
2083 .name = "slim",
2084 .ctl_reg = CM_SLIMCTL,
2085 .div_reg = CM_SLIMDIV,
2086 .int_bits = 12,
2087 .frac_bits = 12,
2088 .is_mash_clock = true,
2089 .tcnt_mux = 25),
2090 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
2091 SOC_ALL,
2092 .name = "smi",
2093 .ctl_reg = CM_SMICTL,
2094 .div_reg = CM_SMIDIV,
2095 .int_bits = 4,
2096 .frac_bits = 8,
2097 .tcnt_mux = 27),
2098 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
2099 SOC_ALL,
2100 .name = "uart",
2101 .ctl_reg = CM_UARTCTL,
2102 .div_reg = CM_UARTDIV,
2103 .int_bits = 10,
2104 .frac_bits = 12,
2105 .tcnt_mux = 28),
2106
2107 /* TV encoder clock. Only operating frequency is 108Mhz. */
2108 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
2109 SOC_ALL,
2110 .name = "vec",
2111 .ctl_reg = CM_VECCTL,
2112 .div_reg = CM_VECDIV,
2113 .int_bits = 4,
2114 .frac_bits = 0,
2115 /*
2116 * Allow rate change propagation only on PLLH_AUX which is
2117 * assigned index 7 in the parent array.
2118 */
2119 .set_rate_parent = BIT(7),
2120 .tcnt_mux = 29),
2121
2122 /* dsi clocks */
2123 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
2124 SOC_ALL,
2125 .name = "dsi0e",
2126 .ctl_reg = CM_DSI0ECTL,
2127 .div_reg = CM_DSI0EDIV,
2128 .int_bits = 4,
2129 .frac_bits = 8,
2130 .tcnt_mux = 18),
2131 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
2132 SOC_ALL,
2133 .name = "dsi1e",
2134 .ctl_reg = CM_DSI1ECTL,
2135 .div_reg = CM_DSI1EDIV,
2136 .int_bits = 4,
2137 .frac_bits = 8,
2138 .tcnt_mux = 19),
2139 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
2140 SOC_ALL,
2141 .name = "dsi0p",
2142 .ctl_reg = CM_DSI0PCTL,
2143 .div_reg = CM_DSI0PDIV,
2144 .int_bits = 0,
2145 .frac_bits = 0,
2146 .tcnt_mux = 12),
2147 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
2148 SOC_ALL,
2149 .name = "dsi1p",
2150 .ctl_reg = CM_DSI1PCTL,
2151 .div_reg = CM_DSI1PDIV,
2152 .int_bits = 0,
2153 .frac_bits = 0,
2154 .tcnt_mux = 13),
2155
2156 /* the gates */
2157
2158 /*
2159 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
2160 * you have the debug bit set in the power manager, which we
2161 * don't bother exposing) are individual gates off of the
2162 * non-stop vpu clock.
2163 */
2164 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
2165 SOC_ALL,
2166 .name = "peri_image",
2167 .parent = "vpu",
2168 .ctl_reg = CM_PERIICTL),
2169};
2170
2171/*
2172 * Permanently take a reference on the parent of the SDRAM clock.
2173 *
2174 * While the SDRAM is being driven by its dedicated PLL most of the
2175 * time, there is a little loop running in the firmware that
2176 * periodically switches the SDRAM to using our CM clock to do PVT
2177 * recalibration, with the assumption that the previously configured
2178 * SDRAM parent is still enabled and running.
2179 */
2180static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
2181{
2182 struct clk *parent = clk_get_parent(sdc);
2183
2184 if (IS_ERR(parent))
2185 return PTR_ERR(parent);
2186
2187 return clk_prepare_enable(parent);
2188}
2189
2190static int bcm2835_clk_probe(struct platform_device *pdev)
2191{
2192 struct device *dev = &pdev->dev;
2193 struct clk_hw **hws;
2194 struct bcm2835_cprman *cprman;
2195 struct resource *res;
2196 const struct bcm2835_clk_desc *desc;
2197 const size_t asize = ARRAY_SIZE(clk_desc_array);
2198 const struct cprman_plat_data *pdata;
2199 size_t i;
2200 int ret;
2201
2202 pdata = of_device_get_match_data(&pdev->dev);
2203 if (!pdata)
2204 return -ENODEV;
2205
2206 cprman = devm_kzalloc(dev,
2207 struct_size(cprman, onecell.hws, asize),
2208 GFP_KERNEL);
2209 if (!cprman)
2210 return -ENOMEM;
2211
2212 spin_lock_init(&cprman->regs_lock);
2213 cprman->dev = dev;
2214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2215 cprman->regs = devm_ioremap_resource(dev, res);
2216 if (IS_ERR(cprman->regs))
2217 return PTR_ERR(cprman->regs);
2218
2219 memcpy(cprman->real_parent_names, cprman_parent_names,
2220 sizeof(cprman_parent_names));
2221 of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
2222 ARRAY_SIZE(cprman_parent_names));
2223
2224 /*
2225 * Make sure the external oscillator has been registered.
2226 *
2227 * The other (DSI) clocks are not present on older device
2228 * trees, which we still need to support for backwards
2229 * compatibility.
2230 */
2231 if (!cprman->real_parent_names[0])
2232 return -ENODEV;
2233
2234 platform_set_drvdata(pdev, cprman);
2235
2236 cprman->onecell.num = asize;
2237 hws = cprman->onecell.hws;
2238
2239 for (i = 0; i < asize; i++) {
2240 desc = &clk_desc_array[i];
2241 if (desc->clk_register && desc->data &&
2242 (desc->supported & pdata->soc)) {
2243 hws[i] = desc->clk_register(cprman, desc->data);
2244 }
2245 }
2246
2247 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
2248 if (ret)
2249 return ret;
2250
2251 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2252 &cprman->onecell);
2253}
2254
2255static const struct cprman_plat_data cprman_bcm2835_plat_data = {
2256 .soc = SOC_BCM2835,
2257};
2258
2259static const struct cprman_plat_data cprman_bcm2711_plat_data = {
2260 .soc = SOC_BCM2711,
2261};
2262
2263static const struct of_device_id bcm2835_clk_of_match[] = {
2264 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2265 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2266 {}
2267};
2268MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
2269
2270static struct platform_driver bcm2835_clk_driver = {
2271 .driver = {
2272 .name = "bcm2835-clk",
2273 .of_match_table = bcm2835_clk_of_match,
2274 },
2275 .probe = bcm2835_clk_probe,
2276};
2277
2278builtin_platform_driver(bcm2835_clk_driver);
2279
2280MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
2281MODULE_DESCRIPTION("BCM2835 clock driver");
2282MODULE_LICENSE("GPL");