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1/*
2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/**
21 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
22 *
23 * The clock tree on the 2835 has several levels. There's a root
24 * oscillator running at 19.2Mhz. After the oscillator there are 5
25 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
26 * and "HDMI displays". Those 5 PLLs each can divide their output to
27 * produce up to 4 channels. Finally, there is the level of clocks to
28 * be consumed by other hardware components (like "H264" or "HDMI
29 * state machine"), which divide off of some subset of the PLL
30 * channels.
31 *
32 * All of the clocks in the tree are exposed in the DT, because the DT
33 * may want to make assignments of the final layer of clocks to the
34 * PLL channels, and some components of the hardware will actually
35 * skip layers of the tree (for example, the pixel clock comes
36 * directly from the PLLH PIX channel without using a CM_*CTL clock
37 * generator).
38 */
39
40#include <linux/clk-provider.h>
41#include <linux/clkdev.h>
42#include <linux/clk/bcm2835.h>
43#include <linux/module.h>
44#include <linux/of.h>
45#include <linux/platform_device.h>
46#include <linux/slab.h>
47#include <dt-bindings/clock/bcm2835.h>
48
49#define CM_PASSWORD 0x5a000000
50
51#define CM_GNRICCTL 0x000
52#define CM_GNRICDIV 0x004
53# define CM_DIV_FRAC_BITS 12
54
55#define CM_VPUCTL 0x008
56#define CM_VPUDIV 0x00c
57#define CM_SYSCTL 0x010
58#define CM_SYSDIV 0x014
59#define CM_PERIACTL 0x018
60#define CM_PERIADIV 0x01c
61#define CM_PERIICTL 0x020
62#define CM_PERIIDIV 0x024
63#define CM_H264CTL 0x028
64#define CM_H264DIV 0x02c
65#define CM_ISPCTL 0x030
66#define CM_ISPDIV 0x034
67#define CM_V3DCTL 0x038
68#define CM_V3DDIV 0x03c
69#define CM_CAM0CTL 0x040
70#define CM_CAM0DIV 0x044
71#define CM_CAM1CTL 0x048
72#define CM_CAM1DIV 0x04c
73#define CM_CCP2CTL 0x050
74#define CM_CCP2DIV 0x054
75#define CM_DSI0ECTL 0x058
76#define CM_DSI0EDIV 0x05c
77#define CM_DSI0PCTL 0x060
78#define CM_DSI0PDIV 0x064
79#define CM_DPICTL 0x068
80#define CM_DPIDIV 0x06c
81#define CM_GP0CTL 0x070
82#define CM_GP0DIV 0x074
83#define CM_GP1CTL 0x078
84#define CM_GP1DIV 0x07c
85#define CM_GP2CTL 0x080
86#define CM_GP2DIV 0x084
87#define CM_HSMCTL 0x088
88#define CM_HSMDIV 0x08c
89#define CM_OTPCTL 0x090
90#define CM_OTPDIV 0x094
91#define CM_PCMCTL 0x098
92#define CM_PCMDIV 0x09c
93#define CM_PWMCTL 0x0a0
94#define CM_PWMDIV 0x0a4
95#define CM_SLIMCTL 0x0a8
96#define CM_SLIMDIV 0x0ac
97#define CM_SMICTL 0x0b0
98#define CM_SMIDIV 0x0b4
99/* no definition for 0x0b8 and 0x0bc */
100#define CM_TCNTCTL 0x0c0
101#define CM_TCNTDIV 0x0c4
102#define CM_TECCTL 0x0c8
103#define CM_TECDIV 0x0cc
104#define CM_TD0CTL 0x0d0
105#define CM_TD0DIV 0x0d4
106#define CM_TD1CTL 0x0d8
107#define CM_TD1DIV 0x0dc
108#define CM_TSENSCTL 0x0e0
109#define CM_TSENSDIV 0x0e4
110#define CM_TIMERCTL 0x0e8
111#define CM_TIMERDIV 0x0ec
112#define CM_UARTCTL 0x0f0
113#define CM_UARTDIV 0x0f4
114#define CM_VECCTL 0x0f8
115#define CM_VECDIV 0x0fc
116#define CM_PULSECTL 0x190
117#define CM_PULSEDIV 0x194
118#define CM_SDCCTL 0x1a8
119#define CM_SDCDIV 0x1ac
120#define CM_ARMCTL 0x1b0
121#define CM_EMMCCTL 0x1c0
122#define CM_EMMCDIV 0x1c4
123
124/* General bits for the CM_*CTL regs */
125# define CM_ENABLE BIT(4)
126# define CM_KILL BIT(5)
127# define CM_GATE_BIT 6
128# define CM_GATE BIT(CM_GATE_BIT)
129# define CM_BUSY BIT(7)
130# define CM_BUSYD BIT(8)
131# define CM_SRC_SHIFT 0
132# define CM_SRC_BITS 4
133# define CM_SRC_MASK 0xf
134# define CM_SRC_GND 0
135# define CM_SRC_OSC 1
136# define CM_SRC_TESTDEBUG0 2
137# define CM_SRC_TESTDEBUG1 3
138# define CM_SRC_PLLA_CORE 4
139# define CM_SRC_PLLA_PER 4
140# define CM_SRC_PLLC_CORE0 5
141# define CM_SRC_PLLC_PER 5
142# define CM_SRC_PLLC_CORE1 8
143# define CM_SRC_PLLD_CORE 6
144# define CM_SRC_PLLD_PER 6
145# define CM_SRC_PLLH_AUX 7
146# define CM_SRC_PLLC_CORE1 8
147# define CM_SRC_PLLC_CORE2 9
148
149#define CM_OSCCOUNT 0x100
150
151#define CM_PLLA 0x104
152# define CM_PLL_ANARST BIT(8)
153# define CM_PLLA_HOLDPER BIT(7)
154# define CM_PLLA_LOADPER BIT(6)
155# define CM_PLLA_HOLDCORE BIT(5)
156# define CM_PLLA_LOADCORE BIT(4)
157# define CM_PLLA_HOLDCCP2 BIT(3)
158# define CM_PLLA_LOADCCP2 BIT(2)
159# define CM_PLLA_HOLDDSI0 BIT(1)
160# define CM_PLLA_LOADDSI0 BIT(0)
161
162#define CM_PLLC 0x108
163# define CM_PLLC_HOLDPER BIT(7)
164# define CM_PLLC_LOADPER BIT(6)
165# define CM_PLLC_HOLDCORE2 BIT(5)
166# define CM_PLLC_LOADCORE2 BIT(4)
167# define CM_PLLC_HOLDCORE1 BIT(3)
168# define CM_PLLC_LOADCORE1 BIT(2)
169# define CM_PLLC_HOLDCORE0 BIT(1)
170# define CM_PLLC_LOADCORE0 BIT(0)
171
172#define CM_PLLD 0x10c
173# define CM_PLLD_HOLDPER BIT(7)
174# define CM_PLLD_LOADPER BIT(6)
175# define CM_PLLD_HOLDCORE BIT(5)
176# define CM_PLLD_LOADCORE BIT(4)
177# define CM_PLLD_HOLDDSI1 BIT(3)
178# define CM_PLLD_LOADDSI1 BIT(2)
179# define CM_PLLD_HOLDDSI0 BIT(1)
180# define CM_PLLD_LOADDSI0 BIT(0)
181
182#define CM_PLLH 0x110
183# define CM_PLLH_LOADRCAL BIT(2)
184# define CM_PLLH_LOADAUX BIT(1)
185# define CM_PLLH_LOADPIX BIT(0)
186
187#define CM_LOCK 0x114
188# define CM_LOCK_FLOCKH BIT(12)
189# define CM_LOCK_FLOCKD BIT(11)
190# define CM_LOCK_FLOCKC BIT(10)
191# define CM_LOCK_FLOCKB BIT(9)
192# define CM_LOCK_FLOCKA BIT(8)
193
194#define CM_EVENT 0x118
195#define CM_DSI1ECTL 0x158
196#define CM_DSI1EDIV 0x15c
197#define CM_DSI1PCTL 0x160
198#define CM_DSI1PDIV 0x164
199#define CM_DFTCTL 0x168
200#define CM_DFTDIV 0x16c
201
202#define CM_PLLB 0x170
203# define CM_PLLB_HOLDARM BIT(1)
204# define CM_PLLB_LOADARM BIT(0)
205
206#define A2W_PLLA_CTRL 0x1100
207#define A2W_PLLC_CTRL 0x1120
208#define A2W_PLLD_CTRL 0x1140
209#define A2W_PLLH_CTRL 0x1160
210#define A2W_PLLB_CTRL 0x11e0
211# define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
212# define A2W_PLL_CTRL_PWRDN BIT(16)
213# define A2W_PLL_CTRL_PDIV_MASK 0x000007000
214# define A2W_PLL_CTRL_PDIV_SHIFT 12
215# define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
216# define A2W_PLL_CTRL_NDIV_SHIFT 0
217
218#define A2W_PLLA_ANA0 0x1010
219#define A2W_PLLC_ANA0 0x1030
220#define A2W_PLLD_ANA0 0x1050
221#define A2W_PLLH_ANA0 0x1070
222#define A2W_PLLB_ANA0 0x10f0
223
224#define A2W_PLL_KA_SHIFT 7
225#define A2W_PLL_KA_MASK GENMASK(9, 7)
226#define A2W_PLL_KI_SHIFT 19
227#define A2W_PLL_KI_MASK GENMASK(21, 19)
228#define A2W_PLL_KP_SHIFT 15
229#define A2W_PLL_KP_MASK GENMASK(18, 15)
230
231#define A2W_PLLH_KA_SHIFT 19
232#define A2W_PLLH_KA_MASK GENMASK(21, 19)
233#define A2W_PLLH_KI_LOW_SHIFT 22
234#define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
235#define A2W_PLLH_KI_HIGH_SHIFT 0
236#define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
237#define A2W_PLLH_KP_SHIFT 1
238#define A2W_PLLH_KP_MASK GENMASK(4, 1)
239
240#define A2W_XOSC_CTRL 0x1190
241# define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
242# define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
243# define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
244# define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
245# define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
246# define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
247# define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
248# define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
249
250#define A2W_PLLA_FRAC 0x1200
251#define A2W_PLLC_FRAC 0x1220
252#define A2W_PLLD_FRAC 0x1240
253#define A2W_PLLH_FRAC 0x1260
254#define A2W_PLLB_FRAC 0x12e0
255# define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
256# define A2W_PLL_FRAC_BITS 20
257
258#define A2W_PLL_CHANNEL_DISABLE BIT(8)
259#define A2W_PLL_DIV_BITS 8
260#define A2W_PLL_DIV_SHIFT 0
261
262#define A2W_PLLA_DSI0 0x1300
263#define A2W_PLLA_CORE 0x1400
264#define A2W_PLLA_PER 0x1500
265#define A2W_PLLA_CCP2 0x1600
266
267#define A2W_PLLC_CORE2 0x1320
268#define A2W_PLLC_CORE1 0x1420
269#define A2W_PLLC_PER 0x1520
270#define A2W_PLLC_CORE0 0x1620
271
272#define A2W_PLLD_DSI0 0x1340
273#define A2W_PLLD_CORE 0x1440
274#define A2W_PLLD_PER 0x1540
275#define A2W_PLLD_DSI1 0x1640
276
277#define A2W_PLLH_AUX 0x1360
278#define A2W_PLLH_RCAL 0x1460
279#define A2W_PLLH_PIX 0x1560
280#define A2W_PLLH_STS 0x1660
281
282#define A2W_PLLH_CTRLR 0x1960
283#define A2W_PLLH_FRACR 0x1a60
284#define A2W_PLLH_AUXR 0x1b60
285#define A2W_PLLH_RCALR 0x1c60
286#define A2W_PLLH_PIXR 0x1d60
287#define A2W_PLLH_STSR 0x1e60
288
289#define A2W_PLLB_ARM 0x13e0
290#define A2W_PLLB_SP0 0x14e0
291#define A2W_PLLB_SP1 0x15e0
292#define A2W_PLLB_SP2 0x16e0
293
294#define LOCK_TIMEOUT_NS 100000000
295#define BCM2835_MAX_FB_RATE 1750000000u
296
297struct bcm2835_cprman {
298 struct device *dev;
299 void __iomem *regs;
300 spinlock_t regs_lock;
301 const char *osc_name;
302
303 struct clk_onecell_data onecell;
304 struct clk *clks[BCM2835_CLOCK_COUNT];
305};
306
307static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
308{
309 writel(CM_PASSWORD | val, cprman->regs + reg);
310}
311
312static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
313{
314 return readl(cprman->regs + reg);
315}
316
317/*
318 * These are fixed clocks. They're probably not all root clocks and it may
319 * be possible to turn them on and off but until this is mapped out better
320 * it's the only way they can be used.
321 */
322void __init bcm2835_init_clocks(void)
323{
324 struct clk *clk;
325 int ret;
326
327 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000);
328 if (IS_ERR(clk))
329 pr_err("apb_pclk not registered\n");
330
331 clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000);
332 if (IS_ERR(clk))
333 pr_err("uart0_pclk not registered\n");
334 ret = clk_register_clkdev(clk, NULL, "20201000.uart");
335 if (ret)
336 pr_err("uart0_pclk alias not registered\n");
337
338 clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000);
339 if (IS_ERR(clk))
340 pr_err("uart1_pclk not registered\n");
341 ret = clk_register_clkdev(clk, NULL, "20215000.uart");
342 if (ret)
343 pr_err("uart1_pclk alias not registered\n");
344}
345
346struct bcm2835_pll_data {
347 const char *name;
348 u32 cm_ctrl_reg;
349 u32 a2w_ctrl_reg;
350 u32 frac_reg;
351 u32 ana_reg_base;
352 u32 reference_enable_mask;
353 /* Bit in CM_LOCK to indicate when the PLL has locked. */
354 u32 lock_mask;
355
356 const struct bcm2835_pll_ana_bits *ana;
357
358 unsigned long min_rate;
359 unsigned long max_rate;
360 /*
361 * Highest rate for the VCO before we have to use the
362 * pre-divide-by-2.
363 */
364 unsigned long max_fb_rate;
365};
366
367struct bcm2835_pll_ana_bits {
368 u32 mask0;
369 u32 set0;
370 u32 mask1;
371 u32 set1;
372 u32 mask3;
373 u32 set3;
374 u32 fb_prediv_mask;
375};
376
377static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
378 .mask0 = 0,
379 .set0 = 0,
380 .mask1 = ~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK),
381 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
382 .mask3 = ~A2W_PLL_KA_MASK,
383 .set3 = (2 << A2W_PLL_KA_SHIFT),
384 .fb_prediv_mask = BIT(14),
385};
386
387static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
388 .mask0 = ~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK),
389 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
390 .mask1 = ~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK),
391 .set1 = (6 << A2W_PLLH_KP_SHIFT),
392 .mask3 = 0,
393 .set3 = 0,
394 .fb_prediv_mask = BIT(11),
395};
396
397/*
398 * PLLA is the auxiliary PLL, used to drive the CCP2 (Compact Camera
399 * Port 2) transmitter clock.
400 *
401 * It is in the PX LDO power domain, which is on when the AUDIO domain
402 * is on.
403 */
404static const struct bcm2835_pll_data bcm2835_plla_data = {
405 .name = "plla",
406 .cm_ctrl_reg = CM_PLLA,
407 .a2w_ctrl_reg = A2W_PLLA_CTRL,
408 .frac_reg = A2W_PLLA_FRAC,
409 .ana_reg_base = A2W_PLLA_ANA0,
410 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
411 .lock_mask = CM_LOCK_FLOCKA,
412
413 .ana = &bcm2835_ana_default,
414
415 .min_rate = 600000000u,
416 .max_rate = 2400000000u,
417 .max_fb_rate = BCM2835_MAX_FB_RATE,
418};
419
420/* PLLB is used for the ARM's clock. */
421static const struct bcm2835_pll_data bcm2835_pllb_data = {
422 .name = "pllb",
423 .cm_ctrl_reg = CM_PLLB,
424 .a2w_ctrl_reg = A2W_PLLB_CTRL,
425 .frac_reg = A2W_PLLB_FRAC,
426 .ana_reg_base = A2W_PLLB_ANA0,
427 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
428 .lock_mask = CM_LOCK_FLOCKB,
429
430 .ana = &bcm2835_ana_default,
431
432 .min_rate = 600000000u,
433 .max_rate = 3000000000u,
434 .max_fb_rate = BCM2835_MAX_FB_RATE,
435};
436
437/*
438 * PLLC is the core PLL, used to drive the core VPU clock.
439 *
440 * It is in the PX LDO power domain, which is on when the AUDIO domain
441 * is on.
442*/
443static const struct bcm2835_pll_data bcm2835_pllc_data = {
444 .name = "pllc",
445 .cm_ctrl_reg = CM_PLLC,
446 .a2w_ctrl_reg = A2W_PLLC_CTRL,
447 .frac_reg = A2W_PLLC_FRAC,
448 .ana_reg_base = A2W_PLLC_ANA0,
449 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
450 .lock_mask = CM_LOCK_FLOCKC,
451
452 .ana = &bcm2835_ana_default,
453
454 .min_rate = 600000000u,
455 .max_rate = 3000000000u,
456 .max_fb_rate = BCM2835_MAX_FB_RATE,
457};
458
459/*
460 * PLLD is the display PLL, used to drive DSI display panels.
461 *
462 * It is in the PX LDO power domain, which is on when the AUDIO domain
463 * is on.
464 */
465static const struct bcm2835_pll_data bcm2835_plld_data = {
466 .name = "plld",
467 .cm_ctrl_reg = CM_PLLD,
468 .a2w_ctrl_reg = A2W_PLLD_CTRL,
469 .frac_reg = A2W_PLLD_FRAC,
470 .ana_reg_base = A2W_PLLD_ANA0,
471 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
472 .lock_mask = CM_LOCK_FLOCKD,
473
474 .ana = &bcm2835_ana_default,
475
476 .min_rate = 600000000u,
477 .max_rate = 2400000000u,
478 .max_fb_rate = BCM2835_MAX_FB_RATE,
479};
480
481/*
482 * PLLH is used to supply the pixel clock or the AUX clock for the TV
483 * encoder.
484 *
485 * It is in the HDMI power domain.
486 */
487static const struct bcm2835_pll_data bcm2835_pllh_data = {
488 "pllh",
489 .cm_ctrl_reg = CM_PLLH,
490 .a2w_ctrl_reg = A2W_PLLH_CTRL,
491 .frac_reg = A2W_PLLH_FRAC,
492 .ana_reg_base = A2W_PLLH_ANA0,
493 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
494 .lock_mask = CM_LOCK_FLOCKH,
495
496 .ana = &bcm2835_ana_pllh,
497
498 .min_rate = 600000000u,
499 .max_rate = 3000000000u,
500 .max_fb_rate = BCM2835_MAX_FB_RATE,
501};
502
503struct bcm2835_pll_divider_data {
504 const char *name;
505 const struct bcm2835_pll_data *source_pll;
506 u32 cm_reg;
507 u32 a2w_reg;
508
509 u32 load_mask;
510 u32 hold_mask;
511 u32 fixed_divider;
512};
513
514static const struct bcm2835_pll_divider_data bcm2835_plla_core_data = {
515 .name = "plla_core",
516 .source_pll = &bcm2835_plla_data,
517 .cm_reg = CM_PLLA,
518 .a2w_reg = A2W_PLLA_CORE,
519 .load_mask = CM_PLLA_LOADCORE,
520 .hold_mask = CM_PLLA_HOLDCORE,
521 .fixed_divider = 1,
522};
523
524static const struct bcm2835_pll_divider_data bcm2835_plla_per_data = {
525 .name = "plla_per",
526 .source_pll = &bcm2835_plla_data,
527 .cm_reg = CM_PLLA,
528 .a2w_reg = A2W_PLLA_PER,
529 .load_mask = CM_PLLA_LOADPER,
530 .hold_mask = CM_PLLA_HOLDPER,
531 .fixed_divider = 1,
532};
533
534static const struct bcm2835_pll_divider_data bcm2835_pllb_arm_data = {
535 .name = "pllb_arm",
536 .source_pll = &bcm2835_pllb_data,
537 .cm_reg = CM_PLLB,
538 .a2w_reg = A2W_PLLB_ARM,
539 .load_mask = CM_PLLB_LOADARM,
540 .hold_mask = CM_PLLB_HOLDARM,
541 .fixed_divider = 1,
542};
543
544static const struct bcm2835_pll_divider_data bcm2835_pllc_core0_data = {
545 .name = "pllc_core0",
546 .source_pll = &bcm2835_pllc_data,
547 .cm_reg = CM_PLLC,
548 .a2w_reg = A2W_PLLC_CORE0,
549 .load_mask = CM_PLLC_LOADCORE0,
550 .hold_mask = CM_PLLC_HOLDCORE0,
551 .fixed_divider = 1,
552};
553
554static const struct bcm2835_pll_divider_data bcm2835_pllc_core1_data = {
555 .name = "pllc_core1", .source_pll = &bcm2835_pllc_data,
556 .cm_reg = CM_PLLC, A2W_PLLC_CORE1,
557 .load_mask = CM_PLLC_LOADCORE1,
558 .hold_mask = CM_PLLC_HOLDCORE1,
559 .fixed_divider = 1,
560};
561
562static const struct bcm2835_pll_divider_data bcm2835_pllc_core2_data = {
563 .name = "pllc_core2",
564 .source_pll = &bcm2835_pllc_data,
565 .cm_reg = CM_PLLC,
566 .a2w_reg = A2W_PLLC_CORE2,
567 .load_mask = CM_PLLC_LOADCORE2,
568 .hold_mask = CM_PLLC_HOLDCORE2,
569 .fixed_divider = 1,
570};
571
572static const struct bcm2835_pll_divider_data bcm2835_pllc_per_data = {
573 .name = "pllc_per",
574 .source_pll = &bcm2835_pllc_data,
575 .cm_reg = CM_PLLC,
576 .a2w_reg = A2W_PLLC_PER,
577 .load_mask = CM_PLLC_LOADPER,
578 .hold_mask = CM_PLLC_HOLDPER,
579 .fixed_divider = 1,
580};
581
582static const struct bcm2835_pll_divider_data bcm2835_plld_core_data = {
583 .name = "plld_core",
584 .source_pll = &bcm2835_plld_data,
585 .cm_reg = CM_PLLD,
586 .a2w_reg = A2W_PLLD_CORE,
587 .load_mask = CM_PLLD_LOADCORE,
588 .hold_mask = CM_PLLD_HOLDCORE,
589 .fixed_divider = 1,
590};
591
592static const struct bcm2835_pll_divider_data bcm2835_plld_per_data = {
593 .name = "plld_per",
594 .source_pll = &bcm2835_plld_data,
595 .cm_reg = CM_PLLD,
596 .a2w_reg = A2W_PLLD_PER,
597 .load_mask = CM_PLLD_LOADPER,
598 .hold_mask = CM_PLLD_HOLDPER,
599 .fixed_divider = 1,
600};
601
602static const struct bcm2835_pll_divider_data bcm2835_pllh_rcal_data = {
603 .name = "pllh_rcal",
604 .source_pll = &bcm2835_pllh_data,
605 .cm_reg = CM_PLLH,
606 .a2w_reg = A2W_PLLH_RCAL,
607 .load_mask = CM_PLLH_LOADRCAL,
608 .hold_mask = 0,
609 .fixed_divider = 10,
610};
611
612static const struct bcm2835_pll_divider_data bcm2835_pllh_aux_data = {
613 .name = "pllh_aux",
614 .source_pll = &bcm2835_pllh_data,
615 .cm_reg = CM_PLLH,
616 .a2w_reg = A2W_PLLH_AUX,
617 .load_mask = CM_PLLH_LOADAUX,
618 .hold_mask = 0,
619 .fixed_divider = 10,
620};
621
622static const struct bcm2835_pll_divider_data bcm2835_pllh_pix_data = {
623 .name = "pllh_pix",
624 .source_pll = &bcm2835_pllh_data,
625 .cm_reg = CM_PLLH,
626 .a2w_reg = A2W_PLLH_PIX,
627 .load_mask = CM_PLLH_LOADPIX,
628 .hold_mask = 0,
629 .fixed_divider = 10,
630};
631
632struct bcm2835_clock_data {
633 const char *name;
634
635 const char *const *parents;
636 int num_mux_parents;
637
638 u32 ctl_reg;
639 u32 div_reg;
640
641 /* Number of integer bits in the divider */
642 u32 int_bits;
643 /* Number of fractional bits in the divider */
644 u32 frac_bits;
645
646 bool is_vpu_clock;
647};
648
649static const char *const bcm2835_clock_per_parents[] = {
650 "gnd",
651 "xosc",
652 "testdebug0",
653 "testdebug1",
654 "plla_per",
655 "pllc_per",
656 "plld_per",
657 "pllh_aux",
658};
659
660static const char *const bcm2835_clock_vpu_parents[] = {
661 "gnd",
662 "xosc",
663 "testdebug0",
664 "testdebug1",
665 "plla_core",
666 "pllc_core0",
667 "plld_core",
668 "pllh_aux",
669 "pllc_core1",
670 "pllc_core2",
671};
672
673static const char *const bcm2835_clock_osc_parents[] = {
674 "gnd",
675 "xosc",
676 "testdebug0",
677 "testdebug1"
678};
679
680/*
681 * Used for a 1Mhz clock for the system clocksource, and also used by
682 * the watchdog timer and the camera pulse generator.
683 */
684static const struct bcm2835_clock_data bcm2835_clock_timer_data = {
685 .name = "timer",
686 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
687 .parents = bcm2835_clock_osc_parents,
688 .ctl_reg = CM_TIMERCTL,
689 .div_reg = CM_TIMERDIV,
690 .int_bits = 6,
691 .frac_bits = 12,
692};
693
694/* One Time Programmable Memory clock. Maximum 10Mhz. */
695static const struct bcm2835_clock_data bcm2835_clock_otp_data = {
696 .name = "otp",
697 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
698 .parents = bcm2835_clock_osc_parents,
699 .ctl_reg = CM_OTPCTL,
700 .div_reg = CM_OTPDIV,
701 .int_bits = 4,
702 .frac_bits = 0,
703};
704
705/*
706 * VPU clock. This doesn't have an enable bit, since it drives the
707 * bus for everything else, and is special so it doesn't need to be
708 * gated for rate changes. It is also known as "clk_audio" in various
709 * hardware documentation.
710 */
711static const struct bcm2835_clock_data bcm2835_clock_vpu_data = {
712 .name = "vpu",
713 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
714 .parents = bcm2835_clock_vpu_parents,
715 .ctl_reg = CM_VPUCTL,
716 .div_reg = CM_VPUDIV,
717 .int_bits = 12,
718 .frac_bits = 8,
719 .is_vpu_clock = true,
720};
721
722static const struct bcm2835_clock_data bcm2835_clock_v3d_data = {
723 .name = "v3d",
724 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
725 .parents = bcm2835_clock_vpu_parents,
726 .ctl_reg = CM_V3DCTL,
727 .div_reg = CM_V3DDIV,
728 .int_bits = 4,
729 .frac_bits = 8,
730};
731
732static const struct bcm2835_clock_data bcm2835_clock_isp_data = {
733 .name = "isp",
734 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
735 .parents = bcm2835_clock_vpu_parents,
736 .ctl_reg = CM_ISPCTL,
737 .div_reg = CM_ISPDIV,
738 .int_bits = 4,
739 .frac_bits = 8,
740};
741
742static const struct bcm2835_clock_data bcm2835_clock_h264_data = {
743 .name = "h264",
744 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
745 .parents = bcm2835_clock_vpu_parents,
746 .ctl_reg = CM_H264CTL,
747 .div_reg = CM_H264DIV,
748 .int_bits = 4,
749 .frac_bits = 8,
750};
751
752/* TV encoder clock. Only operating frequency is 108Mhz. */
753static const struct bcm2835_clock_data bcm2835_clock_vec_data = {
754 .name = "vec",
755 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
756 .parents = bcm2835_clock_per_parents,
757 .ctl_reg = CM_VECCTL,
758 .div_reg = CM_VECDIV,
759 .int_bits = 4,
760 .frac_bits = 0,
761};
762
763static const struct bcm2835_clock_data bcm2835_clock_uart_data = {
764 .name = "uart",
765 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
766 .parents = bcm2835_clock_per_parents,
767 .ctl_reg = CM_UARTCTL,
768 .div_reg = CM_UARTDIV,
769 .int_bits = 10,
770 .frac_bits = 12,
771};
772
773/* HDMI state machine */
774static const struct bcm2835_clock_data bcm2835_clock_hsm_data = {
775 .name = "hsm",
776 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
777 .parents = bcm2835_clock_per_parents,
778 .ctl_reg = CM_HSMCTL,
779 .div_reg = CM_HSMDIV,
780 .int_bits = 4,
781 .frac_bits = 8,
782};
783
784/*
785 * Secondary SDRAM clock. Used for low-voltage modes when the PLL in
786 * the SDRAM controller can't be used.
787 */
788static const struct bcm2835_clock_data bcm2835_clock_sdram_data = {
789 .name = "sdram",
790 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
791 .parents = bcm2835_clock_vpu_parents,
792 .ctl_reg = CM_SDCCTL,
793 .div_reg = CM_SDCDIV,
794 .int_bits = 6,
795 .frac_bits = 0,
796};
797
798/* Clock for the temperature sensor. Generally run at 2Mhz, max 5Mhz. */
799static const struct bcm2835_clock_data bcm2835_clock_tsens_data = {
800 .name = "tsens",
801 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
802 .parents = bcm2835_clock_osc_parents,
803 .ctl_reg = CM_TSENSCTL,
804 .div_reg = CM_TSENSDIV,
805 .int_bits = 5,
806 .frac_bits = 0,
807};
808
809/* Arasan EMMC clock */
810static const struct bcm2835_clock_data bcm2835_clock_emmc_data = {
811 .name = "emmc",
812 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
813 .parents = bcm2835_clock_per_parents,
814 .ctl_reg = CM_EMMCCTL,
815 .div_reg = CM_EMMCDIV,
816 .int_bits = 4,
817 .frac_bits = 8,
818};
819
820static const struct bcm2835_clock_data bcm2835_clock_pwm_data = {
821 .name = "pwm",
822 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
823 .parents = bcm2835_clock_per_parents,
824 .ctl_reg = CM_PWMCTL,
825 .div_reg = CM_PWMDIV,
826 .int_bits = 12,
827 .frac_bits = 12,
828};
829
830struct bcm2835_pll {
831 struct clk_hw hw;
832 struct bcm2835_cprman *cprman;
833 const struct bcm2835_pll_data *data;
834};
835
836static int bcm2835_pll_is_on(struct clk_hw *hw)
837{
838 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
839 struct bcm2835_cprman *cprman = pll->cprman;
840 const struct bcm2835_pll_data *data = pll->data;
841
842 return cprman_read(cprman, data->a2w_ctrl_reg) &
843 A2W_PLL_CTRL_PRST_DISABLE;
844}
845
846static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
847 unsigned long parent_rate,
848 u32 *ndiv, u32 *fdiv)
849{
850 u64 div;
851
852 div = (u64)rate << A2W_PLL_FRAC_BITS;
853 do_div(div, parent_rate);
854
855 *ndiv = div >> A2W_PLL_FRAC_BITS;
856 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
857}
858
859static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
860 u32 ndiv, u32 fdiv, u32 pdiv)
861{
862 u64 rate;
863
864 if (pdiv == 0)
865 return 0;
866
867 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
868 do_div(rate, pdiv);
869 return rate >> A2W_PLL_FRAC_BITS;
870}
871
872static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
873 unsigned long *parent_rate)
874{
875 u32 ndiv, fdiv;
876
877 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
878
879 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
880}
881
882static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
883 unsigned long parent_rate)
884{
885 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
886 struct bcm2835_cprman *cprman = pll->cprman;
887 const struct bcm2835_pll_data *data = pll->data;
888 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
889 u32 ndiv, pdiv, fdiv;
890 bool using_prediv;
891
892 if (parent_rate == 0)
893 return 0;
894
895 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
896 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
897 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
898 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
899 data->ana->fb_prediv_mask;
900
901 if (using_prediv)
902 ndiv *= 2;
903
904 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
905}
906
907static void bcm2835_pll_off(struct clk_hw *hw)
908{
909 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
910 struct bcm2835_cprman *cprman = pll->cprman;
911 const struct bcm2835_pll_data *data = pll->data;
912
913 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
914 cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN);
915}
916
917static int bcm2835_pll_on(struct clk_hw *hw)
918{
919 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
920 struct bcm2835_cprman *cprman = pll->cprman;
921 const struct bcm2835_pll_data *data = pll->data;
922 ktime_t timeout;
923
924 /* Take the PLL out of reset. */
925 cprman_write(cprman, data->cm_ctrl_reg,
926 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
927
928 /* Wait for the PLL to lock. */
929 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
930 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
931 if (ktime_after(ktime_get(), timeout)) {
932 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
933 clk_hw_get_name(hw));
934 return -ETIMEDOUT;
935 }
936
937 cpu_relax();
938 }
939
940 return 0;
941}
942
943static void
944bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
945{
946 int i;
947
948 /*
949 * ANA register setup is done as a series of writes to
950 * ANA3-ANA0, in that order. This lets us write all 4
951 * registers as a single cycle of the serdes interface (taking
952 * 100 xosc clocks), whereas if we were to update ana0, 1, and
953 * 3 individually through their partial-write registers, each
954 * would be their own serdes cycle.
955 */
956 for (i = 3; i >= 0; i--)
957 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
958}
959
960static int bcm2835_pll_set_rate(struct clk_hw *hw,
961 unsigned long rate, unsigned long parent_rate)
962{
963 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
964 struct bcm2835_cprman *cprman = pll->cprman;
965 const struct bcm2835_pll_data *data = pll->data;
966 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
967 u32 ndiv, fdiv, a2w_ctl;
968 u32 ana[4];
969 int i;
970
971 if (rate < data->min_rate || rate > data->max_rate) {
972 dev_err(cprman->dev, "%s: rate out of spec: %lu vs (%lu, %lu)\n",
973 clk_hw_get_name(hw), rate,
974 data->min_rate, data->max_rate);
975 return -EINVAL;
976 }
977
978 if (rate > data->max_fb_rate) {
979 use_fb_prediv = true;
980 rate /= 2;
981 } else {
982 use_fb_prediv = false;
983 }
984
985 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
986
987 for (i = 3; i >= 0; i--)
988 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
989
990 was_using_prediv = ana[1] & data->ana->fb_prediv_mask;
991
992 ana[0] &= ~data->ana->mask0;
993 ana[0] |= data->ana->set0;
994 ana[1] &= ~data->ana->mask1;
995 ana[1] |= data->ana->set1;
996 ana[3] &= ~data->ana->mask3;
997 ana[3] |= data->ana->set3;
998
999 if (was_using_prediv && !use_fb_prediv) {
1000 ana[1] &= ~data->ana->fb_prediv_mask;
1001 do_ana_setup_first = true;
1002 } else if (!was_using_prediv && use_fb_prediv) {
1003 ana[1] |= data->ana->fb_prediv_mask;
1004 do_ana_setup_first = false;
1005 } else {
1006 do_ana_setup_first = true;
1007 }
1008
1009 /* Unmask the reference clock from the oscillator. */
1010 cprman_write(cprman, A2W_XOSC_CTRL,
1011 cprman_read(cprman, A2W_XOSC_CTRL) |
1012 data->reference_enable_mask);
1013
1014 if (do_ana_setup_first)
1015 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
1016
1017 /* Set the PLL multiplier from the oscillator. */
1018 cprman_write(cprman, data->frac_reg, fdiv);
1019
1020 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
1021 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
1022 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
1023 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
1024 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
1025 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
1026
1027 if (!do_ana_setup_first)
1028 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
1029
1030 return 0;
1031}
1032
1033static const struct clk_ops bcm2835_pll_clk_ops = {
1034 .is_prepared = bcm2835_pll_is_on,
1035 .prepare = bcm2835_pll_on,
1036 .unprepare = bcm2835_pll_off,
1037 .recalc_rate = bcm2835_pll_get_rate,
1038 .set_rate = bcm2835_pll_set_rate,
1039 .round_rate = bcm2835_pll_round_rate,
1040};
1041
1042struct bcm2835_pll_divider {
1043 struct clk_divider div;
1044 struct bcm2835_cprman *cprman;
1045 const struct bcm2835_pll_divider_data *data;
1046};
1047
1048static struct bcm2835_pll_divider *
1049bcm2835_pll_divider_from_hw(struct clk_hw *hw)
1050{
1051 return container_of(hw, struct bcm2835_pll_divider, div.hw);
1052}
1053
1054static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
1055{
1056 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
1057 struct bcm2835_cprman *cprman = divider->cprman;
1058 const struct bcm2835_pll_divider_data *data = divider->data;
1059
1060 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
1061}
1062
1063static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
1064 unsigned long rate,
1065 unsigned long *parent_rate)
1066{
1067 return clk_divider_ops.round_rate(hw, rate, parent_rate);
1068}
1069
1070static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
1071 unsigned long parent_rate)
1072{
1073 return clk_divider_ops.recalc_rate(hw, parent_rate);
1074}
1075
1076static void bcm2835_pll_divider_off(struct clk_hw *hw)
1077{
1078 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
1079 struct bcm2835_cprman *cprman = divider->cprman;
1080 const struct bcm2835_pll_divider_data *data = divider->data;
1081
1082 cprman_write(cprman, data->cm_reg,
1083 (cprman_read(cprman, data->cm_reg) &
1084 ~data->load_mask) | data->hold_mask);
1085 cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE);
1086}
1087
1088static int bcm2835_pll_divider_on(struct clk_hw *hw)
1089{
1090 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
1091 struct bcm2835_cprman *cprman = divider->cprman;
1092 const struct bcm2835_pll_divider_data *data = divider->data;
1093
1094 cprman_write(cprman, data->a2w_reg,
1095 cprman_read(cprman, data->a2w_reg) &
1096 ~A2W_PLL_CHANNEL_DISABLE);
1097
1098 cprman_write(cprman, data->cm_reg,
1099 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
1100
1101 return 0;
1102}
1103
1104static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
1105 unsigned long rate,
1106 unsigned long parent_rate)
1107{
1108 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
1109 struct bcm2835_cprman *cprman = divider->cprman;
1110 const struct bcm2835_pll_divider_data *data = divider->data;
1111 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
1112
1113 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1114
1115 div = min(div, max_div);
1116 if (div == max_div)
1117 div = 0;
1118
1119 cprman_write(cprman, data->a2w_reg, div);
1120 cm = cprman_read(cprman, data->cm_reg);
1121 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
1122 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
1123
1124 return 0;
1125}
1126
1127static const struct clk_ops bcm2835_pll_divider_clk_ops = {
1128 .is_prepared = bcm2835_pll_divider_is_on,
1129 .prepare = bcm2835_pll_divider_on,
1130 .unprepare = bcm2835_pll_divider_off,
1131 .recalc_rate = bcm2835_pll_divider_get_rate,
1132 .set_rate = bcm2835_pll_divider_set_rate,
1133 .round_rate = bcm2835_pll_divider_round_rate,
1134};
1135
1136/*
1137 * The CM dividers do fixed-point division, so we can't use the
1138 * generic integer divider code like the PLL dividers do (and we can't
1139 * fake it by having some fixed shifts preceding it in the clock tree,
1140 * because we'd run out of bits in a 32-bit unsigned long).
1141 */
1142struct bcm2835_clock {
1143 struct clk_hw hw;
1144 struct bcm2835_cprman *cprman;
1145 const struct bcm2835_clock_data *data;
1146};
1147
1148static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
1149{
1150 return container_of(hw, struct bcm2835_clock, hw);
1151}
1152
1153static int bcm2835_clock_is_on(struct clk_hw *hw)
1154{
1155 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1156 struct bcm2835_cprman *cprman = clock->cprman;
1157 const struct bcm2835_clock_data *data = clock->data;
1158
1159 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
1160}
1161
1162static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
1163 unsigned long rate,
1164 unsigned long parent_rate,
1165 bool round_up)
1166{
1167 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1168 const struct bcm2835_clock_data *data = clock->data;
1169 u32 unused_frac_mask =
1170 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
1171 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
1172 u64 rem;
1173 u32 div;
1174
1175 rem = do_div(temp, rate);
1176 div = temp;
1177
1178 /* Round up and mask off the unused bits */
1179 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0))
1180 div += unused_frac_mask + 1;
1181 div &= ~unused_frac_mask;
1182
1183 /* Clamp to the limits. */
1184 div = max(div, unused_frac_mask + 1);
1185 div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
1186 CM_DIV_FRAC_BITS - data->frac_bits));
1187
1188 return div;
1189}
1190
1191static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
1192 unsigned long parent_rate,
1193 u32 div)
1194{
1195 const struct bcm2835_clock_data *data = clock->data;
1196 u64 temp;
1197
1198 /*
1199 * The divisor is a 12.12 fixed point field, but only some of
1200 * the bits are populated in any given clock.
1201 */
1202 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
1203 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
1204
1205 if (div == 0)
1206 return 0;
1207
1208 temp = (u64)parent_rate << data->frac_bits;
1209
1210 do_div(temp, div);
1211
1212 return temp;
1213}
1214
1215static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
1216 unsigned long parent_rate)
1217{
1218 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1219 struct bcm2835_cprman *cprman = clock->cprman;
1220 const struct bcm2835_clock_data *data = clock->data;
1221 u32 div = cprman_read(cprman, data->div_reg);
1222
1223 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1224}
1225
1226static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1227{
1228 struct bcm2835_cprman *cprman = clock->cprman;
1229 const struct bcm2835_clock_data *data = clock->data;
1230 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1231
1232 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1233 if (ktime_after(ktime_get(), timeout)) {
1234 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1235 clk_hw_get_name(&clock->hw));
1236 return;
1237 }
1238 cpu_relax();
1239 }
1240}
1241
1242static void bcm2835_clock_off(struct clk_hw *hw)
1243{
1244 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1245 struct bcm2835_cprman *cprman = clock->cprman;
1246 const struct bcm2835_clock_data *data = clock->data;
1247
1248 spin_lock(&cprman->regs_lock);
1249 cprman_write(cprman, data->ctl_reg,
1250 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1251 spin_unlock(&cprman->regs_lock);
1252
1253 /* BUSY will remain high until the divider completes its cycle. */
1254 bcm2835_clock_wait_busy(clock);
1255}
1256
1257static int bcm2835_clock_on(struct clk_hw *hw)
1258{
1259 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1260 struct bcm2835_cprman *cprman = clock->cprman;
1261 const struct bcm2835_clock_data *data = clock->data;
1262
1263 spin_lock(&cprman->regs_lock);
1264 cprman_write(cprman, data->ctl_reg,
1265 cprman_read(cprman, data->ctl_reg) |
1266 CM_ENABLE |
1267 CM_GATE);
1268 spin_unlock(&cprman->regs_lock);
1269
1270 return 0;
1271}
1272
1273static int bcm2835_clock_set_rate(struct clk_hw *hw,
1274 unsigned long rate, unsigned long parent_rate)
1275{
1276 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1277 struct bcm2835_cprman *cprman = clock->cprman;
1278 const struct bcm2835_clock_data *data = clock->data;
1279 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
1280
1281 cprman_write(cprman, data->div_reg, div);
1282
1283 return 0;
1284}
1285
1286static int bcm2835_clock_determine_rate(struct clk_hw *hw,
1287 struct clk_rate_request *req)
1288{
1289 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1290 struct clk_hw *parent, *best_parent = NULL;
1291 unsigned long rate, best_rate = 0;
1292 unsigned long prate, best_prate = 0;
1293 size_t i;
1294 u32 div;
1295
1296 /*
1297 * Select parent clock that results in the closest but lower rate
1298 */
1299 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
1300 parent = clk_hw_get_parent_by_index(hw, i);
1301 if (!parent)
1302 continue;
1303 prate = clk_hw_get_rate(parent);
1304 div = bcm2835_clock_choose_div(hw, req->rate, prate, true);
1305 rate = bcm2835_clock_rate_from_divisor(clock, prate, div);
1306 if (rate > best_rate && rate <= req->rate) {
1307 best_parent = parent;
1308 best_prate = prate;
1309 best_rate = rate;
1310 }
1311 }
1312
1313 if (!best_parent)
1314 return -EINVAL;
1315
1316 req->best_parent_hw = best_parent;
1317 req->best_parent_rate = best_prate;
1318
1319 req->rate = best_rate;
1320
1321 return 0;
1322}
1323
1324static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
1325{
1326 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1327 struct bcm2835_cprman *cprman = clock->cprman;
1328 const struct bcm2835_clock_data *data = clock->data;
1329 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
1330
1331 cprman_write(cprman, data->ctl_reg, src);
1332 return 0;
1333}
1334
1335static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1336{
1337 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1338 struct bcm2835_cprman *cprman = clock->cprman;
1339 const struct bcm2835_clock_data *data = clock->data;
1340 u32 src = cprman_read(cprman, data->ctl_reg);
1341
1342 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1343}
1344
1345
1346static const struct clk_ops bcm2835_clock_clk_ops = {
1347 .is_prepared = bcm2835_clock_is_on,
1348 .prepare = bcm2835_clock_on,
1349 .unprepare = bcm2835_clock_off,
1350 .recalc_rate = bcm2835_clock_get_rate,
1351 .set_rate = bcm2835_clock_set_rate,
1352 .determine_rate = bcm2835_clock_determine_rate,
1353 .set_parent = bcm2835_clock_set_parent,
1354 .get_parent = bcm2835_clock_get_parent,
1355};
1356
1357static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1358{
1359 return true;
1360}
1361
1362/*
1363 * The VPU clock can never be disabled (it doesn't have an ENABLE
1364 * bit), so it gets its own set of clock ops.
1365 */
1366static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1367 .is_prepared = bcm2835_vpu_clock_is_on,
1368 .recalc_rate = bcm2835_clock_get_rate,
1369 .set_rate = bcm2835_clock_set_rate,
1370 .determine_rate = bcm2835_clock_determine_rate,
1371 .set_parent = bcm2835_clock_set_parent,
1372 .get_parent = bcm2835_clock_get_parent,
1373};
1374
1375static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1376 const struct bcm2835_pll_data *data)
1377{
1378 struct bcm2835_pll *pll;
1379 struct clk_init_data init;
1380
1381 memset(&init, 0, sizeof(init));
1382
1383 /* All of the PLLs derive from the external oscillator. */
1384 init.parent_names = &cprman->osc_name;
1385 init.num_parents = 1;
1386 init.name = data->name;
1387 init.ops = &bcm2835_pll_clk_ops;
1388 init.flags = CLK_IGNORE_UNUSED;
1389
1390 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1391 if (!pll)
1392 return NULL;
1393
1394 pll->cprman = cprman;
1395 pll->data = data;
1396 pll->hw.init = &init;
1397
1398 return devm_clk_register(cprman->dev, &pll->hw);
1399}
1400
1401static struct clk *
1402bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1403 const struct bcm2835_pll_divider_data *data)
1404{
1405 struct bcm2835_pll_divider *divider;
1406 struct clk_init_data init;
1407 struct clk *clk;
1408 const char *divider_name;
1409
1410 if (data->fixed_divider != 1) {
1411 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1412 "%s_prediv", data->name);
1413 if (!divider_name)
1414 return NULL;
1415 } else {
1416 divider_name = data->name;
1417 }
1418
1419 memset(&init, 0, sizeof(init));
1420
1421 init.parent_names = &data->source_pll->name;
1422 init.num_parents = 1;
1423 init.name = divider_name;
1424 init.ops = &bcm2835_pll_divider_clk_ops;
1425 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
1426
1427 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1428 if (!divider)
1429 return NULL;
1430
1431 divider->div.reg = cprman->regs + data->a2w_reg;
1432 divider->div.shift = A2W_PLL_DIV_SHIFT;
1433 divider->div.width = A2W_PLL_DIV_BITS;
1434 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
1435 divider->div.lock = &cprman->regs_lock;
1436 divider->div.hw.init = &init;
1437 divider->div.table = NULL;
1438
1439 divider->cprman = cprman;
1440 divider->data = data;
1441
1442 clk = devm_clk_register(cprman->dev, ÷r->div.hw);
1443 if (IS_ERR(clk))
1444 return clk;
1445
1446 /*
1447 * PLLH's channels have a fixed divide by 10 afterwards, which
1448 * is what our consumers are actually using.
1449 */
1450 if (data->fixed_divider != 1) {
1451 return clk_register_fixed_factor(cprman->dev, data->name,
1452 divider_name,
1453 CLK_SET_RATE_PARENT,
1454 1,
1455 data->fixed_divider);
1456 }
1457
1458 return clk;
1459}
1460
1461static struct clk *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1462 const struct bcm2835_clock_data *data)
1463{
1464 struct bcm2835_clock *clock;
1465 struct clk_init_data init;
1466 const char *parents[1 << CM_SRC_BITS];
1467 size_t i;
1468
1469 /*
1470 * Replace our "xosc" references with the oscillator's
1471 * actual name.
1472 */
1473 for (i = 0; i < data->num_mux_parents; i++) {
1474 if (strcmp(data->parents[i], "xosc") == 0)
1475 parents[i] = cprman->osc_name;
1476 else
1477 parents[i] = data->parents[i];
1478 }
1479
1480 memset(&init, 0, sizeof(init));
1481 init.parent_names = parents;
1482 init.num_parents = data->num_mux_parents;
1483 init.name = data->name;
1484 init.flags = CLK_IGNORE_UNUSED;
1485
1486 if (data->is_vpu_clock) {
1487 init.ops = &bcm2835_vpu_clock_clk_ops;
1488 } else {
1489 init.ops = &bcm2835_clock_clk_ops;
1490 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1491 }
1492
1493 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1494 if (!clock)
1495 return NULL;
1496
1497 clock->cprman = cprman;
1498 clock->data = data;
1499 clock->hw.init = &init;
1500
1501 return devm_clk_register(cprman->dev, &clock->hw);
1502}
1503
1504static int bcm2835_clk_probe(struct platform_device *pdev)
1505{
1506 struct device *dev = &pdev->dev;
1507 struct clk **clks;
1508 struct bcm2835_cprman *cprman;
1509 struct resource *res;
1510
1511 cprman = devm_kzalloc(dev, sizeof(*cprman), GFP_KERNEL);
1512 if (!cprman)
1513 return -ENOMEM;
1514
1515 spin_lock_init(&cprman->regs_lock);
1516 cprman->dev = dev;
1517 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1518 cprman->regs = devm_ioremap_resource(dev, res);
1519 if (IS_ERR(cprman->regs))
1520 return PTR_ERR(cprman->regs);
1521
1522 cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0);
1523 if (!cprman->osc_name)
1524 return -ENODEV;
1525
1526 platform_set_drvdata(pdev, cprman);
1527
1528 cprman->onecell.clk_num = BCM2835_CLOCK_COUNT;
1529 cprman->onecell.clks = cprman->clks;
1530 clks = cprman->clks;
1531
1532 clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data);
1533 clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data);
1534 clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data);
1535 clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data);
1536 clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data);
1537
1538 clks[BCM2835_PLLA_CORE] =
1539 bcm2835_register_pll_divider(cprman, &bcm2835_plla_core_data);
1540 clks[BCM2835_PLLA_PER] =
1541 bcm2835_register_pll_divider(cprman, &bcm2835_plla_per_data);
1542 clks[BCM2835_PLLC_CORE0] =
1543 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core0_data);
1544 clks[BCM2835_PLLC_CORE1] =
1545 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core1_data);
1546 clks[BCM2835_PLLC_CORE2] =
1547 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core2_data);
1548 clks[BCM2835_PLLC_PER] =
1549 bcm2835_register_pll_divider(cprman, &bcm2835_pllc_per_data);
1550 clks[BCM2835_PLLD_CORE] =
1551 bcm2835_register_pll_divider(cprman, &bcm2835_plld_core_data);
1552 clks[BCM2835_PLLD_PER] =
1553 bcm2835_register_pll_divider(cprman, &bcm2835_plld_per_data);
1554 clks[BCM2835_PLLH_RCAL] =
1555 bcm2835_register_pll_divider(cprman, &bcm2835_pllh_rcal_data);
1556 clks[BCM2835_PLLH_AUX] =
1557 bcm2835_register_pll_divider(cprman, &bcm2835_pllh_aux_data);
1558 clks[BCM2835_PLLH_PIX] =
1559 bcm2835_register_pll_divider(cprman, &bcm2835_pllh_pix_data);
1560
1561 clks[BCM2835_CLOCK_TIMER] =
1562 bcm2835_register_clock(cprman, &bcm2835_clock_timer_data);
1563 clks[BCM2835_CLOCK_OTP] =
1564 bcm2835_register_clock(cprman, &bcm2835_clock_otp_data);
1565 clks[BCM2835_CLOCK_TSENS] =
1566 bcm2835_register_clock(cprman, &bcm2835_clock_tsens_data);
1567 clks[BCM2835_CLOCK_VPU] =
1568 bcm2835_register_clock(cprman, &bcm2835_clock_vpu_data);
1569 clks[BCM2835_CLOCK_V3D] =
1570 bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
1571 clks[BCM2835_CLOCK_ISP] =
1572 bcm2835_register_clock(cprman, &bcm2835_clock_isp_data);
1573 clks[BCM2835_CLOCK_H264] =
1574 bcm2835_register_clock(cprman, &bcm2835_clock_h264_data);
1575 clks[BCM2835_CLOCK_V3D] =
1576 bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
1577 clks[BCM2835_CLOCK_SDRAM] =
1578 bcm2835_register_clock(cprman, &bcm2835_clock_sdram_data);
1579 clks[BCM2835_CLOCK_UART] =
1580 bcm2835_register_clock(cprman, &bcm2835_clock_uart_data);
1581 clks[BCM2835_CLOCK_VEC] =
1582 bcm2835_register_clock(cprman, &bcm2835_clock_vec_data);
1583 clks[BCM2835_CLOCK_HSM] =
1584 bcm2835_register_clock(cprman, &bcm2835_clock_hsm_data);
1585 clks[BCM2835_CLOCK_EMMC] =
1586 bcm2835_register_clock(cprman, &bcm2835_clock_emmc_data);
1587
1588 /*
1589 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
1590 * you have the debug bit set in the power manager, which we
1591 * don't bother exposing) are individual gates off of the
1592 * non-stop vpu clock.
1593 */
1594 clks[BCM2835_CLOCK_PERI_IMAGE] =
1595 clk_register_gate(dev, "peri_image", "vpu",
1596 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1597 cprman->regs + CM_PERIICTL, CM_GATE_BIT,
1598 0, &cprman->regs_lock);
1599
1600 clks[BCM2835_CLOCK_PWM] =
1601 bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
1602
1603 return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
1604 &cprman->onecell);
1605}
1606
1607static const struct of_device_id bcm2835_clk_of_match[] = {
1608 { .compatible = "brcm,bcm2835-cprman", },
1609 {}
1610};
1611MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
1612
1613static struct platform_driver bcm2835_clk_driver = {
1614 .driver = {
1615 .name = "bcm2835-clk",
1616 .of_match_table = bcm2835_clk_of_match,
1617 },
1618 .probe = bcm2835_clk_probe,
1619};
1620
1621builtin_platform_driver(bcm2835_clk_driver);
1622
1623MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
1624MODULE_DESCRIPTION("BCM2835 clock driver");
1625MODULE_LICENSE("GPL v2");