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1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
33#include <linux/bitops.h>
34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
37#include <linux/ipv6.h>
38#include <linux/slab.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/net_tstamp.h>
42#include <linux/mii.h>
43#include <linux/ethtool.h>
44#include <linux/if.h>
45#include <linux/if_vlan.h>
46#include <linux/pci.h>
47#include <linux/pci-aspm.h>
48#include <linux/delay.h>
49#include <linux/interrupt.h>
50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
53#include <linux/if_ether.h>
54#include <linux/aer.h>
55#include <linux/prefetch.h>
56#include <linux/pm_runtime.h>
57#ifdef CONFIG_IGB_DCA
58#include <linux/dca.h>
59#endif
60#include "igb.h"
61
62#define MAJ 3
63#define MIN 4
64#define BUILD 7
65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
66__stringify(BUILD) "-k"
67char igb_driver_name[] = "igb";
68char igb_driver_version[] = DRV_VERSION;
69static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
72
73static const struct e1000_info *igb_info_tbl[] = {
74 [board_82575] = &e1000_82575_info,
75};
76
77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
108 /* required last entry */
109 {0, }
110};
111
112MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
113
114void igb_reset(struct igb_adapter *);
115static int igb_setup_all_tx_resources(struct igb_adapter *);
116static int igb_setup_all_rx_resources(struct igb_adapter *);
117static void igb_free_all_tx_resources(struct igb_adapter *);
118static void igb_free_all_rx_resources(struct igb_adapter *);
119static void igb_setup_mrqc(struct igb_adapter *);
120static int igb_probe(struct pci_dev *, const struct pci_device_id *);
121static void __devexit igb_remove(struct pci_dev *pdev);
122static int igb_sw_init(struct igb_adapter *);
123static int igb_open(struct net_device *);
124static int igb_close(struct net_device *);
125static void igb_configure_tx(struct igb_adapter *);
126static void igb_configure_rx(struct igb_adapter *);
127static void igb_clean_all_tx_rings(struct igb_adapter *);
128static void igb_clean_all_rx_rings(struct igb_adapter *);
129static void igb_clean_tx_ring(struct igb_ring *);
130static void igb_clean_rx_ring(struct igb_ring *);
131static void igb_set_rx_mode(struct net_device *);
132static void igb_update_phy_info(unsigned long);
133static void igb_watchdog(unsigned long);
134static void igb_watchdog_task(struct work_struct *);
135static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
136static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
137 struct rtnl_link_stats64 *stats);
138static int igb_change_mtu(struct net_device *, int);
139static int igb_set_mac(struct net_device *, void *);
140static void igb_set_uta(struct igb_adapter *adapter);
141static irqreturn_t igb_intr(int irq, void *);
142static irqreturn_t igb_intr_msi(int irq, void *);
143static irqreturn_t igb_msix_other(int irq, void *);
144static irqreturn_t igb_msix_ring(int irq, void *);
145#ifdef CONFIG_IGB_DCA
146static void igb_update_dca(struct igb_q_vector *);
147static void igb_setup_dca(struct igb_adapter *);
148#endif /* CONFIG_IGB_DCA */
149static int igb_poll(struct napi_struct *, int);
150static bool igb_clean_tx_irq(struct igb_q_vector *);
151static bool igb_clean_rx_irq(struct igb_q_vector *, int);
152static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
153static void igb_tx_timeout(struct net_device *);
154static void igb_reset_task(struct work_struct *);
155static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
156static int igb_vlan_rx_add_vid(struct net_device *, u16);
157static int igb_vlan_rx_kill_vid(struct net_device *, u16);
158static void igb_restore_vlan(struct igb_adapter *);
159static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
160static void igb_ping_all_vfs(struct igb_adapter *);
161static void igb_msg_task(struct igb_adapter *);
162static void igb_vmm_control(struct igb_adapter *);
163static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
164static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
165static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
166static int igb_ndo_set_vf_vlan(struct net_device *netdev,
167 int vf, u16 vlan, u8 qos);
168static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
169static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
170 struct ifla_vf_info *ivi);
171static void igb_check_vf_rate_limit(struct igb_adapter *);
172
173#ifdef CONFIG_PCI_IOV
174static int igb_vf_configure(struct igb_adapter *adapter, int vf);
175static int igb_find_enabled_vfs(struct igb_adapter *adapter);
176static int igb_check_vf_assignment(struct igb_adapter *adapter);
177#endif
178
179#ifdef CONFIG_PM
180#ifdef CONFIG_PM_SLEEP
181static int igb_suspend(struct device *);
182#endif
183static int igb_resume(struct device *);
184#ifdef CONFIG_PM_RUNTIME
185static int igb_runtime_suspend(struct device *dev);
186static int igb_runtime_resume(struct device *dev);
187static int igb_runtime_idle(struct device *dev);
188#endif
189static const struct dev_pm_ops igb_pm_ops = {
190 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
191 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
192 igb_runtime_idle)
193};
194#endif
195static void igb_shutdown(struct pci_dev *);
196#ifdef CONFIG_IGB_DCA
197static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
198static struct notifier_block dca_notifier = {
199 .notifier_call = igb_notify_dca,
200 .next = NULL,
201 .priority = 0
202};
203#endif
204#ifdef CONFIG_NET_POLL_CONTROLLER
205/* for netdump / net console */
206static void igb_netpoll(struct net_device *);
207#endif
208#ifdef CONFIG_PCI_IOV
209static unsigned int max_vfs = 0;
210module_param(max_vfs, uint, 0);
211MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
212 "per physical function");
213#endif /* CONFIG_PCI_IOV */
214
215static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
216 pci_channel_state_t);
217static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
218static void igb_io_resume(struct pci_dev *);
219
220static struct pci_error_handlers igb_err_handler = {
221 .error_detected = igb_io_error_detected,
222 .slot_reset = igb_io_slot_reset,
223 .resume = igb_io_resume,
224};
225
226static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
227
228static struct pci_driver igb_driver = {
229 .name = igb_driver_name,
230 .id_table = igb_pci_tbl,
231 .probe = igb_probe,
232 .remove = __devexit_p(igb_remove),
233#ifdef CONFIG_PM
234 .driver.pm = &igb_pm_ops,
235#endif
236 .shutdown = igb_shutdown,
237 .err_handler = &igb_err_handler
238};
239
240MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
241MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
242MODULE_LICENSE("GPL");
243MODULE_VERSION(DRV_VERSION);
244
245#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
246static int debug = -1;
247module_param(debug, int, 0);
248MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
249
250struct igb_reg_info {
251 u32 ofs;
252 char *name;
253};
254
255static const struct igb_reg_info igb_reg_info_tbl[] = {
256
257 /* General Registers */
258 {E1000_CTRL, "CTRL"},
259 {E1000_STATUS, "STATUS"},
260 {E1000_CTRL_EXT, "CTRL_EXT"},
261
262 /* Interrupt Registers */
263 {E1000_ICR, "ICR"},
264
265 /* RX Registers */
266 {E1000_RCTL, "RCTL"},
267 {E1000_RDLEN(0), "RDLEN"},
268 {E1000_RDH(0), "RDH"},
269 {E1000_RDT(0), "RDT"},
270 {E1000_RXDCTL(0), "RXDCTL"},
271 {E1000_RDBAL(0), "RDBAL"},
272 {E1000_RDBAH(0), "RDBAH"},
273
274 /* TX Registers */
275 {E1000_TCTL, "TCTL"},
276 {E1000_TDBAL(0), "TDBAL"},
277 {E1000_TDBAH(0), "TDBAH"},
278 {E1000_TDLEN(0), "TDLEN"},
279 {E1000_TDH(0), "TDH"},
280 {E1000_TDT(0), "TDT"},
281 {E1000_TXDCTL(0), "TXDCTL"},
282 {E1000_TDFH, "TDFH"},
283 {E1000_TDFT, "TDFT"},
284 {E1000_TDFHS, "TDFHS"},
285 {E1000_TDFPC, "TDFPC"},
286
287 /* List Terminator */
288 {}
289};
290
291/*
292 * igb_regdump - register printout routine
293 */
294static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
295{
296 int n = 0;
297 char rname[16];
298 u32 regs[8];
299
300 switch (reginfo->ofs) {
301 case E1000_RDLEN(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_RDLEN(n));
304 break;
305 case E1000_RDH(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDH(n));
308 break;
309 case E1000_RDT(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDT(n));
312 break;
313 case E1000_RXDCTL(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RXDCTL(n));
316 break;
317 case E1000_RDBAL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDBAL(n));
320 break;
321 case E1000_RDBAH(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAH(n));
324 break;
325 case E1000_TDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_TDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_TDBAH(n));
332 break;
333 case E1000_TDLEN(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDLEN(n));
336 break;
337 case E1000_TDH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDH(n));
340 break;
341 case E1000_TDT(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDT(n));
344 break;
345 case E1000_TXDCTL(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TXDCTL(n));
348 break;
349 default:
350 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
351 return;
352 }
353
354 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
355 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
356 regs[2], regs[3]);
357}
358
359/*
360 * igb_dump - Print registers, tx-rings and rx-rings
361 */
362static void igb_dump(struct igb_adapter *adapter)
363{
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
373 u16 i, n;
374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
381 pr_info("Device Name state trans_start "
382 "last_rx\n");
383 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
384 netdev->state, netdev->trans_start, netdev->last_rx);
385 }
386
387 /* Print Registers */
388 dev_info(&adapter->pdev->dev, "Register Dump\n");
389 pr_info(" Register Name Value\n");
390 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
391 reginfo->name; reginfo++) {
392 igb_regdump(hw, reginfo);
393 }
394
395 /* Print TX Ring Summary */
396 if (!netdev || !netif_running(netdev))
397 goto exit;
398
399 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
400 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
401 for (n = 0; n < adapter->num_tx_queues; n++) {
402 struct igb_tx_buffer *buffer_info;
403 tx_ring = adapter->tx_ring[n];
404 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
405 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
406 n, tx_ring->next_to_use, tx_ring->next_to_clean,
407 (u64)buffer_info->dma,
408 buffer_info->length,
409 buffer_info->next_to_watch,
410 (u64)buffer_info->time_stamp);
411 }
412
413 /* Print TX Rings */
414 if (!netif_msg_tx_done(adapter))
415 goto rx_ring_summary;
416
417 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
418
419 /* Transmit Descriptor Formats
420 *
421 * Advanced Transmit Descriptor
422 * +--------------------------------------------------------------+
423 * 0 | Buffer Address [63:0] |
424 * +--------------------------------------------------------------+
425 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
426 * +--------------------------------------------------------------+
427 * 63 46 45 40 39 38 36 35 32 31 24 15 0
428 */
429
430 for (n = 0; n < adapter->num_tx_queues; n++) {
431 tx_ring = adapter->tx_ring[n];
432 pr_info("------------------------------------\n");
433 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
434 pr_info("------------------------------------\n");
435 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
436 "[bi->dma ] leng ntw timestamp "
437 "bi->skb\n");
438
439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
440 const char *next_desc;
441 struct igb_tx_buffer *buffer_info;
442 tx_desc = IGB_TX_DESC(tx_ring, i);
443 buffer_info = &tx_ring->tx_buffer_info[i];
444 u0 = (struct my_u0 *)tx_desc;
445 if (i == tx_ring->next_to_use &&
446 i == tx_ring->next_to_clean)
447 next_desc = " NTC/U";
448 else if (i == tx_ring->next_to_use)
449 next_desc = " NTU";
450 else if (i == tx_ring->next_to_clean)
451 next_desc = " NTC";
452 else
453 next_desc = "";
454
455 pr_info("T [0x%03X] %016llX %016llX %016llX"
456 " %04X %p %016llX %p%s\n", i,
457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
459 (u64)buffer_info->dma,
460 buffer_info->length,
461 buffer_info->next_to_watch,
462 (u64)buffer_info->time_stamp,
463 buffer_info->skb, next_desc);
464
465 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
466 print_hex_dump(KERN_INFO, "",
467 DUMP_PREFIX_ADDRESS,
468 16, 1, phys_to_virt(buffer_info->dma),
469 buffer_info->length, true);
470 }
471 }
472
473 /* Print RX Rings Summary */
474rx_ring_summary:
475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
476 pr_info("Queue [NTU] [NTC]\n");
477 for (n = 0; n < adapter->num_rx_queues; n++) {
478 rx_ring = adapter->rx_ring[n];
479 pr_info(" %5d %5X %5X\n",
480 n, rx_ring->next_to_use, rx_ring->next_to_clean);
481 }
482
483 /* Print RX Rings */
484 if (!netif_msg_rx_status(adapter))
485 goto exit;
486
487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488
489 /* Advanced Receive Descriptor (Read) Format
490 * 63 1 0
491 * +-----------------------------------------------------+
492 * 0 | Packet Buffer Address [63:1] |A0/NSE|
493 * +----------------------------------------------+------+
494 * 8 | Header Buffer Address [63:1] | DD |
495 * +-----------------------------------------------------+
496 *
497 *
498 * Advanced Receive Descriptor (Write-Back) Format
499 *
500 * 63 48 47 32 31 30 21 20 17 16 4 3 0
501 * +------------------------------------------------------+
502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
503 * | Checksum Ident | | | | Type | Type |
504 * +------------------------------------------------------+
505 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
506 * +------------------------------------------------------+
507 * 63 48 47 32 31 20 19 0
508 */
509
510 for (n = 0; n < adapter->num_rx_queues; n++) {
511 rx_ring = adapter->rx_ring[n];
512 pr_info("------------------------------------\n");
513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
514 pr_info("------------------------------------\n");
515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
516 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
517 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
518 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
519
520 for (i = 0; i < rx_ring->count; i++) {
521 const char *next_desc;
522 struct igb_rx_buffer *buffer_info;
523 buffer_info = &rx_ring->rx_buffer_info[i];
524 rx_desc = IGB_RX_DESC(rx_ring, i);
525 u0 = (struct my_u0 *)rx_desc;
526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
527
528 if (i == rx_ring->next_to_use)
529 next_desc = " NTU";
530 else if (i == rx_ring->next_to_clean)
531 next_desc = " NTC";
532 else
533 next_desc = "";
534
535 if (staterr & E1000_RXD_STAT_DD) {
536 /* Descriptor Done */
537 pr_info("%s[0x%03X] %016llX %016llX -------"
538 "--------- %p%s\n", "RWB", i,
539 le64_to_cpu(u0->a),
540 le64_to_cpu(u0->b),
541 buffer_info->skb, next_desc);
542 } else {
543 pr_info("%s[0x%03X] %016llX %016llX %016llX"
544 " %p%s\n", "R ", i,
545 le64_to_cpu(u0->a),
546 le64_to_cpu(u0->b),
547 (u64)buffer_info->dma,
548 buffer_info->skb, next_desc);
549
550 if (netif_msg_pktdata(adapter)) {
551 print_hex_dump(KERN_INFO, "",
552 DUMP_PREFIX_ADDRESS,
553 16, 1,
554 phys_to_virt(buffer_info->dma),
555 IGB_RX_HDR_LEN, true);
556 print_hex_dump(KERN_INFO, "",
557 DUMP_PREFIX_ADDRESS,
558 16, 1,
559 phys_to_virt(
560 buffer_info->page_dma +
561 buffer_info->page_offset),
562 PAGE_SIZE/2, true);
563 }
564 }
565 }
566 }
567
568exit:
569 return;
570}
571
572/**
573 * igb_get_hw_dev - return device
574 * used by hardware layer to print debugging information
575 **/
576struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
577{
578 struct igb_adapter *adapter = hw->back;
579 return adapter->netdev;
580}
581
582/**
583 * igb_init_module - Driver Registration Routine
584 *
585 * igb_init_module is the first routine called when the driver is
586 * loaded. All it does is register with the PCI subsystem.
587 **/
588static int __init igb_init_module(void)
589{
590 int ret;
591 pr_info("%s - version %s\n",
592 igb_driver_string, igb_driver_version);
593
594 pr_info("%s\n", igb_copyright);
595
596#ifdef CONFIG_IGB_DCA
597 dca_register_notify(&dca_notifier);
598#endif
599 ret = pci_register_driver(&igb_driver);
600 return ret;
601}
602
603module_init(igb_init_module);
604
605/**
606 * igb_exit_module - Driver Exit Cleanup Routine
607 *
608 * igb_exit_module is called just before the driver is removed
609 * from memory.
610 **/
611static void __exit igb_exit_module(void)
612{
613#ifdef CONFIG_IGB_DCA
614 dca_unregister_notify(&dca_notifier);
615#endif
616 pci_unregister_driver(&igb_driver);
617}
618
619module_exit(igb_exit_module);
620
621#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
622/**
623 * igb_cache_ring_register - Descriptor ring to register mapping
624 * @adapter: board private structure to initialize
625 *
626 * Once we know the feature-set enabled for the device, we'll cache
627 * the register offset the descriptor ring is assigned to.
628 **/
629static void igb_cache_ring_register(struct igb_adapter *adapter)
630{
631 int i = 0, j = 0;
632 u32 rbase_offset = adapter->vfs_allocated_count;
633
634 switch (adapter->hw.mac.type) {
635 case e1000_82576:
636 /* The queues are allocated for virtualization such that VF 0
637 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
638 * In order to avoid collision we start at the first free queue
639 * and continue consuming queues in the same sequence
640 */
641 if (adapter->vfs_allocated_count) {
642 for (; i < adapter->rss_queues; i++)
643 adapter->rx_ring[i]->reg_idx = rbase_offset +
644 Q_IDX_82576(i);
645 }
646 case e1000_82575:
647 case e1000_82580:
648 case e1000_i350:
649 case e1000_i210:
650 case e1000_i211:
651 default:
652 for (; i < adapter->num_rx_queues; i++)
653 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
654 for (; j < adapter->num_tx_queues; j++)
655 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
656 break;
657 }
658}
659
660static void igb_free_queues(struct igb_adapter *adapter)
661{
662 int i;
663
664 for (i = 0; i < adapter->num_tx_queues; i++) {
665 kfree(adapter->tx_ring[i]);
666 adapter->tx_ring[i] = NULL;
667 }
668 for (i = 0; i < adapter->num_rx_queues; i++) {
669 kfree(adapter->rx_ring[i]);
670 adapter->rx_ring[i] = NULL;
671 }
672 adapter->num_rx_queues = 0;
673 adapter->num_tx_queues = 0;
674}
675
676/**
677 * igb_alloc_queues - Allocate memory for all rings
678 * @adapter: board private structure to initialize
679 *
680 * We allocate one ring per queue at run-time since we don't know the
681 * number of queues at compile-time.
682 **/
683static int igb_alloc_queues(struct igb_adapter *adapter)
684{
685 struct igb_ring *ring;
686 int i;
687 int orig_node = adapter->node;
688
689 for (i = 0; i < adapter->num_tx_queues; i++) {
690 if (orig_node == -1) {
691 int cur_node = next_online_node(adapter->node);
692 if (cur_node == MAX_NUMNODES)
693 cur_node = first_online_node;
694 adapter->node = cur_node;
695 }
696 ring = kzalloc_node(sizeof(struct igb_ring), GFP_KERNEL,
697 adapter->node);
698 if (!ring)
699 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
700 if (!ring)
701 goto err;
702 ring->count = adapter->tx_ring_count;
703 ring->queue_index = i;
704 ring->dev = &adapter->pdev->dev;
705 ring->netdev = adapter->netdev;
706 ring->numa_node = adapter->node;
707 /* For 82575, context index must be unique per ring. */
708 if (adapter->hw.mac.type == e1000_82575)
709 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
710 adapter->tx_ring[i] = ring;
711 }
712 /* Restore the adapter's original node */
713 adapter->node = orig_node;
714
715 for (i = 0; i < adapter->num_rx_queues; i++) {
716 if (orig_node == -1) {
717 int cur_node = next_online_node(adapter->node);
718 if (cur_node == MAX_NUMNODES)
719 cur_node = first_online_node;
720 adapter->node = cur_node;
721 }
722 ring = kzalloc_node(sizeof(struct igb_ring), GFP_KERNEL,
723 adapter->node);
724 if (!ring)
725 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
726 if (!ring)
727 goto err;
728 ring->count = adapter->rx_ring_count;
729 ring->queue_index = i;
730 ring->dev = &adapter->pdev->dev;
731 ring->netdev = adapter->netdev;
732 ring->numa_node = adapter->node;
733 /* set flag indicating ring supports SCTP checksum offload */
734 if (adapter->hw.mac.type >= e1000_82576)
735 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
736
737 /*
738 * On i350, i210, and i211, loopback VLAN packets
739 * have the tag byte-swapped.
740 * */
741 if (adapter->hw.mac.type >= e1000_i350)
742 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
743
744 adapter->rx_ring[i] = ring;
745 }
746 /* Restore the adapter's original node */
747 adapter->node = orig_node;
748
749 igb_cache_ring_register(adapter);
750
751 return 0;
752
753err:
754 /* Restore the adapter's original node */
755 adapter->node = orig_node;
756 igb_free_queues(adapter);
757
758 return -ENOMEM;
759}
760
761/**
762 * igb_write_ivar - configure ivar for given MSI-X vector
763 * @hw: pointer to the HW structure
764 * @msix_vector: vector number we are allocating to a given ring
765 * @index: row index of IVAR register to write within IVAR table
766 * @offset: column offset of in IVAR, should be multiple of 8
767 *
768 * This function is intended to handle the writing of the IVAR register
769 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
770 * each containing an cause allocation for an Rx and Tx ring, and a
771 * variable number of rows depending on the number of queues supported.
772 **/
773static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
774 int index, int offset)
775{
776 u32 ivar = array_rd32(E1000_IVAR0, index);
777
778 /* clear any bits that are currently set */
779 ivar &= ~((u32)0xFF << offset);
780
781 /* write vector and valid bit */
782 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
783
784 array_wr32(E1000_IVAR0, index, ivar);
785}
786
787#define IGB_N0_QUEUE -1
788static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
789{
790 struct igb_adapter *adapter = q_vector->adapter;
791 struct e1000_hw *hw = &adapter->hw;
792 int rx_queue = IGB_N0_QUEUE;
793 int tx_queue = IGB_N0_QUEUE;
794 u32 msixbm = 0;
795
796 if (q_vector->rx.ring)
797 rx_queue = q_vector->rx.ring->reg_idx;
798 if (q_vector->tx.ring)
799 tx_queue = q_vector->tx.ring->reg_idx;
800
801 switch (hw->mac.type) {
802 case e1000_82575:
803 /* The 82575 assigns vectors using a bitmask, which matches the
804 bitmask for the EICR/EIMS/EIMC registers. To assign one
805 or more queues to a vector, we write the appropriate bits
806 into the MSIXBM register for that vector. */
807 if (rx_queue > IGB_N0_QUEUE)
808 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
809 if (tx_queue > IGB_N0_QUEUE)
810 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
811 if (!adapter->msix_entries && msix_vector == 0)
812 msixbm |= E1000_EIMS_OTHER;
813 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
814 q_vector->eims_value = msixbm;
815 break;
816 case e1000_82576:
817 /*
818 * 82576 uses a table that essentially consists of 2 columns
819 * with 8 rows. The ordering is column-major so we use the
820 * lower 3 bits as the row index, and the 4th bit as the
821 * column offset.
822 */
823 if (rx_queue > IGB_N0_QUEUE)
824 igb_write_ivar(hw, msix_vector,
825 rx_queue & 0x7,
826 (rx_queue & 0x8) << 1);
827 if (tx_queue > IGB_N0_QUEUE)
828 igb_write_ivar(hw, msix_vector,
829 tx_queue & 0x7,
830 ((tx_queue & 0x8) << 1) + 8);
831 q_vector->eims_value = 1 << msix_vector;
832 break;
833 case e1000_82580:
834 case e1000_i350:
835 case e1000_i210:
836 case e1000_i211:
837 /*
838 * On 82580 and newer adapters the scheme is similar to 82576
839 * however instead of ordering column-major we have things
840 * ordered row-major. So we traverse the table by using
841 * bit 0 as the column offset, and the remaining bits as the
842 * row index.
843 */
844 if (rx_queue > IGB_N0_QUEUE)
845 igb_write_ivar(hw, msix_vector,
846 rx_queue >> 1,
847 (rx_queue & 0x1) << 4);
848 if (tx_queue > IGB_N0_QUEUE)
849 igb_write_ivar(hw, msix_vector,
850 tx_queue >> 1,
851 ((tx_queue & 0x1) << 4) + 8);
852 q_vector->eims_value = 1 << msix_vector;
853 break;
854 default:
855 BUG();
856 break;
857 }
858
859 /* add q_vector eims value to global eims_enable_mask */
860 adapter->eims_enable_mask |= q_vector->eims_value;
861
862 /* configure q_vector to set itr on first interrupt */
863 q_vector->set_itr = 1;
864}
865
866/**
867 * igb_configure_msix - Configure MSI-X hardware
868 *
869 * igb_configure_msix sets up the hardware to properly
870 * generate MSI-X interrupts.
871 **/
872static void igb_configure_msix(struct igb_adapter *adapter)
873{
874 u32 tmp;
875 int i, vector = 0;
876 struct e1000_hw *hw = &adapter->hw;
877
878 adapter->eims_enable_mask = 0;
879
880 /* set vector for other causes, i.e. link changes */
881 switch (hw->mac.type) {
882 case e1000_82575:
883 tmp = rd32(E1000_CTRL_EXT);
884 /* enable MSI-X PBA support*/
885 tmp |= E1000_CTRL_EXT_PBA_CLR;
886
887 /* Auto-Mask interrupts upon ICR read. */
888 tmp |= E1000_CTRL_EXT_EIAME;
889 tmp |= E1000_CTRL_EXT_IRCA;
890
891 wr32(E1000_CTRL_EXT, tmp);
892
893 /* enable msix_other interrupt */
894 array_wr32(E1000_MSIXBM(0), vector++,
895 E1000_EIMS_OTHER);
896 adapter->eims_other = E1000_EIMS_OTHER;
897
898 break;
899
900 case e1000_82576:
901 case e1000_82580:
902 case e1000_i350:
903 case e1000_i210:
904 case e1000_i211:
905 /* Turn on MSI-X capability first, or our settings
906 * won't stick. And it will take days to debug. */
907 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
908 E1000_GPIE_PBA | E1000_GPIE_EIAME |
909 E1000_GPIE_NSICR);
910
911 /* enable msix_other interrupt */
912 adapter->eims_other = 1 << vector;
913 tmp = (vector++ | E1000_IVAR_VALID) << 8;
914
915 wr32(E1000_IVAR_MISC, tmp);
916 break;
917 default:
918 /* do nothing, since nothing else supports MSI-X */
919 break;
920 } /* switch (hw->mac.type) */
921
922 adapter->eims_enable_mask |= adapter->eims_other;
923
924 for (i = 0; i < adapter->num_q_vectors; i++)
925 igb_assign_vector(adapter->q_vector[i], vector++);
926
927 wrfl();
928}
929
930/**
931 * igb_request_msix - Initialize MSI-X interrupts
932 *
933 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
934 * kernel.
935 **/
936static int igb_request_msix(struct igb_adapter *adapter)
937{
938 struct net_device *netdev = adapter->netdev;
939 struct e1000_hw *hw = &adapter->hw;
940 int i, err = 0, vector = 0;
941
942 err = request_irq(adapter->msix_entries[vector].vector,
943 igb_msix_other, 0, netdev->name, adapter);
944 if (err)
945 goto out;
946 vector++;
947
948 for (i = 0; i < adapter->num_q_vectors; i++) {
949 struct igb_q_vector *q_vector = adapter->q_vector[i];
950
951 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
952
953 if (q_vector->rx.ring && q_vector->tx.ring)
954 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
955 q_vector->rx.ring->queue_index);
956 else if (q_vector->tx.ring)
957 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
958 q_vector->tx.ring->queue_index);
959 else if (q_vector->rx.ring)
960 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
961 q_vector->rx.ring->queue_index);
962 else
963 sprintf(q_vector->name, "%s-unused", netdev->name);
964
965 err = request_irq(adapter->msix_entries[vector].vector,
966 igb_msix_ring, 0, q_vector->name,
967 q_vector);
968 if (err)
969 goto out;
970 vector++;
971 }
972
973 igb_configure_msix(adapter);
974 return 0;
975out:
976 return err;
977}
978
979static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
980{
981 if (adapter->msix_entries) {
982 pci_disable_msix(adapter->pdev);
983 kfree(adapter->msix_entries);
984 adapter->msix_entries = NULL;
985 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
986 pci_disable_msi(adapter->pdev);
987 }
988}
989
990/**
991 * igb_free_q_vectors - Free memory allocated for interrupt vectors
992 * @adapter: board private structure to initialize
993 *
994 * This function frees the memory allocated to the q_vectors. In addition if
995 * NAPI is enabled it will delete any references to the NAPI struct prior
996 * to freeing the q_vector.
997 **/
998static void igb_free_q_vectors(struct igb_adapter *adapter)
999{
1000 int v_idx;
1001
1002 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1003 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1004 adapter->q_vector[v_idx] = NULL;
1005 if (!q_vector)
1006 continue;
1007 netif_napi_del(&q_vector->napi);
1008 kfree(q_vector);
1009 }
1010 adapter->num_q_vectors = 0;
1011}
1012
1013/**
1014 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1015 *
1016 * This function resets the device so that it has 0 rx queues, tx queues, and
1017 * MSI-X interrupts allocated.
1018 */
1019static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1020{
1021 igb_free_queues(adapter);
1022 igb_free_q_vectors(adapter);
1023 igb_reset_interrupt_capability(adapter);
1024}
1025
1026/**
1027 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1028 *
1029 * Attempt to configure interrupts using the best available
1030 * capabilities of the hardware and kernel.
1031 **/
1032static int igb_set_interrupt_capability(struct igb_adapter *adapter)
1033{
1034 int err;
1035 int numvecs, i;
1036
1037 /* Number of supported queues. */
1038 adapter->num_rx_queues = adapter->rss_queues;
1039 if (adapter->vfs_allocated_count)
1040 adapter->num_tx_queues = 1;
1041 else
1042 adapter->num_tx_queues = adapter->rss_queues;
1043
1044 /* start with one vector for every rx queue */
1045 numvecs = adapter->num_rx_queues;
1046
1047 /* if tx handler is separate add 1 for every tx queue */
1048 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1049 numvecs += adapter->num_tx_queues;
1050
1051 /* i210 and i211 can only have 4 MSIX vectors for rx/tx queues. */
1052 if ((adapter->hw.mac.type == e1000_i210)
1053 || (adapter->hw.mac.type == e1000_i211))
1054 numvecs = 4;
1055
1056 /* store the number of vectors reserved for queues */
1057 adapter->num_q_vectors = numvecs;
1058
1059 /* add 1 vector for link status interrupts */
1060 numvecs++;
1061 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1062 GFP_KERNEL);
1063
1064 if (!adapter->msix_entries)
1065 goto msi_only;
1066
1067 for (i = 0; i < numvecs; i++)
1068 adapter->msix_entries[i].entry = i;
1069
1070 err = pci_enable_msix(adapter->pdev,
1071 adapter->msix_entries,
1072 numvecs);
1073 if (err == 0)
1074 goto out;
1075
1076 igb_reset_interrupt_capability(adapter);
1077
1078 /* If we can't do MSI-X, try MSI */
1079msi_only:
1080#ifdef CONFIG_PCI_IOV
1081 /* disable SR-IOV for non MSI-X configurations */
1082 if (adapter->vf_data) {
1083 struct e1000_hw *hw = &adapter->hw;
1084 /* disable iov and allow time for transactions to clear */
1085 pci_disable_sriov(adapter->pdev);
1086 msleep(500);
1087
1088 kfree(adapter->vf_data);
1089 adapter->vf_data = NULL;
1090 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1091 wrfl();
1092 msleep(100);
1093 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1094 }
1095#endif
1096 adapter->vfs_allocated_count = 0;
1097 adapter->rss_queues = 1;
1098 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1099 adapter->num_rx_queues = 1;
1100 adapter->num_tx_queues = 1;
1101 adapter->num_q_vectors = 1;
1102 if (!pci_enable_msi(adapter->pdev))
1103 adapter->flags |= IGB_FLAG_HAS_MSI;
1104out:
1105 /* Notify the stack of the (possibly) reduced queue counts. */
1106 rtnl_lock();
1107 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
1108 err = netif_set_real_num_rx_queues(adapter->netdev,
1109 adapter->num_rx_queues);
1110 rtnl_unlock();
1111 return err;
1112}
1113
1114/**
1115 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1116 * @adapter: board private structure to initialize
1117 *
1118 * We allocate one q_vector per queue interrupt. If allocation fails we
1119 * return -ENOMEM.
1120 **/
1121static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1122{
1123 struct igb_q_vector *q_vector;
1124 struct e1000_hw *hw = &adapter->hw;
1125 int v_idx;
1126 int orig_node = adapter->node;
1127
1128 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1129 if ((adapter->num_q_vectors == (adapter->num_rx_queues +
1130 adapter->num_tx_queues)) &&
1131 (adapter->num_rx_queues == v_idx))
1132 adapter->node = orig_node;
1133 if (orig_node == -1) {
1134 int cur_node = next_online_node(adapter->node);
1135 if (cur_node == MAX_NUMNODES)
1136 cur_node = first_online_node;
1137 adapter->node = cur_node;
1138 }
1139 q_vector = kzalloc_node(sizeof(struct igb_q_vector), GFP_KERNEL,
1140 adapter->node);
1141 if (!q_vector)
1142 q_vector = kzalloc(sizeof(struct igb_q_vector),
1143 GFP_KERNEL);
1144 if (!q_vector)
1145 goto err_out;
1146 q_vector->adapter = adapter;
1147 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
1148 q_vector->itr_val = IGB_START_ITR;
1149 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
1150 adapter->q_vector[v_idx] = q_vector;
1151 }
1152 /* Restore the adapter's original node */
1153 adapter->node = orig_node;
1154
1155 return 0;
1156
1157err_out:
1158 /* Restore the adapter's original node */
1159 adapter->node = orig_node;
1160 igb_free_q_vectors(adapter);
1161 return -ENOMEM;
1162}
1163
1164static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
1165 int ring_idx, int v_idx)
1166{
1167 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1168
1169 q_vector->rx.ring = adapter->rx_ring[ring_idx];
1170 q_vector->rx.ring->q_vector = q_vector;
1171 q_vector->rx.count++;
1172 q_vector->itr_val = adapter->rx_itr_setting;
1173 if (q_vector->itr_val && q_vector->itr_val <= 3)
1174 q_vector->itr_val = IGB_START_ITR;
1175}
1176
1177static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
1178 int ring_idx, int v_idx)
1179{
1180 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1181
1182 q_vector->tx.ring = adapter->tx_ring[ring_idx];
1183 q_vector->tx.ring->q_vector = q_vector;
1184 q_vector->tx.count++;
1185 q_vector->itr_val = adapter->tx_itr_setting;
1186 q_vector->tx.work_limit = adapter->tx_work_limit;
1187 if (q_vector->itr_val && q_vector->itr_val <= 3)
1188 q_vector->itr_val = IGB_START_ITR;
1189}
1190
1191/**
1192 * igb_map_ring_to_vector - maps allocated queues to vectors
1193 *
1194 * This function maps the recently allocated queues to vectors.
1195 **/
1196static int igb_map_ring_to_vector(struct igb_adapter *adapter)
1197{
1198 int i;
1199 int v_idx = 0;
1200
1201 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
1202 (adapter->num_q_vectors < adapter->num_tx_queues))
1203 return -ENOMEM;
1204
1205 if (adapter->num_q_vectors >=
1206 (adapter->num_rx_queues + adapter->num_tx_queues)) {
1207 for (i = 0; i < adapter->num_rx_queues; i++)
1208 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1209 for (i = 0; i < adapter->num_tx_queues; i++)
1210 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1211 } else {
1212 for (i = 0; i < adapter->num_rx_queues; i++) {
1213 if (i < adapter->num_tx_queues)
1214 igb_map_tx_ring_to_vector(adapter, i, v_idx);
1215 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1216 }
1217 for (; i < adapter->num_tx_queues; i++)
1218 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1219 }
1220 return 0;
1221}
1222
1223/**
1224 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1225 *
1226 * This function initializes the interrupts and allocates all of the queues.
1227 **/
1228static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1229{
1230 struct pci_dev *pdev = adapter->pdev;
1231 int err;
1232
1233 err = igb_set_interrupt_capability(adapter);
1234 if (err)
1235 return err;
1236
1237 err = igb_alloc_q_vectors(adapter);
1238 if (err) {
1239 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1240 goto err_alloc_q_vectors;
1241 }
1242
1243 err = igb_alloc_queues(adapter);
1244 if (err) {
1245 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1246 goto err_alloc_queues;
1247 }
1248
1249 err = igb_map_ring_to_vector(adapter);
1250 if (err) {
1251 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
1252 goto err_map_queues;
1253 }
1254
1255
1256 return 0;
1257err_map_queues:
1258 igb_free_queues(adapter);
1259err_alloc_queues:
1260 igb_free_q_vectors(adapter);
1261err_alloc_q_vectors:
1262 igb_reset_interrupt_capability(adapter);
1263 return err;
1264}
1265
1266/**
1267 * igb_request_irq - initialize interrupts
1268 *
1269 * Attempts to configure interrupts using the best available
1270 * capabilities of the hardware and kernel.
1271 **/
1272static int igb_request_irq(struct igb_adapter *adapter)
1273{
1274 struct net_device *netdev = adapter->netdev;
1275 struct pci_dev *pdev = adapter->pdev;
1276 int err = 0;
1277
1278 if (adapter->msix_entries) {
1279 err = igb_request_msix(adapter);
1280 if (!err)
1281 goto request_done;
1282 /* fall back to MSI */
1283 igb_clear_interrupt_scheme(adapter);
1284 if (!pci_enable_msi(pdev))
1285 adapter->flags |= IGB_FLAG_HAS_MSI;
1286 igb_free_all_tx_resources(adapter);
1287 igb_free_all_rx_resources(adapter);
1288 adapter->num_tx_queues = 1;
1289 adapter->num_rx_queues = 1;
1290 adapter->num_q_vectors = 1;
1291 err = igb_alloc_q_vectors(adapter);
1292 if (err) {
1293 dev_err(&pdev->dev,
1294 "Unable to allocate memory for vectors\n");
1295 goto request_done;
1296 }
1297 err = igb_alloc_queues(adapter);
1298 if (err) {
1299 dev_err(&pdev->dev,
1300 "Unable to allocate memory for queues\n");
1301 igb_free_q_vectors(adapter);
1302 goto request_done;
1303 }
1304 igb_setup_all_tx_resources(adapter);
1305 igb_setup_all_rx_resources(adapter);
1306 }
1307
1308 igb_assign_vector(adapter->q_vector[0], 0);
1309
1310 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1311 err = request_irq(pdev->irq, igb_intr_msi, 0,
1312 netdev->name, adapter);
1313 if (!err)
1314 goto request_done;
1315
1316 /* fall back to legacy interrupts */
1317 igb_reset_interrupt_capability(adapter);
1318 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1319 }
1320
1321 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1322 netdev->name, adapter);
1323
1324 if (err)
1325 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1326 err);
1327
1328request_done:
1329 return err;
1330}
1331
1332static void igb_free_irq(struct igb_adapter *adapter)
1333{
1334 if (adapter->msix_entries) {
1335 int vector = 0, i;
1336
1337 free_irq(adapter->msix_entries[vector++].vector, adapter);
1338
1339 for (i = 0; i < adapter->num_q_vectors; i++)
1340 free_irq(adapter->msix_entries[vector++].vector,
1341 adapter->q_vector[i]);
1342 } else {
1343 free_irq(adapter->pdev->irq, adapter);
1344 }
1345}
1346
1347/**
1348 * igb_irq_disable - Mask off interrupt generation on the NIC
1349 * @adapter: board private structure
1350 **/
1351static void igb_irq_disable(struct igb_adapter *adapter)
1352{
1353 struct e1000_hw *hw = &adapter->hw;
1354
1355 /*
1356 * we need to be careful when disabling interrupts. The VFs are also
1357 * mapped into these registers and so clearing the bits can cause
1358 * issues on the VF drivers so we only need to clear what we set
1359 */
1360 if (adapter->msix_entries) {
1361 u32 regval = rd32(E1000_EIAM);
1362 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1363 wr32(E1000_EIMC, adapter->eims_enable_mask);
1364 regval = rd32(E1000_EIAC);
1365 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1366 }
1367
1368 wr32(E1000_IAM, 0);
1369 wr32(E1000_IMC, ~0);
1370 wrfl();
1371 if (adapter->msix_entries) {
1372 int i;
1373 for (i = 0; i < adapter->num_q_vectors; i++)
1374 synchronize_irq(adapter->msix_entries[i].vector);
1375 } else {
1376 synchronize_irq(adapter->pdev->irq);
1377 }
1378}
1379
1380/**
1381 * igb_irq_enable - Enable default interrupt generation settings
1382 * @adapter: board private structure
1383 **/
1384static void igb_irq_enable(struct igb_adapter *adapter)
1385{
1386 struct e1000_hw *hw = &adapter->hw;
1387
1388 if (adapter->msix_entries) {
1389 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1390 u32 regval = rd32(E1000_EIAC);
1391 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1392 regval = rd32(E1000_EIAM);
1393 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1394 wr32(E1000_EIMS, adapter->eims_enable_mask);
1395 if (adapter->vfs_allocated_count) {
1396 wr32(E1000_MBVFIMR, 0xFF);
1397 ims |= E1000_IMS_VMMB;
1398 }
1399 wr32(E1000_IMS, ims);
1400 } else {
1401 wr32(E1000_IMS, IMS_ENABLE_MASK |
1402 E1000_IMS_DRSTA);
1403 wr32(E1000_IAM, IMS_ENABLE_MASK |
1404 E1000_IMS_DRSTA);
1405 }
1406}
1407
1408static void igb_update_mng_vlan(struct igb_adapter *adapter)
1409{
1410 struct e1000_hw *hw = &adapter->hw;
1411 u16 vid = adapter->hw.mng_cookie.vlan_id;
1412 u16 old_vid = adapter->mng_vlan_id;
1413
1414 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1415 /* add VID to filter table */
1416 igb_vfta_set(hw, vid, true);
1417 adapter->mng_vlan_id = vid;
1418 } else {
1419 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1420 }
1421
1422 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1423 (vid != old_vid) &&
1424 !test_bit(old_vid, adapter->active_vlans)) {
1425 /* remove VID from filter table */
1426 igb_vfta_set(hw, old_vid, false);
1427 }
1428}
1429
1430/**
1431 * igb_release_hw_control - release control of the h/w to f/w
1432 * @adapter: address of board private structure
1433 *
1434 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1435 * For ASF and Pass Through versions of f/w this means that the
1436 * driver is no longer loaded.
1437 *
1438 **/
1439static void igb_release_hw_control(struct igb_adapter *adapter)
1440{
1441 struct e1000_hw *hw = &adapter->hw;
1442 u32 ctrl_ext;
1443
1444 /* Let firmware take over control of h/w */
1445 ctrl_ext = rd32(E1000_CTRL_EXT);
1446 wr32(E1000_CTRL_EXT,
1447 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1448}
1449
1450/**
1451 * igb_get_hw_control - get control of the h/w from f/w
1452 * @adapter: address of board private structure
1453 *
1454 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1455 * For ASF and Pass Through versions of f/w this means that
1456 * the driver is loaded.
1457 *
1458 **/
1459static void igb_get_hw_control(struct igb_adapter *adapter)
1460{
1461 struct e1000_hw *hw = &adapter->hw;
1462 u32 ctrl_ext;
1463
1464 /* Let firmware know the driver has taken over */
1465 ctrl_ext = rd32(E1000_CTRL_EXT);
1466 wr32(E1000_CTRL_EXT,
1467 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1468}
1469
1470/**
1471 * igb_configure - configure the hardware for RX and TX
1472 * @adapter: private board structure
1473 **/
1474static void igb_configure(struct igb_adapter *adapter)
1475{
1476 struct net_device *netdev = adapter->netdev;
1477 int i;
1478
1479 igb_get_hw_control(adapter);
1480 igb_set_rx_mode(netdev);
1481
1482 igb_restore_vlan(adapter);
1483
1484 igb_setup_tctl(adapter);
1485 igb_setup_mrqc(adapter);
1486 igb_setup_rctl(adapter);
1487
1488 igb_configure_tx(adapter);
1489 igb_configure_rx(adapter);
1490
1491 igb_rx_fifo_flush_82575(&adapter->hw);
1492
1493 /* call igb_desc_unused which always leaves
1494 * at least 1 descriptor unused to make sure
1495 * next_to_use != next_to_clean */
1496 for (i = 0; i < adapter->num_rx_queues; i++) {
1497 struct igb_ring *ring = adapter->rx_ring[i];
1498 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1499 }
1500}
1501
1502/**
1503 * igb_power_up_link - Power up the phy/serdes link
1504 * @adapter: address of board private structure
1505 **/
1506void igb_power_up_link(struct igb_adapter *adapter)
1507{
1508 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1509 igb_power_up_phy_copper(&adapter->hw);
1510 else
1511 igb_power_up_serdes_link_82575(&adapter->hw);
1512 igb_reset_phy(&adapter->hw);
1513}
1514
1515/**
1516 * igb_power_down_link - Power down the phy/serdes link
1517 * @adapter: address of board private structure
1518 */
1519static void igb_power_down_link(struct igb_adapter *adapter)
1520{
1521 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1522 igb_power_down_phy_copper_82575(&adapter->hw);
1523 else
1524 igb_shutdown_serdes_link_82575(&adapter->hw);
1525}
1526
1527/**
1528 * igb_up - Open the interface and prepare it to handle traffic
1529 * @adapter: board private structure
1530 **/
1531int igb_up(struct igb_adapter *adapter)
1532{
1533 struct e1000_hw *hw = &adapter->hw;
1534 int i;
1535
1536 /* hardware has been reset, we need to reload some things */
1537 igb_configure(adapter);
1538
1539 clear_bit(__IGB_DOWN, &adapter->state);
1540
1541 for (i = 0; i < adapter->num_q_vectors; i++)
1542 napi_enable(&(adapter->q_vector[i]->napi));
1543
1544 if (adapter->msix_entries)
1545 igb_configure_msix(adapter);
1546 else
1547 igb_assign_vector(adapter->q_vector[0], 0);
1548
1549 /* Clear any pending interrupts. */
1550 rd32(E1000_ICR);
1551 igb_irq_enable(adapter);
1552
1553 /* notify VFs that reset has been completed */
1554 if (adapter->vfs_allocated_count) {
1555 u32 reg_data = rd32(E1000_CTRL_EXT);
1556 reg_data |= E1000_CTRL_EXT_PFRSTD;
1557 wr32(E1000_CTRL_EXT, reg_data);
1558 }
1559
1560 netif_tx_start_all_queues(adapter->netdev);
1561
1562 /* start the watchdog. */
1563 hw->mac.get_link_status = 1;
1564 schedule_work(&adapter->watchdog_task);
1565
1566 return 0;
1567}
1568
1569void igb_down(struct igb_adapter *adapter)
1570{
1571 struct net_device *netdev = adapter->netdev;
1572 struct e1000_hw *hw = &adapter->hw;
1573 u32 tctl, rctl;
1574 int i;
1575
1576 /* signal that we're down so the interrupt handler does not
1577 * reschedule our watchdog timer */
1578 set_bit(__IGB_DOWN, &adapter->state);
1579
1580 /* disable receives in the hardware */
1581 rctl = rd32(E1000_RCTL);
1582 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1583 /* flush and sleep below */
1584
1585 netif_tx_stop_all_queues(netdev);
1586
1587 /* disable transmits in the hardware */
1588 tctl = rd32(E1000_TCTL);
1589 tctl &= ~E1000_TCTL_EN;
1590 wr32(E1000_TCTL, tctl);
1591 /* flush both disables and wait for them to finish */
1592 wrfl();
1593 msleep(10);
1594
1595 for (i = 0; i < adapter->num_q_vectors; i++)
1596 napi_disable(&(adapter->q_vector[i]->napi));
1597
1598 igb_irq_disable(adapter);
1599
1600 del_timer_sync(&adapter->watchdog_timer);
1601 del_timer_sync(&adapter->phy_info_timer);
1602
1603 netif_carrier_off(netdev);
1604
1605 /* record the stats before reset*/
1606 spin_lock(&adapter->stats64_lock);
1607 igb_update_stats(adapter, &adapter->stats64);
1608 spin_unlock(&adapter->stats64_lock);
1609
1610 adapter->link_speed = 0;
1611 adapter->link_duplex = 0;
1612
1613 if (!pci_channel_offline(adapter->pdev))
1614 igb_reset(adapter);
1615 igb_clean_all_tx_rings(adapter);
1616 igb_clean_all_rx_rings(adapter);
1617#ifdef CONFIG_IGB_DCA
1618
1619 /* since we reset the hardware DCA settings were cleared */
1620 igb_setup_dca(adapter);
1621#endif
1622}
1623
1624void igb_reinit_locked(struct igb_adapter *adapter)
1625{
1626 WARN_ON(in_interrupt());
1627 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1628 msleep(1);
1629 igb_down(adapter);
1630 igb_up(adapter);
1631 clear_bit(__IGB_RESETTING, &adapter->state);
1632}
1633
1634void igb_reset(struct igb_adapter *adapter)
1635{
1636 struct pci_dev *pdev = adapter->pdev;
1637 struct e1000_hw *hw = &adapter->hw;
1638 struct e1000_mac_info *mac = &hw->mac;
1639 struct e1000_fc_info *fc = &hw->fc;
1640 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1641 u16 hwm;
1642
1643 /* Repartition Pba for greater than 9k mtu
1644 * To take effect CTRL.RST is required.
1645 */
1646 switch (mac->type) {
1647 case e1000_i350:
1648 case e1000_82580:
1649 pba = rd32(E1000_RXPBS);
1650 pba = igb_rxpbs_adjust_82580(pba);
1651 break;
1652 case e1000_82576:
1653 pba = rd32(E1000_RXPBS);
1654 pba &= E1000_RXPBS_SIZE_MASK_82576;
1655 break;
1656 case e1000_82575:
1657 case e1000_i210:
1658 case e1000_i211:
1659 default:
1660 pba = E1000_PBA_34K;
1661 break;
1662 }
1663
1664 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1665 (mac->type < e1000_82576)) {
1666 /* adjust PBA for jumbo frames */
1667 wr32(E1000_PBA, pba);
1668
1669 /* To maintain wire speed transmits, the Tx FIFO should be
1670 * large enough to accommodate two full transmit packets,
1671 * rounded up to the next 1KB and expressed in KB. Likewise,
1672 * the Rx FIFO should be large enough to accommodate at least
1673 * one full receive packet and is similarly rounded up and
1674 * expressed in KB. */
1675 pba = rd32(E1000_PBA);
1676 /* upper 16 bits has Tx packet buffer allocation size in KB */
1677 tx_space = pba >> 16;
1678 /* lower 16 bits has Rx packet buffer allocation size in KB */
1679 pba &= 0xffff;
1680 /* the tx fifo also stores 16 bytes of information about the tx
1681 * but don't include ethernet FCS because hardware appends it */
1682 min_tx_space = (adapter->max_frame_size +
1683 sizeof(union e1000_adv_tx_desc) -
1684 ETH_FCS_LEN) * 2;
1685 min_tx_space = ALIGN(min_tx_space, 1024);
1686 min_tx_space >>= 10;
1687 /* software strips receive CRC, so leave room for it */
1688 min_rx_space = adapter->max_frame_size;
1689 min_rx_space = ALIGN(min_rx_space, 1024);
1690 min_rx_space >>= 10;
1691
1692 /* If current Tx allocation is less than the min Tx FIFO size,
1693 * and the min Tx FIFO size is less than the current Rx FIFO
1694 * allocation, take space away from current Rx allocation */
1695 if (tx_space < min_tx_space &&
1696 ((min_tx_space - tx_space) < pba)) {
1697 pba = pba - (min_tx_space - tx_space);
1698
1699 /* if short on rx space, rx wins and must trump tx
1700 * adjustment */
1701 if (pba < min_rx_space)
1702 pba = min_rx_space;
1703 }
1704 wr32(E1000_PBA, pba);
1705 }
1706
1707 /* flow control settings */
1708 /* The high water mark must be low enough to fit one full frame
1709 * (or the size used for early receive) above it in the Rx FIFO.
1710 * Set it to the lower of:
1711 * - 90% of the Rx FIFO size, or
1712 * - the full Rx FIFO size minus one full frame */
1713 hwm = min(((pba << 10) * 9 / 10),
1714 ((pba << 10) - 2 * adapter->max_frame_size));
1715
1716 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1717 fc->low_water = fc->high_water - 16;
1718 fc->pause_time = 0xFFFF;
1719 fc->send_xon = 1;
1720 fc->current_mode = fc->requested_mode;
1721
1722 /* disable receive for all VFs and wait one second */
1723 if (adapter->vfs_allocated_count) {
1724 int i;
1725 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1726 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1727
1728 /* ping all the active vfs to let them know we are going down */
1729 igb_ping_all_vfs(adapter);
1730
1731 /* disable transmits and receives */
1732 wr32(E1000_VFRE, 0);
1733 wr32(E1000_VFTE, 0);
1734 }
1735
1736 /* Allow time for pending master requests to run */
1737 hw->mac.ops.reset_hw(hw);
1738 wr32(E1000_WUC, 0);
1739
1740 if (hw->mac.ops.init_hw(hw))
1741 dev_err(&pdev->dev, "Hardware Error\n");
1742
1743 /*
1744 * Flow control settings reset on hardware reset, so guarantee flow
1745 * control is off when forcing speed.
1746 */
1747 if (!hw->mac.autoneg)
1748 igb_force_mac_fc(hw);
1749
1750 igb_init_dmac(adapter, pba);
1751 if (!netif_running(adapter->netdev))
1752 igb_power_down_link(adapter);
1753
1754 igb_update_mng_vlan(adapter);
1755
1756 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1757 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1758
1759 igb_get_phy_info(hw);
1760}
1761
1762static netdev_features_t igb_fix_features(struct net_device *netdev,
1763 netdev_features_t features)
1764{
1765 /*
1766 * Since there is no support for separate rx/tx vlan accel
1767 * enable/disable make sure tx flag is always in same state as rx.
1768 */
1769 if (features & NETIF_F_HW_VLAN_RX)
1770 features |= NETIF_F_HW_VLAN_TX;
1771 else
1772 features &= ~NETIF_F_HW_VLAN_TX;
1773
1774 return features;
1775}
1776
1777static int igb_set_features(struct net_device *netdev,
1778 netdev_features_t features)
1779{
1780 netdev_features_t changed = netdev->features ^ features;
1781 struct igb_adapter *adapter = netdev_priv(netdev);
1782
1783 if (changed & NETIF_F_HW_VLAN_RX)
1784 igb_vlan_mode(netdev, features);
1785
1786 if (!(changed & NETIF_F_RXALL))
1787 return 0;
1788
1789 netdev->features = features;
1790
1791 if (netif_running(netdev))
1792 igb_reinit_locked(adapter);
1793 else
1794 igb_reset(adapter);
1795
1796 return 0;
1797}
1798
1799static const struct net_device_ops igb_netdev_ops = {
1800 .ndo_open = igb_open,
1801 .ndo_stop = igb_close,
1802 .ndo_start_xmit = igb_xmit_frame,
1803 .ndo_get_stats64 = igb_get_stats64,
1804 .ndo_set_rx_mode = igb_set_rx_mode,
1805 .ndo_set_mac_address = igb_set_mac,
1806 .ndo_change_mtu = igb_change_mtu,
1807 .ndo_do_ioctl = igb_ioctl,
1808 .ndo_tx_timeout = igb_tx_timeout,
1809 .ndo_validate_addr = eth_validate_addr,
1810 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1811 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1812 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1813 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1814 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1815 .ndo_get_vf_config = igb_ndo_get_vf_config,
1816#ifdef CONFIG_NET_POLL_CONTROLLER
1817 .ndo_poll_controller = igb_netpoll,
1818#endif
1819 .ndo_fix_features = igb_fix_features,
1820 .ndo_set_features = igb_set_features,
1821};
1822
1823/**
1824 * igb_probe - Device Initialization Routine
1825 * @pdev: PCI device information struct
1826 * @ent: entry in igb_pci_tbl
1827 *
1828 * Returns 0 on success, negative on failure
1829 *
1830 * igb_probe initializes an adapter identified by a pci_dev structure.
1831 * The OS initialization, configuring of the adapter private structure,
1832 * and a hardware reset occur.
1833 **/
1834static int __devinit igb_probe(struct pci_dev *pdev,
1835 const struct pci_device_id *ent)
1836{
1837 struct net_device *netdev;
1838 struct igb_adapter *adapter;
1839 struct e1000_hw *hw;
1840 u16 eeprom_data = 0;
1841 s32 ret_val;
1842 static int global_quad_port_a; /* global quad port a indication */
1843 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1844 unsigned long mmio_start, mmio_len;
1845 int err, pci_using_dac;
1846 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1847 u8 part_str[E1000_PBANUM_LENGTH];
1848
1849 /* Catch broken hardware that put the wrong VF device ID in
1850 * the PCIe SR-IOV capability.
1851 */
1852 if (pdev->is_virtfn) {
1853 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1854 pci_name(pdev), pdev->vendor, pdev->device);
1855 return -EINVAL;
1856 }
1857
1858 err = pci_enable_device_mem(pdev);
1859 if (err)
1860 return err;
1861
1862 pci_using_dac = 0;
1863 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1864 if (!err) {
1865 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1866 if (!err)
1867 pci_using_dac = 1;
1868 } else {
1869 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1870 if (err) {
1871 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1872 if (err) {
1873 dev_err(&pdev->dev, "No usable DMA "
1874 "configuration, aborting\n");
1875 goto err_dma;
1876 }
1877 }
1878 }
1879
1880 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1881 IORESOURCE_MEM),
1882 igb_driver_name);
1883 if (err)
1884 goto err_pci_reg;
1885
1886 pci_enable_pcie_error_reporting(pdev);
1887
1888 pci_set_master(pdev);
1889 pci_save_state(pdev);
1890
1891 err = -ENOMEM;
1892 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1893 IGB_MAX_TX_QUEUES);
1894 if (!netdev)
1895 goto err_alloc_etherdev;
1896
1897 SET_NETDEV_DEV(netdev, &pdev->dev);
1898
1899 pci_set_drvdata(pdev, netdev);
1900 adapter = netdev_priv(netdev);
1901 adapter->netdev = netdev;
1902 adapter->pdev = pdev;
1903 hw = &adapter->hw;
1904 hw->back = adapter;
1905 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1906
1907 mmio_start = pci_resource_start(pdev, 0);
1908 mmio_len = pci_resource_len(pdev, 0);
1909
1910 err = -EIO;
1911 hw->hw_addr = ioremap(mmio_start, mmio_len);
1912 if (!hw->hw_addr)
1913 goto err_ioremap;
1914
1915 netdev->netdev_ops = &igb_netdev_ops;
1916 igb_set_ethtool_ops(netdev);
1917 netdev->watchdog_timeo = 5 * HZ;
1918
1919 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1920
1921 netdev->mem_start = mmio_start;
1922 netdev->mem_end = mmio_start + mmio_len;
1923
1924 /* PCI config space info */
1925 hw->vendor_id = pdev->vendor;
1926 hw->device_id = pdev->device;
1927 hw->revision_id = pdev->revision;
1928 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1929 hw->subsystem_device_id = pdev->subsystem_device;
1930
1931 /* Copy the default MAC, PHY and NVM function pointers */
1932 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1933 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1934 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1935 /* Initialize skew-specific constants */
1936 err = ei->get_invariants(hw);
1937 if (err)
1938 goto err_sw_init;
1939
1940 /* setup the private structure */
1941 err = igb_sw_init(adapter);
1942 if (err)
1943 goto err_sw_init;
1944
1945 igb_get_bus_info_pcie(hw);
1946
1947 hw->phy.autoneg_wait_to_complete = false;
1948
1949 /* Copper options */
1950 if (hw->phy.media_type == e1000_media_type_copper) {
1951 hw->phy.mdix = AUTO_ALL_MODES;
1952 hw->phy.disable_polarity_correction = false;
1953 hw->phy.ms_type = e1000_ms_hw_default;
1954 }
1955
1956 if (igb_check_reset_block(hw))
1957 dev_info(&pdev->dev,
1958 "PHY reset is blocked due to SOL/IDER session.\n");
1959
1960 /*
1961 * features is initialized to 0 in allocation, it might have bits
1962 * set by igb_sw_init so we should use an or instead of an
1963 * assignment.
1964 */
1965 netdev->features |= NETIF_F_SG |
1966 NETIF_F_IP_CSUM |
1967 NETIF_F_IPV6_CSUM |
1968 NETIF_F_TSO |
1969 NETIF_F_TSO6 |
1970 NETIF_F_RXHASH |
1971 NETIF_F_RXCSUM |
1972 NETIF_F_HW_VLAN_RX |
1973 NETIF_F_HW_VLAN_TX;
1974
1975 /* copy netdev features into list of user selectable features */
1976 netdev->hw_features |= netdev->features;
1977 netdev->hw_features |= NETIF_F_RXALL;
1978
1979 /* set this bit last since it cannot be part of hw_features */
1980 netdev->features |= NETIF_F_HW_VLAN_FILTER;
1981
1982 netdev->vlan_features |= NETIF_F_TSO |
1983 NETIF_F_TSO6 |
1984 NETIF_F_IP_CSUM |
1985 NETIF_F_IPV6_CSUM |
1986 NETIF_F_SG;
1987
1988 netdev->priv_flags |= IFF_SUPP_NOFCS;
1989
1990 if (pci_using_dac) {
1991 netdev->features |= NETIF_F_HIGHDMA;
1992 netdev->vlan_features |= NETIF_F_HIGHDMA;
1993 }
1994
1995 if (hw->mac.type >= e1000_82576) {
1996 netdev->hw_features |= NETIF_F_SCTP_CSUM;
1997 netdev->features |= NETIF_F_SCTP_CSUM;
1998 }
1999
2000 netdev->priv_flags |= IFF_UNICAST_FLT;
2001
2002 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2003
2004 /* before reading the NVM, reset the controller to put the device in a
2005 * known good starting state */
2006 hw->mac.ops.reset_hw(hw);
2007
2008 /*
2009 * make sure the NVM is good , i211 parts have special NVM that
2010 * doesn't contain a checksum
2011 */
2012 if (hw->mac.type != e1000_i211) {
2013 if (hw->nvm.ops.validate(hw) < 0) {
2014 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2015 err = -EIO;
2016 goto err_eeprom;
2017 }
2018 }
2019
2020 /* copy the MAC address out of the NVM */
2021 if (hw->mac.ops.read_mac_addr(hw))
2022 dev_err(&pdev->dev, "NVM Read Error\n");
2023
2024 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2025 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
2026
2027 if (!is_valid_ether_addr(netdev->perm_addr)) {
2028 dev_err(&pdev->dev, "Invalid MAC Address\n");
2029 err = -EIO;
2030 goto err_eeprom;
2031 }
2032
2033 setup_timer(&adapter->watchdog_timer, igb_watchdog,
2034 (unsigned long) adapter);
2035 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2036 (unsigned long) adapter);
2037
2038 INIT_WORK(&adapter->reset_task, igb_reset_task);
2039 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2040
2041 /* Initialize link properties that are user-changeable */
2042 adapter->fc_autoneg = true;
2043 hw->mac.autoneg = true;
2044 hw->phy.autoneg_advertised = 0x2f;
2045
2046 hw->fc.requested_mode = e1000_fc_default;
2047 hw->fc.current_mode = e1000_fc_default;
2048
2049 igb_validate_mdi_setting(hw);
2050
2051 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
2052 * enable the ACPI Magic Packet filter
2053 */
2054
2055 if (hw->bus.func == 0)
2056 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
2057 else if (hw->mac.type >= e1000_82580)
2058 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2059 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2060 &eeprom_data);
2061 else if (hw->bus.func == 1)
2062 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2063
2064 if (eeprom_data & eeprom_apme_mask)
2065 adapter->eeprom_wol |= E1000_WUFC_MAG;
2066
2067 /* now that we have the eeprom settings, apply the special cases where
2068 * the eeprom may be wrong or the board simply won't support wake on
2069 * lan on a particular port */
2070 switch (pdev->device) {
2071 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2072 adapter->eeprom_wol = 0;
2073 break;
2074 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2075 case E1000_DEV_ID_82576_FIBER:
2076 case E1000_DEV_ID_82576_SERDES:
2077 /* Wake events only supported on port A for dual fiber
2078 * regardless of eeprom setting */
2079 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2080 adapter->eeprom_wol = 0;
2081 break;
2082 case E1000_DEV_ID_82576_QUAD_COPPER:
2083 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2084 /* if quad port adapter, disable WoL on all but port A */
2085 if (global_quad_port_a != 0)
2086 adapter->eeprom_wol = 0;
2087 else
2088 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2089 /* Reset for multiple quad port adapters */
2090 if (++global_quad_port_a == 4)
2091 global_quad_port_a = 0;
2092 break;
2093 }
2094
2095 /* initialize the wol settings based on the eeprom settings */
2096 adapter->wol = adapter->eeprom_wol;
2097 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2098
2099 /* reset the hardware with the new settings */
2100 igb_reset(adapter);
2101
2102 /* let the f/w know that the h/w is now under the control of the
2103 * driver. */
2104 igb_get_hw_control(adapter);
2105
2106 strcpy(netdev->name, "eth%d");
2107 err = register_netdev(netdev);
2108 if (err)
2109 goto err_register;
2110
2111 /* carrier off reporting is important to ethtool even BEFORE open */
2112 netif_carrier_off(netdev);
2113
2114#ifdef CONFIG_IGB_DCA
2115 if (dca_add_requester(&pdev->dev) == 0) {
2116 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2117 dev_info(&pdev->dev, "DCA enabled\n");
2118 igb_setup_dca(adapter);
2119 }
2120
2121#endif
2122#ifdef CONFIG_IGB_PTP
2123 /* do hw tstamp init after resetting */
2124 igb_ptp_init(adapter);
2125
2126#endif
2127 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2128 /* print bus type/speed/width info */
2129 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2130 netdev->name,
2131 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2132 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2133 "unknown"),
2134 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2135 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2136 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2137 "unknown"),
2138 netdev->dev_addr);
2139
2140 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2141 if (ret_val)
2142 strcpy(part_str, "Unknown");
2143 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2144 dev_info(&pdev->dev,
2145 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2146 adapter->msix_entries ? "MSI-X" :
2147 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2148 adapter->num_rx_queues, adapter->num_tx_queues);
2149 switch (hw->mac.type) {
2150 case e1000_i350:
2151 case e1000_i210:
2152 case e1000_i211:
2153 igb_set_eee_i350(hw);
2154 break;
2155 default:
2156 break;
2157 }
2158
2159 pm_runtime_put_noidle(&pdev->dev);
2160 return 0;
2161
2162err_register:
2163 igb_release_hw_control(adapter);
2164err_eeprom:
2165 if (!igb_check_reset_block(hw))
2166 igb_reset_phy(hw);
2167
2168 if (hw->flash_address)
2169 iounmap(hw->flash_address);
2170err_sw_init:
2171 igb_clear_interrupt_scheme(adapter);
2172 iounmap(hw->hw_addr);
2173err_ioremap:
2174 free_netdev(netdev);
2175err_alloc_etherdev:
2176 pci_release_selected_regions(pdev,
2177 pci_select_bars(pdev, IORESOURCE_MEM));
2178err_pci_reg:
2179err_dma:
2180 pci_disable_device(pdev);
2181 return err;
2182}
2183
2184/**
2185 * igb_remove - Device Removal Routine
2186 * @pdev: PCI device information struct
2187 *
2188 * igb_remove is called by the PCI subsystem to alert the driver
2189 * that it should release a PCI device. The could be caused by a
2190 * Hot-Plug event, or because the driver is going to be removed from
2191 * memory.
2192 **/
2193static void __devexit igb_remove(struct pci_dev *pdev)
2194{
2195 struct net_device *netdev = pci_get_drvdata(pdev);
2196 struct igb_adapter *adapter = netdev_priv(netdev);
2197 struct e1000_hw *hw = &adapter->hw;
2198
2199 pm_runtime_get_noresume(&pdev->dev);
2200#ifdef CONFIG_IGB_PTP
2201 igb_ptp_remove(adapter);
2202
2203#endif
2204 /*
2205 * The watchdog timer may be rescheduled, so explicitly
2206 * disable watchdog from being rescheduled.
2207 */
2208 set_bit(__IGB_DOWN, &adapter->state);
2209 del_timer_sync(&adapter->watchdog_timer);
2210 del_timer_sync(&adapter->phy_info_timer);
2211
2212 cancel_work_sync(&adapter->reset_task);
2213 cancel_work_sync(&adapter->watchdog_task);
2214
2215#ifdef CONFIG_IGB_DCA
2216 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2217 dev_info(&pdev->dev, "DCA disabled\n");
2218 dca_remove_requester(&pdev->dev);
2219 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2220 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2221 }
2222#endif
2223
2224 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2225 * would have already happened in close and is redundant. */
2226 igb_release_hw_control(adapter);
2227
2228 unregister_netdev(netdev);
2229
2230 igb_clear_interrupt_scheme(adapter);
2231
2232#ifdef CONFIG_PCI_IOV
2233 /* reclaim resources allocated to VFs */
2234 if (adapter->vf_data) {
2235 /* disable iov and allow time for transactions to clear */
2236 if (!igb_check_vf_assignment(adapter)) {
2237 pci_disable_sriov(pdev);
2238 msleep(500);
2239 } else {
2240 dev_info(&pdev->dev, "VF(s) assigned to guests!\n");
2241 }
2242
2243 kfree(adapter->vf_data);
2244 adapter->vf_data = NULL;
2245 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2246 wrfl();
2247 msleep(100);
2248 dev_info(&pdev->dev, "IOV Disabled\n");
2249 }
2250#endif
2251
2252 iounmap(hw->hw_addr);
2253 if (hw->flash_address)
2254 iounmap(hw->flash_address);
2255 pci_release_selected_regions(pdev,
2256 pci_select_bars(pdev, IORESOURCE_MEM));
2257
2258 kfree(adapter->shadow_vfta);
2259 free_netdev(netdev);
2260
2261 pci_disable_pcie_error_reporting(pdev);
2262
2263 pci_disable_device(pdev);
2264}
2265
2266/**
2267 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2268 * @adapter: board private structure to initialize
2269 *
2270 * This function initializes the vf specific data storage and then attempts to
2271 * allocate the VFs. The reason for ordering it this way is because it is much
2272 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2273 * the memory for the VFs.
2274 **/
2275static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2276{
2277#ifdef CONFIG_PCI_IOV
2278 struct pci_dev *pdev = adapter->pdev;
2279 struct e1000_hw *hw = &adapter->hw;
2280 int old_vfs = igb_find_enabled_vfs(adapter);
2281 int i;
2282
2283 /* Virtualization features not supported on i210 family. */
2284 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2285 return;
2286
2287 if (old_vfs) {
2288 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2289 "max_vfs setting of %d\n", old_vfs, max_vfs);
2290 adapter->vfs_allocated_count = old_vfs;
2291 }
2292
2293 if (!adapter->vfs_allocated_count)
2294 return;
2295
2296 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2297 sizeof(struct vf_data_storage), GFP_KERNEL);
2298
2299 /* if allocation failed then we do not support SR-IOV */
2300 if (!adapter->vf_data) {
2301 adapter->vfs_allocated_count = 0;
2302 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2303 "Data Storage\n");
2304 goto out;
2305 }
2306
2307 if (!old_vfs) {
2308 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2309 goto err_out;
2310 }
2311 dev_info(&pdev->dev, "%d VFs allocated\n",
2312 adapter->vfs_allocated_count);
2313 for (i = 0; i < adapter->vfs_allocated_count; i++)
2314 igb_vf_configure(adapter, i);
2315
2316 /* DMA Coalescing is not supported in IOV mode. */
2317 adapter->flags &= ~IGB_FLAG_DMAC;
2318 goto out;
2319err_out:
2320 kfree(adapter->vf_data);
2321 adapter->vf_data = NULL;
2322 adapter->vfs_allocated_count = 0;
2323out:
2324 return;
2325#endif /* CONFIG_PCI_IOV */
2326}
2327
2328/**
2329 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2330 * @adapter: board private structure to initialize
2331 *
2332 * igb_sw_init initializes the Adapter private data structure.
2333 * Fields are initialized based on PCI device information and
2334 * OS network device settings (MTU size).
2335 **/
2336static int __devinit igb_sw_init(struct igb_adapter *adapter)
2337{
2338 struct e1000_hw *hw = &adapter->hw;
2339 struct net_device *netdev = adapter->netdev;
2340 struct pci_dev *pdev = adapter->pdev;
2341
2342 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2343
2344 /* set default ring sizes */
2345 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2346 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2347
2348 /* set default ITR values */
2349 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2350 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2351
2352 /* set default work limits */
2353 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2354
2355 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2356 VLAN_HLEN;
2357 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2358
2359 adapter->node = -1;
2360
2361 spin_lock_init(&adapter->stats64_lock);
2362#ifdef CONFIG_PCI_IOV
2363 switch (hw->mac.type) {
2364 case e1000_82576:
2365 case e1000_i350:
2366 if (max_vfs > 7) {
2367 dev_warn(&pdev->dev,
2368 "Maximum of 7 VFs per PF, using max\n");
2369 adapter->vfs_allocated_count = 7;
2370 } else
2371 adapter->vfs_allocated_count = max_vfs;
2372 break;
2373 case e1000_i210:
2374 case e1000_i211:
2375 adapter->vfs_allocated_count = 0;
2376 break;
2377 default:
2378 break;
2379 }
2380#endif /* CONFIG_PCI_IOV */
2381 switch (hw->mac.type) {
2382 case e1000_i210:
2383 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES_I210,
2384 num_online_cpus());
2385 break;
2386 case e1000_i211:
2387 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES_I211,
2388 num_online_cpus());
2389 break;
2390 default:
2391 adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES,
2392 num_online_cpus());
2393 break;
2394 }
2395 /* i350 cannot do RSS and SR-IOV at the same time */
2396 if (hw->mac.type == e1000_i350 && adapter->vfs_allocated_count)
2397 adapter->rss_queues = 1;
2398
2399 /*
2400 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
2401 * then we should combine the queues into a queue pair in order to
2402 * conserve interrupts due to limited supply
2403 */
2404 if ((adapter->rss_queues > 4) ||
2405 ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
2406 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2407
2408 /* Setup and initialize a copy of the hw vlan table array */
2409 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2410 E1000_VLAN_FILTER_TBL_SIZE,
2411 GFP_ATOMIC);
2412
2413 /* This call may decrease the number of queues */
2414 if (igb_init_interrupt_scheme(adapter)) {
2415 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2416 return -ENOMEM;
2417 }
2418
2419 igb_probe_vfs(adapter);
2420
2421 /* Explicitly disable IRQ since the NIC can be in any state. */
2422 igb_irq_disable(adapter);
2423
2424 if (hw->mac.type >= e1000_i350)
2425 adapter->flags &= ~IGB_FLAG_DMAC;
2426
2427 set_bit(__IGB_DOWN, &adapter->state);
2428 return 0;
2429}
2430
2431/**
2432 * igb_open - Called when a network interface is made active
2433 * @netdev: network interface device structure
2434 *
2435 * Returns 0 on success, negative value on failure
2436 *
2437 * The open entry point is called when a network interface is made
2438 * active by the system (IFF_UP). At this point all resources needed
2439 * for transmit and receive operations are allocated, the interrupt
2440 * handler is registered with the OS, the watchdog timer is started,
2441 * and the stack is notified that the interface is ready.
2442 **/
2443static int __igb_open(struct net_device *netdev, bool resuming)
2444{
2445 struct igb_adapter *adapter = netdev_priv(netdev);
2446 struct e1000_hw *hw = &adapter->hw;
2447 struct pci_dev *pdev = adapter->pdev;
2448 int err;
2449 int i;
2450
2451 /* disallow open during test */
2452 if (test_bit(__IGB_TESTING, &adapter->state)) {
2453 WARN_ON(resuming);
2454 return -EBUSY;
2455 }
2456
2457 if (!resuming)
2458 pm_runtime_get_sync(&pdev->dev);
2459
2460 netif_carrier_off(netdev);
2461
2462 /* allocate transmit descriptors */
2463 err = igb_setup_all_tx_resources(adapter);
2464 if (err)
2465 goto err_setup_tx;
2466
2467 /* allocate receive descriptors */
2468 err = igb_setup_all_rx_resources(adapter);
2469 if (err)
2470 goto err_setup_rx;
2471
2472 igb_power_up_link(adapter);
2473
2474 /* before we allocate an interrupt, we must be ready to handle it.
2475 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2476 * as soon as we call pci_request_irq, so we have to setup our
2477 * clean_rx handler before we do so. */
2478 igb_configure(adapter);
2479
2480 err = igb_request_irq(adapter);
2481 if (err)
2482 goto err_req_irq;
2483
2484 /* From here on the code is the same as igb_up() */
2485 clear_bit(__IGB_DOWN, &adapter->state);
2486
2487 for (i = 0; i < adapter->num_q_vectors; i++)
2488 napi_enable(&(adapter->q_vector[i]->napi));
2489
2490 /* Clear any pending interrupts. */
2491 rd32(E1000_ICR);
2492
2493 igb_irq_enable(adapter);
2494
2495 /* notify VFs that reset has been completed */
2496 if (adapter->vfs_allocated_count) {
2497 u32 reg_data = rd32(E1000_CTRL_EXT);
2498 reg_data |= E1000_CTRL_EXT_PFRSTD;
2499 wr32(E1000_CTRL_EXT, reg_data);
2500 }
2501
2502 netif_tx_start_all_queues(netdev);
2503
2504 if (!resuming)
2505 pm_runtime_put(&pdev->dev);
2506
2507 /* start the watchdog. */
2508 hw->mac.get_link_status = 1;
2509 schedule_work(&adapter->watchdog_task);
2510
2511 return 0;
2512
2513err_req_irq:
2514 igb_release_hw_control(adapter);
2515 igb_power_down_link(adapter);
2516 igb_free_all_rx_resources(adapter);
2517err_setup_rx:
2518 igb_free_all_tx_resources(adapter);
2519err_setup_tx:
2520 igb_reset(adapter);
2521 if (!resuming)
2522 pm_runtime_put(&pdev->dev);
2523
2524 return err;
2525}
2526
2527static int igb_open(struct net_device *netdev)
2528{
2529 return __igb_open(netdev, false);
2530}
2531
2532/**
2533 * igb_close - Disables a network interface
2534 * @netdev: network interface device structure
2535 *
2536 * Returns 0, this is not allowed to fail
2537 *
2538 * The close entry point is called when an interface is de-activated
2539 * by the OS. The hardware is still under the driver's control, but
2540 * needs to be disabled. A global MAC reset is issued to stop the
2541 * hardware, and all transmit and receive resources are freed.
2542 **/
2543static int __igb_close(struct net_device *netdev, bool suspending)
2544{
2545 struct igb_adapter *adapter = netdev_priv(netdev);
2546 struct pci_dev *pdev = adapter->pdev;
2547
2548 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2549
2550 if (!suspending)
2551 pm_runtime_get_sync(&pdev->dev);
2552
2553 igb_down(adapter);
2554 igb_free_irq(adapter);
2555
2556 igb_free_all_tx_resources(adapter);
2557 igb_free_all_rx_resources(adapter);
2558
2559 if (!suspending)
2560 pm_runtime_put_sync(&pdev->dev);
2561 return 0;
2562}
2563
2564static int igb_close(struct net_device *netdev)
2565{
2566 return __igb_close(netdev, false);
2567}
2568
2569/**
2570 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2571 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2572 *
2573 * Return 0 on success, negative on failure
2574 **/
2575int igb_setup_tx_resources(struct igb_ring *tx_ring)
2576{
2577 struct device *dev = tx_ring->dev;
2578 int orig_node = dev_to_node(dev);
2579 int size;
2580
2581 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2582 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
2583 if (!tx_ring->tx_buffer_info)
2584 tx_ring->tx_buffer_info = vzalloc(size);
2585 if (!tx_ring->tx_buffer_info)
2586 goto err;
2587
2588 /* round up to nearest 4K */
2589 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2590 tx_ring->size = ALIGN(tx_ring->size, 4096);
2591
2592 set_dev_node(dev, tx_ring->numa_node);
2593 tx_ring->desc = dma_alloc_coherent(dev,
2594 tx_ring->size,
2595 &tx_ring->dma,
2596 GFP_KERNEL);
2597 set_dev_node(dev, orig_node);
2598 if (!tx_ring->desc)
2599 tx_ring->desc = dma_alloc_coherent(dev,
2600 tx_ring->size,
2601 &tx_ring->dma,
2602 GFP_KERNEL);
2603
2604 if (!tx_ring->desc)
2605 goto err;
2606
2607 tx_ring->next_to_use = 0;
2608 tx_ring->next_to_clean = 0;
2609
2610 return 0;
2611
2612err:
2613 vfree(tx_ring->tx_buffer_info);
2614 dev_err(dev,
2615 "Unable to allocate memory for the transmit descriptor ring\n");
2616 return -ENOMEM;
2617}
2618
2619/**
2620 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2621 * (Descriptors) for all queues
2622 * @adapter: board private structure
2623 *
2624 * Return 0 on success, negative on failure
2625 **/
2626static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2627{
2628 struct pci_dev *pdev = adapter->pdev;
2629 int i, err = 0;
2630
2631 for (i = 0; i < adapter->num_tx_queues; i++) {
2632 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2633 if (err) {
2634 dev_err(&pdev->dev,
2635 "Allocation for Tx Queue %u failed\n", i);
2636 for (i--; i >= 0; i--)
2637 igb_free_tx_resources(adapter->tx_ring[i]);
2638 break;
2639 }
2640 }
2641
2642 return err;
2643}
2644
2645/**
2646 * igb_setup_tctl - configure the transmit control registers
2647 * @adapter: Board private structure
2648 **/
2649void igb_setup_tctl(struct igb_adapter *adapter)
2650{
2651 struct e1000_hw *hw = &adapter->hw;
2652 u32 tctl;
2653
2654 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2655 wr32(E1000_TXDCTL(0), 0);
2656
2657 /* Program the Transmit Control Register */
2658 tctl = rd32(E1000_TCTL);
2659 tctl &= ~E1000_TCTL_CT;
2660 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2661 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2662
2663 igb_config_collision_dist(hw);
2664
2665 /* Enable transmits */
2666 tctl |= E1000_TCTL_EN;
2667
2668 wr32(E1000_TCTL, tctl);
2669}
2670
2671/**
2672 * igb_configure_tx_ring - Configure transmit ring after Reset
2673 * @adapter: board private structure
2674 * @ring: tx ring to configure
2675 *
2676 * Configure a transmit ring after a reset.
2677 **/
2678void igb_configure_tx_ring(struct igb_adapter *adapter,
2679 struct igb_ring *ring)
2680{
2681 struct e1000_hw *hw = &adapter->hw;
2682 u32 txdctl = 0;
2683 u64 tdba = ring->dma;
2684 int reg_idx = ring->reg_idx;
2685
2686 /* disable the queue */
2687 wr32(E1000_TXDCTL(reg_idx), 0);
2688 wrfl();
2689 mdelay(10);
2690
2691 wr32(E1000_TDLEN(reg_idx),
2692 ring->count * sizeof(union e1000_adv_tx_desc));
2693 wr32(E1000_TDBAL(reg_idx),
2694 tdba & 0x00000000ffffffffULL);
2695 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2696
2697 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2698 wr32(E1000_TDH(reg_idx), 0);
2699 writel(0, ring->tail);
2700
2701 txdctl |= IGB_TX_PTHRESH;
2702 txdctl |= IGB_TX_HTHRESH << 8;
2703 txdctl |= IGB_TX_WTHRESH << 16;
2704
2705 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2706 wr32(E1000_TXDCTL(reg_idx), txdctl);
2707}
2708
2709/**
2710 * igb_configure_tx - Configure transmit Unit after Reset
2711 * @adapter: board private structure
2712 *
2713 * Configure the Tx unit of the MAC after a reset.
2714 **/
2715static void igb_configure_tx(struct igb_adapter *adapter)
2716{
2717 int i;
2718
2719 for (i = 0; i < adapter->num_tx_queues; i++)
2720 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
2721}
2722
2723/**
2724 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2725 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2726 *
2727 * Returns 0 on success, negative on failure
2728 **/
2729int igb_setup_rx_resources(struct igb_ring *rx_ring)
2730{
2731 struct device *dev = rx_ring->dev;
2732 int orig_node = dev_to_node(dev);
2733 int size, desc_len;
2734
2735 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
2736 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
2737 if (!rx_ring->rx_buffer_info)
2738 rx_ring->rx_buffer_info = vzalloc(size);
2739 if (!rx_ring->rx_buffer_info)
2740 goto err;
2741
2742 desc_len = sizeof(union e1000_adv_rx_desc);
2743
2744 /* Round up to nearest 4K */
2745 rx_ring->size = rx_ring->count * desc_len;
2746 rx_ring->size = ALIGN(rx_ring->size, 4096);
2747
2748 set_dev_node(dev, rx_ring->numa_node);
2749 rx_ring->desc = dma_alloc_coherent(dev,
2750 rx_ring->size,
2751 &rx_ring->dma,
2752 GFP_KERNEL);
2753 set_dev_node(dev, orig_node);
2754 if (!rx_ring->desc)
2755 rx_ring->desc = dma_alloc_coherent(dev,
2756 rx_ring->size,
2757 &rx_ring->dma,
2758 GFP_KERNEL);
2759
2760 if (!rx_ring->desc)
2761 goto err;
2762
2763 rx_ring->next_to_clean = 0;
2764 rx_ring->next_to_use = 0;
2765
2766 return 0;
2767
2768err:
2769 vfree(rx_ring->rx_buffer_info);
2770 rx_ring->rx_buffer_info = NULL;
2771 dev_err(dev, "Unable to allocate memory for the receive descriptor"
2772 " ring\n");
2773 return -ENOMEM;
2774}
2775
2776/**
2777 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2778 * (Descriptors) for all queues
2779 * @adapter: board private structure
2780 *
2781 * Return 0 on success, negative on failure
2782 **/
2783static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2784{
2785 struct pci_dev *pdev = adapter->pdev;
2786 int i, err = 0;
2787
2788 for (i = 0; i < adapter->num_rx_queues; i++) {
2789 err = igb_setup_rx_resources(adapter->rx_ring[i]);
2790 if (err) {
2791 dev_err(&pdev->dev,
2792 "Allocation for Rx Queue %u failed\n", i);
2793 for (i--; i >= 0; i--)
2794 igb_free_rx_resources(adapter->rx_ring[i]);
2795 break;
2796 }
2797 }
2798
2799 return err;
2800}
2801
2802/**
2803 * igb_setup_mrqc - configure the multiple receive queue control registers
2804 * @adapter: Board private structure
2805 **/
2806static void igb_setup_mrqc(struct igb_adapter *adapter)
2807{
2808 struct e1000_hw *hw = &adapter->hw;
2809 u32 mrqc, rxcsum;
2810 u32 j, num_rx_queues, shift = 0, shift2 = 0;
2811 union e1000_reta {
2812 u32 dword;
2813 u8 bytes[4];
2814 } reta;
2815 static const u8 rsshash[40] = {
2816 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
2817 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
2818 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
2819 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };
2820
2821 /* Fill out hash function seeds */
2822 for (j = 0; j < 10; j++) {
2823 u32 rsskey = rsshash[(j * 4)];
2824 rsskey |= rsshash[(j * 4) + 1] << 8;
2825 rsskey |= rsshash[(j * 4) + 2] << 16;
2826 rsskey |= rsshash[(j * 4) + 3] << 24;
2827 array_wr32(E1000_RSSRK(0), j, rsskey);
2828 }
2829
2830 num_rx_queues = adapter->rss_queues;
2831
2832 if (adapter->vfs_allocated_count) {
2833 /* 82575 and 82576 supports 2 RSS queues for VMDq */
2834 switch (hw->mac.type) {
2835 case e1000_i350:
2836 case e1000_82580:
2837 num_rx_queues = 1;
2838 shift = 0;
2839 break;
2840 case e1000_82576:
2841 shift = 3;
2842 num_rx_queues = 2;
2843 break;
2844 case e1000_82575:
2845 shift = 2;
2846 shift2 = 6;
2847 default:
2848 break;
2849 }
2850 } else {
2851 if (hw->mac.type == e1000_82575)
2852 shift = 6;
2853 }
2854
2855 for (j = 0; j < (32 * 4); j++) {
2856 reta.bytes[j & 3] = (j % num_rx_queues) << shift;
2857 if (shift2)
2858 reta.bytes[j & 3] |= num_rx_queues << shift2;
2859 if ((j & 3) == 3)
2860 wr32(E1000_RETA(j >> 2), reta.dword);
2861 }
2862
2863 /*
2864 * Disable raw packet checksumming so that RSS hash is placed in
2865 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2866 * offloads as they are enabled by default
2867 */
2868 rxcsum = rd32(E1000_RXCSUM);
2869 rxcsum |= E1000_RXCSUM_PCSD;
2870
2871 if (adapter->hw.mac.type >= e1000_82576)
2872 /* Enable Receive Checksum Offload for SCTP */
2873 rxcsum |= E1000_RXCSUM_CRCOFL;
2874
2875 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2876 wr32(E1000_RXCSUM, rxcsum);
2877 /*
2878 * Generate RSS hash based on TCP port numbers and/or
2879 * IPv4/v6 src and dst addresses since UDP cannot be
2880 * hashed reliably due to IP fragmentation
2881 */
2882
2883 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2884 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2885 E1000_MRQC_RSS_FIELD_IPV6 |
2886 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2887 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
2888
2889 /* If VMDq is enabled then we set the appropriate mode for that, else
2890 * we default to RSS so that an RSS hash is calculated per packet even
2891 * if we are only using one queue */
2892 if (adapter->vfs_allocated_count) {
2893 if (hw->mac.type > e1000_82575) {
2894 /* Set the default pool for the PF's first queue */
2895 u32 vtctl = rd32(E1000_VT_CTL);
2896 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2897 E1000_VT_CTL_DISABLE_DEF_POOL);
2898 vtctl |= adapter->vfs_allocated_count <<
2899 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2900 wr32(E1000_VT_CTL, vtctl);
2901 }
2902 if (adapter->rss_queues > 1)
2903 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2904 else
2905 mrqc |= E1000_MRQC_ENABLE_VMDQ;
2906 } else {
2907 if (hw->mac.type != e1000_i211)
2908 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
2909 }
2910 igb_vmm_control(adapter);
2911
2912 wr32(E1000_MRQC, mrqc);
2913}
2914
2915/**
2916 * igb_setup_rctl - configure the receive control registers
2917 * @adapter: Board private structure
2918 **/
2919void igb_setup_rctl(struct igb_adapter *adapter)
2920{
2921 struct e1000_hw *hw = &adapter->hw;
2922 u32 rctl;
2923
2924 rctl = rd32(E1000_RCTL);
2925
2926 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2927 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2928
2929 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2930 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2931
2932 /*
2933 * enable stripping of CRC. It's unlikely this will break BMC
2934 * redirection as it did with e1000. Newer features require
2935 * that the HW strips the CRC.
2936 */
2937 rctl |= E1000_RCTL_SECRC;
2938
2939 /* disable store bad packets and clear size bits. */
2940 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2941
2942 /* enable LPE to prevent packets larger than max_frame_size */
2943 rctl |= E1000_RCTL_LPE;
2944
2945 /* disable queue 0 to prevent tail write w/o re-config */
2946 wr32(E1000_RXDCTL(0), 0);
2947
2948 /* Attention!!! For SR-IOV PF driver operations you must enable
2949 * queue drop for all VF and PF queues to prevent head of line blocking
2950 * if an un-trusted VF does not provide descriptors to hardware.
2951 */
2952 if (adapter->vfs_allocated_count) {
2953 /* set all queue drop enable bits */
2954 wr32(E1000_QDE, ALL_QUEUES);
2955 }
2956
2957 /* This is useful for sniffing bad packets. */
2958 if (adapter->netdev->features & NETIF_F_RXALL) {
2959 /* UPE and MPE will be handled by normal PROMISC logic
2960 * in e1000e_set_rx_mode */
2961 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2962 E1000_RCTL_BAM | /* RX All Bcast Pkts */
2963 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2964
2965 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
2966 E1000_RCTL_DPF | /* Allow filtered pause */
2967 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
2968 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
2969 * and that breaks VLANs.
2970 */
2971 }
2972
2973 wr32(E1000_RCTL, rctl);
2974}
2975
2976static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2977 int vfn)
2978{
2979 struct e1000_hw *hw = &adapter->hw;
2980 u32 vmolr;
2981
2982 /* if it isn't the PF check to see if VFs are enabled and
2983 * increase the size to support vlan tags */
2984 if (vfn < adapter->vfs_allocated_count &&
2985 adapter->vf_data[vfn].vlans_enabled)
2986 size += VLAN_TAG_SIZE;
2987
2988 vmolr = rd32(E1000_VMOLR(vfn));
2989 vmolr &= ~E1000_VMOLR_RLPML_MASK;
2990 vmolr |= size | E1000_VMOLR_LPE;
2991 wr32(E1000_VMOLR(vfn), vmolr);
2992
2993 return 0;
2994}
2995
2996/**
2997 * igb_rlpml_set - set maximum receive packet size
2998 * @adapter: board private structure
2999 *
3000 * Configure maximum receivable packet size.
3001 **/
3002static void igb_rlpml_set(struct igb_adapter *adapter)
3003{
3004 u32 max_frame_size = adapter->max_frame_size;
3005 struct e1000_hw *hw = &adapter->hw;
3006 u16 pf_id = adapter->vfs_allocated_count;
3007
3008 if (pf_id) {
3009 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3010 /*
3011 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3012 * to our max jumbo frame size, in case we need to enable
3013 * jumbo frames on one of the rings later.
3014 * This will not pass over-length frames into the default
3015 * queue because it's gated by the VMOLR.RLPML.
3016 */
3017 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3018 }
3019
3020 wr32(E1000_RLPML, max_frame_size);
3021}
3022
3023static inline void igb_set_vmolr(struct igb_adapter *adapter,
3024 int vfn, bool aupe)
3025{
3026 struct e1000_hw *hw = &adapter->hw;
3027 u32 vmolr;
3028
3029 /*
3030 * This register exists only on 82576 and newer so if we are older then
3031 * we should exit and do nothing
3032 */
3033 if (hw->mac.type < e1000_82576)
3034 return;
3035
3036 vmolr = rd32(E1000_VMOLR(vfn));
3037 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3038 if (aupe)
3039 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3040 else
3041 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3042
3043 /* clear all bits that might not be set */
3044 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3045
3046 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3047 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3048 /*
3049 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3050 * multicast packets
3051 */
3052 if (vfn <= adapter->vfs_allocated_count)
3053 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3054
3055 wr32(E1000_VMOLR(vfn), vmolr);
3056}
3057
3058/**
3059 * igb_configure_rx_ring - Configure a receive ring after Reset
3060 * @adapter: board private structure
3061 * @ring: receive ring to be configured
3062 *
3063 * Configure the Rx unit of the MAC after a reset.
3064 **/
3065void igb_configure_rx_ring(struct igb_adapter *adapter,
3066 struct igb_ring *ring)
3067{
3068 struct e1000_hw *hw = &adapter->hw;
3069 u64 rdba = ring->dma;
3070 int reg_idx = ring->reg_idx;
3071 u32 srrctl = 0, rxdctl = 0;
3072
3073 /* disable the queue */
3074 wr32(E1000_RXDCTL(reg_idx), 0);
3075
3076 /* Set DMA base address registers */
3077 wr32(E1000_RDBAL(reg_idx),
3078 rdba & 0x00000000ffffffffULL);
3079 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3080 wr32(E1000_RDLEN(reg_idx),
3081 ring->count * sizeof(union e1000_adv_rx_desc));
3082
3083 /* initialize head and tail */
3084 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3085 wr32(E1000_RDH(reg_idx), 0);
3086 writel(0, ring->tail);
3087
3088 /* set descriptor configuration */
3089 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3090#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3091 srrctl |= IGB_RXBUFFER_16384 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3092#else
3093 srrctl |= (PAGE_SIZE / 2) >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3094#endif
3095 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3096 if (hw->mac.type >= e1000_82580)
3097 srrctl |= E1000_SRRCTL_TIMESTAMP;
3098 /* Only set Drop Enable if we are supporting multiple queues */
3099 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3100 srrctl |= E1000_SRRCTL_DROP_EN;
3101
3102 wr32(E1000_SRRCTL(reg_idx), srrctl);
3103
3104 /* set filtering for VMDQ pools */
3105 igb_set_vmolr(adapter, reg_idx & 0x7, true);
3106
3107 rxdctl |= IGB_RX_PTHRESH;
3108 rxdctl |= IGB_RX_HTHRESH << 8;
3109 rxdctl |= IGB_RX_WTHRESH << 16;
3110
3111 /* enable receive descriptor fetching */
3112 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3113 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3114}
3115
3116/**
3117 * igb_configure_rx - Configure receive Unit after Reset
3118 * @adapter: board private structure
3119 *
3120 * Configure the Rx unit of the MAC after a reset.
3121 **/
3122static void igb_configure_rx(struct igb_adapter *adapter)
3123{
3124 int i;
3125
3126 /* set UTA to appropriate mode */
3127 igb_set_uta(adapter);
3128
3129 /* set the correct pool for the PF default MAC address in entry 0 */
3130 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3131 adapter->vfs_allocated_count);
3132
3133 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3134 * the Base and Length of the Rx Descriptor Ring */
3135 for (i = 0; i < adapter->num_rx_queues; i++)
3136 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3137}
3138
3139/**
3140 * igb_free_tx_resources - Free Tx Resources per Queue
3141 * @tx_ring: Tx descriptor ring for a specific queue
3142 *
3143 * Free all transmit software resources
3144 **/
3145void igb_free_tx_resources(struct igb_ring *tx_ring)
3146{
3147 igb_clean_tx_ring(tx_ring);
3148
3149 vfree(tx_ring->tx_buffer_info);
3150 tx_ring->tx_buffer_info = NULL;
3151
3152 /* if not set, then don't free */
3153 if (!tx_ring->desc)
3154 return;
3155
3156 dma_free_coherent(tx_ring->dev, tx_ring->size,
3157 tx_ring->desc, tx_ring->dma);
3158
3159 tx_ring->desc = NULL;
3160}
3161
3162/**
3163 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3164 * @adapter: board private structure
3165 *
3166 * Free all transmit software resources
3167 **/
3168static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3169{
3170 int i;
3171
3172 for (i = 0; i < adapter->num_tx_queues; i++)
3173 igb_free_tx_resources(adapter->tx_ring[i]);
3174}
3175
3176void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3177 struct igb_tx_buffer *tx_buffer)
3178{
3179 if (tx_buffer->skb) {
3180 dev_kfree_skb_any(tx_buffer->skb);
3181 if (tx_buffer->dma)
3182 dma_unmap_single(ring->dev,
3183 tx_buffer->dma,
3184 tx_buffer->length,
3185 DMA_TO_DEVICE);
3186 } else if (tx_buffer->dma) {
3187 dma_unmap_page(ring->dev,
3188 tx_buffer->dma,
3189 tx_buffer->length,
3190 DMA_TO_DEVICE);
3191 }
3192 tx_buffer->next_to_watch = NULL;
3193 tx_buffer->skb = NULL;
3194 tx_buffer->dma = 0;
3195 /* buffer_info must be completely set up in the transmit path */
3196}
3197
3198/**
3199 * igb_clean_tx_ring - Free Tx Buffers
3200 * @tx_ring: ring to be cleaned
3201 **/
3202static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3203{
3204 struct igb_tx_buffer *buffer_info;
3205 unsigned long size;
3206 u16 i;
3207
3208 if (!tx_ring->tx_buffer_info)
3209 return;
3210 /* Free all the Tx ring sk_buffs */
3211
3212 for (i = 0; i < tx_ring->count; i++) {
3213 buffer_info = &tx_ring->tx_buffer_info[i];
3214 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3215 }
3216
3217 netdev_tx_reset_queue(txring_txq(tx_ring));
3218
3219 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3220 memset(tx_ring->tx_buffer_info, 0, size);
3221
3222 /* Zero out the descriptor ring */
3223 memset(tx_ring->desc, 0, tx_ring->size);
3224
3225 tx_ring->next_to_use = 0;
3226 tx_ring->next_to_clean = 0;
3227}
3228
3229/**
3230 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3231 * @adapter: board private structure
3232 **/
3233static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3234{
3235 int i;
3236
3237 for (i = 0; i < adapter->num_tx_queues; i++)
3238 igb_clean_tx_ring(adapter->tx_ring[i]);
3239}
3240
3241/**
3242 * igb_free_rx_resources - Free Rx Resources
3243 * @rx_ring: ring to clean the resources from
3244 *
3245 * Free all receive software resources
3246 **/
3247void igb_free_rx_resources(struct igb_ring *rx_ring)
3248{
3249 igb_clean_rx_ring(rx_ring);
3250
3251 vfree(rx_ring->rx_buffer_info);
3252 rx_ring->rx_buffer_info = NULL;
3253
3254 /* if not set, then don't free */
3255 if (!rx_ring->desc)
3256 return;
3257
3258 dma_free_coherent(rx_ring->dev, rx_ring->size,
3259 rx_ring->desc, rx_ring->dma);
3260
3261 rx_ring->desc = NULL;
3262}
3263
3264/**
3265 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3266 * @adapter: board private structure
3267 *
3268 * Free all receive software resources
3269 **/
3270static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3271{
3272 int i;
3273
3274 for (i = 0; i < adapter->num_rx_queues; i++)
3275 igb_free_rx_resources(adapter->rx_ring[i]);
3276}
3277
3278/**
3279 * igb_clean_rx_ring - Free Rx Buffers per Queue
3280 * @rx_ring: ring to free buffers from
3281 **/
3282static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3283{
3284 unsigned long size;
3285 u16 i;
3286
3287 if (!rx_ring->rx_buffer_info)
3288 return;
3289
3290 /* Free all the Rx ring sk_buffs */
3291 for (i = 0; i < rx_ring->count; i++) {
3292 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3293 if (buffer_info->dma) {
3294 dma_unmap_single(rx_ring->dev,
3295 buffer_info->dma,
3296 IGB_RX_HDR_LEN,
3297 DMA_FROM_DEVICE);
3298 buffer_info->dma = 0;
3299 }
3300
3301 if (buffer_info->skb) {
3302 dev_kfree_skb(buffer_info->skb);
3303 buffer_info->skb = NULL;
3304 }
3305 if (buffer_info->page_dma) {
3306 dma_unmap_page(rx_ring->dev,
3307 buffer_info->page_dma,
3308 PAGE_SIZE / 2,
3309 DMA_FROM_DEVICE);
3310 buffer_info->page_dma = 0;
3311 }
3312 if (buffer_info->page) {
3313 put_page(buffer_info->page);
3314 buffer_info->page = NULL;
3315 buffer_info->page_offset = 0;
3316 }
3317 }
3318
3319 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3320 memset(rx_ring->rx_buffer_info, 0, size);
3321
3322 /* Zero out the descriptor ring */
3323 memset(rx_ring->desc, 0, rx_ring->size);
3324
3325 rx_ring->next_to_clean = 0;
3326 rx_ring->next_to_use = 0;
3327}
3328
3329/**
3330 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3331 * @adapter: board private structure
3332 **/
3333static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3334{
3335 int i;
3336
3337 for (i = 0; i < adapter->num_rx_queues; i++)
3338 igb_clean_rx_ring(adapter->rx_ring[i]);
3339}
3340
3341/**
3342 * igb_set_mac - Change the Ethernet Address of the NIC
3343 * @netdev: network interface device structure
3344 * @p: pointer to an address structure
3345 *
3346 * Returns 0 on success, negative on failure
3347 **/
3348static int igb_set_mac(struct net_device *netdev, void *p)
3349{
3350 struct igb_adapter *adapter = netdev_priv(netdev);
3351 struct e1000_hw *hw = &adapter->hw;
3352 struct sockaddr *addr = p;
3353
3354 if (!is_valid_ether_addr(addr->sa_data))
3355 return -EADDRNOTAVAIL;
3356
3357 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3358 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3359
3360 /* set the correct pool for the new PF MAC address in entry 0 */
3361 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3362 adapter->vfs_allocated_count);
3363
3364 return 0;
3365}
3366
3367/**
3368 * igb_write_mc_addr_list - write multicast addresses to MTA
3369 * @netdev: network interface device structure
3370 *
3371 * Writes multicast address list to the MTA hash table.
3372 * Returns: -ENOMEM on failure
3373 * 0 on no addresses written
3374 * X on writing X addresses to MTA
3375 **/
3376static int igb_write_mc_addr_list(struct net_device *netdev)
3377{
3378 struct igb_adapter *adapter = netdev_priv(netdev);
3379 struct e1000_hw *hw = &adapter->hw;
3380 struct netdev_hw_addr *ha;
3381 u8 *mta_list;
3382 int i;
3383
3384 if (netdev_mc_empty(netdev)) {
3385 /* nothing to program, so clear mc list */
3386 igb_update_mc_addr_list(hw, NULL, 0);
3387 igb_restore_vf_multicasts(adapter);
3388 return 0;
3389 }
3390
3391 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3392 if (!mta_list)
3393 return -ENOMEM;
3394
3395 /* The shared function expects a packed array of only addresses. */
3396 i = 0;
3397 netdev_for_each_mc_addr(ha, netdev)
3398 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3399
3400 igb_update_mc_addr_list(hw, mta_list, i);
3401 kfree(mta_list);
3402
3403 return netdev_mc_count(netdev);
3404}
3405
3406/**
3407 * igb_write_uc_addr_list - write unicast addresses to RAR table
3408 * @netdev: network interface device structure
3409 *
3410 * Writes unicast address list to the RAR table.
3411 * Returns: -ENOMEM on failure/insufficient address space
3412 * 0 on no addresses written
3413 * X on writing X addresses to the RAR table
3414 **/
3415static int igb_write_uc_addr_list(struct net_device *netdev)
3416{
3417 struct igb_adapter *adapter = netdev_priv(netdev);
3418 struct e1000_hw *hw = &adapter->hw;
3419 unsigned int vfn = adapter->vfs_allocated_count;
3420 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3421 int count = 0;
3422
3423 /* return ENOMEM indicating insufficient memory for addresses */
3424 if (netdev_uc_count(netdev) > rar_entries)
3425 return -ENOMEM;
3426
3427 if (!netdev_uc_empty(netdev) && rar_entries) {
3428 struct netdev_hw_addr *ha;
3429
3430 netdev_for_each_uc_addr(ha, netdev) {
3431 if (!rar_entries)
3432 break;
3433 igb_rar_set_qsel(adapter, ha->addr,
3434 rar_entries--,
3435 vfn);
3436 count++;
3437 }
3438 }
3439 /* write the addresses in reverse order to avoid write combining */
3440 for (; rar_entries > 0 ; rar_entries--) {
3441 wr32(E1000_RAH(rar_entries), 0);
3442 wr32(E1000_RAL(rar_entries), 0);
3443 }
3444 wrfl();
3445
3446 return count;
3447}
3448
3449/**
3450 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3451 * @netdev: network interface device structure
3452 *
3453 * The set_rx_mode entry point is called whenever the unicast or multicast
3454 * address lists or the network interface flags are updated. This routine is
3455 * responsible for configuring the hardware for proper unicast, multicast,
3456 * promiscuous mode, and all-multi behavior.
3457 **/
3458static void igb_set_rx_mode(struct net_device *netdev)
3459{
3460 struct igb_adapter *adapter = netdev_priv(netdev);
3461 struct e1000_hw *hw = &adapter->hw;
3462 unsigned int vfn = adapter->vfs_allocated_count;
3463 u32 rctl, vmolr = 0;
3464 int count;
3465
3466 /* Check for Promiscuous and All Multicast modes */
3467 rctl = rd32(E1000_RCTL);
3468
3469 /* clear the effected bits */
3470 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3471
3472 if (netdev->flags & IFF_PROMISC) {
3473 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3474 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3475 } else {
3476 if (netdev->flags & IFF_ALLMULTI) {
3477 rctl |= E1000_RCTL_MPE;
3478 vmolr |= E1000_VMOLR_MPME;
3479 } else {
3480 /*
3481 * Write addresses to the MTA, if the attempt fails
3482 * then we should just turn on promiscuous mode so
3483 * that we can at least receive multicast traffic
3484 */
3485 count = igb_write_mc_addr_list(netdev);
3486 if (count < 0) {
3487 rctl |= E1000_RCTL_MPE;
3488 vmolr |= E1000_VMOLR_MPME;
3489 } else if (count) {
3490 vmolr |= E1000_VMOLR_ROMPE;
3491 }
3492 }
3493 /*
3494 * Write addresses to available RAR registers, if there is not
3495 * sufficient space to store all the addresses then enable
3496 * unicast promiscuous mode
3497 */
3498 count = igb_write_uc_addr_list(netdev);
3499 if (count < 0) {
3500 rctl |= E1000_RCTL_UPE;
3501 vmolr |= E1000_VMOLR_ROPE;
3502 }
3503 rctl |= E1000_RCTL_VFE;
3504 }
3505 wr32(E1000_RCTL, rctl);
3506
3507 /*
3508 * In order to support SR-IOV and eventually VMDq it is necessary to set
3509 * the VMOLR to enable the appropriate modes. Without this workaround
3510 * we will have issues with VLAN tag stripping not being done for frames
3511 * that are only arriving because we are the default pool
3512 */
3513 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3514 return;
3515
3516 vmolr |= rd32(E1000_VMOLR(vfn)) &
3517 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3518 wr32(E1000_VMOLR(vfn), vmolr);
3519 igb_restore_vf_multicasts(adapter);
3520}
3521
3522static void igb_check_wvbr(struct igb_adapter *adapter)
3523{
3524 struct e1000_hw *hw = &adapter->hw;
3525 u32 wvbr = 0;
3526
3527 switch (hw->mac.type) {
3528 case e1000_82576:
3529 case e1000_i350:
3530 if (!(wvbr = rd32(E1000_WVBR)))
3531 return;
3532 break;
3533 default:
3534 break;
3535 }
3536
3537 adapter->wvbr |= wvbr;
3538}
3539
3540#define IGB_STAGGERED_QUEUE_OFFSET 8
3541
3542static void igb_spoof_check(struct igb_adapter *adapter)
3543{
3544 int j;
3545
3546 if (!adapter->wvbr)
3547 return;
3548
3549 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3550 if (adapter->wvbr & (1 << j) ||
3551 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3552 dev_warn(&adapter->pdev->dev,
3553 "Spoof event(s) detected on VF %d\n", j);
3554 adapter->wvbr &=
3555 ~((1 << j) |
3556 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3557 }
3558 }
3559}
3560
3561/* Need to wait a few seconds after link up to get diagnostic information from
3562 * the phy */
3563static void igb_update_phy_info(unsigned long data)
3564{
3565 struct igb_adapter *adapter = (struct igb_adapter *) data;
3566 igb_get_phy_info(&adapter->hw);
3567}
3568
3569/**
3570 * igb_has_link - check shared code for link and determine up/down
3571 * @adapter: pointer to driver private info
3572 **/
3573bool igb_has_link(struct igb_adapter *adapter)
3574{
3575 struct e1000_hw *hw = &adapter->hw;
3576 bool link_active = false;
3577 s32 ret_val = 0;
3578
3579 /* get_link_status is set on LSC (link status) interrupt or
3580 * rx sequence error interrupt. get_link_status will stay
3581 * false until the e1000_check_for_link establishes link
3582 * for copper adapters ONLY
3583 */
3584 switch (hw->phy.media_type) {
3585 case e1000_media_type_copper:
3586 if (hw->mac.get_link_status) {
3587 ret_val = hw->mac.ops.check_for_link(hw);
3588 link_active = !hw->mac.get_link_status;
3589 } else {
3590 link_active = true;
3591 }
3592 break;
3593 case e1000_media_type_internal_serdes:
3594 ret_val = hw->mac.ops.check_for_link(hw);
3595 link_active = hw->mac.serdes_has_link;
3596 break;
3597 default:
3598 case e1000_media_type_unknown:
3599 break;
3600 }
3601
3602 return link_active;
3603}
3604
3605static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3606{
3607 bool ret = false;
3608 u32 ctrl_ext, thstat;
3609
3610 /* check for thermal sensor event on i350 copper only */
3611 if (hw->mac.type == e1000_i350) {
3612 thstat = rd32(E1000_THSTAT);
3613 ctrl_ext = rd32(E1000_CTRL_EXT);
3614
3615 if ((hw->phy.media_type == e1000_media_type_copper) &&
3616 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3617 ret = !!(thstat & event);
3618 }
3619 }
3620
3621 return ret;
3622}
3623
3624/**
3625 * igb_watchdog - Timer Call-back
3626 * @data: pointer to adapter cast into an unsigned long
3627 **/
3628static void igb_watchdog(unsigned long data)
3629{
3630 struct igb_adapter *adapter = (struct igb_adapter *)data;
3631 /* Do the rest outside of interrupt context */
3632 schedule_work(&adapter->watchdog_task);
3633}
3634
3635static void igb_watchdog_task(struct work_struct *work)
3636{
3637 struct igb_adapter *adapter = container_of(work,
3638 struct igb_adapter,
3639 watchdog_task);
3640 struct e1000_hw *hw = &adapter->hw;
3641 struct net_device *netdev = adapter->netdev;
3642 u32 link;
3643 int i;
3644
3645 link = igb_has_link(adapter);
3646 if (link) {
3647 /* Cancel scheduled suspend requests. */
3648 pm_runtime_resume(netdev->dev.parent);
3649
3650 if (!netif_carrier_ok(netdev)) {
3651 u32 ctrl;
3652 hw->mac.ops.get_speed_and_duplex(hw,
3653 &adapter->link_speed,
3654 &adapter->link_duplex);
3655
3656 ctrl = rd32(E1000_CTRL);
3657 /* Links status message must follow this format */
3658 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3659 "Duplex, Flow Control: %s\n",
3660 netdev->name,
3661 adapter->link_speed,
3662 adapter->link_duplex == FULL_DUPLEX ?
3663 "Full" : "Half",
3664 (ctrl & E1000_CTRL_TFCE) &&
3665 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3666 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3667 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
3668
3669 /* check for thermal sensor event */
3670 if (igb_thermal_sensor_event(hw,
3671 E1000_THSTAT_LINK_THROTTLE)) {
3672 netdev_info(netdev, "The network adapter link "
3673 "speed was downshifted because it "
3674 "overheated\n");
3675 }
3676
3677 /* adjust timeout factor according to speed/duplex */
3678 adapter->tx_timeout_factor = 1;
3679 switch (adapter->link_speed) {
3680 case SPEED_10:
3681 adapter->tx_timeout_factor = 14;
3682 break;
3683 case SPEED_100:
3684 /* maybe add some timeout factor ? */
3685 break;
3686 }
3687
3688 netif_carrier_on(netdev);
3689
3690 igb_ping_all_vfs(adapter);
3691 igb_check_vf_rate_limit(adapter);
3692
3693 /* link state has changed, schedule phy info update */
3694 if (!test_bit(__IGB_DOWN, &adapter->state))
3695 mod_timer(&adapter->phy_info_timer,
3696 round_jiffies(jiffies + 2 * HZ));
3697 }
3698 } else {
3699 if (netif_carrier_ok(netdev)) {
3700 adapter->link_speed = 0;
3701 adapter->link_duplex = 0;
3702
3703 /* check for thermal sensor event */
3704 if (igb_thermal_sensor_event(hw,
3705 E1000_THSTAT_PWR_DOWN)) {
3706 netdev_err(netdev, "The network adapter was "
3707 "stopped because it overheated\n");
3708 }
3709
3710 /* Links status message must follow this format */
3711 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3712 netdev->name);
3713 netif_carrier_off(netdev);
3714
3715 igb_ping_all_vfs(adapter);
3716
3717 /* link state has changed, schedule phy info update */
3718 if (!test_bit(__IGB_DOWN, &adapter->state))
3719 mod_timer(&adapter->phy_info_timer,
3720 round_jiffies(jiffies + 2 * HZ));
3721
3722 pm_schedule_suspend(netdev->dev.parent,
3723 MSEC_PER_SEC * 5);
3724 }
3725 }
3726
3727 spin_lock(&adapter->stats64_lock);
3728 igb_update_stats(adapter, &adapter->stats64);
3729 spin_unlock(&adapter->stats64_lock);
3730
3731 for (i = 0; i < adapter->num_tx_queues; i++) {
3732 struct igb_ring *tx_ring = adapter->tx_ring[i];
3733 if (!netif_carrier_ok(netdev)) {
3734 /* We've lost link, so the controller stops DMA,
3735 * but we've got queued Tx work that's never going
3736 * to get done, so reset controller to flush Tx.
3737 * (Do the reset outside of interrupt context). */
3738 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3739 adapter->tx_timeout_count++;
3740 schedule_work(&adapter->reset_task);
3741 /* return immediately since reset is imminent */
3742 return;
3743 }
3744 }
3745
3746 /* Force detection of hung controller every watchdog period */
3747 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
3748 }
3749
3750 /* Cause software interrupt to ensure rx ring is cleaned */
3751 if (adapter->msix_entries) {
3752 u32 eics = 0;
3753 for (i = 0; i < adapter->num_q_vectors; i++)
3754 eics |= adapter->q_vector[i]->eims_value;
3755 wr32(E1000_EICS, eics);
3756 } else {
3757 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3758 }
3759
3760 igb_spoof_check(adapter);
3761
3762 /* Reset the timer */
3763 if (!test_bit(__IGB_DOWN, &adapter->state))
3764 mod_timer(&adapter->watchdog_timer,
3765 round_jiffies(jiffies + 2 * HZ));
3766}
3767
3768enum latency_range {
3769 lowest_latency = 0,
3770 low_latency = 1,
3771 bulk_latency = 2,
3772 latency_invalid = 255
3773};
3774
3775/**
3776 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3777 *
3778 * Stores a new ITR value based on strictly on packet size. This
3779 * algorithm is less sophisticated than that used in igb_update_itr,
3780 * due to the difficulty of synchronizing statistics across multiple
3781 * receive rings. The divisors and thresholds used by this function
3782 * were determined based on theoretical maximum wire speed and testing
3783 * data, in order to minimize response time while increasing bulk
3784 * throughput.
3785 * This functionality is controlled by the InterruptThrottleRate module
3786 * parameter (see igb_param.c)
3787 * NOTE: This function is called only when operating in a multiqueue
3788 * receive environment.
3789 * @q_vector: pointer to q_vector
3790 **/
3791static void igb_update_ring_itr(struct igb_q_vector *q_vector)
3792{
3793 int new_val = q_vector->itr_val;
3794 int avg_wire_size = 0;
3795 struct igb_adapter *adapter = q_vector->adapter;
3796 unsigned int packets;
3797
3798 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3799 * ints/sec - ITR timer value of 120 ticks.
3800 */
3801 if (adapter->link_speed != SPEED_1000) {
3802 new_val = IGB_4K_ITR;
3803 goto set_itr_val;
3804 }
3805
3806 packets = q_vector->rx.total_packets;
3807 if (packets)
3808 avg_wire_size = q_vector->rx.total_bytes / packets;
3809
3810 packets = q_vector->tx.total_packets;
3811 if (packets)
3812 avg_wire_size = max_t(u32, avg_wire_size,
3813 q_vector->tx.total_bytes / packets);
3814
3815 /* if avg_wire_size isn't set no work was done */
3816 if (!avg_wire_size)
3817 goto clear_counts;
3818
3819 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3820 avg_wire_size += 24;
3821
3822 /* Don't starve jumbo frames */
3823 avg_wire_size = min(avg_wire_size, 3000);
3824
3825 /* Give a little boost to mid-size frames */
3826 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3827 new_val = avg_wire_size / 3;
3828 else
3829 new_val = avg_wire_size / 2;
3830
3831 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3832 if (new_val < IGB_20K_ITR &&
3833 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3834 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3835 new_val = IGB_20K_ITR;
3836
3837set_itr_val:
3838 if (new_val != q_vector->itr_val) {
3839 q_vector->itr_val = new_val;
3840 q_vector->set_itr = 1;
3841 }
3842clear_counts:
3843 q_vector->rx.total_bytes = 0;
3844 q_vector->rx.total_packets = 0;
3845 q_vector->tx.total_bytes = 0;
3846 q_vector->tx.total_packets = 0;
3847}
3848
3849/**
3850 * igb_update_itr - update the dynamic ITR value based on statistics
3851 * Stores a new ITR value based on packets and byte
3852 * counts during the last interrupt. The advantage of per interrupt
3853 * computation is faster updates and more accurate ITR for the current
3854 * traffic pattern. Constants in this function were computed
3855 * based on theoretical maximum wire speed and thresholds were set based
3856 * on testing data as well as attempting to minimize response time
3857 * while increasing bulk throughput.
3858 * this functionality is controlled by the InterruptThrottleRate module
3859 * parameter (see igb_param.c)
3860 * NOTE: These calculations are only valid when operating in a single-
3861 * queue environment.
3862 * @q_vector: pointer to q_vector
3863 * @ring_container: ring info to update the itr for
3864 **/
3865static void igb_update_itr(struct igb_q_vector *q_vector,
3866 struct igb_ring_container *ring_container)
3867{
3868 unsigned int packets = ring_container->total_packets;
3869 unsigned int bytes = ring_container->total_bytes;
3870 u8 itrval = ring_container->itr;
3871
3872 /* no packets, exit with status unchanged */
3873 if (packets == 0)
3874 return;
3875
3876 switch (itrval) {
3877 case lowest_latency:
3878 /* handle TSO and jumbo frames */
3879 if (bytes/packets > 8000)
3880 itrval = bulk_latency;
3881 else if ((packets < 5) && (bytes > 512))
3882 itrval = low_latency;
3883 break;
3884 case low_latency: /* 50 usec aka 20000 ints/s */
3885 if (bytes > 10000) {
3886 /* this if handles the TSO accounting */
3887 if (bytes/packets > 8000) {
3888 itrval = bulk_latency;
3889 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3890 itrval = bulk_latency;
3891 } else if ((packets > 35)) {
3892 itrval = lowest_latency;
3893 }
3894 } else if (bytes/packets > 2000) {
3895 itrval = bulk_latency;
3896 } else if (packets <= 2 && bytes < 512) {
3897 itrval = lowest_latency;
3898 }
3899 break;
3900 case bulk_latency: /* 250 usec aka 4000 ints/s */
3901 if (bytes > 25000) {
3902 if (packets > 35)
3903 itrval = low_latency;
3904 } else if (bytes < 1500) {
3905 itrval = low_latency;
3906 }
3907 break;
3908 }
3909
3910 /* clear work counters since we have the values we need */
3911 ring_container->total_bytes = 0;
3912 ring_container->total_packets = 0;
3913
3914 /* write updated itr to ring container */
3915 ring_container->itr = itrval;
3916}
3917
3918static void igb_set_itr(struct igb_q_vector *q_vector)
3919{
3920 struct igb_adapter *adapter = q_vector->adapter;
3921 u32 new_itr = q_vector->itr_val;
3922 u8 current_itr = 0;
3923
3924 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3925 if (adapter->link_speed != SPEED_1000) {
3926 current_itr = 0;
3927 new_itr = IGB_4K_ITR;
3928 goto set_itr_now;
3929 }
3930
3931 igb_update_itr(q_vector, &q_vector->tx);
3932 igb_update_itr(q_vector, &q_vector->rx);
3933
3934 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
3935
3936 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3937 if (current_itr == lowest_latency &&
3938 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3939 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3940 current_itr = low_latency;
3941
3942 switch (current_itr) {
3943 /* counts and packets in update_itr are dependent on these numbers */
3944 case lowest_latency:
3945 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
3946 break;
3947 case low_latency:
3948 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
3949 break;
3950 case bulk_latency:
3951 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
3952 break;
3953 default:
3954 break;
3955 }
3956
3957set_itr_now:
3958 if (new_itr != q_vector->itr_val) {
3959 /* this attempts to bias the interrupt rate towards Bulk
3960 * by adding intermediate steps when interrupt rate is
3961 * increasing */
3962 new_itr = new_itr > q_vector->itr_val ?
3963 max((new_itr * q_vector->itr_val) /
3964 (new_itr + (q_vector->itr_val >> 2)),
3965 new_itr) :
3966 new_itr;
3967 /* Don't write the value here; it resets the adapter's
3968 * internal timer, and causes us to delay far longer than
3969 * we should between interrupts. Instead, we write the ITR
3970 * value at the beginning of the next interrupt so the timing
3971 * ends up being correct.
3972 */
3973 q_vector->itr_val = new_itr;
3974 q_vector->set_itr = 1;
3975 }
3976}
3977
3978static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3979 u32 type_tucmd, u32 mss_l4len_idx)
3980{
3981 struct e1000_adv_tx_context_desc *context_desc;
3982 u16 i = tx_ring->next_to_use;
3983
3984 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3985
3986 i++;
3987 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3988
3989 /* set bits to identify this as an advanced context descriptor */
3990 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
3991
3992 /* For 82575, context index must be unique per ring. */
3993 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
3994 mss_l4len_idx |= tx_ring->reg_idx << 4;
3995
3996 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3997 context_desc->seqnum_seed = 0;
3998 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
3999 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4000}
4001
4002static int igb_tso(struct igb_ring *tx_ring,
4003 struct igb_tx_buffer *first,
4004 u8 *hdr_len)
4005{
4006 struct sk_buff *skb = first->skb;
4007 u32 vlan_macip_lens, type_tucmd;
4008 u32 mss_l4len_idx, l4len;
4009
4010 if (!skb_is_gso(skb))
4011 return 0;
4012
4013 if (skb_header_cloned(skb)) {
4014 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4015 if (err)
4016 return err;
4017 }
4018
4019 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4020 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4021
4022 if (first->protocol == __constant_htons(ETH_P_IP)) {
4023 struct iphdr *iph = ip_hdr(skb);
4024 iph->tot_len = 0;
4025 iph->check = 0;
4026 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4027 iph->daddr, 0,
4028 IPPROTO_TCP,
4029 0);
4030 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4031 first->tx_flags |= IGB_TX_FLAGS_TSO |
4032 IGB_TX_FLAGS_CSUM |
4033 IGB_TX_FLAGS_IPV4;
4034 } else if (skb_is_gso_v6(skb)) {
4035 ipv6_hdr(skb)->payload_len = 0;
4036 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4037 &ipv6_hdr(skb)->daddr,
4038 0, IPPROTO_TCP, 0);
4039 first->tx_flags |= IGB_TX_FLAGS_TSO |
4040 IGB_TX_FLAGS_CSUM;
4041 }
4042
4043 /* compute header lengths */
4044 l4len = tcp_hdrlen(skb);
4045 *hdr_len = skb_transport_offset(skb) + l4len;
4046
4047 /* update gso size and bytecount with header size */
4048 first->gso_segs = skb_shinfo(skb)->gso_segs;
4049 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4050
4051 /* MSS L4LEN IDX */
4052 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4053 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4054
4055 /* VLAN MACLEN IPLEN */
4056 vlan_macip_lens = skb_network_header_len(skb);
4057 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4058 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4059
4060 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4061
4062 return 1;
4063}
4064
4065static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4066{
4067 struct sk_buff *skb = first->skb;
4068 u32 vlan_macip_lens = 0;
4069 u32 mss_l4len_idx = 0;
4070 u32 type_tucmd = 0;
4071
4072 if (skb->ip_summed != CHECKSUM_PARTIAL) {
4073 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4074 return;
4075 } else {
4076 u8 l4_hdr = 0;
4077 switch (first->protocol) {
4078 case __constant_htons(ETH_P_IP):
4079 vlan_macip_lens |= skb_network_header_len(skb);
4080 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4081 l4_hdr = ip_hdr(skb)->protocol;
4082 break;
4083 case __constant_htons(ETH_P_IPV6):
4084 vlan_macip_lens |= skb_network_header_len(skb);
4085 l4_hdr = ipv6_hdr(skb)->nexthdr;
4086 break;
4087 default:
4088 if (unlikely(net_ratelimit())) {
4089 dev_warn(tx_ring->dev,
4090 "partial checksum but proto=%x!\n",
4091 first->protocol);
4092 }
4093 break;
4094 }
4095
4096 switch (l4_hdr) {
4097 case IPPROTO_TCP:
4098 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4099 mss_l4len_idx = tcp_hdrlen(skb) <<
4100 E1000_ADVTXD_L4LEN_SHIFT;
4101 break;
4102 case IPPROTO_SCTP:
4103 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4104 mss_l4len_idx = sizeof(struct sctphdr) <<
4105 E1000_ADVTXD_L4LEN_SHIFT;
4106 break;
4107 case IPPROTO_UDP:
4108 mss_l4len_idx = sizeof(struct udphdr) <<
4109 E1000_ADVTXD_L4LEN_SHIFT;
4110 break;
4111 default:
4112 if (unlikely(net_ratelimit())) {
4113 dev_warn(tx_ring->dev,
4114 "partial checksum but l4 proto=%x!\n",
4115 l4_hdr);
4116 }
4117 break;
4118 }
4119
4120 /* update TX checksum flag */
4121 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4122 }
4123
4124 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4125 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4126
4127 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4128}
4129
4130static __le32 igb_tx_cmd_type(u32 tx_flags)
4131{
4132 /* set type for advanced descriptor with frame checksum insertion */
4133 __le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA |
4134 E1000_ADVTXD_DCMD_IFCS |
4135 E1000_ADVTXD_DCMD_DEXT);
4136
4137 /* set HW vlan bit if vlan is present */
4138 if (tx_flags & IGB_TX_FLAGS_VLAN)
4139 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE);
4140
4141 /* set timestamp bit if present */
4142 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
4143 cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP);
4144
4145 /* set segmentation bits for TSO */
4146 if (tx_flags & IGB_TX_FLAGS_TSO)
4147 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE);
4148
4149 return cmd_type;
4150}
4151
4152static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4153 union e1000_adv_tx_desc *tx_desc,
4154 u32 tx_flags, unsigned int paylen)
4155{
4156 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4157
4158 /* 82575 requires a unique index per ring if any offload is enabled */
4159 if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) &&
4160 test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4161 olinfo_status |= tx_ring->reg_idx << 4;
4162
4163 /* insert L4 checksum */
4164 if (tx_flags & IGB_TX_FLAGS_CSUM) {
4165 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4166
4167 /* insert IPv4 checksum */
4168 if (tx_flags & IGB_TX_FLAGS_IPV4)
4169 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4170 }
4171
4172 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4173}
4174
4175/*
4176 * The largest size we can write to the descriptor is 65535. In order to
4177 * maintain a power of two alignment we have to limit ourselves to 32K.
4178 */
4179#define IGB_MAX_TXD_PWR 15
4180#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
4181
4182static void igb_tx_map(struct igb_ring *tx_ring,
4183 struct igb_tx_buffer *first,
4184 const u8 hdr_len)
4185{
4186 struct sk_buff *skb = first->skb;
4187 struct igb_tx_buffer *tx_buffer_info;
4188 union e1000_adv_tx_desc *tx_desc;
4189 dma_addr_t dma;
4190 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
4191 unsigned int data_len = skb->data_len;
4192 unsigned int size = skb_headlen(skb);
4193 unsigned int paylen = skb->len - hdr_len;
4194 __le32 cmd_type;
4195 u32 tx_flags = first->tx_flags;
4196 u16 i = tx_ring->next_to_use;
4197
4198 tx_desc = IGB_TX_DESC(tx_ring, i);
4199
4200 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen);
4201 cmd_type = igb_tx_cmd_type(tx_flags);
4202
4203 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4204 if (dma_mapping_error(tx_ring->dev, dma))
4205 goto dma_error;
4206
4207 /* record length, and DMA address */
4208 first->length = size;
4209 first->dma = dma;
4210 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4211
4212 for (;;) {
4213 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4214 tx_desc->read.cmd_type_len =
4215 cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD);
4216
4217 i++;
4218 tx_desc++;
4219 if (i == tx_ring->count) {
4220 tx_desc = IGB_TX_DESC(tx_ring, 0);
4221 i = 0;
4222 }
4223
4224 dma += IGB_MAX_DATA_PER_TXD;
4225 size -= IGB_MAX_DATA_PER_TXD;
4226
4227 tx_desc->read.olinfo_status = 0;
4228 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4229 }
4230
4231 if (likely(!data_len))
4232 break;
4233
4234 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
4235
4236 i++;
4237 tx_desc++;
4238 if (i == tx_ring->count) {
4239 tx_desc = IGB_TX_DESC(tx_ring, 0);
4240 i = 0;
4241 }
4242
4243 size = skb_frag_size(frag);
4244 data_len -= size;
4245
4246 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4247 size, DMA_TO_DEVICE);
4248 if (dma_mapping_error(tx_ring->dev, dma))
4249 goto dma_error;
4250
4251 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4252 tx_buffer_info->length = size;
4253 tx_buffer_info->dma = dma;
4254
4255 tx_desc->read.olinfo_status = 0;
4256 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4257
4258 frag++;
4259 }
4260
4261 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4262
4263 /* write last descriptor with RS and EOP bits */
4264 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD);
4265 if (unlikely(skb->no_fcs))
4266 cmd_type &= ~(cpu_to_le32(E1000_ADVTXD_DCMD_IFCS));
4267 tx_desc->read.cmd_type_len = cmd_type;
4268
4269 /* set the timestamp */
4270 first->time_stamp = jiffies;
4271
4272 /*
4273 * Force memory writes to complete before letting h/w know there
4274 * are new descriptors to fetch. (Only applicable for weak-ordered
4275 * memory model archs, such as IA-64).
4276 *
4277 * We also need this memory barrier to make certain all of the
4278 * status bits have been updated before next_to_watch is written.
4279 */
4280 wmb();
4281
4282 /* set next_to_watch value indicating a packet is present */
4283 first->next_to_watch = tx_desc;
4284
4285 i++;
4286 if (i == tx_ring->count)
4287 i = 0;
4288
4289 tx_ring->next_to_use = i;
4290
4291 writel(i, tx_ring->tail);
4292
4293 /* we need this if more than one processor can write to our tail
4294 * at a time, it syncronizes IO on IA64/Altix systems */
4295 mmiowb();
4296
4297 return;
4298
4299dma_error:
4300 dev_err(tx_ring->dev, "TX DMA map failed\n");
4301
4302 /* clear dma mappings for failed tx_buffer_info map */
4303 for (;;) {
4304 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4305 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4306 if (tx_buffer_info == first)
4307 break;
4308 if (i == 0)
4309 i = tx_ring->count;
4310 i--;
4311 }
4312
4313 tx_ring->next_to_use = i;
4314}
4315
4316static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4317{
4318 struct net_device *netdev = tx_ring->netdev;
4319
4320 netif_stop_subqueue(netdev, tx_ring->queue_index);
4321
4322 /* Herbert's original patch had:
4323 * smp_mb__after_netif_stop_queue();
4324 * but since that doesn't exist yet, just open code it. */
4325 smp_mb();
4326
4327 /* We need to check again in a case another CPU has just
4328 * made room available. */
4329 if (igb_desc_unused(tx_ring) < size)
4330 return -EBUSY;
4331
4332 /* A reprieve! */
4333 netif_wake_subqueue(netdev, tx_ring->queue_index);
4334
4335 u64_stats_update_begin(&tx_ring->tx_syncp2);
4336 tx_ring->tx_stats.restart_queue2++;
4337 u64_stats_update_end(&tx_ring->tx_syncp2);
4338
4339 return 0;
4340}
4341
4342static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4343{
4344 if (igb_desc_unused(tx_ring) >= size)
4345 return 0;
4346 return __igb_maybe_stop_tx(tx_ring, size);
4347}
4348
4349netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4350 struct igb_ring *tx_ring)
4351{
4352 struct igb_tx_buffer *first;
4353 int tso;
4354 u32 tx_flags = 0;
4355 __be16 protocol = vlan_get_protocol(skb);
4356 u8 hdr_len = 0;
4357
4358 /* need: 1 descriptor per page,
4359 * + 2 desc gap to keep tail from touching head,
4360 * + 1 desc for skb->data,
4361 * + 1 desc for context descriptor,
4362 * otherwise try next time */
4363 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
4364 /* this is a hard error */
4365 return NETDEV_TX_BUSY;
4366 }
4367
4368 /* record the location of the first descriptor for this packet */
4369 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4370 first->skb = skb;
4371 first->bytecount = skb->len;
4372 first->gso_segs = 1;
4373
4374 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4375 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4376 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4377 }
4378
4379 if (vlan_tx_tag_present(skb)) {
4380 tx_flags |= IGB_TX_FLAGS_VLAN;
4381 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4382 }
4383
4384 /* record initial flags and protocol */
4385 first->tx_flags = tx_flags;
4386 first->protocol = protocol;
4387
4388 tso = igb_tso(tx_ring, first, &hdr_len);
4389 if (tso < 0)
4390 goto out_drop;
4391 else if (!tso)
4392 igb_tx_csum(tx_ring, first);
4393
4394 igb_tx_map(tx_ring, first, hdr_len);
4395
4396 /* Make sure there is space in the ring for the next send. */
4397 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
4398
4399 return NETDEV_TX_OK;
4400
4401out_drop:
4402 igb_unmap_and_free_tx_resource(tx_ring, first);
4403
4404 return NETDEV_TX_OK;
4405}
4406
4407static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4408 struct sk_buff *skb)
4409{
4410 unsigned int r_idx = skb->queue_mapping;
4411
4412 if (r_idx >= adapter->num_tx_queues)
4413 r_idx = r_idx % adapter->num_tx_queues;
4414
4415 return adapter->tx_ring[r_idx];
4416}
4417
4418static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4419 struct net_device *netdev)
4420{
4421 struct igb_adapter *adapter = netdev_priv(netdev);
4422
4423 if (test_bit(__IGB_DOWN, &adapter->state)) {
4424 dev_kfree_skb_any(skb);
4425 return NETDEV_TX_OK;
4426 }
4427
4428 if (skb->len <= 0) {
4429 dev_kfree_skb_any(skb);
4430 return NETDEV_TX_OK;
4431 }
4432
4433 /*
4434 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4435 * in order to meet this minimum size requirement.
4436 */
4437 if (skb->len < 17) {
4438 if (skb_padto(skb, 17))
4439 return NETDEV_TX_OK;
4440 skb->len = 17;
4441 }
4442
4443 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4444}
4445
4446/**
4447 * igb_tx_timeout - Respond to a Tx Hang
4448 * @netdev: network interface device structure
4449 **/
4450static void igb_tx_timeout(struct net_device *netdev)
4451{
4452 struct igb_adapter *adapter = netdev_priv(netdev);
4453 struct e1000_hw *hw = &adapter->hw;
4454
4455 /* Do the reset outside of interrupt context */
4456 adapter->tx_timeout_count++;
4457
4458 if (hw->mac.type >= e1000_82580)
4459 hw->dev_spec._82575.global_device_reset = true;
4460
4461 schedule_work(&adapter->reset_task);
4462 wr32(E1000_EICS,
4463 (adapter->eims_enable_mask & ~adapter->eims_other));
4464}
4465
4466static void igb_reset_task(struct work_struct *work)
4467{
4468 struct igb_adapter *adapter;
4469 adapter = container_of(work, struct igb_adapter, reset_task);
4470
4471 igb_dump(adapter);
4472 netdev_err(adapter->netdev, "Reset adapter\n");
4473 igb_reinit_locked(adapter);
4474}
4475
4476/**
4477 * igb_get_stats64 - Get System Network Statistics
4478 * @netdev: network interface device structure
4479 * @stats: rtnl_link_stats64 pointer
4480 *
4481 **/
4482static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4483 struct rtnl_link_stats64 *stats)
4484{
4485 struct igb_adapter *adapter = netdev_priv(netdev);
4486
4487 spin_lock(&adapter->stats64_lock);
4488 igb_update_stats(adapter, &adapter->stats64);
4489 memcpy(stats, &adapter->stats64, sizeof(*stats));
4490 spin_unlock(&adapter->stats64_lock);
4491
4492 return stats;
4493}
4494
4495/**
4496 * igb_change_mtu - Change the Maximum Transfer Unit
4497 * @netdev: network interface device structure
4498 * @new_mtu: new value for maximum frame size
4499 *
4500 * Returns 0 on success, negative on failure
4501 **/
4502static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4503{
4504 struct igb_adapter *adapter = netdev_priv(netdev);
4505 struct pci_dev *pdev = adapter->pdev;
4506 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4507
4508 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4509 dev_err(&pdev->dev, "Invalid MTU setting\n");
4510 return -EINVAL;
4511 }
4512
4513#define MAX_STD_JUMBO_FRAME_SIZE 9238
4514 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4515 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4516 return -EINVAL;
4517 }
4518
4519 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4520 msleep(1);
4521
4522 /* igb_down has a dependency on max_frame_size */
4523 adapter->max_frame_size = max_frame;
4524
4525 if (netif_running(netdev))
4526 igb_down(adapter);
4527
4528 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4529 netdev->mtu, new_mtu);
4530 netdev->mtu = new_mtu;
4531
4532 if (netif_running(netdev))
4533 igb_up(adapter);
4534 else
4535 igb_reset(adapter);
4536
4537 clear_bit(__IGB_RESETTING, &adapter->state);
4538
4539 return 0;
4540}
4541
4542/**
4543 * igb_update_stats - Update the board statistics counters
4544 * @adapter: board private structure
4545 **/
4546
4547void igb_update_stats(struct igb_adapter *adapter,
4548 struct rtnl_link_stats64 *net_stats)
4549{
4550 struct e1000_hw *hw = &adapter->hw;
4551 struct pci_dev *pdev = adapter->pdev;
4552 u32 reg, mpc;
4553 u16 phy_tmp;
4554 int i;
4555 u64 bytes, packets;
4556 unsigned int start;
4557 u64 _bytes, _packets;
4558
4559#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4560
4561 /*
4562 * Prevent stats update while adapter is being reset, or if the pci
4563 * connection is down.
4564 */
4565 if (adapter->link_speed == 0)
4566 return;
4567 if (pci_channel_offline(pdev))
4568 return;
4569
4570 bytes = 0;
4571 packets = 0;
4572 for (i = 0; i < adapter->num_rx_queues; i++) {
4573 u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
4574 struct igb_ring *ring = adapter->rx_ring[i];
4575
4576 ring->rx_stats.drops += rqdpc_tmp;
4577 net_stats->rx_fifo_errors += rqdpc_tmp;
4578
4579 do {
4580 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4581 _bytes = ring->rx_stats.bytes;
4582 _packets = ring->rx_stats.packets;
4583 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4584 bytes += _bytes;
4585 packets += _packets;
4586 }
4587
4588 net_stats->rx_bytes = bytes;
4589 net_stats->rx_packets = packets;
4590
4591 bytes = 0;
4592 packets = 0;
4593 for (i = 0; i < adapter->num_tx_queues; i++) {
4594 struct igb_ring *ring = adapter->tx_ring[i];
4595 do {
4596 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4597 _bytes = ring->tx_stats.bytes;
4598 _packets = ring->tx_stats.packets;
4599 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4600 bytes += _bytes;
4601 packets += _packets;
4602 }
4603 net_stats->tx_bytes = bytes;
4604 net_stats->tx_packets = packets;
4605
4606 /* read stats registers */
4607 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4608 adapter->stats.gprc += rd32(E1000_GPRC);
4609 adapter->stats.gorc += rd32(E1000_GORCL);
4610 rd32(E1000_GORCH); /* clear GORCL */
4611 adapter->stats.bprc += rd32(E1000_BPRC);
4612 adapter->stats.mprc += rd32(E1000_MPRC);
4613 adapter->stats.roc += rd32(E1000_ROC);
4614
4615 adapter->stats.prc64 += rd32(E1000_PRC64);
4616 adapter->stats.prc127 += rd32(E1000_PRC127);
4617 adapter->stats.prc255 += rd32(E1000_PRC255);
4618 adapter->stats.prc511 += rd32(E1000_PRC511);
4619 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4620 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4621 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4622 adapter->stats.sec += rd32(E1000_SEC);
4623
4624 mpc = rd32(E1000_MPC);
4625 adapter->stats.mpc += mpc;
4626 net_stats->rx_fifo_errors += mpc;
4627 adapter->stats.scc += rd32(E1000_SCC);
4628 adapter->stats.ecol += rd32(E1000_ECOL);
4629 adapter->stats.mcc += rd32(E1000_MCC);
4630 adapter->stats.latecol += rd32(E1000_LATECOL);
4631 adapter->stats.dc += rd32(E1000_DC);
4632 adapter->stats.rlec += rd32(E1000_RLEC);
4633 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4634 adapter->stats.xontxc += rd32(E1000_XONTXC);
4635 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4636 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4637 adapter->stats.fcruc += rd32(E1000_FCRUC);
4638 adapter->stats.gptc += rd32(E1000_GPTC);
4639 adapter->stats.gotc += rd32(E1000_GOTCL);
4640 rd32(E1000_GOTCH); /* clear GOTCL */
4641 adapter->stats.rnbc += rd32(E1000_RNBC);
4642 adapter->stats.ruc += rd32(E1000_RUC);
4643 adapter->stats.rfc += rd32(E1000_RFC);
4644 adapter->stats.rjc += rd32(E1000_RJC);
4645 adapter->stats.tor += rd32(E1000_TORH);
4646 adapter->stats.tot += rd32(E1000_TOTH);
4647 adapter->stats.tpr += rd32(E1000_TPR);
4648
4649 adapter->stats.ptc64 += rd32(E1000_PTC64);
4650 adapter->stats.ptc127 += rd32(E1000_PTC127);
4651 adapter->stats.ptc255 += rd32(E1000_PTC255);
4652 adapter->stats.ptc511 += rd32(E1000_PTC511);
4653 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4654 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4655
4656 adapter->stats.mptc += rd32(E1000_MPTC);
4657 adapter->stats.bptc += rd32(E1000_BPTC);
4658
4659 adapter->stats.tpt += rd32(E1000_TPT);
4660 adapter->stats.colc += rd32(E1000_COLC);
4661
4662 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4663 /* read internal phy specific stats */
4664 reg = rd32(E1000_CTRL_EXT);
4665 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4666 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4667 adapter->stats.tncrs += rd32(E1000_TNCRS);
4668 }
4669
4670 adapter->stats.tsctc += rd32(E1000_TSCTC);
4671 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4672
4673 adapter->stats.iac += rd32(E1000_IAC);
4674 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4675 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4676 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4677 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4678 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4679 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4680 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4681 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4682
4683 /* Fill out the OS statistics structure */
4684 net_stats->multicast = adapter->stats.mprc;
4685 net_stats->collisions = adapter->stats.colc;
4686
4687 /* Rx Errors */
4688
4689 /* RLEC on some newer hardware can be incorrect so build
4690 * our own version based on RUC and ROC */
4691 net_stats->rx_errors = adapter->stats.rxerrc +
4692 adapter->stats.crcerrs + adapter->stats.algnerrc +
4693 adapter->stats.ruc + adapter->stats.roc +
4694 adapter->stats.cexterr;
4695 net_stats->rx_length_errors = adapter->stats.ruc +
4696 adapter->stats.roc;
4697 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4698 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4699 net_stats->rx_missed_errors = adapter->stats.mpc;
4700
4701 /* Tx Errors */
4702 net_stats->tx_errors = adapter->stats.ecol +
4703 adapter->stats.latecol;
4704 net_stats->tx_aborted_errors = adapter->stats.ecol;
4705 net_stats->tx_window_errors = adapter->stats.latecol;
4706 net_stats->tx_carrier_errors = adapter->stats.tncrs;
4707
4708 /* Tx Dropped needs to be maintained elsewhere */
4709
4710 /* Phy Stats */
4711 if (hw->phy.media_type == e1000_media_type_copper) {
4712 if ((adapter->link_speed == SPEED_1000) &&
4713 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4714 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4715 adapter->phy_stats.idle_errors += phy_tmp;
4716 }
4717 }
4718
4719 /* Management Stats */
4720 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4721 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4722 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4723
4724 /* OS2BMC Stats */
4725 reg = rd32(E1000_MANC);
4726 if (reg & E1000_MANC_EN_BMC2OS) {
4727 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4728 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4729 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4730 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4731 }
4732}
4733
4734static irqreturn_t igb_msix_other(int irq, void *data)
4735{
4736 struct igb_adapter *adapter = data;
4737 struct e1000_hw *hw = &adapter->hw;
4738 u32 icr = rd32(E1000_ICR);
4739 /* reading ICR causes bit 31 of EICR to be cleared */
4740
4741 if (icr & E1000_ICR_DRSTA)
4742 schedule_work(&adapter->reset_task);
4743
4744 if (icr & E1000_ICR_DOUTSYNC) {
4745 /* HW is reporting DMA is out of sync */
4746 adapter->stats.doosync++;
4747 /* The DMA Out of Sync is also indication of a spoof event
4748 * in IOV mode. Check the Wrong VM Behavior register to
4749 * see if it is really a spoof event. */
4750 igb_check_wvbr(adapter);
4751 }
4752
4753 /* Check for a mailbox event */
4754 if (icr & E1000_ICR_VMMB)
4755 igb_msg_task(adapter);
4756
4757 if (icr & E1000_ICR_LSC) {
4758 hw->mac.get_link_status = 1;
4759 /* guard against interrupt when we're going down */
4760 if (!test_bit(__IGB_DOWN, &adapter->state))
4761 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4762 }
4763
4764 wr32(E1000_EIMS, adapter->eims_other);
4765
4766 return IRQ_HANDLED;
4767}
4768
4769static void igb_write_itr(struct igb_q_vector *q_vector)
4770{
4771 struct igb_adapter *adapter = q_vector->adapter;
4772 u32 itr_val = q_vector->itr_val & 0x7FFC;
4773
4774 if (!q_vector->set_itr)
4775 return;
4776
4777 if (!itr_val)
4778 itr_val = 0x4;
4779
4780 if (adapter->hw.mac.type == e1000_82575)
4781 itr_val |= itr_val << 16;
4782 else
4783 itr_val |= E1000_EITR_CNT_IGNR;
4784
4785 writel(itr_val, q_vector->itr_register);
4786 q_vector->set_itr = 0;
4787}
4788
4789static irqreturn_t igb_msix_ring(int irq, void *data)
4790{
4791 struct igb_q_vector *q_vector = data;
4792
4793 /* Write the ITR value calculated from the previous interrupt. */
4794 igb_write_itr(q_vector);
4795
4796 napi_schedule(&q_vector->napi);
4797
4798 return IRQ_HANDLED;
4799}
4800
4801#ifdef CONFIG_IGB_DCA
4802static void igb_update_dca(struct igb_q_vector *q_vector)
4803{
4804 struct igb_adapter *adapter = q_vector->adapter;
4805 struct e1000_hw *hw = &adapter->hw;
4806 int cpu = get_cpu();
4807
4808 if (q_vector->cpu == cpu)
4809 goto out_no_update;
4810
4811 if (q_vector->tx.ring) {
4812 int q = q_vector->tx.ring->reg_idx;
4813 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4814 if (hw->mac.type == e1000_82575) {
4815 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4816 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
4817 } else {
4818 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4819 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4820 E1000_DCA_TXCTRL_CPUID_SHIFT;
4821 }
4822 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4823 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4824 }
4825 if (q_vector->rx.ring) {
4826 int q = q_vector->rx.ring->reg_idx;
4827 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4828 if (hw->mac.type == e1000_82575) {
4829 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
4830 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
4831 } else {
4832 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4833 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4834 E1000_DCA_RXCTRL_CPUID_SHIFT;
4835 }
4836 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4837 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4838 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4839 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
4840 }
4841 q_vector->cpu = cpu;
4842out_no_update:
4843 put_cpu();
4844}
4845
4846static void igb_setup_dca(struct igb_adapter *adapter)
4847{
4848 struct e1000_hw *hw = &adapter->hw;
4849 int i;
4850
4851 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
4852 return;
4853
4854 /* Always use CB2 mode, difference is masked in the CB driver. */
4855 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4856
4857 for (i = 0; i < adapter->num_q_vectors; i++) {
4858 adapter->q_vector[i]->cpu = -1;
4859 igb_update_dca(adapter->q_vector[i]);
4860 }
4861}
4862
4863static int __igb_notify_dca(struct device *dev, void *data)
4864{
4865 struct net_device *netdev = dev_get_drvdata(dev);
4866 struct igb_adapter *adapter = netdev_priv(netdev);
4867 struct pci_dev *pdev = adapter->pdev;
4868 struct e1000_hw *hw = &adapter->hw;
4869 unsigned long event = *(unsigned long *)data;
4870
4871 switch (event) {
4872 case DCA_PROVIDER_ADD:
4873 /* if already enabled, don't do it again */
4874 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
4875 break;
4876 if (dca_add_requester(dev) == 0) {
4877 adapter->flags |= IGB_FLAG_DCA_ENABLED;
4878 dev_info(&pdev->dev, "DCA enabled\n");
4879 igb_setup_dca(adapter);
4880 break;
4881 }
4882 /* Fall Through since DCA is disabled. */
4883 case DCA_PROVIDER_REMOVE:
4884 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
4885 /* without this a class_device is left
4886 * hanging around in the sysfs model */
4887 dca_remove_requester(dev);
4888 dev_info(&pdev->dev, "DCA disabled\n");
4889 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
4890 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
4891 }
4892 break;
4893 }
4894
4895 return 0;
4896}
4897
4898static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4899 void *p)
4900{
4901 int ret_val;
4902
4903 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4904 __igb_notify_dca);
4905
4906 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4907}
4908#endif /* CONFIG_IGB_DCA */
4909
4910#ifdef CONFIG_PCI_IOV
4911static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4912{
4913 unsigned char mac_addr[ETH_ALEN];
4914 struct pci_dev *pdev = adapter->pdev;
4915 struct e1000_hw *hw = &adapter->hw;
4916 struct pci_dev *pvfdev;
4917 unsigned int device_id;
4918 u16 thisvf_devfn;
4919
4920 random_ether_addr(mac_addr);
4921 igb_set_vf_mac(adapter, vf, mac_addr);
4922
4923 switch (adapter->hw.mac.type) {
4924 case e1000_82576:
4925 device_id = IGB_82576_VF_DEV_ID;
4926 /* VF Stride for 82576 is 2 */
4927 thisvf_devfn = (pdev->devfn + 0x80 + (vf << 1)) |
4928 (pdev->devfn & 1);
4929 break;
4930 case e1000_i350:
4931 device_id = IGB_I350_VF_DEV_ID;
4932 /* VF Stride for I350 is 4 */
4933 thisvf_devfn = (pdev->devfn + 0x80 + (vf << 2)) |
4934 (pdev->devfn & 3);
4935 break;
4936 default:
4937 device_id = 0;
4938 thisvf_devfn = 0;
4939 break;
4940 }
4941
4942 pvfdev = pci_get_device(hw->vendor_id, device_id, NULL);
4943 while (pvfdev) {
4944 if (pvfdev->devfn == thisvf_devfn)
4945 break;
4946 pvfdev = pci_get_device(hw->vendor_id,
4947 device_id, pvfdev);
4948 }
4949
4950 if (pvfdev)
4951 adapter->vf_data[vf].vfdev = pvfdev;
4952 else
4953 dev_err(&pdev->dev,
4954 "Couldn't find pci dev ptr for VF %4.4x\n",
4955 thisvf_devfn);
4956 return pvfdev != NULL;
4957}
4958
4959static int igb_find_enabled_vfs(struct igb_adapter *adapter)
4960{
4961 struct e1000_hw *hw = &adapter->hw;
4962 struct pci_dev *pdev = adapter->pdev;
4963 struct pci_dev *pvfdev;
4964 u16 vf_devfn = 0;
4965 u16 vf_stride;
4966 unsigned int device_id;
4967 int vfs_found = 0;
4968
4969 switch (adapter->hw.mac.type) {
4970 case e1000_82576:
4971 device_id = IGB_82576_VF_DEV_ID;
4972 /* VF Stride for 82576 is 2 */
4973 vf_stride = 2;
4974 break;
4975 case e1000_i350:
4976 device_id = IGB_I350_VF_DEV_ID;
4977 /* VF Stride for I350 is 4 */
4978 vf_stride = 4;
4979 break;
4980 default:
4981 device_id = 0;
4982 vf_stride = 0;
4983 break;
4984 }
4985
4986 vf_devfn = pdev->devfn + 0x80;
4987 pvfdev = pci_get_device(hw->vendor_id, device_id, NULL);
4988 while (pvfdev) {
4989 if (pvfdev->devfn == vf_devfn &&
4990 (pvfdev->bus->number >= pdev->bus->number))
4991 vfs_found++;
4992 vf_devfn += vf_stride;
4993 pvfdev = pci_get_device(hw->vendor_id,
4994 device_id, pvfdev);
4995 }
4996
4997 return vfs_found;
4998}
4999
5000static int igb_check_vf_assignment(struct igb_adapter *adapter)
5001{
5002 int i;
5003 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5004 if (adapter->vf_data[i].vfdev) {
5005 if (adapter->vf_data[i].vfdev->dev_flags &
5006 PCI_DEV_FLAGS_ASSIGNED)
5007 return true;
5008 }
5009 }
5010 return false;
5011}
5012
5013#endif
5014static void igb_ping_all_vfs(struct igb_adapter *adapter)
5015{
5016 struct e1000_hw *hw = &adapter->hw;
5017 u32 ping;
5018 int i;
5019
5020 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5021 ping = E1000_PF_CONTROL_MSG;
5022 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5023 ping |= E1000_VT_MSGTYPE_CTS;
5024 igb_write_mbx(hw, &ping, 1, i);
5025 }
5026}
5027
5028static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5029{
5030 struct e1000_hw *hw = &adapter->hw;
5031 u32 vmolr = rd32(E1000_VMOLR(vf));
5032 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5033
5034 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5035 IGB_VF_FLAG_MULTI_PROMISC);
5036 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5037
5038 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5039 vmolr |= E1000_VMOLR_MPME;
5040 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5041 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5042 } else {
5043 /*
5044 * if we have hashes and we are clearing a multicast promisc
5045 * flag we need to write the hashes to the MTA as this step
5046 * was previously skipped
5047 */
5048 if (vf_data->num_vf_mc_hashes > 30) {
5049 vmolr |= E1000_VMOLR_MPME;
5050 } else if (vf_data->num_vf_mc_hashes) {
5051 int j;
5052 vmolr |= E1000_VMOLR_ROMPE;
5053 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5054 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5055 }
5056 }
5057
5058 wr32(E1000_VMOLR(vf), vmolr);
5059
5060 /* there are flags left unprocessed, likely not supported */
5061 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5062 return -EINVAL;
5063
5064 return 0;
5065
5066}
5067
5068static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5069 u32 *msgbuf, u32 vf)
5070{
5071 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5072 u16 *hash_list = (u16 *)&msgbuf[1];
5073 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5074 int i;
5075
5076 /* salt away the number of multicast addresses assigned
5077 * to this VF for later use to restore when the PF multi cast
5078 * list changes
5079 */
5080 vf_data->num_vf_mc_hashes = n;
5081
5082 /* only up to 30 hash values supported */
5083 if (n > 30)
5084 n = 30;
5085
5086 /* store the hashes for later use */
5087 for (i = 0; i < n; i++)
5088 vf_data->vf_mc_hashes[i] = hash_list[i];
5089
5090 /* Flush and reset the mta with the new values */
5091 igb_set_rx_mode(adapter->netdev);
5092
5093 return 0;
5094}
5095
5096static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5097{
5098 struct e1000_hw *hw = &adapter->hw;
5099 struct vf_data_storage *vf_data;
5100 int i, j;
5101
5102 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5103 u32 vmolr = rd32(E1000_VMOLR(i));
5104 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5105
5106 vf_data = &adapter->vf_data[i];
5107
5108 if ((vf_data->num_vf_mc_hashes > 30) ||
5109 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5110 vmolr |= E1000_VMOLR_MPME;
5111 } else if (vf_data->num_vf_mc_hashes) {
5112 vmolr |= E1000_VMOLR_ROMPE;
5113 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5114 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5115 }
5116 wr32(E1000_VMOLR(i), vmolr);
5117 }
5118}
5119
5120static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5121{
5122 struct e1000_hw *hw = &adapter->hw;
5123 u32 pool_mask, reg, vid;
5124 int i;
5125
5126 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5127
5128 /* Find the vlan filter for this id */
5129 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5130 reg = rd32(E1000_VLVF(i));
5131
5132 /* remove the vf from the pool */
5133 reg &= ~pool_mask;
5134
5135 /* if pool is empty then remove entry from vfta */
5136 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5137 (reg & E1000_VLVF_VLANID_ENABLE)) {
5138 reg = 0;
5139 vid = reg & E1000_VLVF_VLANID_MASK;
5140 igb_vfta_set(hw, vid, false);
5141 }
5142
5143 wr32(E1000_VLVF(i), reg);
5144 }
5145
5146 adapter->vf_data[vf].vlans_enabled = 0;
5147}
5148
5149static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5150{
5151 struct e1000_hw *hw = &adapter->hw;
5152 u32 reg, i;
5153
5154 /* The vlvf table only exists on 82576 hardware and newer */
5155 if (hw->mac.type < e1000_82576)
5156 return -1;
5157
5158 /* we only need to do this if VMDq is enabled */
5159 if (!adapter->vfs_allocated_count)
5160 return -1;
5161
5162 /* Find the vlan filter for this id */
5163 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5164 reg = rd32(E1000_VLVF(i));
5165 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5166 vid == (reg & E1000_VLVF_VLANID_MASK))
5167 break;
5168 }
5169
5170 if (add) {
5171 if (i == E1000_VLVF_ARRAY_SIZE) {
5172 /* Did not find a matching VLAN ID entry that was
5173 * enabled. Search for a free filter entry, i.e.
5174 * one without the enable bit set
5175 */
5176 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5177 reg = rd32(E1000_VLVF(i));
5178 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5179 break;
5180 }
5181 }
5182 if (i < E1000_VLVF_ARRAY_SIZE) {
5183 /* Found an enabled/available entry */
5184 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5185
5186 /* if !enabled we need to set this up in vfta */
5187 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5188 /* add VID to filter table */
5189 igb_vfta_set(hw, vid, true);
5190 reg |= E1000_VLVF_VLANID_ENABLE;
5191 }
5192 reg &= ~E1000_VLVF_VLANID_MASK;
5193 reg |= vid;
5194 wr32(E1000_VLVF(i), reg);
5195
5196 /* do not modify RLPML for PF devices */
5197 if (vf >= adapter->vfs_allocated_count)
5198 return 0;
5199
5200 if (!adapter->vf_data[vf].vlans_enabled) {
5201 u32 size;
5202 reg = rd32(E1000_VMOLR(vf));
5203 size = reg & E1000_VMOLR_RLPML_MASK;
5204 size += 4;
5205 reg &= ~E1000_VMOLR_RLPML_MASK;
5206 reg |= size;
5207 wr32(E1000_VMOLR(vf), reg);
5208 }
5209
5210 adapter->vf_data[vf].vlans_enabled++;
5211 }
5212 } else {
5213 if (i < E1000_VLVF_ARRAY_SIZE) {
5214 /* remove vf from the pool */
5215 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5216 /* if pool is empty then remove entry from vfta */
5217 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5218 reg = 0;
5219 igb_vfta_set(hw, vid, false);
5220 }
5221 wr32(E1000_VLVF(i), reg);
5222
5223 /* do not modify RLPML for PF devices */
5224 if (vf >= adapter->vfs_allocated_count)
5225 return 0;
5226
5227 adapter->vf_data[vf].vlans_enabled--;
5228 if (!adapter->vf_data[vf].vlans_enabled) {
5229 u32 size;
5230 reg = rd32(E1000_VMOLR(vf));
5231 size = reg & E1000_VMOLR_RLPML_MASK;
5232 size -= 4;
5233 reg &= ~E1000_VMOLR_RLPML_MASK;
5234 reg |= size;
5235 wr32(E1000_VMOLR(vf), reg);
5236 }
5237 }
5238 }
5239 return 0;
5240}
5241
5242static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5243{
5244 struct e1000_hw *hw = &adapter->hw;
5245
5246 if (vid)
5247 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5248 else
5249 wr32(E1000_VMVIR(vf), 0);
5250}
5251
5252static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5253 int vf, u16 vlan, u8 qos)
5254{
5255 int err = 0;
5256 struct igb_adapter *adapter = netdev_priv(netdev);
5257
5258 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5259 return -EINVAL;
5260 if (vlan || qos) {
5261 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5262 if (err)
5263 goto out;
5264 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5265 igb_set_vmolr(adapter, vf, !vlan);
5266 adapter->vf_data[vf].pf_vlan = vlan;
5267 adapter->vf_data[vf].pf_qos = qos;
5268 dev_info(&adapter->pdev->dev,
5269 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5270 if (test_bit(__IGB_DOWN, &adapter->state)) {
5271 dev_warn(&adapter->pdev->dev,
5272 "The VF VLAN has been set,"
5273 " but the PF device is not up.\n");
5274 dev_warn(&adapter->pdev->dev,
5275 "Bring the PF device up before"
5276 " attempting to use the VF device.\n");
5277 }
5278 } else {
5279 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5280 false, vf);
5281 igb_set_vmvir(adapter, vlan, vf);
5282 igb_set_vmolr(adapter, vf, true);
5283 adapter->vf_data[vf].pf_vlan = 0;
5284 adapter->vf_data[vf].pf_qos = 0;
5285 }
5286out:
5287 return err;
5288}
5289
5290static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5291{
5292 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5293 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5294
5295 return igb_vlvf_set(adapter, vid, add, vf);
5296}
5297
5298static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5299{
5300 /* clear flags - except flag that indicates PF has set the MAC */
5301 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5302 adapter->vf_data[vf].last_nack = jiffies;
5303
5304 /* reset offloads to defaults */
5305 igb_set_vmolr(adapter, vf, true);
5306
5307 /* reset vlans for device */
5308 igb_clear_vf_vfta(adapter, vf);
5309 if (adapter->vf_data[vf].pf_vlan)
5310 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5311 adapter->vf_data[vf].pf_vlan,
5312 adapter->vf_data[vf].pf_qos);
5313 else
5314 igb_clear_vf_vfta(adapter, vf);
5315
5316 /* reset multicast table array for vf */
5317 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5318
5319 /* Flush and reset the mta with the new values */
5320 igb_set_rx_mode(adapter->netdev);
5321}
5322
5323static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5324{
5325 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5326
5327 /* generate a new mac address as we were hotplug removed/added */
5328 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5329 random_ether_addr(vf_mac);
5330
5331 /* process remaining reset events */
5332 igb_vf_reset(adapter, vf);
5333}
5334
5335static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5336{
5337 struct e1000_hw *hw = &adapter->hw;
5338 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5339 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5340 u32 reg, msgbuf[3];
5341 u8 *addr = (u8 *)(&msgbuf[1]);
5342
5343 /* process all the same items cleared in a function level reset */
5344 igb_vf_reset(adapter, vf);
5345
5346 /* set vf mac address */
5347 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5348
5349 /* enable transmit and receive for vf */
5350 reg = rd32(E1000_VFTE);
5351 wr32(E1000_VFTE, reg | (1 << vf));
5352 reg = rd32(E1000_VFRE);
5353 wr32(E1000_VFRE, reg | (1 << vf));
5354
5355 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5356
5357 /* reply to reset with ack and vf mac address */
5358 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5359 memcpy(addr, vf_mac, 6);
5360 igb_write_mbx(hw, msgbuf, 3, vf);
5361}
5362
5363static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5364{
5365 /*
5366 * The VF MAC Address is stored in a packed array of bytes
5367 * starting at the second 32 bit word of the msg array
5368 */
5369 unsigned char *addr = (char *)&msg[1];
5370 int err = -1;
5371
5372 if (is_valid_ether_addr(addr))
5373 err = igb_set_vf_mac(adapter, vf, addr);
5374
5375 return err;
5376}
5377
5378static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5379{
5380 struct e1000_hw *hw = &adapter->hw;
5381 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5382 u32 msg = E1000_VT_MSGTYPE_NACK;
5383
5384 /* if device isn't clear to send it shouldn't be reading either */
5385 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5386 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5387 igb_write_mbx(hw, &msg, 1, vf);
5388 vf_data->last_nack = jiffies;
5389 }
5390}
5391
5392static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5393{
5394 struct pci_dev *pdev = adapter->pdev;
5395 u32 msgbuf[E1000_VFMAILBOX_SIZE];
5396 struct e1000_hw *hw = &adapter->hw;
5397 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5398 s32 retval;
5399
5400 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5401
5402 if (retval) {
5403 /* if receive failed revoke VF CTS stats and restart init */
5404 dev_err(&pdev->dev, "Error receiving message from VF\n");
5405 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5406 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5407 return;
5408 goto out;
5409 }
5410
5411 /* this is a message we already processed, do nothing */
5412 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5413 return;
5414
5415 /*
5416 * until the vf completes a reset it should not be
5417 * allowed to start any configuration.
5418 */
5419
5420 if (msgbuf[0] == E1000_VF_RESET) {
5421 igb_vf_reset_msg(adapter, vf);
5422 return;
5423 }
5424
5425 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5426 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5427 return;
5428 retval = -1;
5429 goto out;
5430 }
5431
5432 switch ((msgbuf[0] & 0xFFFF)) {
5433 case E1000_VF_SET_MAC_ADDR:
5434 retval = -EINVAL;
5435 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5436 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5437 else
5438 dev_warn(&pdev->dev,
5439 "VF %d attempted to override administratively "
5440 "set MAC address\nReload the VF driver to "
5441 "resume operations\n", vf);
5442 break;
5443 case E1000_VF_SET_PROMISC:
5444 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5445 break;
5446 case E1000_VF_SET_MULTICAST:
5447 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5448 break;
5449 case E1000_VF_SET_LPE:
5450 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5451 break;
5452 case E1000_VF_SET_VLAN:
5453 retval = -1;
5454 if (vf_data->pf_vlan)
5455 dev_warn(&pdev->dev,
5456 "VF %d attempted to override administratively "
5457 "set VLAN tag\nReload the VF driver to "
5458 "resume operations\n", vf);
5459 else
5460 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5461 break;
5462 default:
5463 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5464 retval = -1;
5465 break;
5466 }
5467
5468 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5469out:
5470 /* notify the VF of the results of what it sent us */
5471 if (retval)
5472 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5473 else
5474 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5475
5476 igb_write_mbx(hw, msgbuf, 1, vf);
5477}
5478
5479static void igb_msg_task(struct igb_adapter *adapter)
5480{
5481 struct e1000_hw *hw = &adapter->hw;
5482 u32 vf;
5483
5484 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5485 /* process any reset requests */
5486 if (!igb_check_for_rst(hw, vf))
5487 igb_vf_reset_event(adapter, vf);
5488
5489 /* process any messages pending */
5490 if (!igb_check_for_msg(hw, vf))
5491 igb_rcv_msg_from_vf(adapter, vf);
5492
5493 /* process any acks */
5494 if (!igb_check_for_ack(hw, vf))
5495 igb_rcv_ack_from_vf(adapter, vf);
5496 }
5497}
5498
5499/**
5500 * igb_set_uta - Set unicast filter table address
5501 * @adapter: board private structure
5502 *
5503 * The unicast table address is a register array of 32-bit registers.
5504 * The table is meant to be used in a way similar to how the MTA is used
5505 * however due to certain limitations in the hardware it is necessary to
5506 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5507 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
5508 **/
5509static void igb_set_uta(struct igb_adapter *adapter)
5510{
5511 struct e1000_hw *hw = &adapter->hw;
5512 int i;
5513
5514 /* The UTA table only exists on 82576 hardware and newer */
5515 if (hw->mac.type < e1000_82576)
5516 return;
5517
5518 /* we only need to do this if VMDq is enabled */
5519 if (!adapter->vfs_allocated_count)
5520 return;
5521
5522 for (i = 0; i < hw->mac.uta_reg_count; i++)
5523 array_wr32(E1000_UTA, i, ~0);
5524}
5525
5526/**
5527 * igb_intr_msi - Interrupt Handler
5528 * @irq: interrupt number
5529 * @data: pointer to a network interface device structure
5530 **/
5531static irqreturn_t igb_intr_msi(int irq, void *data)
5532{
5533 struct igb_adapter *adapter = data;
5534 struct igb_q_vector *q_vector = adapter->q_vector[0];
5535 struct e1000_hw *hw = &adapter->hw;
5536 /* read ICR disables interrupts using IAM */
5537 u32 icr = rd32(E1000_ICR);
5538
5539 igb_write_itr(q_vector);
5540
5541 if (icr & E1000_ICR_DRSTA)
5542 schedule_work(&adapter->reset_task);
5543
5544 if (icr & E1000_ICR_DOUTSYNC) {
5545 /* HW is reporting DMA is out of sync */
5546 adapter->stats.doosync++;
5547 }
5548
5549 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5550 hw->mac.get_link_status = 1;
5551 if (!test_bit(__IGB_DOWN, &adapter->state))
5552 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5553 }
5554
5555 napi_schedule(&q_vector->napi);
5556
5557 return IRQ_HANDLED;
5558}
5559
5560/**
5561 * igb_intr - Legacy Interrupt Handler
5562 * @irq: interrupt number
5563 * @data: pointer to a network interface device structure
5564 **/
5565static irqreturn_t igb_intr(int irq, void *data)
5566{
5567 struct igb_adapter *adapter = data;
5568 struct igb_q_vector *q_vector = adapter->q_vector[0];
5569 struct e1000_hw *hw = &adapter->hw;
5570 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5571 * need for the IMC write */
5572 u32 icr = rd32(E1000_ICR);
5573
5574 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5575 * not set, then the adapter didn't send an interrupt */
5576 if (!(icr & E1000_ICR_INT_ASSERTED))
5577 return IRQ_NONE;
5578
5579 igb_write_itr(q_vector);
5580
5581 if (icr & E1000_ICR_DRSTA)
5582 schedule_work(&adapter->reset_task);
5583
5584 if (icr & E1000_ICR_DOUTSYNC) {
5585 /* HW is reporting DMA is out of sync */
5586 adapter->stats.doosync++;
5587 }
5588
5589 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5590 hw->mac.get_link_status = 1;
5591 /* guard against interrupt when we're going down */
5592 if (!test_bit(__IGB_DOWN, &adapter->state))
5593 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5594 }
5595
5596 napi_schedule(&q_vector->napi);
5597
5598 return IRQ_HANDLED;
5599}
5600
5601static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5602{
5603 struct igb_adapter *adapter = q_vector->adapter;
5604 struct e1000_hw *hw = &adapter->hw;
5605
5606 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5607 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5608 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5609 igb_set_itr(q_vector);
5610 else
5611 igb_update_ring_itr(q_vector);
5612 }
5613
5614 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5615 if (adapter->msix_entries)
5616 wr32(E1000_EIMS, q_vector->eims_value);
5617 else
5618 igb_irq_enable(adapter);
5619 }
5620}
5621
5622/**
5623 * igb_poll - NAPI Rx polling callback
5624 * @napi: napi polling structure
5625 * @budget: count of how many packets we should handle
5626 **/
5627static int igb_poll(struct napi_struct *napi, int budget)
5628{
5629 struct igb_q_vector *q_vector = container_of(napi,
5630 struct igb_q_vector,
5631 napi);
5632 bool clean_complete = true;
5633
5634#ifdef CONFIG_IGB_DCA
5635 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5636 igb_update_dca(q_vector);
5637#endif
5638 if (q_vector->tx.ring)
5639 clean_complete = igb_clean_tx_irq(q_vector);
5640
5641 if (q_vector->rx.ring)
5642 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5643
5644 /* If all work not completed, return budget and keep polling */
5645 if (!clean_complete)
5646 return budget;
5647
5648 /* If not enough Rx work done, exit the polling mode */
5649 napi_complete(napi);
5650 igb_ring_irq_enable(q_vector);
5651
5652 return 0;
5653}
5654
5655#ifdef CONFIG_IGB_PTP
5656/**
5657 * igb_tx_hwtstamp - utility function which checks for TX time stamp
5658 * @q_vector: pointer to q_vector containing needed info
5659 * @buffer: pointer to igb_tx_buffer structure
5660 *
5661 * If we were asked to do hardware stamping and such a time stamp is
5662 * available, then it must have been for this skb here because we only
5663 * allow only one such packet into the queue.
5664 */
5665static void igb_tx_hwtstamp(struct igb_q_vector *q_vector,
5666 struct igb_tx_buffer *buffer_info)
5667{
5668 struct igb_adapter *adapter = q_vector->adapter;
5669 struct e1000_hw *hw = &adapter->hw;
5670 struct skb_shared_hwtstamps shhwtstamps;
5671 u64 regval;
5672
5673 /* if skb does not support hw timestamp or TX stamp not valid exit */
5674 if (likely(!(buffer_info->tx_flags & IGB_TX_FLAGS_TSTAMP)) ||
5675 !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
5676 return;
5677
5678 regval = rd32(E1000_TXSTMPL);
5679 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
5680
5681 igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
5682 skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
5683}
5684
5685#endif
5686/**
5687 * igb_clean_tx_irq - Reclaim resources after transmit completes
5688 * @q_vector: pointer to q_vector containing needed info
5689 * returns true if ring is completely cleaned
5690 **/
5691static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5692{
5693 struct igb_adapter *adapter = q_vector->adapter;
5694 struct igb_ring *tx_ring = q_vector->tx.ring;
5695 struct igb_tx_buffer *tx_buffer;
5696 union e1000_adv_tx_desc *tx_desc, *eop_desc;
5697 unsigned int total_bytes = 0, total_packets = 0;
5698 unsigned int budget = q_vector->tx.work_limit;
5699 unsigned int i = tx_ring->next_to_clean;
5700
5701 if (test_bit(__IGB_DOWN, &adapter->state))
5702 return true;
5703
5704 tx_buffer = &tx_ring->tx_buffer_info[i];
5705 tx_desc = IGB_TX_DESC(tx_ring, i);
5706 i -= tx_ring->count;
5707
5708 for (; budget; budget--) {
5709 eop_desc = tx_buffer->next_to_watch;
5710
5711 /* prevent any other reads prior to eop_desc */
5712 rmb();
5713
5714 /* if next_to_watch is not set then there is no work pending */
5715 if (!eop_desc)
5716 break;
5717
5718 /* if DD is not set pending work has not been completed */
5719 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5720 break;
5721
5722 /* clear next_to_watch to prevent false hangs */
5723 tx_buffer->next_to_watch = NULL;
5724
5725 /* update the statistics for this packet */
5726 total_bytes += tx_buffer->bytecount;
5727 total_packets += tx_buffer->gso_segs;
5728
5729#ifdef CONFIG_IGB_PTP
5730 /* retrieve hardware timestamp */
5731 igb_tx_hwtstamp(q_vector, tx_buffer);
5732
5733#endif
5734 /* free the skb */
5735 dev_kfree_skb_any(tx_buffer->skb);
5736 tx_buffer->skb = NULL;
5737
5738 /* unmap skb header data */
5739 dma_unmap_single(tx_ring->dev,
5740 tx_buffer->dma,
5741 tx_buffer->length,
5742 DMA_TO_DEVICE);
5743
5744 /* clear last DMA location and unmap remaining buffers */
5745 while (tx_desc != eop_desc) {
5746 tx_buffer->dma = 0;
5747
5748 tx_buffer++;
5749 tx_desc++;
5750 i++;
5751 if (unlikely(!i)) {
5752 i -= tx_ring->count;
5753 tx_buffer = tx_ring->tx_buffer_info;
5754 tx_desc = IGB_TX_DESC(tx_ring, 0);
5755 }
5756
5757 /* unmap any remaining paged data */
5758 if (tx_buffer->dma) {
5759 dma_unmap_page(tx_ring->dev,
5760 tx_buffer->dma,
5761 tx_buffer->length,
5762 DMA_TO_DEVICE);
5763 }
5764 }
5765
5766 /* clear last DMA location */
5767 tx_buffer->dma = 0;
5768
5769 /* move us one more past the eop_desc for start of next pkt */
5770 tx_buffer++;
5771 tx_desc++;
5772 i++;
5773 if (unlikely(!i)) {
5774 i -= tx_ring->count;
5775 tx_buffer = tx_ring->tx_buffer_info;
5776 tx_desc = IGB_TX_DESC(tx_ring, 0);
5777 }
5778 }
5779
5780 netdev_tx_completed_queue(txring_txq(tx_ring),
5781 total_packets, total_bytes);
5782 i += tx_ring->count;
5783 tx_ring->next_to_clean = i;
5784 u64_stats_update_begin(&tx_ring->tx_syncp);
5785 tx_ring->tx_stats.bytes += total_bytes;
5786 tx_ring->tx_stats.packets += total_packets;
5787 u64_stats_update_end(&tx_ring->tx_syncp);
5788 q_vector->tx.total_bytes += total_bytes;
5789 q_vector->tx.total_packets += total_packets;
5790
5791 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
5792 struct e1000_hw *hw = &adapter->hw;
5793
5794 eop_desc = tx_buffer->next_to_watch;
5795
5796 /* Detect a transmit hang in hardware, this serializes the
5797 * check with the clearing of time_stamp and movement of i */
5798 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5799 if (eop_desc &&
5800 time_after(jiffies, tx_buffer->time_stamp +
5801 (adapter->tx_timeout_factor * HZ)) &&
5802 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
5803
5804 /* detected Tx unit hang */
5805 dev_err(tx_ring->dev,
5806 "Detected Tx Unit Hang\n"
5807 " Tx Queue <%d>\n"
5808 " TDH <%x>\n"
5809 " TDT <%x>\n"
5810 " next_to_use <%x>\n"
5811 " next_to_clean <%x>\n"
5812 "buffer_info[next_to_clean]\n"
5813 " time_stamp <%lx>\n"
5814 " next_to_watch <%p>\n"
5815 " jiffies <%lx>\n"
5816 " desc.status <%x>\n",
5817 tx_ring->queue_index,
5818 rd32(E1000_TDH(tx_ring->reg_idx)),
5819 readl(tx_ring->tail),
5820 tx_ring->next_to_use,
5821 tx_ring->next_to_clean,
5822 tx_buffer->time_stamp,
5823 eop_desc,
5824 jiffies,
5825 eop_desc->wb.status);
5826 netif_stop_subqueue(tx_ring->netdev,
5827 tx_ring->queue_index);
5828
5829 /* we are about to reset, no point in enabling stuff */
5830 return true;
5831 }
5832 }
5833
5834 if (unlikely(total_packets &&
5835 netif_carrier_ok(tx_ring->netdev) &&
5836 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5837 /* Make sure that anybody stopping the queue after this
5838 * sees the new next_to_clean.
5839 */
5840 smp_mb();
5841 if (__netif_subqueue_stopped(tx_ring->netdev,
5842 tx_ring->queue_index) &&
5843 !(test_bit(__IGB_DOWN, &adapter->state))) {
5844 netif_wake_subqueue(tx_ring->netdev,
5845 tx_ring->queue_index);
5846
5847 u64_stats_update_begin(&tx_ring->tx_syncp);
5848 tx_ring->tx_stats.restart_queue++;
5849 u64_stats_update_end(&tx_ring->tx_syncp);
5850 }
5851 }
5852
5853 return !!budget;
5854}
5855
5856static inline void igb_rx_checksum(struct igb_ring *ring,
5857 union e1000_adv_rx_desc *rx_desc,
5858 struct sk_buff *skb)
5859{
5860 skb_checksum_none_assert(skb);
5861
5862 /* Ignore Checksum bit is set */
5863 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
5864 return;
5865
5866 /* Rx checksum disabled via ethtool */
5867 if (!(ring->netdev->features & NETIF_F_RXCSUM))
5868 return;
5869
5870 /* TCP/UDP checksum error bit is set */
5871 if (igb_test_staterr(rx_desc,
5872 E1000_RXDEXT_STATERR_TCPE |
5873 E1000_RXDEXT_STATERR_IPE)) {
5874 /*
5875 * work around errata with sctp packets where the TCPE aka
5876 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5877 * packets, (aka let the stack check the crc32c)
5878 */
5879 if (!((skb->len == 60) &&
5880 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
5881 u64_stats_update_begin(&ring->rx_syncp);
5882 ring->rx_stats.csum_err++;
5883 u64_stats_update_end(&ring->rx_syncp);
5884 }
5885 /* let the stack verify checksum errors */
5886 return;
5887 }
5888 /* It must be a TCP or UDP packet with a valid checksum */
5889 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
5890 E1000_RXD_STAT_UDPCS))
5891 skb->ip_summed = CHECKSUM_UNNECESSARY;
5892
5893 dev_dbg(ring->dev, "cksum success: bits %08X\n",
5894 le32_to_cpu(rx_desc->wb.upper.status_error));
5895}
5896
5897static inline void igb_rx_hash(struct igb_ring *ring,
5898 union e1000_adv_rx_desc *rx_desc,
5899 struct sk_buff *skb)
5900{
5901 if (ring->netdev->features & NETIF_F_RXHASH)
5902 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
5903}
5904
5905#ifdef CONFIG_IGB_PTP
5906static void igb_rx_hwtstamp(struct igb_q_vector *q_vector,
5907 union e1000_adv_rx_desc *rx_desc,
5908 struct sk_buff *skb)
5909{
5910 struct igb_adapter *adapter = q_vector->adapter;
5911 struct e1000_hw *hw = &adapter->hw;
5912 u64 regval;
5913
5914 if (!igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP |
5915 E1000_RXDADV_STAT_TS))
5916 return;
5917
5918 /*
5919 * If this bit is set, then the RX registers contain the time stamp. No
5920 * other packet will be time stamped until we read these registers, so
5921 * read the registers to make them available again. Because only one
5922 * packet can be time stamped at a time, we know that the register
5923 * values must belong to this one here and therefore we don't need to
5924 * compare any of the additional attributes stored for it.
5925 *
5926 * If nothing went wrong, then it should have a shared tx_flags that we
5927 * can turn into a skb_shared_hwtstamps.
5928 */
5929 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
5930 u32 *stamp = (u32 *)skb->data;
5931 regval = le32_to_cpu(*(stamp + 2));
5932 regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
5933 skb_pull(skb, IGB_TS_HDR_LEN);
5934 } else {
5935 if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
5936 return;
5937
5938 regval = rd32(E1000_RXSTMPL);
5939 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
5940 }
5941
5942 igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
5943}
5944
5945#endif
5946static void igb_rx_vlan(struct igb_ring *ring,
5947 union e1000_adv_rx_desc *rx_desc,
5948 struct sk_buff *skb)
5949{
5950 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
5951 u16 vid;
5952 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
5953 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags))
5954 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
5955 else
5956 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
5957
5958 __vlan_hwaccel_put_tag(skb, vid);
5959 }
5960}
5961
5962static inline u16 igb_get_hlen(union e1000_adv_rx_desc *rx_desc)
5963{
5964 /* HW will not DMA in data larger than the given buffer, even if it
5965 * parses the (NFS, of course) header to be larger. In that case, it
5966 * fills the header buffer and spills the rest into the page.
5967 */
5968 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
5969 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
5970 if (hlen > IGB_RX_HDR_LEN)
5971 hlen = IGB_RX_HDR_LEN;
5972 return hlen;
5973}
5974
5975static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget)
5976{
5977 struct igb_ring *rx_ring = q_vector->rx.ring;
5978 union e1000_adv_rx_desc *rx_desc;
5979 const int current_node = numa_node_id();
5980 unsigned int total_bytes = 0, total_packets = 0;
5981 u16 cleaned_count = igb_desc_unused(rx_ring);
5982 u16 i = rx_ring->next_to_clean;
5983
5984 rx_desc = IGB_RX_DESC(rx_ring, i);
5985
5986 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
5987 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
5988 struct sk_buff *skb = buffer_info->skb;
5989 union e1000_adv_rx_desc *next_rxd;
5990
5991 buffer_info->skb = NULL;
5992 prefetch(skb->data);
5993
5994 i++;
5995 if (i == rx_ring->count)
5996 i = 0;
5997
5998 next_rxd = IGB_RX_DESC(rx_ring, i);
5999 prefetch(next_rxd);
6000
6001 /*
6002 * This memory barrier is needed to keep us from reading
6003 * any other fields out of the rx_desc until we know the
6004 * RXD_STAT_DD bit is set
6005 */
6006 rmb();
6007
6008 if (!skb_is_nonlinear(skb)) {
6009 __skb_put(skb, igb_get_hlen(rx_desc));
6010 dma_unmap_single(rx_ring->dev, buffer_info->dma,
6011 IGB_RX_HDR_LEN,
6012 DMA_FROM_DEVICE);
6013 buffer_info->dma = 0;
6014 }
6015
6016 if (rx_desc->wb.upper.length) {
6017 u16 length = le16_to_cpu(rx_desc->wb.upper.length);
6018
6019 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
6020 buffer_info->page,
6021 buffer_info->page_offset,
6022 length);
6023
6024 skb->len += length;
6025 skb->data_len += length;
6026 skb->truesize += PAGE_SIZE / 2;
6027
6028 if ((page_count(buffer_info->page) != 1) ||
6029 (page_to_nid(buffer_info->page) != current_node))
6030 buffer_info->page = NULL;
6031 else
6032 get_page(buffer_info->page);
6033
6034 dma_unmap_page(rx_ring->dev, buffer_info->page_dma,
6035 PAGE_SIZE / 2, DMA_FROM_DEVICE);
6036 buffer_info->page_dma = 0;
6037 }
6038
6039 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)) {
6040 struct igb_rx_buffer *next_buffer;
6041 next_buffer = &rx_ring->rx_buffer_info[i];
6042 buffer_info->skb = next_buffer->skb;
6043 buffer_info->dma = next_buffer->dma;
6044 next_buffer->skb = skb;
6045 next_buffer->dma = 0;
6046 goto next_desc;
6047 }
6048
6049 if (unlikely((igb_test_staterr(rx_desc,
6050 E1000_RXDEXT_ERR_FRAME_ERR_MASK))
6051 && !(rx_ring->netdev->features & NETIF_F_RXALL))) {
6052 dev_kfree_skb_any(skb);
6053 goto next_desc;
6054 }
6055
6056#ifdef CONFIG_IGB_PTP
6057 igb_rx_hwtstamp(q_vector, rx_desc, skb);
6058#endif
6059 igb_rx_hash(rx_ring, rx_desc, skb);
6060 igb_rx_checksum(rx_ring, rx_desc, skb);
6061 igb_rx_vlan(rx_ring, rx_desc, skb);
6062
6063 total_bytes += skb->len;
6064 total_packets++;
6065
6066 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6067
6068 napi_gro_receive(&q_vector->napi, skb);
6069
6070 budget--;
6071next_desc:
6072 if (!budget)
6073 break;
6074
6075 cleaned_count++;
6076 /* return some buffers to hardware, one at a time is too slow */
6077 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6078 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6079 cleaned_count = 0;
6080 }
6081
6082 /* use prefetched values */
6083 rx_desc = next_rxd;
6084 }
6085
6086 rx_ring->next_to_clean = i;
6087 u64_stats_update_begin(&rx_ring->rx_syncp);
6088 rx_ring->rx_stats.packets += total_packets;
6089 rx_ring->rx_stats.bytes += total_bytes;
6090 u64_stats_update_end(&rx_ring->rx_syncp);
6091 q_vector->rx.total_packets += total_packets;
6092 q_vector->rx.total_bytes += total_bytes;
6093
6094 if (cleaned_count)
6095 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6096
6097 return !!budget;
6098}
6099
6100static bool igb_alloc_mapped_skb(struct igb_ring *rx_ring,
6101 struct igb_rx_buffer *bi)
6102{
6103 struct sk_buff *skb = bi->skb;
6104 dma_addr_t dma = bi->dma;
6105
6106 if (dma)
6107 return true;
6108
6109 if (likely(!skb)) {
6110 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6111 IGB_RX_HDR_LEN);
6112 bi->skb = skb;
6113 if (!skb) {
6114 rx_ring->rx_stats.alloc_failed++;
6115 return false;
6116 }
6117
6118 /* initialize skb for ring */
6119 skb_record_rx_queue(skb, rx_ring->queue_index);
6120 }
6121
6122 dma = dma_map_single(rx_ring->dev, skb->data,
6123 IGB_RX_HDR_LEN, DMA_FROM_DEVICE);
6124
6125 if (dma_mapping_error(rx_ring->dev, dma)) {
6126 rx_ring->rx_stats.alloc_failed++;
6127 return false;
6128 }
6129
6130 bi->dma = dma;
6131 return true;
6132}
6133
6134static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6135 struct igb_rx_buffer *bi)
6136{
6137 struct page *page = bi->page;
6138 dma_addr_t page_dma = bi->page_dma;
6139 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
6140
6141 if (page_dma)
6142 return true;
6143
6144 if (!page) {
6145 page = alloc_page(GFP_ATOMIC | __GFP_COLD);
6146 bi->page = page;
6147 if (unlikely(!page)) {
6148 rx_ring->rx_stats.alloc_failed++;
6149 return false;
6150 }
6151 }
6152
6153 page_dma = dma_map_page(rx_ring->dev, page,
6154 page_offset, PAGE_SIZE / 2,
6155 DMA_FROM_DEVICE);
6156
6157 if (dma_mapping_error(rx_ring->dev, page_dma)) {
6158 rx_ring->rx_stats.alloc_failed++;
6159 return false;
6160 }
6161
6162 bi->page_dma = page_dma;
6163 bi->page_offset = page_offset;
6164 return true;
6165}
6166
6167/**
6168 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6169 * @adapter: address of board private structure
6170 **/
6171void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6172{
6173 union e1000_adv_rx_desc *rx_desc;
6174 struct igb_rx_buffer *bi;
6175 u16 i = rx_ring->next_to_use;
6176
6177 rx_desc = IGB_RX_DESC(rx_ring, i);
6178 bi = &rx_ring->rx_buffer_info[i];
6179 i -= rx_ring->count;
6180
6181 while (cleaned_count--) {
6182 if (!igb_alloc_mapped_skb(rx_ring, bi))
6183 break;
6184
6185 /* Refresh the desc even if buffer_addrs didn't change
6186 * because each write-back erases this info. */
6187 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
6188
6189 if (!igb_alloc_mapped_page(rx_ring, bi))
6190 break;
6191
6192 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
6193
6194 rx_desc++;
6195 bi++;
6196 i++;
6197 if (unlikely(!i)) {
6198 rx_desc = IGB_RX_DESC(rx_ring, 0);
6199 bi = rx_ring->rx_buffer_info;
6200 i -= rx_ring->count;
6201 }
6202
6203 /* clear the hdr_addr for the next_to_use descriptor */
6204 rx_desc->read.hdr_addr = 0;
6205 }
6206
6207 i += rx_ring->count;
6208
6209 if (rx_ring->next_to_use != i) {
6210 rx_ring->next_to_use = i;
6211
6212 /* Force memory writes to complete before letting h/w
6213 * know there are new descriptors to fetch. (Only
6214 * applicable for weak-ordered memory model archs,
6215 * such as IA-64). */
6216 wmb();
6217 writel(i, rx_ring->tail);
6218 }
6219}
6220
6221/**
6222 * igb_mii_ioctl -
6223 * @netdev:
6224 * @ifreq:
6225 * @cmd:
6226 **/
6227static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6228{
6229 struct igb_adapter *adapter = netdev_priv(netdev);
6230 struct mii_ioctl_data *data = if_mii(ifr);
6231
6232 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6233 return -EOPNOTSUPP;
6234
6235 switch (cmd) {
6236 case SIOCGMIIPHY:
6237 data->phy_id = adapter->hw.phy.addr;
6238 break;
6239 case SIOCGMIIREG:
6240 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6241 &data->val_out))
6242 return -EIO;
6243 break;
6244 case SIOCSMIIREG:
6245 default:
6246 return -EOPNOTSUPP;
6247 }
6248 return 0;
6249}
6250
6251/**
6252 * igb_hwtstamp_ioctl - control hardware time stamping
6253 * @netdev:
6254 * @ifreq:
6255 * @cmd:
6256 *
6257 * Outgoing time stamping can be enabled and disabled. Play nice and
6258 * disable it when requested, although it shouldn't case any overhead
6259 * when no packet needs it. At most one packet in the queue may be
6260 * marked for time stamping, otherwise it would be impossible to tell
6261 * for sure to which packet the hardware time stamp belongs.
6262 *
6263 * Incoming time stamping has to be configured via the hardware
6264 * filters. Not all combinations are supported, in particular event
6265 * type has to be specified. Matching the kind of event packet is
6266 * not supported, with the exception of "all V2 events regardless of
6267 * level 2 or 4".
6268 *
6269 **/
6270static int igb_hwtstamp_ioctl(struct net_device *netdev,
6271 struct ifreq *ifr, int cmd)
6272{
6273 struct igb_adapter *adapter = netdev_priv(netdev);
6274 struct e1000_hw *hw = &adapter->hw;
6275 struct hwtstamp_config config;
6276 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
6277 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
6278 u32 tsync_rx_cfg = 0;
6279 bool is_l4 = false;
6280 bool is_l2 = false;
6281 u32 regval;
6282
6283 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6284 return -EFAULT;
6285
6286 /* reserved for future extensions */
6287 if (config.flags)
6288 return -EINVAL;
6289
6290 switch (config.tx_type) {
6291 case HWTSTAMP_TX_OFF:
6292 tsync_tx_ctl = 0;
6293 case HWTSTAMP_TX_ON:
6294 break;
6295 default:
6296 return -ERANGE;
6297 }
6298
6299 switch (config.rx_filter) {
6300 case HWTSTAMP_FILTER_NONE:
6301 tsync_rx_ctl = 0;
6302 break;
6303 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6304 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6305 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6306 case HWTSTAMP_FILTER_ALL:
6307 /*
6308 * register TSYNCRXCFG must be set, therefore it is not
6309 * possible to time stamp both Sync and Delay_Req messages
6310 * => fall back to time stamping all packets
6311 */
6312 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
6313 config.rx_filter = HWTSTAMP_FILTER_ALL;
6314 break;
6315 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6316 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
6317 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
6318 is_l4 = true;
6319 break;
6320 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6321 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
6322 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
6323 is_l4 = true;
6324 break;
6325 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6326 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6327 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
6328 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
6329 is_l2 = true;
6330 is_l4 = true;
6331 config.rx_filter = HWTSTAMP_FILTER_SOME;
6332 break;
6333 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6334 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6335 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
6336 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
6337 is_l2 = true;
6338 is_l4 = true;
6339 config.rx_filter = HWTSTAMP_FILTER_SOME;
6340 break;
6341 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6342 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6343 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6344 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
6345 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
6346 is_l2 = true;
6347 is_l4 = true;
6348 break;
6349 default:
6350 return -ERANGE;
6351 }
6352
6353 if (hw->mac.type == e1000_82575) {
6354 if (tsync_rx_ctl | tsync_tx_ctl)
6355 return -EINVAL;
6356 return 0;
6357 }
6358
6359 /*
6360 * Per-packet timestamping only works if all packets are
6361 * timestamped, so enable timestamping in all packets as
6362 * long as one rx filter was configured.
6363 */
6364 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
6365 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
6366 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
6367 }
6368
6369 /* enable/disable TX */
6370 regval = rd32(E1000_TSYNCTXCTL);
6371 regval &= ~E1000_TSYNCTXCTL_ENABLED;
6372 regval |= tsync_tx_ctl;
6373 wr32(E1000_TSYNCTXCTL, regval);
6374
6375 /* enable/disable RX */
6376 regval = rd32(E1000_TSYNCRXCTL);
6377 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
6378 regval |= tsync_rx_ctl;
6379 wr32(E1000_TSYNCRXCTL, regval);
6380
6381 /* define which PTP packets are time stamped */
6382 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
6383
6384 /* define ethertype filter for timestamped packets */
6385 if (is_l2)
6386 wr32(E1000_ETQF(3),
6387 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
6388 E1000_ETQF_1588 | /* enable timestamping */
6389 ETH_P_1588)); /* 1588 eth protocol type */
6390 else
6391 wr32(E1000_ETQF(3), 0);
6392
6393#define PTP_PORT 319
6394 /* L4 Queue Filter[3]: filter by destination port and protocol */
6395 if (is_l4) {
6396 u32 ftqf = (IPPROTO_UDP /* UDP */
6397 | E1000_FTQF_VF_BP /* VF not compared */
6398 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
6399 | E1000_FTQF_MASK); /* mask all inputs */
6400 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
6401
6402 wr32(E1000_IMIR(3), htons(PTP_PORT));
6403 wr32(E1000_IMIREXT(3),
6404 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
6405 if (hw->mac.type == e1000_82576) {
6406 /* enable source port check */
6407 wr32(E1000_SPQF(3), htons(PTP_PORT));
6408 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
6409 }
6410 wr32(E1000_FTQF(3), ftqf);
6411 } else {
6412 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
6413 }
6414 wrfl();
6415
6416 adapter->hwtstamp_config = config;
6417
6418 /* clear TX/RX time stamp registers, just to be sure */
6419 regval = rd32(E1000_TXSTMPH);
6420 regval = rd32(E1000_RXSTMPH);
6421
6422 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
6423 -EFAULT : 0;
6424}
6425
6426/**
6427 * igb_ioctl -
6428 * @netdev:
6429 * @ifreq:
6430 * @cmd:
6431 **/
6432static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6433{
6434 switch (cmd) {
6435 case SIOCGMIIPHY:
6436 case SIOCGMIIREG:
6437 case SIOCSMIIREG:
6438 return igb_mii_ioctl(netdev, ifr, cmd);
6439 case SIOCSHWTSTAMP:
6440 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
6441 default:
6442 return -EOPNOTSUPP;
6443 }
6444}
6445
6446s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6447{
6448 struct igb_adapter *adapter = hw->back;
6449 u16 cap_offset;
6450
6451 cap_offset = adapter->pdev->pcie_cap;
6452 if (!cap_offset)
6453 return -E1000_ERR_CONFIG;
6454
6455 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
6456
6457 return 0;
6458}
6459
6460s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6461{
6462 struct igb_adapter *adapter = hw->back;
6463 u16 cap_offset;
6464
6465 cap_offset = adapter->pdev->pcie_cap;
6466 if (!cap_offset)
6467 return -E1000_ERR_CONFIG;
6468
6469 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
6470
6471 return 0;
6472}
6473
6474static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6475{
6476 struct igb_adapter *adapter = netdev_priv(netdev);
6477 struct e1000_hw *hw = &adapter->hw;
6478 u32 ctrl, rctl;
6479 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
6480
6481 if (enable) {
6482 /* enable VLAN tag insert/strip */
6483 ctrl = rd32(E1000_CTRL);
6484 ctrl |= E1000_CTRL_VME;
6485 wr32(E1000_CTRL, ctrl);
6486
6487 /* Disable CFI check */
6488 rctl = rd32(E1000_RCTL);
6489 rctl &= ~E1000_RCTL_CFIEN;
6490 wr32(E1000_RCTL, rctl);
6491 } else {
6492 /* disable VLAN tag insert/strip */
6493 ctrl = rd32(E1000_CTRL);
6494 ctrl &= ~E1000_CTRL_VME;
6495 wr32(E1000_CTRL, ctrl);
6496 }
6497
6498 igb_rlpml_set(adapter);
6499}
6500
6501static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6502{
6503 struct igb_adapter *adapter = netdev_priv(netdev);
6504 struct e1000_hw *hw = &adapter->hw;
6505 int pf_id = adapter->vfs_allocated_count;
6506
6507 /* attempt to add filter to vlvf array */
6508 igb_vlvf_set(adapter, vid, true, pf_id);
6509
6510 /* add the filter since PF can receive vlans w/o entry in vlvf */
6511 igb_vfta_set(hw, vid, true);
6512
6513 set_bit(vid, adapter->active_vlans);
6514
6515 return 0;
6516}
6517
6518static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6519{
6520 struct igb_adapter *adapter = netdev_priv(netdev);
6521 struct e1000_hw *hw = &adapter->hw;
6522 int pf_id = adapter->vfs_allocated_count;
6523 s32 err;
6524
6525 /* remove vlan from VLVF table array */
6526 err = igb_vlvf_set(adapter, vid, false, pf_id);
6527
6528 /* if vid was not present in VLVF just remove it from table */
6529 if (err)
6530 igb_vfta_set(hw, vid, false);
6531
6532 clear_bit(vid, adapter->active_vlans);
6533
6534 return 0;
6535}
6536
6537static void igb_restore_vlan(struct igb_adapter *adapter)
6538{
6539 u16 vid;
6540
6541 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6542
6543 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6544 igb_vlan_rx_add_vid(adapter->netdev, vid);
6545}
6546
6547int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
6548{
6549 struct pci_dev *pdev = adapter->pdev;
6550 struct e1000_mac_info *mac = &adapter->hw.mac;
6551
6552 mac->autoneg = 0;
6553
6554 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6555 * for the switch() below to work */
6556 if ((spd & 1) || (dplx & ~1))
6557 goto err_inval;
6558
6559 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6560 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
6561 spd != SPEED_1000 &&
6562 dplx != DUPLEX_FULL)
6563 goto err_inval;
6564
6565 switch (spd + dplx) {
6566 case SPEED_10 + DUPLEX_HALF:
6567 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6568 break;
6569 case SPEED_10 + DUPLEX_FULL:
6570 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6571 break;
6572 case SPEED_100 + DUPLEX_HALF:
6573 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6574 break;
6575 case SPEED_100 + DUPLEX_FULL:
6576 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6577 break;
6578 case SPEED_1000 + DUPLEX_FULL:
6579 mac->autoneg = 1;
6580 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6581 break;
6582 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6583 default:
6584 goto err_inval;
6585 }
6586 return 0;
6587
6588err_inval:
6589 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6590 return -EINVAL;
6591}
6592
6593static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6594 bool runtime)
6595{
6596 struct net_device *netdev = pci_get_drvdata(pdev);
6597 struct igb_adapter *adapter = netdev_priv(netdev);
6598 struct e1000_hw *hw = &adapter->hw;
6599 u32 ctrl, rctl, status;
6600 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6601#ifdef CONFIG_PM
6602 int retval = 0;
6603#endif
6604
6605 netif_device_detach(netdev);
6606
6607 if (netif_running(netdev))
6608 __igb_close(netdev, true);
6609
6610 igb_clear_interrupt_scheme(adapter);
6611
6612#ifdef CONFIG_PM
6613 retval = pci_save_state(pdev);
6614 if (retval)
6615 return retval;
6616#endif
6617
6618 status = rd32(E1000_STATUS);
6619 if (status & E1000_STATUS_LU)
6620 wufc &= ~E1000_WUFC_LNKC;
6621
6622 if (wufc) {
6623 igb_setup_rctl(adapter);
6624 igb_set_rx_mode(netdev);
6625
6626 /* turn on all-multi mode if wake on multicast is enabled */
6627 if (wufc & E1000_WUFC_MC) {
6628 rctl = rd32(E1000_RCTL);
6629 rctl |= E1000_RCTL_MPE;
6630 wr32(E1000_RCTL, rctl);
6631 }
6632
6633 ctrl = rd32(E1000_CTRL);
6634 /* advertise wake from D3Cold */
6635 #define E1000_CTRL_ADVD3WUC 0x00100000
6636 /* phy power management enable */
6637 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6638 ctrl |= E1000_CTRL_ADVD3WUC;
6639 wr32(E1000_CTRL, ctrl);
6640
6641 /* Allow time for pending master requests to run */
6642 igb_disable_pcie_master(hw);
6643
6644 wr32(E1000_WUC, E1000_WUC_PME_EN);
6645 wr32(E1000_WUFC, wufc);
6646 } else {
6647 wr32(E1000_WUC, 0);
6648 wr32(E1000_WUFC, 0);
6649 }
6650
6651 *enable_wake = wufc || adapter->en_mng_pt;
6652 if (!*enable_wake)
6653 igb_power_down_link(adapter);
6654 else
6655 igb_power_up_link(adapter);
6656
6657 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6658 * would have already happened in close and is redundant. */
6659 igb_release_hw_control(adapter);
6660
6661 pci_disable_device(pdev);
6662
6663 return 0;
6664}
6665
6666#ifdef CONFIG_PM
6667#ifdef CONFIG_PM_SLEEP
6668static int igb_suspend(struct device *dev)
6669{
6670 int retval;
6671 bool wake;
6672 struct pci_dev *pdev = to_pci_dev(dev);
6673
6674 retval = __igb_shutdown(pdev, &wake, 0);
6675 if (retval)
6676 return retval;
6677
6678 if (wake) {
6679 pci_prepare_to_sleep(pdev);
6680 } else {
6681 pci_wake_from_d3(pdev, false);
6682 pci_set_power_state(pdev, PCI_D3hot);
6683 }
6684
6685 return 0;
6686}
6687#endif /* CONFIG_PM_SLEEP */
6688
6689static int igb_resume(struct device *dev)
6690{
6691 struct pci_dev *pdev = to_pci_dev(dev);
6692 struct net_device *netdev = pci_get_drvdata(pdev);
6693 struct igb_adapter *adapter = netdev_priv(netdev);
6694 struct e1000_hw *hw = &adapter->hw;
6695 u32 err;
6696
6697 pci_set_power_state(pdev, PCI_D0);
6698 pci_restore_state(pdev);
6699 pci_save_state(pdev);
6700
6701 err = pci_enable_device_mem(pdev);
6702 if (err) {
6703 dev_err(&pdev->dev,
6704 "igb: Cannot enable PCI device from suspend\n");
6705 return err;
6706 }
6707 pci_set_master(pdev);
6708
6709 pci_enable_wake(pdev, PCI_D3hot, 0);
6710 pci_enable_wake(pdev, PCI_D3cold, 0);
6711
6712 if (igb_init_interrupt_scheme(adapter)) {
6713 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6714 return -ENOMEM;
6715 }
6716
6717 igb_reset(adapter);
6718
6719 /* let the f/w know that the h/w is now under the control of the
6720 * driver. */
6721 igb_get_hw_control(adapter);
6722
6723 wr32(E1000_WUS, ~0);
6724
6725 if (netdev->flags & IFF_UP) {
6726 err = __igb_open(netdev, true);
6727 if (err)
6728 return err;
6729 }
6730
6731 netif_device_attach(netdev);
6732 return 0;
6733}
6734
6735#ifdef CONFIG_PM_RUNTIME
6736static int igb_runtime_idle(struct device *dev)
6737{
6738 struct pci_dev *pdev = to_pci_dev(dev);
6739 struct net_device *netdev = pci_get_drvdata(pdev);
6740 struct igb_adapter *adapter = netdev_priv(netdev);
6741
6742 if (!igb_has_link(adapter))
6743 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6744
6745 return -EBUSY;
6746}
6747
6748static int igb_runtime_suspend(struct device *dev)
6749{
6750 struct pci_dev *pdev = to_pci_dev(dev);
6751 int retval;
6752 bool wake;
6753
6754 retval = __igb_shutdown(pdev, &wake, 1);
6755 if (retval)
6756 return retval;
6757
6758 if (wake) {
6759 pci_prepare_to_sleep(pdev);
6760 } else {
6761 pci_wake_from_d3(pdev, false);
6762 pci_set_power_state(pdev, PCI_D3hot);
6763 }
6764
6765 return 0;
6766}
6767
6768static int igb_runtime_resume(struct device *dev)
6769{
6770 return igb_resume(dev);
6771}
6772#endif /* CONFIG_PM_RUNTIME */
6773#endif
6774
6775static void igb_shutdown(struct pci_dev *pdev)
6776{
6777 bool wake;
6778
6779 __igb_shutdown(pdev, &wake, 0);
6780
6781 if (system_state == SYSTEM_POWER_OFF) {
6782 pci_wake_from_d3(pdev, wake);
6783 pci_set_power_state(pdev, PCI_D3hot);
6784 }
6785}
6786
6787#ifdef CONFIG_NET_POLL_CONTROLLER
6788/*
6789 * Polling 'interrupt' - used by things like netconsole to send skbs
6790 * without having to re-enable interrupts. It's not called while
6791 * the interrupt routine is executing.
6792 */
6793static void igb_netpoll(struct net_device *netdev)
6794{
6795 struct igb_adapter *adapter = netdev_priv(netdev);
6796 struct e1000_hw *hw = &adapter->hw;
6797 struct igb_q_vector *q_vector;
6798 int i;
6799
6800 for (i = 0; i < adapter->num_q_vectors; i++) {
6801 q_vector = adapter->q_vector[i];
6802 if (adapter->msix_entries)
6803 wr32(E1000_EIMC, q_vector->eims_value);
6804 else
6805 igb_irq_disable(adapter);
6806 napi_schedule(&q_vector->napi);
6807 }
6808}
6809#endif /* CONFIG_NET_POLL_CONTROLLER */
6810
6811/**
6812 * igb_io_error_detected - called when PCI error is detected
6813 * @pdev: Pointer to PCI device
6814 * @state: The current pci connection state
6815 *
6816 * This function is called after a PCI bus error affecting
6817 * this device has been detected.
6818 */
6819static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6820 pci_channel_state_t state)
6821{
6822 struct net_device *netdev = pci_get_drvdata(pdev);
6823 struct igb_adapter *adapter = netdev_priv(netdev);
6824
6825 netif_device_detach(netdev);
6826
6827 if (state == pci_channel_io_perm_failure)
6828 return PCI_ERS_RESULT_DISCONNECT;
6829
6830 if (netif_running(netdev))
6831 igb_down(adapter);
6832 pci_disable_device(pdev);
6833
6834 /* Request a slot slot reset. */
6835 return PCI_ERS_RESULT_NEED_RESET;
6836}
6837
6838/**
6839 * igb_io_slot_reset - called after the pci bus has been reset.
6840 * @pdev: Pointer to PCI device
6841 *
6842 * Restart the card from scratch, as if from a cold-boot. Implementation
6843 * resembles the first-half of the igb_resume routine.
6844 */
6845static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6846{
6847 struct net_device *netdev = pci_get_drvdata(pdev);
6848 struct igb_adapter *adapter = netdev_priv(netdev);
6849 struct e1000_hw *hw = &adapter->hw;
6850 pci_ers_result_t result;
6851 int err;
6852
6853 if (pci_enable_device_mem(pdev)) {
6854 dev_err(&pdev->dev,
6855 "Cannot re-enable PCI device after reset.\n");
6856 result = PCI_ERS_RESULT_DISCONNECT;
6857 } else {
6858 pci_set_master(pdev);
6859 pci_restore_state(pdev);
6860 pci_save_state(pdev);
6861
6862 pci_enable_wake(pdev, PCI_D3hot, 0);
6863 pci_enable_wake(pdev, PCI_D3cold, 0);
6864
6865 igb_reset(adapter);
6866 wr32(E1000_WUS, ~0);
6867 result = PCI_ERS_RESULT_RECOVERED;
6868 }
6869
6870 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6871 if (err) {
6872 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6873 "failed 0x%0x\n", err);
6874 /* non-fatal, continue */
6875 }
6876
6877 return result;
6878}
6879
6880/**
6881 * igb_io_resume - called when traffic can start flowing again.
6882 * @pdev: Pointer to PCI device
6883 *
6884 * This callback is called when the error recovery driver tells us that
6885 * its OK to resume normal operation. Implementation resembles the
6886 * second-half of the igb_resume routine.
6887 */
6888static void igb_io_resume(struct pci_dev *pdev)
6889{
6890 struct net_device *netdev = pci_get_drvdata(pdev);
6891 struct igb_adapter *adapter = netdev_priv(netdev);
6892
6893 if (netif_running(netdev)) {
6894 if (igb_up(adapter)) {
6895 dev_err(&pdev->dev, "igb_up failed after reset\n");
6896 return;
6897 }
6898 }
6899
6900 netif_device_attach(netdev);
6901
6902 /* let the f/w know that the h/w is now under the control of the
6903 * driver. */
6904 igb_get_hw_control(adapter);
6905}
6906
6907static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6908 u8 qsel)
6909{
6910 u32 rar_low, rar_high;
6911 struct e1000_hw *hw = &adapter->hw;
6912
6913 /* HW expects these in little endian so we reverse the byte order
6914 * from network order (big endian) to little endian
6915 */
6916 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6917 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6918 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6919
6920 /* Indicate to hardware the Address is Valid. */
6921 rar_high |= E1000_RAH_AV;
6922
6923 if (hw->mac.type == e1000_82575)
6924 rar_high |= E1000_RAH_POOL_1 * qsel;
6925 else
6926 rar_high |= E1000_RAH_POOL_1 << qsel;
6927
6928 wr32(E1000_RAL(index), rar_low);
6929 wrfl();
6930 wr32(E1000_RAH(index), rar_high);
6931 wrfl();
6932}
6933
6934static int igb_set_vf_mac(struct igb_adapter *adapter,
6935 int vf, unsigned char *mac_addr)
6936{
6937 struct e1000_hw *hw = &adapter->hw;
6938 /* VF MAC addresses start at end of receive addresses and moves
6939 * torwards the first, as a result a collision should not be possible */
6940 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6941
6942 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
6943
6944 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
6945
6946 return 0;
6947}
6948
6949static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6950{
6951 struct igb_adapter *adapter = netdev_priv(netdev);
6952 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6953 return -EINVAL;
6954 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6955 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6956 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6957 " change effective.");
6958 if (test_bit(__IGB_DOWN, &adapter->state)) {
6959 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6960 " but the PF device is not up.\n");
6961 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6962 " attempting to use the VF device.\n");
6963 }
6964 return igb_set_vf_mac(adapter, vf, mac);
6965}
6966
6967static int igb_link_mbps(int internal_link_speed)
6968{
6969 switch (internal_link_speed) {
6970 case SPEED_100:
6971 return 100;
6972 case SPEED_1000:
6973 return 1000;
6974 default:
6975 return 0;
6976 }
6977}
6978
6979static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
6980 int link_speed)
6981{
6982 int rf_dec, rf_int;
6983 u32 bcnrc_val;
6984
6985 if (tx_rate != 0) {
6986 /* Calculate the rate factor values to set */
6987 rf_int = link_speed / tx_rate;
6988 rf_dec = (link_speed - (rf_int * tx_rate));
6989 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
6990
6991 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
6992 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
6993 E1000_RTTBCNRC_RF_INT_MASK);
6994 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
6995 } else {
6996 bcnrc_val = 0;
6997 }
6998
6999 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7000 wr32(E1000_RTTBCNRC, bcnrc_val);
7001}
7002
7003static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7004{
7005 int actual_link_speed, i;
7006 bool reset_rate = false;
7007
7008 /* VF TX rate limit was not set or not supported */
7009 if ((adapter->vf_rate_link_speed == 0) ||
7010 (adapter->hw.mac.type != e1000_82576))
7011 return;
7012
7013 actual_link_speed = igb_link_mbps(adapter->link_speed);
7014 if (actual_link_speed != adapter->vf_rate_link_speed) {
7015 reset_rate = true;
7016 adapter->vf_rate_link_speed = 0;
7017 dev_info(&adapter->pdev->dev,
7018 "Link speed has been changed. VF Transmit "
7019 "rate is disabled\n");
7020 }
7021
7022 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7023 if (reset_rate)
7024 adapter->vf_data[i].tx_rate = 0;
7025
7026 igb_set_vf_rate_limit(&adapter->hw, i,
7027 adapter->vf_data[i].tx_rate,
7028 actual_link_speed);
7029 }
7030}
7031
7032static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7033{
7034 struct igb_adapter *adapter = netdev_priv(netdev);
7035 struct e1000_hw *hw = &adapter->hw;
7036 int actual_link_speed;
7037
7038 if (hw->mac.type != e1000_82576)
7039 return -EOPNOTSUPP;
7040
7041 actual_link_speed = igb_link_mbps(adapter->link_speed);
7042 if ((vf >= adapter->vfs_allocated_count) ||
7043 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7044 (tx_rate < 0) || (tx_rate > actual_link_speed))
7045 return -EINVAL;
7046
7047 adapter->vf_rate_link_speed = actual_link_speed;
7048 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7049 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7050
7051 return 0;
7052}
7053
7054static int igb_ndo_get_vf_config(struct net_device *netdev,
7055 int vf, struct ifla_vf_info *ivi)
7056{
7057 struct igb_adapter *adapter = netdev_priv(netdev);
7058 if (vf >= adapter->vfs_allocated_count)
7059 return -EINVAL;
7060 ivi->vf = vf;
7061 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7062 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7063 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7064 ivi->qos = adapter->vf_data[vf].pf_qos;
7065 return 0;
7066}
7067
7068static void igb_vmm_control(struct igb_adapter *adapter)
7069{
7070 struct e1000_hw *hw = &adapter->hw;
7071 u32 reg;
7072
7073 switch (hw->mac.type) {
7074 case e1000_82575:
7075 case e1000_i210:
7076 case e1000_i211:
7077 default:
7078 /* replication is not supported for 82575 */
7079 return;
7080 case e1000_82576:
7081 /* notify HW that the MAC is adding vlan tags */
7082 reg = rd32(E1000_DTXCTL);
7083 reg |= E1000_DTXCTL_VLAN_ADDED;
7084 wr32(E1000_DTXCTL, reg);
7085 case e1000_82580:
7086 /* enable replication vlan tag stripping */
7087 reg = rd32(E1000_RPLOLR);
7088 reg |= E1000_RPLOLR_STRVLAN;
7089 wr32(E1000_RPLOLR, reg);
7090 case e1000_i350:
7091 /* none of the above registers are supported by i350 */
7092 break;
7093 }
7094
7095 if (adapter->vfs_allocated_count) {
7096 igb_vmdq_set_loopback_pf(hw, true);
7097 igb_vmdq_set_replication_pf(hw, true);
7098 igb_vmdq_set_anti_spoofing_pf(hw, true,
7099 adapter->vfs_allocated_count);
7100 } else {
7101 igb_vmdq_set_loopback_pf(hw, false);
7102 igb_vmdq_set_replication_pf(hw, false);
7103 }
7104}
7105
7106static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7107{
7108 struct e1000_hw *hw = &adapter->hw;
7109 u32 dmac_thr;
7110 u16 hwm;
7111
7112 if (hw->mac.type > e1000_82580) {
7113 if (adapter->flags & IGB_FLAG_DMAC) {
7114 u32 reg;
7115
7116 /* force threshold to 0. */
7117 wr32(E1000_DMCTXTH, 0);
7118
7119 /*
7120 * DMA Coalescing high water mark needs to be greater
7121 * than the Rx threshold. Set hwm to PBA - max frame
7122 * size in 16B units, capping it at PBA - 6KB.
7123 */
7124 hwm = 64 * pba - adapter->max_frame_size / 16;
7125 if (hwm < 64 * (pba - 6))
7126 hwm = 64 * (pba - 6);
7127 reg = rd32(E1000_FCRTC);
7128 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7129 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7130 & E1000_FCRTC_RTH_COAL_MASK);
7131 wr32(E1000_FCRTC, reg);
7132
7133 /*
7134 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7135 * frame size, capping it at PBA - 10KB.
7136 */
7137 dmac_thr = pba - adapter->max_frame_size / 512;
7138 if (dmac_thr < pba - 10)
7139 dmac_thr = pba - 10;
7140 reg = rd32(E1000_DMACR);
7141 reg &= ~E1000_DMACR_DMACTHR_MASK;
7142 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7143 & E1000_DMACR_DMACTHR_MASK);
7144
7145 /* transition to L0x or L1 if available..*/
7146 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7147
7148 /* watchdog timer= +-1000 usec in 32usec intervals */
7149 reg |= (1000 >> 5);
7150
7151 /* Disable BMC-to-OS Watchdog Enable */
7152 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7153 wr32(E1000_DMACR, reg);
7154
7155 /*
7156 * no lower threshold to disable
7157 * coalescing(smart fifb)-UTRESH=0
7158 */
7159 wr32(E1000_DMCRTRH, 0);
7160
7161 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7162
7163 wr32(E1000_DMCTLX, reg);
7164
7165 /*
7166 * free space in tx packet buffer to wake from
7167 * DMA coal
7168 */
7169 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7170 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7171
7172 /*
7173 * make low power state decision controlled
7174 * by DMA coal
7175 */
7176 reg = rd32(E1000_PCIEMISC);
7177 reg &= ~E1000_PCIEMISC_LX_DECISION;
7178 wr32(E1000_PCIEMISC, reg);
7179 } /* endif adapter->dmac is not disabled */
7180 } else if (hw->mac.type == e1000_82580) {
7181 u32 reg = rd32(E1000_PCIEMISC);
7182 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7183 wr32(E1000_DMACR, 0);
7184 }
7185}
7186
7187/* igb_main.c */
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/bitops.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/netdevice.h>
13#include <linux/ipv6.h>
14#include <linux/slab.h>
15#include <net/checksum.h>
16#include <net/ip6_checksum.h>
17#include <net/pkt_sched.h>
18#include <net/pkt_cls.h>
19#include <linux/net_tstamp.h>
20#include <linux/mii.h>
21#include <linux/ethtool.h>
22#include <linux/if.h>
23#include <linux/if_vlan.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/ip.h>
28#include <linux/tcp.h>
29#include <linux/sctp.h>
30#include <linux/if_ether.h>
31#include <linux/aer.h>
32#include <linux/prefetch.h>
33#include <linux/bpf.h>
34#include <linux/bpf_trace.h>
35#include <linux/pm_runtime.h>
36#include <linux/etherdevice.h>
37#ifdef CONFIG_IGB_DCA
38#include <linux/dca.h>
39#endif
40#include <linux/i2c.h>
41#include "igb.h"
42
43enum queue_mode {
44 QUEUE_MODE_STRICT_PRIORITY,
45 QUEUE_MODE_STREAM_RESERVATION,
46};
47
48enum tx_queue_prio {
49 TX_QUEUE_PRIO_HIGH,
50 TX_QUEUE_PRIO_LOW,
51};
52
53char igb_driver_name[] = "igb";
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
56static const char igb_copyright[] =
57 "Copyright (c) 2007-2014 Intel Corporation.";
58
59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static const struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
99 /* required last entry */
100 {0, }
101};
102
103MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
104
105static int igb_setup_all_tx_resources(struct igb_adapter *);
106static int igb_setup_all_rx_resources(struct igb_adapter *);
107static void igb_free_all_tx_resources(struct igb_adapter *);
108static void igb_free_all_rx_resources(struct igb_adapter *);
109static void igb_setup_mrqc(struct igb_adapter *);
110static int igb_probe(struct pci_dev *, const struct pci_device_id *);
111static void igb_remove(struct pci_dev *pdev);
112static int igb_sw_init(struct igb_adapter *);
113int igb_open(struct net_device *);
114int igb_close(struct net_device *);
115static void igb_configure(struct igb_adapter *);
116static void igb_configure_tx(struct igb_adapter *);
117static void igb_configure_rx(struct igb_adapter *);
118static void igb_clean_all_tx_rings(struct igb_adapter *);
119static void igb_clean_all_rx_rings(struct igb_adapter *);
120static void igb_clean_tx_ring(struct igb_ring *);
121static void igb_clean_rx_ring(struct igb_ring *);
122static void igb_set_rx_mode(struct net_device *);
123static void igb_update_phy_info(struct timer_list *);
124static void igb_watchdog(struct timer_list *);
125static void igb_watchdog_task(struct work_struct *);
126static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
127static void igb_get_stats64(struct net_device *dev,
128 struct rtnl_link_stats64 *stats);
129static int igb_change_mtu(struct net_device *, int);
130static int igb_set_mac(struct net_device *, void *);
131static void igb_set_uta(struct igb_adapter *adapter, bool set);
132static irqreturn_t igb_intr(int irq, void *);
133static irqreturn_t igb_intr_msi(int irq, void *);
134static irqreturn_t igb_msix_other(int irq, void *);
135static irqreturn_t igb_msix_ring(int irq, void *);
136#ifdef CONFIG_IGB_DCA
137static void igb_update_dca(struct igb_q_vector *);
138static void igb_setup_dca(struct igb_adapter *);
139#endif /* CONFIG_IGB_DCA */
140static int igb_poll(struct napi_struct *, int);
141static bool igb_clean_tx_irq(struct igb_q_vector *, int);
142static int igb_clean_rx_irq(struct igb_q_vector *, int);
143static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
144static void igb_tx_timeout(struct net_device *, unsigned int txqueue);
145static void igb_reset_task(struct work_struct *);
146static void igb_vlan_mode(struct net_device *netdev,
147 netdev_features_t features);
148static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
149static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
150static void igb_restore_vlan(struct igb_adapter *);
151static void igb_rar_set_index(struct igb_adapter *, u32);
152static void igb_ping_all_vfs(struct igb_adapter *);
153static void igb_msg_task(struct igb_adapter *);
154static void igb_vmm_control(struct igb_adapter *);
155static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
156static void igb_flush_mac_table(struct igb_adapter *);
157static int igb_available_rars(struct igb_adapter *, u8);
158static void igb_set_default_mac_filter(struct igb_adapter *);
159static int igb_uc_sync(struct net_device *, const unsigned char *);
160static int igb_uc_unsync(struct net_device *, const unsigned char *);
161static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
162static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
163static int igb_ndo_set_vf_vlan(struct net_device *netdev,
164 int vf, u16 vlan, u8 qos, __be16 vlan_proto);
165static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
166static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
167 bool setting);
168static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
169 bool setting);
170static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 struct ifla_vf_info *ivi);
172static void igb_check_vf_rate_limit(struct igb_adapter *);
173static void igb_nfc_filter_exit(struct igb_adapter *adapter);
174static void igb_nfc_filter_restore(struct igb_adapter *adapter);
175
176#ifdef CONFIG_PCI_IOV
177static int igb_vf_configure(struct igb_adapter *adapter, int vf);
178static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
179static int igb_disable_sriov(struct pci_dev *dev);
180static int igb_pci_disable_sriov(struct pci_dev *dev);
181#endif
182
183static int igb_suspend(struct device *);
184static int igb_resume(struct device *);
185static int igb_runtime_suspend(struct device *dev);
186static int igb_runtime_resume(struct device *dev);
187static int igb_runtime_idle(struct device *dev);
188static const struct dev_pm_ops igb_pm_ops = {
189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
191 igb_runtime_idle)
192};
193static void igb_shutdown(struct pci_dev *);
194static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
195#ifdef CONFIG_IGB_DCA
196static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
197static struct notifier_block dca_notifier = {
198 .notifier_call = igb_notify_dca,
199 .next = NULL,
200 .priority = 0
201};
202#endif
203#ifdef CONFIG_PCI_IOV
204static unsigned int max_vfs;
205module_param(max_vfs, uint, 0);
206MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
207#endif /* CONFIG_PCI_IOV */
208
209static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
210 pci_channel_state_t);
211static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
212static void igb_io_resume(struct pci_dev *);
213
214static const struct pci_error_handlers igb_err_handler = {
215 .error_detected = igb_io_error_detected,
216 .slot_reset = igb_io_slot_reset,
217 .resume = igb_io_resume,
218};
219
220static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
221
222static struct pci_driver igb_driver = {
223 .name = igb_driver_name,
224 .id_table = igb_pci_tbl,
225 .probe = igb_probe,
226 .remove = igb_remove,
227#ifdef CONFIG_PM
228 .driver.pm = &igb_pm_ops,
229#endif
230 .shutdown = igb_shutdown,
231 .sriov_configure = igb_pci_sriov_configure,
232 .err_handler = &igb_err_handler
233};
234
235MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
236MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
237MODULE_LICENSE("GPL v2");
238
239#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
240static int debug = -1;
241module_param(debug, int, 0);
242MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
243
244struct igb_reg_info {
245 u32 ofs;
246 char *name;
247};
248
249static const struct igb_reg_info igb_reg_info_tbl[] = {
250
251 /* General Registers */
252 {E1000_CTRL, "CTRL"},
253 {E1000_STATUS, "STATUS"},
254 {E1000_CTRL_EXT, "CTRL_EXT"},
255
256 /* Interrupt Registers */
257 {E1000_ICR, "ICR"},
258
259 /* RX Registers */
260 {E1000_RCTL, "RCTL"},
261 {E1000_RDLEN(0), "RDLEN"},
262 {E1000_RDH(0), "RDH"},
263 {E1000_RDT(0), "RDT"},
264 {E1000_RXDCTL(0), "RXDCTL"},
265 {E1000_RDBAL(0), "RDBAL"},
266 {E1000_RDBAH(0), "RDBAH"},
267
268 /* TX Registers */
269 {E1000_TCTL, "TCTL"},
270 {E1000_TDBAL(0), "TDBAL"},
271 {E1000_TDBAH(0), "TDBAH"},
272 {E1000_TDLEN(0), "TDLEN"},
273 {E1000_TDH(0), "TDH"},
274 {E1000_TDT(0), "TDT"},
275 {E1000_TXDCTL(0), "TXDCTL"},
276 {E1000_TDFH, "TDFH"},
277 {E1000_TDFT, "TDFT"},
278 {E1000_TDFHS, "TDFHS"},
279 {E1000_TDFPC, "TDFPC"},
280
281 /* List Terminator */
282 {}
283};
284
285/* igb_regdump - register printout routine */
286static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
287{
288 int n = 0;
289 char rname[16];
290 u32 regs[8];
291
292 switch (reginfo->ofs) {
293 case E1000_RDLEN(0):
294 for (n = 0; n < 4; n++)
295 regs[n] = rd32(E1000_RDLEN(n));
296 break;
297 case E1000_RDH(0):
298 for (n = 0; n < 4; n++)
299 regs[n] = rd32(E1000_RDH(n));
300 break;
301 case E1000_RDT(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_RDT(n));
304 break;
305 case E1000_RXDCTL(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RXDCTL(n));
308 break;
309 case E1000_RDBAL(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDBAL(n));
312 break;
313 case E1000_RDBAH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDBAH(n));
316 break;
317 case E1000_TDBAL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_TDBAL(n));
320 break;
321 case E1000_TDBAH(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_TDBAH(n));
324 break;
325 case E1000_TDLEN(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_TDLEN(n));
328 break;
329 case E1000_TDH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_TDH(n));
332 break;
333 case E1000_TDT(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDT(n));
336 break;
337 case E1000_TXDCTL(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TXDCTL(n));
340 break;
341 default:
342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
343 return;
344 }
345
346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
348 regs[2], regs[3]);
349}
350
351/* igb_dump - Print registers, Tx-rings and Rx-rings */
352static void igb_dump(struct igb_adapter *adapter)
353{
354 struct net_device *netdev = adapter->netdev;
355 struct e1000_hw *hw = &adapter->hw;
356 struct igb_reg_info *reginfo;
357 struct igb_ring *tx_ring;
358 union e1000_adv_tx_desc *tx_desc;
359 struct my_u0 { __le64 a; __le64 b; } *u0;
360 struct igb_ring *rx_ring;
361 union e1000_adv_rx_desc *rx_desc;
362 u32 staterr;
363 u16 i, n;
364
365 if (!netif_msg_hw(adapter))
366 return;
367
368 /* Print netdevice Info */
369 if (netdev) {
370 dev_info(&adapter->pdev->dev, "Net device Info\n");
371 pr_info("Device Name state trans_start\n");
372 pr_info("%-15s %016lX %016lX\n", netdev->name,
373 netdev->state, dev_trans_start(netdev));
374 }
375
376 /* Print Registers */
377 dev_info(&adapter->pdev->dev, "Register Dump\n");
378 pr_info(" Register Name Value\n");
379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
380 reginfo->name; reginfo++) {
381 igb_regdump(hw, reginfo);
382 }
383
384 /* Print TX Ring Summary */
385 if (!netdev || !netif_running(netdev))
386 goto exit;
387
388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
390 for (n = 0; n < adapter->num_tx_queues; n++) {
391 struct igb_tx_buffer *buffer_info;
392 tx_ring = adapter->tx_ring[n];
393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
395 n, tx_ring->next_to_use, tx_ring->next_to_clean,
396 (u64)dma_unmap_addr(buffer_info, dma),
397 dma_unmap_len(buffer_info, len),
398 buffer_info->next_to_watch,
399 (u64)buffer_info->time_stamp);
400 }
401
402 /* Print TX Rings */
403 if (!netif_msg_tx_done(adapter))
404 goto rx_ring_summary;
405
406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
407
408 /* Transmit Descriptor Formats
409 *
410 * Advanced Transmit Descriptor
411 * +--------------------------------------------------------------+
412 * 0 | Buffer Address [63:0] |
413 * +--------------------------------------------------------------+
414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
415 * +--------------------------------------------------------------+
416 * 63 46 45 40 39 38 36 35 32 31 24 15 0
417 */
418
419 for (n = 0; n < adapter->num_tx_queues; n++) {
420 tx_ring = adapter->tx_ring[n];
421 pr_info("------------------------------------\n");
422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
423 pr_info("------------------------------------\n");
424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
425
426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
427 const char *next_desc;
428 struct igb_tx_buffer *buffer_info;
429 tx_desc = IGB_TX_DESC(tx_ring, i);
430 buffer_info = &tx_ring->tx_buffer_info[i];
431 u0 = (struct my_u0 *)tx_desc;
432 if (i == tx_ring->next_to_use &&
433 i == tx_ring->next_to_clean)
434 next_desc = " NTC/U";
435 else if (i == tx_ring->next_to_use)
436 next_desc = " NTU";
437 else if (i == tx_ring->next_to_clean)
438 next_desc = " NTC";
439 else
440 next_desc = "";
441
442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
443 i, le64_to_cpu(u0->a),
444 le64_to_cpu(u0->b),
445 (u64)dma_unmap_addr(buffer_info, dma),
446 dma_unmap_len(buffer_info, len),
447 buffer_info->next_to_watch,
448 (u64)buffer_info->time_stamp,
449 buffer_info->skb, next_desc);
450
451 if (netif_msg_pktdata(adapter) && buffer_info->skb)
452 print_hex_dump(KERN_INFO, "",
453 DUMP_PREFIX_ADDRESS,
454 16, 1, buffer_info->skb->data,
455 dma_unmap_len(buffer_info, len),
456 true);
457 }
458 }
459
460 /* Print RX Rings Summary */
461rx_ring_summary:
462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
463 pr_info("Queue [NTU] [NTC]\n");
464 for (n = 0; n < adapter->num_rx_queues; n++) {
465 rx_ring = adapter->rx_ring[n];
466 pr_info(" %5d %5X %5X\n",
467 n, rx_ring->next_to_use, rx_ring->next_to_clean);
468 }
469
470 /* Print RX Rings */
471 if (!netif_msg_rx_status(adapter))
472 goto exit;
473
474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
475
476 /* Advanced Receive Descriptor (Read) Format
477 * 63 1 0
478 * +-----------------------------------------------------+
479 * 0 | Packet Buffer Address [63:1] |A0/NSE|
480 * +----------------------------------------------+------+
481 * 8 | Header Buffer Address [63:1] | DD |
482 * +-----------------------------------------------------+
483 *
484 *
485 * Advanced Receive Descriptor (Write-Back) Format
486 *
487 * 63 48 47 32 31 30 21 20 17 16 4 3 0
488 * +------------------------------------------------------+
489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
490 * | Checksum Ident | | | | Type | Type |
491 * +------------------------------------------------------+
492 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
493 * +------------------------------------------------------+
494 * 63 48 47 32 31 20 19 0
495 */
496
497 for (n = 0; n < adapter->num_rx_queues; n++) {
498 rx_ring = adapter->rx_ring[n];
499 pr_info("------------------------------------\n");
500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
501 pr_info("------------------------------------\n");
502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
504
505 for (i = 0; i < rx_ring->count; i++) {
506 const char *next_desc;
507 struct igb_rx_buffer *buffer_info;
508 buffer_info = &rx_ring->rx_buffer_info[i];
509 rx_desc = IGB_RX_DESC(rx_ring, i);
510 u0 = (struct my_u0 *)rx_desc;
511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512
513 if (i == rx_ring->next_to_use)
514 next_desc = " NTU";
515 else if (i == rx_ring->next_to_clean)
516 next_desc = " NTC";
517 else
518 next_desc = "";
519
520 if (staterr & E1000_RXD_STAT_DD) {
521 /* Descriptor Done */
522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
523 "RWB", i,
524 le64_to_cpu(u0->a),
525 le64_to_cpu(u0->b),
526 next_desc);
527 } else {
528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
529 "R ", i,
530 le64_to_cpu(u0->a),
531 le64_to_cpu(u0->b),
532 (u64)buffer_info->dma,
533 next_desc);
534
535 if (netif_msg_pktdata(adapter) &&
536 buffer_info->dma && buffer_info->page) {
537 print_hex_dump(KERN_INFO, "",
538 DUMP_PREFIX_ADDRESS,
539 16, 1,
540 page_address(buffer_info->page) +
541 buffer_info->page_offset,
542 igb_rx_bufsz(rx_ring), true);
543 }
544 }
545 }
546 }
547
548exit:
549 return;
550}
551
552/**
553 * igb_get_i2c_data - Reads the I2C SDA data bit
554 * @data: opaque pointer to adapter struct
555 *
556 * Returns the I2C data bit value
557 **/
558static int igb_get_i2c_data(void *data)
559{
560 struct igb_adapter *adapter = (struct igb_adapter *)data;
561 struct e1000_hw *hw = &adapter->hw;
562 s32 i2cctl = rd32(E1000_I2CPARAMS);
563
564 return !!(i2cctl & E1000_I2C_DATA_IN);
565}
566
567/**
568 * igb_set_i2c_data - Sets the I2C data bit
569 * @data: pointer to hardware structure
570 * @state: I2C data value (0 or 1) to set
571 *
572 * Sets the I2C data bit
573 **/
574static void igb_set_i2c_data(void *data, int state)
575{
576 struct igb_adapter *adapter = (struct igb_adapter *)data;
577 struct e1000_hw *hw = &adapter->hw;
578 s32 i2cctl = rd32(E1000_I2CPARAMS);
579
580 if (state)
581 i2cctl |= E1000_I2C_DATA_OUT;
582 else
583 i2cctl &= ~E1000_I2C_DATA_OUT;
584
585 i2cctl &= ~E1000_I2C_DATA_OE_N;
586 i2cctl |= E1000_I2C_CLK_OE_N;
587 wr32(E1000_I2CPARAMS, i2cctl);
588 wrfl();
589
590}
591
592/**
593 * igb_set_i2c_clk - Sets the I2C SCL clock
594 * @data: pointer to hardware structure
595 * @state: state to set clock
596 *
597 * Sets the I2C clock line to state
598 **/
599static void igb_set_i2c_clk(void *data, int state)
600{
601 struct igb_adapter *adapter = (struct igb_adapter *)data;
602 struct e1000_hw *hw = &adapter->hw;
603 s32 i2cctl = rd32(E1000_I2CPARAMS);
604
605 if (state) {
606 i2cctl |= E1000_I2C_CLK_OUT;
607 i2cctl &= ~E1000_I2C_CLK_OE_N;
608 } else {
609 i2cctl &= ~E1000_I2C_CLK_OUT;
610 i2cctl &= ~E1000_I2C_CLK_OE_N;
611 }
612 wr32(E1000_I2CPARAMS, i2cctl);
613 wrfl();
614}
615
616/**
617 * igb_get_i2c_clk - Gets the I2C SCL clock state
618 * @data: pointer to hardware structure
619 *
620 * Gets the I2C clock state
621 **/
622static int igb_get_i2c_clk(void *data)
623{
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
627
628 return !!(i2cctl & E1000_I2C_CLK_IN);
629}
630
631static const struct i2c_algo_bit_data igb_i2c_algo = {
632 .setsda = igb_set_i2c_data,
633 .setscl = igb_set_i2c_clk,
634 .getsda = igb_get_i2c_data,
635 .getscl = igb_get_i2c_clk,
636 .udelay = 5,
637 .timeout = 20,
638};
639
640/**
641 * igb_get_hw_dev - return device
642 * @hw: pointer to hardware structure
643 *
644 * used by hardware layer to print debugging information
645 **/
646struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
647{
648 struct igb_adapter *adapter = hw->back;
649 return adapter->netdev;
650}
651
652/**
653 * igb_init_module - Driver Registration Routine
654 *
655 * igb_init_module is the first routine called when the driver is
656 * loaded. All it does is register with the PCI subsystem.
657 **/
658static int __init igb_init_module(void)
659{
660 int ret;
661
662 pr_info("%s\n", igb_driver_string);
663 pr_info("%s\n", igb_copyright);
664
665#ifdef CONFIG_IGB_DCA
666 dca_register_notify(&dca_notifier);
667#endif
668 ret = pci_register_driver(&igb_driver);
669 return ret;
670}
671
672module_init(igb_init_module);
673
674/**
675 * igb_exit_module - Driver Exit Cleanup Routine
676 *
677 * igb_exit_module is called just before the driver is removed
678 * from memory.
679 **/
680static void __exit igb_exit_module(void)
681{
682#ifdef CONFIG_IGB_DCA
683 dca_unregister_notify(&dca_notifier);
684#endif
685 pci_unregister_driver(&igb_driver);
686}
687
688module_exit(igb_exit_module);
689
690#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
691/**
692 * igb_cache_ring_register - Descriptor ring to register mapping
693 * @adapter: board private structure to initialize
694 *
695 * Once we know the feature-set enabled for the device, we'll cache
696 * the register offset the descriptor ring is assigned to.
697 **/
698static void igb_cache_ring_register(struct igb_adapter *adapter)
699{
700 int i = 0, j = 0;
701 u32 rbase_offset = adapter->vfs_allocated_count;
702
703 switch (adapter->hw.mac.type) {
704 case e1000_82576:
705 /* The queues are allocated for virtualization such that VF 0
706 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
707 * In order to avoid collision we start at the first free queue
708 * and continue consuming queues in the same sequence
709 */
710 if (adapter->vfs_allocated_count) {
711 for (; i < adapter->rss_queues; i++)
712 adapter->rx_ring[i]->reg_idx = rbase_offset +
713 Q_IDX_82576(i);
714 }
715 fallthrough;
716 case e1000_82575:
717 case e1000_82580:
718 case e1000_i350:
719 case e1000_i354:
720 case e1000_i210:
721 case e1000_i211:
722 default:
723 for (; i < adapter->num_rx_queues; i++)
724 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
725 for (; j < adapter->num_tx_queues; j++)
726 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
727 break;
728 }
729}
730
731u32 igb_rd32(struct e1000_hw *hw, u32 reg)
732{
733 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
734 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
735 u32 value = 0;
736
737 if (E1000_REMOVED(hw_addr))
738 return ~value;
739
740 value = readl(&hw_addr[reg]);
741
742 /* reads should not return all F's */
743 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
744 struct net_device *netdev = igb->netdev;
745 hw->hw_addr = NULL;
746 netdev_err(netdev, "PCIe link lost\n");
747 WARN(pci_device_is_present(igb->pdev),
748 "igb: Failed to read reg 0x%x!\n", reg);
749 }
750
751 return value;
752}
753
754/**
755 * igb_write_ivar - configure ivar for given MSI-X vector
756 * @hw: pointer to the HW structure
757 * @msix_vector: vector number we are allocating to a given ring
758 * @index: row index of IVAR register to write within IVAR table
759 * @offset: column offset of in IVAR, should be multiple of 8
760 *
761 * This function is intended to handle the writing of the IVAR register
762 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
763 * each containing an cause allocation for an Rx and Tx ring, and a
764 * variable number of rows depending on the number of queues supported.
765 **/
766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
767 int index, int offset)
768{
769 u32 ivar = array_rd32(E1000_IVAR0, index);
770
771 /* clear any bits that are currently set */
772 ivar &= ~((u32)0xFF << offset);
773
774 /* write vector and valid bit */
775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
776
777 array_wr32(E1000_IVAR0, index, ivar);
778}
779
780#define IGB_N0_QUEUE -1
781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
782{
783 struct igb_adapter *adapter = q_vector->adapter;
784 struct e1000_hw *hw = &adapter->hw;
785 int rx_queue = IGB_N0_QUEUE;
786 int tx_queue = IGB_N0_QUEUE;
787 u32 msixbm = 0;
788
789 if (q_vector->rx.ring)
790 rx_queue = q_vector->rx.ring->reg_idx;
791 if (q_vector->tx.ring)
792 tx_queue = q_vector->tx.ring->reg_idx;
793
794 switch (hw->mac.type) {
795 case e1000_82575:
796 /* The 82575 assigns vectors using a bitmask, which matches the
797 * bitmask for the EICR/EIMS/EIMC registers. To assign one
798 * or more queues to a vector, we write the appropriate bits
799 * into the MSIXBM register for that vector.
800 */
801 if (rx_queue > IGB_N0_QUEUE)
802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
803 if (tx_queue > IGB_N0_QUEUE)
804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
806 msixbm |= E1000_EIMS_OTHER;
807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
808 q_vector->eims_value = msixbm;
809 break;
810 case e1000_82576:
811 /* 82576 uses a table that essentially consists of 2 columns
812 * with 8 rows. The ordering is column-major so we use the
813 * lower 3 bits as the row index, and the 4th bit as the
814 * column offset.
815 */
816 if (rx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
818 rx_queue & 0x7,
819 (rx_queue & 0x8) << 1);
820 if (tx_queue > IGB_N0_QUEUE)
821 igb_write_ivar(hw, msix_vector,
822 tx_queue & 0x7,
823 ((tx_queue & 0x8) << 1) + 8);
824 q_vector->eims_value = BIT(msix_vector);
825 break;
826 case e1000_82580:
827 case e1000_i350:
828 case e1000_i354:
829 case e1000_i210:
830 case e1000_i211:
831 /* On 82580 and newer adapters the scheme is similar to 82576
832 * however instead of ordering column-major we have things
833 * ordered row-major. So we traverse the table by using
834 * bit 0 as the column offset, and the remaining bits as the
835 * row index.
836 */
837 if (rx_queue > IGB_N0_QUEUE)
838 igb_write_ivar(hw, msix_vector,
839 rx_queue >> 1,
840 (rx_queue & 0x1) << 4);
841 if (tx_queue > IGB_N0_QUEUE)
842 igb_write_ivar(hw, msix_vector,
843 tx_queue >> 1,
844 ((tx_queue & 0x1) << 4) + 8);
845 q_vector->eims_value = BIT(msix_vector);
846 break;
847 default:
848 BUG();
849 break;
850 }
851
852 /* add q_vector eims value to global eims_enable_mask */
853 adapter->eims_enable_mask |= q_vector->eims_value;
854
855 /* configure q_vector to set itr on first interrupt */
856 q_vector->set_itr = 1;
857}
858
859/**
860 * igb_configure_msix - Configure MSI-X hardware
861 * @adapter: board private structure to initialize
862 *
863 * igb_configure_msix sets up the hardware to properly
864 * generate MSI-X interrupts.
865 **/
866static void igb_configure_msix(struct igb_adapter *adapter)
867{
868 u32 tmp;
869 int i, vector = 0;
870 struct e1000_hw *hw = &adapter->hw;
871
872 adapter->eims_enable_mask = 0;
873
874 /* set vector for other causes, i.e. link changes */
875 switch (hw->mac.type) {
876 case e1000_82575:
877 tmp = rd32(E1000_CTRL_EXT);
878 /* enable MSI-X PBA support*/
879 tmp |= E1000_CTRL_EXT_PBA_CLR;
880
881 /* Auto-Mask interrupts upon ICR read. */
882 tmp |= E1000_CTRL_EXT_EIAME;
883 tmp |= E1000_CTRL_EXT_IRCA;
884
885 wr32(E1000_CTRL_EXT, tmp);
886
887 /* enable msix_other interrupt */
888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
889 adapter->eims_other = E1000_EIMS_OTHER;
890
891 break;
892
893 case e1000_82576:
894 case e1000_82580:
895 case e1000_i350:
896 case e1000_i354:
897 case e1000_i210:
898 case e1000_i211:
899 /* Turn on MSI-X capability first, or our settings
900 * won't stick. And it will take days to debug.
901 */
902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
903 E1000_GPIE_PBA | E1000_GPIE_EIAME |
904 E1000_GPIE_NSICR);
905
906 /* enable msix_other interrupt */
907 adapter->eims_other = BIT(vector);
908 tmp = (vector++ | E1000_IVAR_VALID) << 8;
909
910 wr32(E1000_IVAR_MISC, tmp);
911 break;
912 default:
913 /* do nothing, since nothing else supports MSI-X */
914 break;
915 } /* switch (hw->mac.type) */
916
917 adapter->eims_enable_mask |= adapter->eims_other;
918
919 for (i = 0; i < adapter->num_q_vectors; i++)
920 igb_assign_vector(adapter->q_vector[i], vector++);
921
922 wrfl();
923}
924
925/**
926 * igb_request_msix - Initialize MSI-X interrupts
927 * @adapter: board private structure to initialize
928 *
929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
930 * kernel.
931 **/
932static int igb_request_msix(struct igb_adapter *adapter)
933{
934 unsigned int num_q_vectors = adapter->num_q_vectors;
935 struct net_device *netdev = adapter->netdev;
936 int i, err = 0, vector = 0, free_vector = 0;
937
938 err = request_irq(adapter->msix_entries[vector].vector,
939 igb_msix_other, 0, netdev->name, adapter);
940 if (err)
941 goto err_out;
942
943 if (num_q_vectors > MAX_Q_VECTORS) {
944 num_q_vectors = MAX_Q_VECTORS;
945 dev_warn(&adapter->pdev->dev,
946 "The number of queue vectors (%d) is higher than max allowed (%d)\n",
947 adapter->num_q_vectors, MAX_Q_VECTORS);
948 }
949 for (i = 0; i < num_q_vectors; i++) {
950 struct igb_q_vector *q_vector = adapter->q_vector[i];
951
952 vector++;
953
954 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
955
956 if (q_vector->rx.ring && q_vector->tx.ring)
957 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
958 q_vector->rx.ring->queue_index);
959 else if (q_vector->tx.ring)
960 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
961 q_vector->tx.ring->queue_index);
962 else if (q_vector->rx.ring)
963 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
964 q_vector->rx.ring->queue_index);
965 else
966 sprintf(q_vector->name, "%s-unused", netdev->name);
967
968 err = request_irq(adapter->msix_entries[vector].vector,
969 igb_msix_ring, 0, q_vector->name,
970 q_vector);
971 if (err)
972 goto err_free;
973 }
974
975 igb_configure_msix(adapter);
976 return 0;
977
978err_free:
979 /* free already assigned IRQs */
980 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
981
982 vector--;
983 for (i = 0; i < vector; i++) {
984 free_irq(adapter->msix_entries[free_vector++].vector,
985 adapter->q_vector[i]);
986 }
987err_out:
988 return err;
989}
990
991/**
992 * igb_free_q_vector - Free memory allocated for specific interrupt vector
993 * @adapter: board private structure to initialize
994 * @v_idx: Index of vector to be freed
995 *
996 * This function frees the memory allocated to the q_vector.
997 **/
998static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
999{
1000 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1001
1002 adapter->q_vector[v_idx] = NULL;
1003
1004 /* igb_get_stats64() might access the rings on this vector,
1005 * we must wait a grace period before freeing it.
1006 */
1007 if (q_vector)
1008 kfree_rcu(q_vector, rcu);
1009}
1010
1011/**
1012 * igb_reset_q_vector - Reset config for interrupt vector
1013 * @adapter: board private structure to initialize
1014 * @v_idx: Index of vector to be reset
1015 *
1016 * If NAPI is enabled it will delete any references to the
1017 * NAPI struct. This is preparation for igb_free_q_vector.
1018 **/
1019static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1020{
1021 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1022
1023 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1024 * allocated. So, q_vector is NULL so we should stop here.
1025 */
1026 if (!q_vector)
1027 return;
1028
1029 if (q_vector->tx.ring)
1030 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1031
1032 if (q_vector->rx.ring)
1033 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1034
1035 netif_napi_del(&q_vector->napi);
1036
1037}
1038
1039static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1040{
1041 int v_idx = adapter->num_q_vectors;
1042
1043 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1044 pci_disable_msix(adapter->pdev);
1045 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1046 pci_disable_msi(adapter->pdev);
1047
1048 while (v_idx--)
1049 igb_reset_q_vector(adapter, v_idx);
1050}
1051
1052/**
1053 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1054 * @adapter: board private structure to initialize
1055 *
1056 * This function frees the memory allocated to the q_vectors. In addition if
1057 * NAPI is enabled it will delete any references to the NAPI struct prior
1058 * to freeing the q_vector.
1059 **/
1060static void igb_free_q_vectors(struct igb_adapter *adapter)
1061{
1062 int v_idx = adapter->num_q_vectors;
1063
1064 adapter->num_tx_queues = 0;
1065 adapter->num_rx_queues = 0;
1066 adapter->num_q_vectors = 0;
1067
1068 while (v_idx--) {
1069 igb_reset_q_vector(adapter, v_idx);
1070 igb_free_q_vector(adapter, v_idx);
1071 }
1072}
1073
1074/**
1075 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1076 * @adapter: board private structure to initialize
1077 *
1078 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1079 * MSI-X interrupts allocated.
1080 */
1081static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1082{
1083 igb_free_q_vectors(adapter);
1084 igb_reset_interrupt_capability(adapter);
1085}
1086
1087/**
1088 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1089 * @adapter: board private structure to initialize
1090 * @msix: boolean value of MSIX capability
1091 *
1092 * Attempt to configure interrupts using the best available
1093 * capabilities of the hardware and kernel.
1094 **/
1095static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1096{
1097 int err;
1098 int numvecs, i;
1099
1100 if (!msix)
1101 goto msi_only;
1102 adapter->flags |= IGB_FLAG_HAS_MSIX;
1103
1104 /* Number of supported queues. */
1105 adapter->num_rx_queues = adapter->rss_queues;
1106 if (adapter->vfs_allocated_count)
1107 adapter->num_tx_queues = 1;
1108 else
1109 adapter->num_tx_queues = adapter->rss_queues;
1110
1111 /* start with one vector for every Rx queue */
1112 numvecs = adapter->num_rx_queues;
1113
1114 /* if Tx handler is separate add 1 for every Tx queue */
1115 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1116 numvecs += adapter->num_tx_queues;
1117
1118 /* store the number of vectors reserved for queues */
1119 adapter->num_q_vectors = numvecs;
1120
1121 /* add 1 vector for link status interrupts */
1122 numvecs++;
1123 for (i = 0; i < numvecs; i++)
1124 adapter->msix_entries[i].entry = i;
1125
1126 err = pci_enable_msix_range(adapter->pdev,
1127 adapter->msix_entries,
1128 numvecs,
1129 numvecs);
1130 if (err > 0)
1131 return;
1132
1133 igb_reset_interrupt_capability(adapter);
1134
1135 /* If we can't do MSI-X, try MSI */
1136msi_only:
1137 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1138#ifdef CONFIG_PCI_IOV
1139 /* disable SR-IOV for non MSI-X configurations */
1140 if (adapter->vf_data) {
1141 struct e1000_hw *hw = &adapter->hw;
1142 /* disable iov and allow time for transactions to clear */
1143 pci_disable_sriov(adapter->pdev);
1144 msleep(500);
1145
1146 kfree(adapter->vf_mac_list);
1147 adapter->vf_mac_list = NULL;
1148 kfree(adapter->vf_data);
1149 adapter->vf_data = NULL;
1150 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1151 wrfl();
1152 msleep(100);
1153 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1154 }
1155#endif
1156 adapter->vfs_allocated_count = 0;
1157 adapter->rss_queues = 1;
1158 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1159 adapter->num_rx_queues = 1;
1160 adapter->num_tx_queues = 1;
1161 adapter->num_q_vectors = 1;
1162 if (!pci_enable_msi(adapter->pdev))
1163 adapter->flags |= IGB_FLAG_HAS_MSI;
1164}
1165
1166static void igb_add_ring(struct igb_ring *ring,
1167 struct igb_ring_container *head)
1168{
1169 head->ring = ring;
1170 head->count++;
1171}
1172
1173/**
1174 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1175 * @adapter: board private structure to initialize
1176 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1177 * @v_idx: index of vector in adapter struct
1178 * @txr_count: total number of Tx rings to allocate
1179 * @txr_idx: index of first Tx ring to allocate
1180 * @rxr_count: total number of Rx rings to allocate
1181 * @rxr_idx: index of first Rx ring to allocate
1182 *
1183 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1184 **/
1185static int igb_alloc_q_vector(struct igb_adapter *adapter,
1186 int v_count, int v_idx,
1187 int txr_count, int txr_idx,
1188 int rxr_count, int rxr_idx)
1189{
1190 struct igb_q_vector *q_vector;
1191 struct igb_ring *ring;
1192 int ring_count;
1193 size_t size;
1194
1195 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1196 if (txr_count > 1 || rxr_count > 1)
1197 return -ENOMEM;
1198
1199 ring_count = txr_count + rxr_count;
1200 size = struct_size(q_vector, ring, ring_count);
1201
1202 /* allocate q_vector and rings */
1203 q_vector = adapter->q_vector[v_idx];
1204 if (!q_vector) {
1205 q_vector = kzalloc(size, GFP_KERNEL);
1206 } else if (size > ksize(q_vector)) {
1207 kfree_rcu(q_vector, rcu);
1208 q_vector = kzalloc(size, GFP_KERNEL);
1209 } else {
1210 memset(q_vector, 0, size);
1211 }
1212 if (!q_vector)
1213 return -ENOMEM;
1214
1215 /* initialize NAPI */
1216 netif_napi_add(adapter->netdev, &q_vector->napi,
1217 igb_poll, 64);
1218
1219 /* tie q_vector and adapter together */
1220 adapter->q_vector[v_idx] = q_vector;
1221 q_vector->adapter = adapter;
1222
1223 /* initialize work limits */
1224 q_vector->tx.work_limit = adapter->tx_work_limit;
1225
1226 /* initialize ITR configuration */
1227 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1228 q_vector->itr_val = IGB_START_ITR;
1229
1230 /* initialize pointer to rings */
1231 ring = q_vector->ring;
1232
1233 /* intialize ITR */
1234 if (rxr_count) {
1235 /* rx or rx/tx vector */
1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1237 q_vector->itr_val = adapter->rx_itr_setting;
1238 } else {
1239 /* tx only vector */
1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1241 q_vector->itr_val = adapter->tx_itr_setting;
1242 }
1243
1244 if (txr_count) {
1245 /* assign generic ring traits */
1246 ring->dev = &adapter->pdev->dev;
1247 ring->netdev = adapter->netdev;
1248
1249 /* configure backlink on ring */
1250 ring->q_vector = q_vector;
1251
1252 /* update q_vector Tx values */
1253 igb_add_ring(ring, &q_vector->tx);
1254
1255 /* For 82575, context index must be unique per ring. */
1256 if (adapter->hw.mac.type == e1000_82575)
1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1258
1259 /* apply Tx specific ring traits */
1260 ring->count = adapter->tx_ring_count;
1261 ring->queue_index = txr_idx;
1262
1263 ring->cbs_enable = false;
1264 ring->idleslope = 0;
1265 ring->sendslope = 0;
1266 ring->hicredit = 0;
1267 ring->locredit = 0;
1268
1269 u64_stats_init(&ring->tx_syncp);
1270 u64_stats_init(&ring->tx_syncp2);
1271
1272 /* assign ring to adapter */
1273 adapter->tx_ring[txr_idx] = ring;
1274
1275 /* push pointer to next ring */
1276 ring++;
1277 }
1278
1279 if (rxr_count) {
1280 /* assign generic ring traits */
1281 ring->dev = &adapter->pdev->dev;
1282 ring->netdev = adapter->netdev;
1283
1284 /* configure backlink on ring */
1285 ring->q_vector = q_vector;
1286
1287 /* update q_vector Rx values */
1288 igb_add_ring(ring, &q_vector->rx);
1289
1290 /* set flag indicating ring supports SCTP checksum offload */
1291 if (adapter->hw.mac.type >= e1000_82576)
1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1293
1294 /* On i350, i354, i210, and i211, loopback VLAN packets
1295 * have the tag byte-swapped.
1296 */
1297 if (adapter->hw.mac.type >= e1000_i350)
1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1299
1300 /* apply Rx specific ring traits */
1301 ring->count = adapter->rx_ring_count;
1302 ring->queue_index = rxr_idx;
1303
1304 u64_stats_init(&ring->rx_syncp);
1305
1306 /* assign ring to adapter */
1307 adapter->rx_ring[rxr_idx] = ring;
1308 }
1309
1310 return 0;
1311}
1312
1313
1314/**
1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316 * @adapter: board private structure to initialize
1317 *
1318 * We allocate one q_vector per queue interrupt. If allocation fails we
1319 * return -ENOMEM.
1320 **/
1321static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1322{
1323 int q_vectors = adapter->num_q_vectors;
1324 int rxr_remaining = adapter->num_rx_queues;
1325 int txr_remaining = adapter->num_tx_queues;
1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327 int err;
1328
1329 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330 for (; rxr_remaining; v_idx++) {
1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332 0, 0, 1, rxr_idx);
1333
1334 if (err)
1335 goto err_out;
1336
1337 /* update counts and index */
1338 rxr_remaining--;
1339 rxr_idx++;
1340 }
1341 }
1342
1343 for (; v_idx < q_vectors; v_idx++) {
1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1346
1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 tqpv, txr_idx, rqpv, rxr_idx);
1349
1350 if (err)
1351 goto err_out;
1352
1353 /* update counts and index */
1354 rxr_remaining -= rqpv;
1355 txr_remaining -= tqpv;
1356 rxr_idx++;
1357 txr_idx++;
1358 }
1359
1360 return 0;
1361
1362err_out:
1363 adapter->num_tx_queues = 0;
1364 adapter->num_rx_queues = 0;
1365 adapter->num_q_vectors = 0;
1366
1367 while (v_idx--)
1368 igb_free_q_vector(adapter, v_idx);
1369
1370 return -ENOMEM;
1371}
1372
1373/**
1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375 * @adapter: board private structure to initialize
1376 * @msix: boolean value of MSIX capability
1377 *
1378 * This function initializes the interrupts and allocates all of the queues.
1379 **/
1380static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1381{
1382 struct pci_dev *pdev = adapter->pdev;
1383 int err;
1384
1385 igb_set_interrupt_capability(adapter, msix);
1386
1387 err = igb_alloc_q_vectors(adapter);
1388 if (err) {
1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 goto err_alloc_q_vectors;
1391 }
1392
1393 igb_cache_ring_register(adapter);
1394
1395 return 0;
1396
1397err_alloc_q_vectors:
1398 igb_reset_interrupt_capability(adapter);
1399 return err;
1400}
1401
1402/**
1403 * igb_request_irq - initialize interrupts
1404 * @adapter: board private structure to initialize
1405 *
1406 * Attempts to configure interrupts using the best available
1407 * capabilities of the hardware and kernel.
1408 **/
1409static int igb_request_irq(struct igb_adapter *adapter)
1410{
1411 struct net_device *netdev = adapter->netdev;
1412 struct pci_dev *pdev = adapter->pdev;
1413 int err = 0;
1414
1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1416 err = igb_request_msix(adapter);
1417 if (!err)
1418 goto request_done;
1419 /* fall back to MSI */
1420 igb_free_all_tx_resources(adapter);
1421 igb_free_all_rx_resources(adapter);
1422
1423 igb_clear_interrupt_scheme(adapter);
1424 err = igb_init_interrupt_scheme(adapter, false);
1425 if (err)
1426 goto request_done;
1427
1428 igb_setup_all_tx_resources(adapter);
1429 igb_setup_all_rx_resources(adapter);
1430 igb_configure(adapter);
1431 }
1432
1433 igb_assign_vector(adapter->q_vector[0], 0);
1434
1435 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1436 err = request_irq(pdev->irq, igb_intr_msi, 0,
1437 netdev->name, adapter);
1438 if (!err)
1439 goto request_done;
1440
1441 /* fall back to legacy interrupts */
1442 igb_reset_interrupt_capability(adapter);
1443 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1444 }
1445
1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1447 netdev->name, adapter);
1448
1449 if (err)
1450 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1451 err);
1452
1453request_done:
1454 return err;
1455}
1456
1457static void igb_free_irq(struct igb_adapter *adapter)
1458{
1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1460 int vector = 0, i;
1461
1462 free_irq(adapter->msix_entries[vector++].vector, adapter);
1463
1464 for (i = 0; i < adapter->num_q_vectors; i++)
1465 free_irq(adapter->msix_entries[vector++].vector,
1466 adapter->q_vector[i]);
1467 } else {
1468 free_irq(adapter->pdev->irq, adapter);
1469 }
1470}
1471
1472/**
1473 * igb_irq_disable - Mask off interrupt generation on the NIC
1474 * @adapter: board private structure
1475 **/
1476static void igb_irq_disable(struct igb_adapter *adapter)
1477{
1478 struct e1000_hw *hw = &adapter->hw;
1479
1480 /* we need to be careful when disabling interrupts. The VFs are also
1481 * mapped into these registers and so clearing the bits can cause
1482 * issues on the VF drivers so we only need to clear what we set
1483 */
1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1485 u32 regval = rd32(E1000_EIAM);
1486
1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489 regval = rd32(E1000_EIAC);
1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1491 }
1492
1493 wr32(E1000_IAM, 0);
1494 wr32(E1000_IMC, ~0);
1495 wrfl();
1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1497 int i;
1498
1499 for (i = 0; i < adapter->num_q_vectors; i++)
1500 synchronize_irq(adapter->msix_entries[i].vector);
1501 } else {
1502 synchronize_irq(adapter->pdev->irq);
1503 }
1504}
1505
1506/**
1507 * igb_irq_enable - Enable default interrupt generation settings
1508 * @adapter: board private structure
1509 **/
1510static void igb_irq_enable(struct igb_adapter *adapter)
1511{
1512 struct e1000_hw *hw = &adapter->hw;
1513
1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1516 u32 regval = rd32(E1000_EIAC);
1517
1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519 regval = rd32(E1000_EIAM);
1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1521 wr32(E1000_EIMS, adapter->eims_enable_mask);
1522 if (adapter->vfs_allocated_count) {
1523 wr32(E1000_MBVFIMR, 0xFF);
1524 ims |= E1000_IMS_VMMB;
1525 }
1526 wr32(E1000_IMS, ims);
1527 } else {
1528 wr32(E1000_IMS, IMS_ENABLE_MASK |
1529 E1000_IMS_DRSTA);
1530 wr32(E1000_IAM, IMS_ENABLE_MASK |
1531 E1000_IMS_DRSTA);
1532 }
1533}
1534
1535static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536{
1537 struct e1000_hw *hw = &adapter->hw;
1538 u16 pf_id = adapter->vfs_allocated_count;
1539 u16 vid = adapter->hw.mng_cookie.vlan_id;
1540 u16 old_vid = adapter->mng_vlan_id;
1541
1542 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1543 /* add VID to filter table */
1544 igb_vfta_set(hw, vid, pf_id, true, true);
1545 adapter->mng_vlan_id = vid;
1546 } else {
1547 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1548 }
1549
1550 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1551 (vid != old_vid) &&
1552 !test_bit(old_vid, adapter->active_vlans)) {
1553 /* remove VID from filter table */
1554 igb_vfta_set(hw, vid, pf_id, false, true);
1555 }
1556}
1557
1558/**
1559 * igb_release_hw_control - release control of the h/w to f/w
1560 * @adapter: address of board private structure
1561 *
1562 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1563 * For ASF and Pass Through versions of f/w this means that the
1564 * driver is no longer loaded.
1565 **/
1566static void igb_release_hw_control(struct igb_adapter *adapter)
1567{
1568 struct e1000_hw *hw = &adapter->hw;
1569 u32 ctrl_ext;
1570
1571 /* Let firmware take over control of h/w */
1572 ctrl_ext = rd32(E1000_CTRL_EXT);
1573 wr32(E1000_CTRL_EXT,
1574 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1575}
1576
1577/**
1578 * igb_get_hw_control - get control of the h/w from f/w
1579 * @adapter: address of board private structure
1580 *
1581 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1582 * For ASF and Pass Through versions of f/w this means that
1583 * the driver is loaded.
1584 **/
1585static void igb_get_hw_control(struct igb_adapter *adapter)
1586{
1587 struct e1000_hw *hw = &adapter->hw;
1588 u32 ctrl_ext;
1589
1590 /* Let firmware know the driver has taken over */
1591 ctrl_ext = rd32(E1000_CTRL_EXT);
1592 wr32(E1000_CTRL_EXT,
1593 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1594}
1595
1596static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1597{
1598 struct net_device *netdev = adapter->netdev;
1599 struct e1000_hw *hw = &adapter->hw;
1600
1601 WARN_ON(hw->mac.type != e1000_i210);
1602
1603 if (enable)
1604 adapter->flags |= IGB_FLAG_FQTSS;
1605 else
1606 adapter->flags &= ~IGB_FLAG_FQTSS;
1607
1608 if (netif_running(netdev))
1609 schedule_work(&adapter->reset_task);
1610}
1611
1612static bool is_fqtss_enabled(struct igb_adapter *adapter)
1613{
1614 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1615}
1616
1617static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1618 enum tx_queue_prio prio)
1619{
1620 u32 val;
1621
1622 WARN_ON(hw->mac.type != e1000_i210);
1623 WARN_ON(queue < 0 || queue > 4);
1624
1625 val = rd32(E1000_I210_TXDCTL(queue));
1626
1627 if (prio == TX_QUEUE_PRIO_HIGH)
1628 val |= E1000_TXDCTL_PRIORITY;
1629 else
1630 val &= ~E1000_TXDCTL_PRIORITY;
1631
1632 wr32(E1000_I210_TXDCTL(queue), val);
1633}
1634
1635static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1636{
1637 u32 val;
1638
1639 WARN_ON(hw->mac.type != e1000_i210);
1640 WARN_ON(queue < 0 || queue > 1);
1641
1642 val = rd32(E1000_I210_TQAVCC(queue));
1643
1644 if (mode == QUEUE_MODE_STREAM_RESERVATION)
1645 val |= E1000_TQAVCC_QUEUEMODE;
1646 else
1647 val &= ~E1000_TQAVCC_QUEUEMODE;
1648
1649 wr32(E1000_I210_TQAVCC(queue), val);
1650}
1651
1652static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1653{
1654 int i;
1655
1656 for (i = 0; i < adapter->num_tx_queues; i++) {
1657 if (adapter->tx_ring[i]->cbs_enable)
1658 return true;
1659 }
1660
1661 return false;
1662}
1663
1664static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1665{
1666 int i;
1667
1668 for (i = 0; i < adapter->num_tx_queues; i++) {
1669 if (adapter->tx_ring[i]->launchtime_enable)
1670 return true;
1671 }
1672
1673 return false;
1674}
1675
1676/**
1677 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1678 * @adapter: pointer to adapter struct
1679 * @queue: queue number
1680 *
1681 * Configure CBS and Launchtime for a given hardware queue.
1682 * Parameters are retrieved from the correct Tx ring, so
1683 * igb_save_cbs_params() and igb_save_txtime_params() should be used
1684 * for setting those correctly prior to this function being called.
1685 **/
1686static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1687{
1688 struct net_device *netdev = adapter->netdev;
1689 struct e1000_hw *hw = &adapter->hw;
1690 struct igb_ring *ring;
1691 u32 tqavcc, tqavctrl;
1692 u16 value;
1693
1694 WARN_ON(hw->mac.type != e1000_i210);
1695 WARN_ON(queue < 0 || queue > 1);
1696 ring = adapter->tx_ring[queue];
1697
1698 /* If any of the Qav features is enabled, configure queues as SR and
1699 * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1700 * as SP.
1701 */
1702 if (ring->cbs_enable || ring->launchtime_enable) {
1703 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1704 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1705 } else {
1706 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1707 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1708 }
1709
1710 /* If CBS is enabled, set DataTranARB and config its parameters. */
1711 if (ring->cbs_enable || queue == 0) {
1712 /* i210 does not allow the queue 0 to be in the Strict
1713 * Priority mode while the Qav mode is enabled, so,
1714 * instead of disabling strict priority mode, we give
1715 * queue 0 the maximum of credits possible.
1716 *
1717 * See section 8.12.19 of the i210 datasheet, "Note:
1718 * Queue0 QueueMode must be set to 1b when
1719 * TransmitMode is set to Qav."
1720 */
1721 if (queue == 0 && !ring->cbs_enable) {
1722 /* max "linkspeed" idleslope in kbps */
1723 ring->idleslope = 1000000;
1724 ring->hicredit = ETH_FRAME_LEN;
1725 }
1726
1727 /* Always set data transfer arbitration to credit-based
1728 * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1729 * the queues.
1730 */
1731 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1732 tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1733 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1734
1735 /* According to i210 datasheet section 7.2.7.7, we should set
1736 * the 'idleSlope' field from TQAVCC register following the
1737 * equation:
1738 *
1739 * For 100 Mbps link speed:
1740 *
1741 * value = BW * 0x7735 * 0.2 (E1)
1742 *
1743 * For 1000Mbps link speed:
1744 *
1745 * value = BW * 0x7735 * 2 (E2)
1746 *
1747 * E1 and E2 can be merged into one equation as shown below.
1748 * Note that 'link-speed' is in Mbps.
1749 *
1750 * value = BW * 0x7735 * 2 * link-speed
1751 * -------------- (E3)
1752 * 1000
1753 *
1754 * 'BW' is the percentage bandwidth out of full link speed
1755 * which can be found with the following equation. Note that
1756 * idleSlope here is the parameter from this function which
1757 * is in kbps.
1758 *
1759 * BW = idleSlope
1760 * ----------------- (E4)
1761 * link-speed * 1000
1762 *
1763 * That said, we can come up with a generic equation to
1764 * calculate the value we should set it TQAVCC register by
1765 * replacing 'BW' in E3 by E4. The resulting equation is:
1766 *
1767 * value = idleSlope * 0x7735 * 2 * link-speed
1768 * ----------------- -------------- (E5)
1769 * link-speed * 1000 1000
1770 *
1771 * 'link-speed' is present in both sides of the fraction so
1772 * it is canceled out. The final equation is the following:
1773 *
1774 * value = idleSlope * 61034
1775 * ----------------- (E6)
1776 * 1000000
1777 *
1778 * NOTE: For i210, given the above, we can see that idleslope
1779 * is represented in 16.38431 kbps units by the value at
1780 * the TQAVCC register (1Gbps / 61034), which reduces
1781 * the granularity for idleslope increments.
1782 * For instance, if you want to configure a 2576kbps
1783 * idleslope, the value to be written on the register
1784 * would have to be 157.23. If rounded down, you end
1785 * up with less bandwidth available than originally
1786 * required (~2572 kbps). If rounded up, you end up
1787 * with a higher bandwidth (~2589 kbps). Below the
1788 * approach we take is to always round up the
1789 * calculated value, so the resulting bandwidth might
1790 * be slightly higher for some configurations.
1791 */
1792 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1793
1794 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1795 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1796 tqavcc |= value;
1797 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1798
1799 wr32(E1000_I210_TQAVHC(queue),
1800 0x80000000 + ring->hicredit * 0x7735);
1801 } else {
1802
1803 /* Set idleSlope to zero. */
1804 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1805 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1806 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1807
1808 /* Set hiCredit to zero. */
1809 wr32(E1000_I210_TQAVHC(queue), 0);
1810
1811 /* If CBS is not enabled for any queues anymore, then return to
1812 * the default state of Data Transmission Arbitration on
1813 * TQAVCTRL.
1814 */
1815 if (!is_any_cbs_enabled(adapter)) {
1816 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1817 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1818 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1819 }
1820 }
1821
1822 /* If LaunchTime is enabled, set DataTranTIM. */
1823 if (ring->launchtime_enable) {
1824 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1825 * for any of the SR queues, and configure fetchtime delta.
1826 * XXX NOTE:
1827 * - LaunchTime will be enabled for all SR queues.
1828 * - A fixed offset can be added relative to the launch
1829 * time of all packets if configured at reg LAUNCH_OS0.
1830 * We are keeping it as 0 for now (default value).
1831 */
1832 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1833 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1834 E1000_TQAVCTRL_FETCHTIME_DELTA;
1835 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1836 } else {
1837 /* If Launchtime is not enabled for any SR queues anymore,
1838 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1839 * effectively disabling Launchtime.
1840 */
1841 if (!is_any_txtime_enabled(adapter)) {
1842 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1843 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1844 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1845 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1846 }
1847 }
1848
1849 /* XXX: In i210 controller the sendSlope and loCredit parameters from
1850 * CBS are not configurable by software so we don't do any 'controller
1851 * configuration' in respect to these parameters.
1852 */
1853
1854 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1855 ring->cbs_enable ? "enabled" : "disabled",
1856 ring->launchtime_enable ? "enabled" : "disabled",
1857 queue,
1858 ring->idleslope, ring->sendslope,
1859 ring->hicredit, ring->locredit);
1860}
1861
1862static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1863 bool enable)
1864{
1865 struct igb_ring *ring;
1866
1867 if (queue < 0 || queue > adapter->num_tx_queues)
1868 return -EINVAL;
1869
1870 ring = adapter->tx_ring[queue];
1871 ring->launchtime_enable = enable;
1872
1873 return 0;
1874}
1875
1876static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1877 bool enable, int idleslope, int sendslope,
1878 int hicredit, int locredit)
1879{
1880 struct igb_ring *ring;
1881
1882 if (queue < 0 || queue > adapter->num_tx_queues)
1883 return -EINVAL;
1884
1885 ring = adapter->tx_ring[queue];
1886
1887 ring->cbs_enable = enable;
1888 ring->idleslope = idleslope;
1889 ring->sendslope = sendslope;
1890 ring->hicredit = hicredit;
1891 ring->locredit = locredit;
1892
1893 return 0;
1894}
1895
1896/**
1897 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1898 * @adapter: pointer to adapter struct
1899 *
1900 * Configure TQAVCTRL register switching the controller's Tx mode
1901 * if FQTSS mode is enabled or disabled. Additionally, will issue
1902 * a call to igb_config_tx_modes() per queue so any previously saved
1903 * Tx parameters are applied.
1904 **/
1905static void igb_setup_tx_mode(struct igb_adapter *adapter)
1906{
1907 struct net_device *netdev = adapter->netdev;
1908 struct e1000_hw *hw = &adapter->hw;
1909 u32 val;
1910
1911 /* Only i210 controller supports changing the transmission mode. */
1912 if (hw->mac.type != e1000_i210)
1913 return;
1914
1915 if (is_fqtss_enabled(adapter)) {
1916 int i, max_queue;
1917
1918 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1919 * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1920 * so SP queues wait for SR ones.
1921 */
1922 val = rd32(E1000_I210_TQAVCTRL);
1923 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1924 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1925 wr32(E1000_I210_TQAVCTRL, val);
1926
1927 /* Configure Tx and Rx packet buffers sizes as described in
1928 * i210 datasheet section 7.2.7.7.
1929 */
1930 val = rd32(E1000_TXPBS);
1931 val &= ~I210_TXPBSIZE_MASK;
1932 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |
1933 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;
1934 wr32(E1000_TXPBS, val);
1935
1936 val = rd32(E1000_RXPBS);
1937 val &= ~I210_RXPBSIZE_MASK;
1938 val |= I210_RXPBSIZE_PB_30KB;
1939 wr32(E1000_RXPBS, val);
1940
1941 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1942 * register should not exceed the buffer size programmed in
1943 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1944 * so according to the datasheet we should set MAX_TPKT_SIZE to
1945 * 4kB / 64.
1946 *
1947 * However, when we do so, no frame from queue 2 and 3 are
1948 * transmitted. It seems the MAX_TPKT_SIZE should not be great
1949 * or _equal_ to the buffer size programmed in TXPBS. For this
1950 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1951 */
1952 val = (4096 - 1) / 64;
1953 wr32(E1000_I210_DTXMXPKTSZ, val);
1954
1955 /* Since FQTSS mode is enabled, apply any CBS configuration
1956 * previously set. If no previous CBS configuration has been
1957 * done, then the initial configuration is applied, which means
1958 * CBS is disabled.
1959 */
1960 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1961 adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1962
1963 for (i = 0; i < max_queue; i++) {
1964 igb_config_tx_modes(adapter, i);
1965 }
1966 } else {
1967 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1968 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1969 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1970
1971 val = rd32(E1000_I210_TQAVCTRL);
1972 /* According to Section 8.12.21, the other flags we've set when
1973 * enabling FQTSS are not relevant when disabling FQTSS so we
1974 * don't set they here.
1975 */
1976 val &= ~E1000_TQAVCTRL_XMIT_MODE;
1977 wr32(E1000_I210_TQAVCTRL, val);
1978 }
1979
1980 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1981 "enabled" : "disabled");
1982}
1983
1984/**
1985 * igb_configure - configure the hardware for RX and TX
1986 * @adapter: private board structure
1987 **/
1988static void igb_configure(struct igb_adapter *adapter)
1989{
1990 struct net_device *netdev = adapter->netdev;
1991 int i;
1992
1993 igb_get_hw_control(adapter);
1994 igb_set_rx_mode(netdev);
1995 igb_setup_tx_mode(adapter);
1996
1997 igb_restore_vlan(adapter);
1998
1999 igb_setup_tctl(adapter);
2000 igb_setup_mrqc(adapter);
2001 igb_setup_rctl(adapter);
2002
2003 igb_nfc_filter_restore(adapter);
2004 igb_configure_tx(adapter);
2005 igb_configure_rx(adapter);
2006
2007 igb_rx_fifo_flush_82575(&adapter->hw);
2008
2009 /* call igb_desc_unused which always leaves
2010 * at least 1 descriptor unused to make sure
2011 * next_to_use != next_to_clean
2012 */
2013 for (i = 0; i < adapter->num_rx_queues; i++) {
2014 struct igb_ring *ring = adapter->rx_ring[i];
2015 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
2016 }
2017}
2018
2019/**
2020 * igb_power_up_link - Power up the phy/serdes link
2021 * @adapter: address of board private structure
2022 **/
2023void igb_power_up_link(struct igb_adapter *adapter)
2024{
2025 igb_reset_phy(&adapter->hw);
2026
2027 if (adapter->hw.phy.media_type == e1000_media_type_copper)
2028 igb_power_up_phy_copper(&adapter->hw);
2029 else
2030 igb_power_up_serdes_link_82575(&adapter->hw);
2031
2032 igb_setup_link(&adapter->hw);
2033}
2034
2035/**
2036 * igb_power_down_link - Power down the phy/serdes link
2037 * @adapter: address of board private structure
2038 */
2039static void igb_power_down_link(struct igb_adapter *adapter)
2040{
2041 if (adapter->hw.phy.media_type == e1000_media_type_copper)
2042 igb_power_down_phy_copper_82575(&adapter->hw);
2043 else
2044 igb_shutdown_serdes_link_82575(&adapter->hw);
2045}
2046
2047/**
2048 * igb_check_swap_media - Detect and switch function for Media Auto Sense
2049 * @adapter: address of the board private structure
2050 **/
2051static void igb_check_swap_media(struct igb_adapter *adapter)
2052{
2053 struct e1000_hw *hw = &adapter->hw;
2054 u32 ctrl_ext, connsw;
2055 bool swap_now = false;
2056
2057 ctrl_ext = rd32(E1000_CTRL_EXT);
2058 connsw = rd32(E1000_CONNSW);
2059
2060 /* need to live swap if current media is copper and we have fiber/serdes
2061 * to go to.
2062 */
2063
2064 if ((hw->phy.media_type == e1000_media_type_copper) &&
2065 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2066 swap_now = true;
2067 } else if ((hw->phy.media_type != e1000_media_type_copper) &&
2068 !(connsw & E1000_CONNSW_SERDESD)) {
2069 /* copper signal takes time to appear */
2070 if (adapter->copper_tries < 4) {
2071 adapter->copper_tries++;
2072 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2073 wr32(E1000_CONNSW, connsw);
2074 return;
2075 } else {
2076 adapter->copper_tries = 0;
2077 if ((connsw & E1000_CONNSW_PHYSD) &&
2078 (!(connsw & E1000_CONNSW_PHY_PDN))) {
2079 swap_now = true;
2080 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2081 wr32(E1000_CONNSW, connsw);
2082 }
2083 }
2084 }
2085
2086 if (!swap_now)
2087 return;
2088
2089 switch (hw->phy.media_type) {
2090 case e1000_media_type_copper:
2091 netdev_info(adapter->netdev,
2092 "MAS: changing media to fiber/serdes\n");
2093 ctrl_ext |=
2094 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2095 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2096 adapter->copper_tries = 0;
2097 break;
2098 case e1000_media_type_internal_serdes:
2099 case e1000_media_type_fiber:
2100 netdev_info(adapter->netdev,
2101 "MAS: changing media to copper\n");
2102 ctrl_ext &=
2103 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2104 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2105 break;
2106 default:
2107 /* shouldn't get here during regular operation */
2108 netdev_err(adapter->netdev,
2109 "AMS: Invalid media type found, returning\n");
2110 break;
2111 }
2112 wr32(E1000_CTRL_EXT, ctrl_ext);
2113}
2114
2115/**
2116 * igb_up - Open the interface and prepare it to handle traffic
2117 * @adapter: board private structure
2118 **/
2119int igb_up(struct igb_adapter *adapter)
2120{
2121 struct e1000_hw *hw = &adapter->hw;
2122 int i;
2123
2124 /* hardware has been reset, we need to reload some things */
2125 igb_configure(adapter);
2126
2127 clear_bit(__IGB_DOWN, &adapter->state);
2128
2129 for (i = 0; i < adapter->num_q_vectors; i++)
2130 napi_enable(&(adapter->q_vector[i]->napi));
2131
2132 if (adapter->flags & IGB_FLAG_HAS_MSIX)
2133 igb_configure_msix(adapter);
2134 else
2135 igb_assign_vector(adapter->q_vector[0], 0);
2136
2137 /* Clear any pending interrupts. */
2138 rd32(E1000_TSICR);
2139 rd32(E1000_ICR);
2140 igb_irq_enable(adapter);
2141
2142 /* notify VFs that reset has been completed */
2143 if (adapter->vfs_allocated_count) {
2144 u32 reg_data = rd32(E1000_CTRL_EXT);
2145
2146 reg_data |= E1000_CTRL_EXT_PFRSTD;
2147 wr32(E1000_CTRL_EXT, reg_data);
2148 }
2149
2150 netif_tx_start_all_queues(adapter->netdev);
2151
2152 /* start the watchdog. */
2153 hw->mac.get_link_status = 1;
2154 schedule_work(&adapter->watchdog_task);
2155
2156 if ((adapter->flags & IGB_FLAG_EEE) &&
2157 (!hw->dev_spec._82575.eee_disable))
2158 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2159
2160 return 0;
2161}
2162
2163void igb_down(struct igb_adapter *adapter)
2164{
2165 struct net_device *netdev = adapter->netdev;
2166 struct e1000_hw *hw = &adapter->hw;
2167 u32 tctl, rctl;
2168 int i;
2169
2170 /* signal that we're down so the interrupt handler does not
2171 * reschedule our watchdog timer
2172 */
2173 set_bit(__IGB_DOWN, &adapter->state);
2174
2175 /* disable receives in the hardware */
2176 rctl = rd32(E1000_RCTL);
2177 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2178 /* flush and sleep below */
2179
2180 igb_nfc_filter_exit(adapter);
2181
2182 netif_carrier_off(netdev);
2183 netif_tx_stop_all_queues(netdev);
2184
2185 /* disable transmits in the hardware */
2186 tctl = rd32(E1000_TCTL);
2187 tctl &= ~E1000_TCTL_EN;
2188 wr32(E1000_TCTL, tctl);
2189 /* flush both disables and wait for them to finish */
2190 wrfl();
2191 usleep_range(10000, 11000);
2192
2193 igb_irq_disable(adapter);
2194
2195 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2196
2197 for (i = 0; i < adapter->num_q_vectors; i++) {
2198 if (adapter->q_vector[i]) {
2199 napi_synchronize(&adapter->q_vector[i]->napi);
2200 napi_disable(&adapter->q_vector[i]->napi);
2201 }
2202 }
2203
2204 del_timer_sync(&adapter->watchdog_timer);
2205 del_timer_sync(&adapter->phy_info_timer);
2206
2207 /* record the stats before reset*/
2208 spin_lock(&adapter->stats64_lock);
2209 igb_update_stats(adapter);
2210 spin_unlock(&adapter->stats64_lock);
2211
2212 adapter->link_speed = 0;
2213 adapter->link_duplex = 0;
2214
2215 if (!pci_channel_offline(adapter->pdev))
2216 igb_reset(adapter);
2217
2218 /* clear VLAN promisc flag so VFTA will be updated if necessary */
2219 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2220
2221 igb_clean_all_tx_rings(adapter);
2222 igb_clean_all_rx_rings(adapter);
2223#ifdef CONFIG_IGB_DCA
2224
2225 /* since we reset the hardware DCA settings were cleared */
2226 igb_setup_dca(adapter);
2227#endif
2228}
2229
2230void igb_reinit_locked(struct igb_adapter *adapter)
2231{
2232 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2233 usleep_range(1000, 2000);
2234 igb_down(adapter);
2235 igb_up(adapter);
2236 clear_bit(__IGB_RESETTING, &adapter->state);
2237}
2238
2239/** igb_enable_mas - Media Autosense re-enable after swap
2240 *
2241 * @adapter: adapter struct
2242 **/
2243static void igb_enable_mas(struct igb_adapter *adapter)
2244{
2245 struct e1000_hw *hw = &adapter->hw;
2246 u32 connsw = rd32(E1000_CONNSW);
2247
2248 /* configure for SerDes media detect */
2249 if ((hw->phy.media_type == e1000_media_type_copper) &&
2250 (!(connsw & E1000_CONNSW_SERDESD))) {
2251 connsw |= E1000_CONNSW_ENRGSRC;
2252 connsw |= E1000_CONNSW_AUTOSENSE_EN;
2253 wr32(E1000_CONNSW, connsw);
2254 wrfl();
2255 }
2256}
2257
2258void igb_reset(struct igb_adapter *adapter)
2259{
2260 struct pci_dev *pdev = adapter->pdev;
2261 struct e1000_hw *hw = &adapter->hw;
2262 struct e1000_mac_info *mac = &hw->mac;
2263 struct e1000_fc_info *fc = &hw->fc;
2264 u32 pba, hwm;
2265
2266 /* Repartition Pba for greater than 9k mtu
2267 * To take effect CTRL.RST is required.
2268 */
2269 switch (mac->type) {
2270 case e1000_i350:
2271 case e1000_i354:
2272 case e1000_82580:
2273 pba = rd32(E1000_RXPBS);
2274 pba = igb_rxpbs_adjust_82580(pba);
2275 break;
2276 case e1000_82576:
2277 pba = rd32(E1000_RXPBS);
2278 pba &= E1000_RXPBS_SIZE_MASK_82576;
2279 break;
2280 case e1000_82575:
2281 case e1000_i210:
2282 case e1000_i211:
2283 default:
2284 pba = E1000_PBA_34K;
2285 break;
2286 }
2287
2288 if (mac->type == e1000_82575) {
2289 u32 min_rx_space, min_tx_space, needed_tx_space;
2290
2291 /* write Rx PBA so that hardware can report correct Tx PBA */
2292 wr32(E1000_PBA, pba);
2293
2294 /* To maintain wire speed transmits, the Tx FIFO should be
2295 * large enough to accommodate two full transmit packets,
2296 * rounded up to the next 1KB and expressed in KB. Likewise,
2297 * the Rx FIFO should be large enough to accommodate at least
2298 * one full receive packet and is similarly rounded up and
2299 * expressed in KB.
2300 */
2301 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2302
2303 /* The Tx FIFO also stores 16 bytes of information about the Tx
2304 * but don't include Ethernet FCS because hardware appends it.
2305 * We only need to round down to the nearest 512 byte block
2306 * count since the value we care about is 2 frames, not 1.
2307 */
2308 min_tx_space = adapter->max_frame_size;
2309 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2310 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2311
2312 /* upper 16 bits has Tx packet buffer allocation size in KB */
2313 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2314
2315 /* If current Tx allocation is less than the min Tx FIFO size,
2316 * and the min Tx FIFO size is less than the current Rx FIFO
2317 * allocation, take space away from current Rx allocation.
2318 */
2319 if (needed_tx_space < pba) {
2320 pba -= needed_tx_space;
2321
2322 /* if short on Rx space, Rx wins and must trump Tx
2323 * adjustment
2324 */
2325 if (pba < min_rx_space)
2326 pba = min_rx_space;
2327 }
2328
2329 /* adjust PBA for jumbo frames */
2330 wr32(E1000_PBA, pba);
2331 }
2332
2333 /* flow control settings
2334 * The high water mark must be low enough to fit one full frame
2335 * after transmitting the pause frame. As such we must have enough
2336 * space to allow for us to complete our current transmit and then
2337 * receive the frame that is in progress from the link partner.
2338 * Set it to:
2339 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2340 */
2341 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2342
2343 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
2344 fc->low_water = fc->high_water - 16;
2345 fc->pause_time = 0xFFFF;
2346 fc->send_xon = 1;
2347 fc->current_mode = fc->requested_mode;
2348
2349 /* disable receive for all VFs and wait one second */
2350 if (adapter->vfs_allocated_count) {
2351 int i;
2352
2353 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2354 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2355
2356 /* ping all the active vfs to let them know we are going down */
2357 igb_ping_all_vfs(adapter);
2358
2359 /* disable transmits and receives */
2360 wr32(E1000_VFRE, 0);
2361 wr32(E1000_VFTE, 0);
2362 }
2363
2364 /* Allow time for pending master requests to run */
2365 hw->mac.ops.reset_hw(hw);
2366 wr32(E1000_WUC, 0);
2367
2368 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2369 /* need to resetup here after media swap */
2370 adapter->ei.get_invariants(hw);
2371 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2372 }
2373 if ((mac->type == e1000_82575 || mac->type == e1000_i350) &&
2374 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2375 igb_enable_mas(adapter);
2376 }
2377 if (hw->mac.ops.init_hw(hw))
2378 dev_err(&pdev->dev, "Hardware Error\n");
2379
2380 /* RAR registers were cleared during init_hw, clear mac table */
2381 igb_flush_mac_table(adapter);
2382 __dev_uc_unsync(adapter->netdev, NULL);
2383
2384 /* Recover default RAR entry */
2385 igb_set_default_mac_filter(adapter);
2386
2387 /* Flow control settings reset on hardware reset, so guarantee flow
2388 * control is off when forcing speed.
2389 */
2390 if (!hw->mac.autoneg)
2391 igb_force_mac_fc(hw);
2392
2393 igb_init_dmac(adapter, pba);
2394#ifdef CONFIG_IGB_HWMON
2395 /* Re-initialize the thermal sensor on i350 devices. */
2396 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2397 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2398 /* If present, re-initialize the external thermal sensor
2399 * interface.
2400 */
2401 if (adapter->ets)
2402 mac->ops.init_thermal_sensor_thresh(hw);
2403 }
2404 }
2405#endif
2406 /* Re-establish EEE setting */
2407 if (hw->phy.media_type == e1000_media_type_copper) {
2408 switch (mac->type) {
2409 case e1000_i350:
2410 case e1000_i210:
2411 case e1000_i211:
2412 igb_set_eee_i350(hw, true, true);
2413 break;
2414 case e1000_i354:
2415 igb_set_eee_i354(hw, true, true);
2416 break;
2417 default:
2418 break;
2419 }
2420 }
2421 if (!netif_running(adapter->netdev))
2422 igb_power_down_link(adapter);
2423
2424 igb_update_mng_vlan(adapter);
2425
2426 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2427 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2428
2429 /* Re-enable PTP, where applicable. */
2430 if (adapter->ptp_flags & IGB_PTP_ENABLED)
2431 igb_ptp_reset(adapter);
2432
2433 igb_get_phy_info(hw);
2434}
2435
2436static netdev_features_t igb_fix_features(struct net_device *netdev,
2437 netdev_features_t features)
2438{
2439 /* Since there is no support for separate Rx/Tx vlan accel
2440 * enable/disable make sure Tx flag is always in same state as Rx.
2441 */
2442 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2443 features |= NETIF_F_HW_VLAN_CTAG_TX;
2444 else
2445 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2446
2447 return features;
2448}
2449
2450static int igb_set_features(struct net_device *netdev,
2451 netdev_features_t features)
2452{
2453 netdev_features_t changed = netdev->features ^ features;
2454 struct igb_adapter *adapter = netdev_priv(netdev);
2455
2456 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2457 igb_vlan_mode(netdev, features);
2458
2459 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2460 return 0;
2461
2462 if (!(features & NETIF_F_NTUPLE)) {
2463 struct hlist_node *node2;
2464 struct igb_nfc_filter *rule;
2465
2466 spin_lock(&adapter->nfc_lock);
2467 hlist_for_each_entry_safe(rule, node2,
2468 &adapter->nfc_filter_list, nfc_node) {
2469 igb_erase_filter(adapter, rule);
2470 hlist_del(&rule->nfc_node);
2471 kfree(rule);
2472 }
2473 spin_unlock(&adapter->nfc_lock);
2474 adapter->nfc_filter_count = 0;
2475 }
2476
2477 netdev->features = features;
2478
2479 if (netif_running(netdev))
2480 igb_reinit_locked(adapter);
2481 else
2482 igb_reset(adapter);
2483
2484 return 1;
2485}
2486
2487static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2488 struct net_device *dev,
2489 const unsigned char *addr, u16 vid,
2490 u16 flags,
2491 struct netlink_ext_ack *extack)
2492{
2493 /* guarantee we can provide a unique filter for the unicast address */
2494 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2495 struct igb_adapter *adapter = netdev_priv(dev);
2496 int vfn = adapter->vfs_allocated_count;
2497
2498 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2499 return -ENOMEM;
2500 }
2501
2502 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2503}
2504
2505#define IGB_MAX_MAC_HDR_LEN 127
2506#define IGB_MAX_NETWORK_HDR_LEN 511
2507
2508static netdev_features_t
2509igb_features_check(struct sk_buff *skb, struct net_device *dev,
2510 netdev_features_t features)
2511{
2512 unsigned int network_hdr_len, mac_hdr_len;
2513
2514 /* Make certain the headers can be described by a context descriptor */
2515 mac_hdr_len = skb_network_header(skb) - skb->data;
2516 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2517 return features & ~(NETIF_F_HW_CSUM |
2518 NETIF_F_SCTP_CRC |
2519 NETIF_F_GSO_UDP_L4 |
2520 NETIF_F_HW_VLAN_CTAG_TX |
2521 NETIF_F_TSO |
2522 NETIF_F_TSO6);
2523
2524 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2525 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN))
2526 return features & ~(NETIF_F_HW_CSUM |
2527 NETIF_F_SCTP_CRC |
2528 NETIF_F_GSO_UDP_L4 |
2529 NETIF_F_TSO |
2530 NETIF_F_TSO6);
2531
2532 /* We can only support IPV4 TSO in tunnels if we can mangle the
2533 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2534 */
2535 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2536 features &= ~NETIF_F_TSO;
2537
2538 return features;
2539}
2540
2541static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2542{
2543 if (!is_fqtss_enabled(adapter)) {
2544 enable_fqtss(adapter, true);
2545 return;
2546 }
2547
2548 igb_config_tx_modes(adapter, queue);
2549
2550 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2551 enable_fqtss(adapter, false);
2552}
2553
2554static int igb_offload_cbs(struct igb_adapter *adapter,
2555 struct tc_cbs_qopt_offload *qopt)
2556{
2557 struct e1000_hw *hw = &adapter->hw;
2558 int err;
2559
2560 /* CBS offloading is only supported by i210 controller. */
2561 if (hw->mac.type != e1000_i210)
2562 return -EOPNOTSUPP;
2563
2564 /* CBS offloading is only supported by queue 0 and queue 1. */
2565 if (qopt->queue < 0 || qopt->queue > 1)
2566 return -EINVAL;
2567
2568 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2569 qopt->idleslope, qopt->sendslope,
2570 qopt->hicredit, qopt->locredit);
2571 if (err)
2572 return err;
2573
2574 igb_offload_apply(adapter, qopt->queue);
2575
2576 return 0;
2577}
2578
2579#define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2580#define VLAN_PRIO_FULL_MASK (0x07)
2581
2582static int igb_parse_cls_flower(struct igb_adapter *adapter,
2583 struct flow_cls_offload *f,
2584 int traffic_class,
2585 struct igb_nfc_filter *input)
2586{
2587 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2588 struct flow_dissector *dissector = rule->match.dissector;
2589 struct netlink_ext_ack *extack = f->common.extack;
2590
2591 if (dissector->used_keys &
2592 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) |
2593 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2594 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2595 BIT(FLOW_DISSECTOR_KEY_VLAN))) {
2596 NL_SET_ERR_MSG_MOD(extack,
2597 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2598 return -EOPNOTSUPP;
2599 }
2600
2601 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2602 struct flow_match_eth_addrs match;
2603
2604 flow_rule_match_eth_addrs(rule, &match);
2605 if (!is_zero_ether_addr(match.mask->dst)) {
2606 if (!is_broadcast_ether_addr(match.mask->dst)) {
2607 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2608 return -EINVAL;
2609 }
2610
2611 input->filter.match_flags |=
2612 IGB_FILTER_FLAG_DST_MAC_ADDR;
2613 ether_addr_copy(input->filter.dst_addr, match.key->dst);
2614 }
2615
2616 if (!is_zero_ether_addr(match.mask->src)) {
2617 if (!is_broadcast_ether_addr(match.mask->src)) {
2618 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2619 return -EINVAL;
2620 }
2621
2622 input->filter.match_flags |=
2623 IGB_FILTER_FLAG_SRC_MAC_ADDR;
2624 ether_addr_copy(input->filter.src_addr, match.key->src);
2625 }
2626 }
2627
2628 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2629 struct flow_match_basic match;
2630
2631 flow_rule_match_basic(rule, &match);
2632 if (match.mask->n_proto) {
2633 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2634 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2635 return -EINVAL;
2636 }
2637
2638 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2639 input->filter.etype = match.key->n_proto;
2640 }
2641 }
2642
2643 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2644 struct flow_match_vlan match;
2645
2646 flow_rule_match_vlan(rule, &match);
2647 if (match.mask->vlan_priority) {
2648 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2649 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2650 return -EINVAL;
2651 }
2652
2653 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2654 input->filter.vlan_tci =
2655 (__force __be16)match.key->vlan_priority;
2656 }
2657 }
2658
2659 input->action = traffic_class;
2660 input->cookie = f->cookie;
2661
2662 return 0;
2663}
2664
2665static int igb_configure_clsflower(struct igb_adapter *adapter,
2666 struct flow_cls_offload *cls_flower)
2667{
2668 struct netlink_ext_ack *extack = cls_flower->common.extack;
2669 struct igb_nfc_filter *filter, *f;
2670 int err, tc;
2671
2672 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2673 if (tc < 0) {
2674 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2675 return -EINVAL;
2676 }
2677
2678 filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2679 if (!filter)
2680 return -ENOMEM;
2681
2682 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2683 if (err < 0)
2684 goto err_parse;
2685
2686 spin_lock(&adapter->nfc_lock);
2687
2688 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2689 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2690 err = -EEXIST;
2691 NL_SET_ERR_MSG_MOD(extack,
2692 "This filter is already set in ethtool");
2693 goto err_locked;
2694 }
2695 }
2696
2697 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2698 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2699 err = -EEXIST;
2700 NL_SET_ERR_MSG_MOD(extack,
2701 "This filter is already set in cls_flower");
2702 goto err_locked;
2703 }
2704 }
2705
2706 err = igb_add_filter(adapter, filter);
2707 if (err < 0) {
2708 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2709 goto err_locked;
2710 }
2711
2712 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2713
2714 spin_unlock(&adapter->nfc_lock);
2715
2716 return 0;
2717
2718err_locked:
2719 spin_unlock(&adapter->nfc_lock);
2720
2721err_parse:
2722 kfree(filter);
2723
2724 return err;
2725}
2726
2727static int igb_delete_clsflower(struct igb_adapter *adapter,
2728 struct flow_cls_offload *cls_flower)
2729{
2730 struct igb_nfc_filter *filter;
2731 int err;
2732
2733 spin_lock(&adapter->nfc_lock);
2734
2735 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2736 if (filter->cookie == cls_flower->cookie)
2737 break;
2738
2739 if (!filter) {
2740 err = -ENOENT;
2741 goto out;
2742 }
2743
2744 err = igb_erase_filter(adapter, filter);
2745 if (err < 0)
2746 goto out;
2747
2748 hlist_del(&filter->nfc_node);
2749 kfree(filter);
2750
2751out:
2752 spin_unlock(&adapter->nfc_lock);
2753
2754 return err;
2755}
2756
2757static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2758 struct flow_cls_offload *cls_flower)
2759{
2760 switch (cls_flower->command) {
2761 case FLOW_CLS_REPLACE:
2762 return igb_configure_clsflower(adapter, cls_flower);
2763 case FLOW_CLS_DESTROY:
2764 return igb_delete_clsflower(adapter, cls_flower);
2765 case FLOW_CLS_STATS:
2766 return -EOPNOTSUPP;
2767 default:
2768 return -EOPNOTSUPP;
2769 }
2770}
2771
2772static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2773 void *cb_priv)
2774{
2775 struct igb_adapter *adapter = cb_priv;
2776
2777 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2778 return -EOPNOTSUPP;
2779
2780 switch (type) {
2781 case TC_SETUP_CLSFLOWER:
2782 return igb_setup_tc_cls_flower(adapter, type_data);
2783
2784 default:
2785 return -EOPNOTSUPP;
2786 }
2787}
2788
2789static int igb_offload_txtime(struct igb_adapter *adapter,
2790 struct tc_etf_qopt_offload *qopt)
2791{
2792 struct e1000_hw *hw = &adapter->hw;
2793 int err;
2794
2795 /* Launchtime offloading is only supported by i210 controller. */
2796 if (hw->mac.type != e1000_i210)
2797 return -EOPNOTSUPP;
2798
2799 /* Launchtime offloading is only supported by queues 0 and 1. */
2800 if (qopt->queue < 0 || qopt->queue > 1)
2801 return -EINVAL;
2802
2803 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2804 if (err)
2805 return err;
2806
2807 igb_offload_apply(adapter, qopt->queue);
2808
2809 return 0;
2810}
2811
2812static LIST_HEAD(igb_block_cb_list);
2813
2814static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2815 void *type_data)
2816{
2817 struct igb_adapter *adapter = netdev_priv(dev);
2818
2819 switch (type) {
2820 case TC_SETUP_QDISC_CBS:
2821 return igb_offload_cbs(adapter, type_data);
2822 case TC_SETUP_BLOCK:
2823 return flow_block_cb_setup_simple(type_data,
2824 &igb_block_cb_list,
2825 igb_setup_tc_block_cb,
2826 adapter, adapter, true);
2827
2828 case TC_SETUP_QDISC_ETF:
2829 return igb_offload_txtime(adapter, type_data);
2830
2831 default:
2832 return -EOPNOTSUPP;
2833 }
2834}
2835
2836static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf)
2837{
2838 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD;
2839 struct igb_adapter *adapter = netdev_priv(dev);
2840 struct bpf_prog *prog = bpf->prog, *old_prog;
2841 bool running = netif_running(dev);
2842 bool need_reset;
2843
2844 /* verify igb ring attributes are sufficient for XDP */
2845 for (i = 0; i < adapter->num_rx_queues; i++) {
2846 struct igb_ring *ring = adapter->rx_ring[i];
2847
2848 if (frame_size > igb_rx_bufsz(ring)) {
2849 NL_SET_ERR_MSG_MOD(bpf->extack,
2850 "The RX buffer size is too small for the frame size");
2851 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n",
2852 igb_rx_bufsz(ring), frame_size);
2853 return -EINVAL;
2854 }
2855 }
2856
2857 old_prog = xchg(&adapter->xdp_prog, prog);
2858 need_reset = (!!prog != !!old_prog);
2859
2860 /* device is up and bpf is added/removed, must setup the RX queues */
2861 if (need_reset && running) {
2862 igb_close(dev);
2863 } else {
2864 for (i = 0; i < adapter->num_rx_queues; i++)
2865 (void)xchg(&adapter->rx_ring[i]->xdp_prog,
2866 adapter->xdp_prog);
2867 }
2868
2869 if (old_prog)
2870 bpf_prog_put(old_prog);
2871
2872 /* bpf is just replaced, RXQ and MTU are already setup */
2873 if (!need_reset)
2874 return 0;
2875
2876 if (running)
2877 igb_open(dev);
2878
2879 return 0;
2880}
2881
2882static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2883{
2884 switch (xdp->command) {
2885 case XDP_SETUP_PROG:
2886 return igb_xdp_setup(dev, xdp);
2887 default:
2888 return -EINVAL;
2889 }
2890}
2891
2892static void igb_xdp_ring_update_tail(struct igb_ring *ring)
2893{
2894 /* Force memory writes to complete before letting h/w know there
2895 * are new descriptors to fetch.
2896 */
2897 wmb();
2898 writel(ring->next_to_use, ring->tail);
2899}
2900
2901static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter)
2902{
2903 unsigned int r_idx = smp_processor_id();
2904
2905 if (r_idx >= adapter->num_tx_queues)
2906 r_idx = r_idx % adapter->num_tx_queues;
2907
2908 return adapter->tx_ring[r_idx];
2909}
2910
2911static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp)
2912{
2913 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2914 int cpu = smp_processor_id();
2915 struct igb_ring *tx_ring;
2916 struct netdev_queue *nq;
2917 u32 ret;
2918
2919 if (unlikely(!xdpf))
2920 return IGB_XDP_CONSUMED;
2921
2922 /* During program transitions its possible adapter->xdp_prog is assigned
2923 * but ring has not been configured yet. In this case simply abort xmit.
2924 */
2925 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2926 if (unlikely(!tx_ring))
2927 return IGB_XDP_CONSUMED;
2928
2929 nq = txring_txq(tx_ring);
2930 __netif_tx_lock(nq, cpu);
2931 /* Avoid transmit queue timeout since we share it with the slow path */
2932 nq->trans_start = jiffies;
2933 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2934 __netif_tx_unlock(nq);
2935
2936 return ret;
2937}
2938
2939static int igb_xdp_xmit(struct net_device *dev, int n,
2940 struct xdp_frame **frames, u32 flags)
2941{
2942 struct igb_adapter *adapter = netdev_priv(dev);
2943 int cpu = smp_processor_id();
2944 struct igb_ring *tx_ring;
2945 struct netdev_queue *nq;
2946 int nxmit = 0;
2947 int i;
2948
2949 if (unlikely(test_bit(__IGB_DOWN, &adapter->state)))
2950 return -ENETDOWN;
2951
2952 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2953 return -EINVAL;
2954
2955 /* During program transitions its possible adapter->xdp_prog is assigned
2956 * but ring has not been configured yet. In this case simply abort xmit.
2957 */
2958 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2959 if (unlikely(!tx_ring))
2960 return -ENXIO;
2961
2962 nq = txring_txq(tx_ring);
2963 __netif_tx_lock(nq, cpu);
2964
2965 /* Avoid transmit queue timeout since we share it with the slow path */
2966 nq->trans_start = jiffies;
2967
2968 for (i = 0; i < n; i++) {
2969 struct xdp_frame *xdpf = frames[i];
2970 int err;
2971
2972 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2973 if (err != IGB_XDP_TX)
2974 break;
2975 nxmit++;
2976 }
2977
2978 __netif_tx_unlock(nq);
2979
2980 if (unlikely(flags & XDP_XMIT_FLUSH))
2981 igb_xdp_ring_update_tail(tx_ring);
2982
2983 return nxmit;
2984}
2985
2986static const struct net_device_ops igb_netdev_ops = {
2987 .ndo_open = igb_open,
2988 .ndo_stop = igb_close,
2989 .ndo_start_xmit = igb_xmit_frame,
2990 .ndo_get_stats64 = igb_get_stats64,
2991 .ndo_set_rx_mode = igb_set_rx_mode,
2992 .ndo_set_mac_address = igb_set_mac,
2993 .ndo_change_mtu = igb_change_mtu,
2994 .ndo_do_ioctl = igb_ioctl,
2995 .ndo_tx_timeout = igb_tx_timeout,
2996 .ndo_validate_addr = eth_validate_addr,
2997 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2998 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2999 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
3000 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
3001 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
3002 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
3003 .ndo_set_vf_trust = igb_ndo_set_vf_trust,
3004 .ndo_get_vf_config = igb_ndo_get_vf_config,
3005 .ndo_fix_features = igb_fix_features,
3006 .ndo_set_features = igb_set_features,
3007 .ndo_fdb_add = igb_ndo_fdb_add,
3008 .ndo_features_check = igb_features_check,
3009 .ndo_setup_tc = igb_setup_tc,
3010 .ndo_bpf = igb_xdp,
3011 .ndo_xdp_xmit = igb_xdp_xmit,
3012};
3013
3014/**
3015 * igb_set_fw_version - Configure version string for ethtool
3016 * @adapter: adapter struct
3017 **/
3018void igb_set_fw_version(struct igb_adapter *adapter)
3019{
3020 struct e1000_hw *hw = &adapter->hw;
3021 struct e1000_fw_version fw;
3022
3023 igb_get_fw_version(hw, &fw);
3024
3025 switch (hw->mac.type) {
3026 case e1000_i210:
3027 case e1000_i211:
3028 if (!(igb_get_flash_presence_i210(hw))) {
3029 snprintf(adapter->fw_version,
3030 sizeof(adapter->fw_version),
3031 "%2d.%2d-%d",
3032 fw.invm_major, fw.invm_minor,
3033 fw.invm_img_type);
3034 break;
3035 }
3036 fallthrough;
3037 default:
3038 /* if option is rom valid, display its version too */
3039 if (fw.or_valid) {
3040 snprintf(adapter->fw_version,
3041 sizeof(adapter->fw_version),
3042 "%d.%d, 0x%08x, %d.%d.%d",
3043 fw.eep_major, fw.eep_minor, fw.etrack_id,
3044 fw.or_major, fw.or_build, fw.or_patch);
3045 /* no option rom */
3046 } else if (fw.etrack_id != 0X0000) {
3047 snprintf(adapter->fw_version,
3048 sizeof(adapter->fw_version),
3049 "%d.%d, 0x%08x",
3050 fw.eep_major, fw.eep_minor, fw.etrack_id);
3051 } else {
3052 snprintf(adapter->fw_version,
3053 sizeof(adapter->fw_version),
3054 "%d.%d.%d",
3055 fw.eep_major, fw.eep_minor, fw.eep_build);
3056 }
3057 break;
3058 }
3059}
3060
3061/**
3062 * igb_init_mas - init Media Autosense feature if enabled in the NVM
3063 *
3064 * @adapter: adapter struct
3065 **/
3066static void igb_init_mas(struct igb_adapter *adapter)
3067{
3068 struct e1000_hw *hw = &adapter->hw;
3069 u16 eeprom_data;
3070
3071 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
3072 switch (hw->bus.func) {
3073 case E1000_FUNC_0:
3074 if (eeprom_data & IGB_MAS_ENABLE_0) {
3075 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3076 netdev_info(adapter->netdev,
3077 "MAS: Enabling Media Autosense for port %d\n",
3078 hw->bus.func);
3079 }
3080 break;
3081 case E1000_FUNC_1:
3082 if (eeprom_data & IGB_MAS_ENABLE_1) {
3083 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3084 netdev_info(adapter->netdev,
3085 "MAS: Enabling Media Autosense for port %d\n",
3086 hw->bus.func);
3087 }
3088 break;
3089 case E1000_FUNC_2:
3090 if (eeprom_data & IGB_MAS_ENABLE_2) {
3091 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3092 netdev_info(adapter->netdev,
3093 "MAS: Enabling Media Autosense for port %d\n",
3094 hw->bus.func);
3095 }
3096 break;
3097 case E1000_FUNC_3:
3098 if (eeprom_data & IGB_MAS_ENABLE_3) {
3099 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3100 netdev_info(adapter->netdev,
3101 "MAS: Enabling Media Autosense for port %d\n",
3102 hw->bus.func);
3103 }
3104 break;
3105 default:
3106 /* Shouldn't get here */
3107 netdev_err(adapter->netdev,
3108 "MAS: Invalid port configuration, returning\n");
3109 break;
3110 }
3111}
3112
3113/**
3114 * igb_init_i2c - Init I2C interface
3115 * @adapter: pointer to adapter structure
3116 **/
3117static s32 igb_init_i2c(struct igb_adapter *adapter)
3118{
3119 s32 status = 0;
3120
3121 /* I2C interface supported on i350 devices */
3122 if (adapter->hw.mac.type != e1000_i350)
3123 return 0;
3124
3125 /* Initialize the i2c bus which is controlled by the registers.
3126 * This bus will use the i2c_algo_bit structure that implements
3127 * the protocol through toggling of the 4 bits in the register.
3128 */
3129 adapter->i2c_adap.owner = THIS_MODULE;
3130 adapter->i2c_algo = igb_i2c_algo;
3131 adapter->i2c_algo.data = adapter;
3132 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
3133 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
3134 strlcpy(adapter->i2c_adap.name, "igb BB",
3135 sizeof(adapter->i2c_adap.name));
3136 status = i2c_bit_add_bus(&adapter->i2c_adap);
3137 return status;
3138}
3139
3140/**
3141 * igb_probe - Device Initialization Routine
3142 * @pdev: PCI device information struct
3143 * @ent: entry in igb_pci_tbl
3144 *
3145 * Returns 0 on success, negative on failure
3146 *
3147 * igb_probe initializes an adapter identified by a pci_dev structure.
3148 * The OS initialization, configuring of the adapter private structure,
3149 * and a hardware reset occur.
3150 **/
3151static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3152{
3153 struct net_device *netdev;
3154 struct igb_adapter *adapter;
3155 struct e1000_hw *hw;
3156 u16 eeprom_data = 0;
3157 s32 ret_val;
3158 static int global_quad_port_a; /* global quad port a indication */
3159 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3160 int err, pci_using_dac;
3161 u8 part_str[E1000_PBANUM_LENGTH];
3162
3163 /* Catch broken hardware that put the wrong VF device ID in
3164 * the PCIe SR-IOV capability.
3165 */
3166 if (pdev->is_virtfn) {
3167 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n",
3168 pci_name(pdev), pdev->vendor, pdev->device);
3169 return -EINVAL;
3170 }
3171
3172 err = pci_enable_device_mem(pdev);
3173 if (err)
3174 return err;
3175
3176 pci_using_dac = 0;
3177 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3178 if (!err) {
3179 pci_using_dac = 1;
3180 } else {
3181 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3182 if (err) {
3183 dev_err(&pdev->dev,
3184 "No usable DMA configuration, aborting\n");
3185 goto err_dma;
3186 }
3187 }
3188
3189 err = pci_request_mem_regions(pdev, igb_driver_name);
3190 if (err)
3191 goto err_pci_reg;
3192
3193 pci_enable_pcie_error_reporting(pdev);
3194
3195 pci_set_master(pdev);
3196 pci_save_state(pdev);
3197
3198 err = -ENOMEM;
3199 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3200 IGB_MAX_TX_QUEUES);
3201 if (!netdev)
3202 goto err_alloc_etherdev;
3203
3204 SET_NETDEV_DEV(netdev, &pdev->dev);
3205
3206 pci_set_drvdata(pdev, netdev);
3207 adapter = netdev_priv(netdev);
3208 adapter->netdev = netdev;
3209 adapter->pdev = pdev;
3210 hw = &adapter->hw;
3211 hw->back = adapter;
3212 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3213
3214 err = -EIO;
3215 adapter->io_addr = pci_iomap(pdev, 0, 0);
3216 if (!adapter->io_addr)
3217 goto err_ioremap;
3218 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3219 hw->hw_addr = adapter->io_addr;
3220
3221 netdev->netdev_ops = &igb_netdev_ops;
3222 igb_set_ethtool_ops(netdev);
3223 netdev->watchdog_timeo = 5 * HZ;
3224
3225 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
3226
3227 netdev->mem_start = pci_resource_start(pdev, 0);
3228 netdev->mem_end = pci_resource_end(pdev, 0);
3229
3230 /* PCI config space info */
3231 hw->vendor_id = pdev->vendor;
3232 hw->device_id = pdev->device;
3233 hw->revision_id = pdev->revision;
3234 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3235 hw->subsystem_device_id = pdev->subsystem_device;
3236
3237 /* Copy the default MAC, PHY and NVM function pointers */
3238 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3239 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3240 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3241 /* Initialize skew-specific constants */
3242 err = ei->get_invariants(hw);
3243 if (err)
3244 goto err_sw_init;
3245
3246 /* setup the private structure */
3247 err = igb_sw_init(adapter);
3248 if (err)
3249 goto err_sw_init;
3250
3251 igb_get_bus_info_pcie(hw);
3252
3253 hw->phy.autoneg_wait_to_complete = false;
3254
3255 /* Copper options */
3256 if (hw->phy.media_type == e1000_media_type_copper) {
3257 hw->phy.mdix = AUTO_ALL_MODES;
3258 hw->phy.disable_polarity_correction = false;
3259 hw->phy.ms_type = e1000_ms_hw_default;
3260 }
3261
3262 if (igb_check_reset_block(hw))
3263 dev_info(&pdev->dev,
3264 "PHY reset is blocked due to SOL/IDER session.\n");
3265
3266 /* features is initialized to 0 in allocation, it might have bits
3267 * set by igb_sw_init so we should use an or instead of an
3268 * assignment.
3269 */
3270 netdev->features |= NETIF_F_SG |
3271 NETIF_F_TSO |
3272 NETIF_F_TSO6 |
3273 NETIF_F_RXHASH |
3274 NETIF_F_RXCSUM |
3275 NETIF_F_HW_CSUM;
3276
3277 if (hw->mac.type >= e1000_82576)
3278 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
3279
3280 if (hw->mac.type >= e1000_i350)
3281 netdev->features |= NETIF_F_HW_TC;
3282
3283#define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3284 NETIF_F_GSO_GRE_CSUM | \
3285 NETIF_F_GSO_IPXIP4 | \
3286 NETIF_F_GSO_IPXIP6 | \
3287 NETIF_F_GSO_UDP_TUNNEL | \
3288 NETIF_F_GSO_UDP_TUNNEL_CSUM)
3289
3290 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3291 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3292
3293 /* copy netdev features into list of user selectable features */
3294 netdev->hw_features |= netdev->features |
3295 NETIF_F_HW_VLAN_CTAG_RX |
3296 NETIF_F_HW_VLAN_CTAG_TX |
3297 NETIF_F_RXALL;
3298
3299 if (hw->mac.type >= e1000_i350)
3300 netdev->hw_features |= NETIF_F_NTUPLE;
3301
3302 if (pci_using_dac)
3303 netdev->features |= NETIF_F_HIGHDMA;
3304
3305 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3306 netdev->mpls_features |= NETIF_F_HW_CSUM;
3307 netdev->hw_enc_features |= netdev->vlan_features;
3308
3309 /* set this bit last since it cannot be part of vlan_features */
3310 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3311 NETIF_F_HW_VLAN_CTAG_RX |
3312 NETIF_F_HW_VLAN_CTAG_TX;
3313
3314 netdev->priv_flags |= IFF_SUPP_NOFCS;
3315
3316 netdev->priv_flags |= IFF_UNICAST_FLT;
3317
3318 /* MTU range: 68 - 9216 */
3319 netdev->min_mtu = ETH_MIN_MTU;
3320 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3321
3322 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
3323
3324 /* before reading the NVM, reset the controller to put the device in a
3325 * known good starting state
3326 */
3327 hw->mac.ops.reset_hw(hw);
3328
3329 /* make sure the NVM is good , i211/i210 parts can have special NVM
3330 * that doesn't contain a checksum
3331 */
3332 switch (hw->mac.type) {
3333 case e1000_i210:
3334 case e1000_i211:
3335 if (igb_get_flash_presence_i210(hw)) {
3336 if (hw->nvm.ops.validate(hw) < 0) {
3337 dev_err(&pdev->dev,
3338 "The NVM Checksum Is Not Valid\n");
3339 err = -EIO;
3340 goto err_eeprom;
3341 }
3342 }
3343 break;
3344 default:
3345 if (hw->nvm.ops.validate(hw) < 0) {
3346 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
3347 err = -EIO;
3348 goto err_eeprom;
3349 }
3350 break;
3351 }
3352
3353 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3354 /* copy the MAC address out of the NVM */
3355 if (hw->mac.ops.read_mac_addr(hw))
3356 dev_err(&pdev->dev, "NVM Read Error\n");
3357 }
3358
3359 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
3360
3361 if (!is_valid_ether_addr(netdev->dev_addr)) {
3362 dev_err(&pdev->dev, "Invalid MAC Address\n");
3363 err = -EIO;
3364 goto err_eeprom;
3365 }
3366
3367 igb_set_default_mac_filter(adapter);
3368
3369 /* get firmware version for ethtool -i */
3370 igb_set_fw_version(adapter);
3371
3372 /* configure RXPBSIZE and TXPBSIZE */
3373 if (hw->mac.type == e1000_i210) {
3374 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
3375 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
3376 }
3377
3378 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
3379 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
3380
3381 INIT_WORK(&adapter->reset_task, igb_reset_task);
3382 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
3383
3384 /* Initialize link properties that are user-changeable */
3385 adapter->fc_autoneg = true;
3386 hw->mac.autoneg = true;
3387 hw->phy.autoneg_advertised = 0x2f;
3388
3389 hw->fc.requested_mode = e1000_fc_default;
3390 hw->fc.current_mode = e1000_fc_default;
3391
3392 igb_validate_mdi_setting(hw);
3393
3394 /* By default, support wake on port A */
3395 if (hw->bus.func == 0)
3396 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3397
3398 /* Check the NVM for wake support on non-port A ports */
3399 if (hw->mac.type >= e1000_82580)
3400 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
3401 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
3402 &eeprom_data);
3403 else if (hw->bus.func == 1)
3404 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3405
3406 if (eeprom_data & IGB_EEPROM_APME)
3407 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3408
3409 /* now that we have the eeprom settings, apply the special cases where
3410 * the eeprom may be wrong or the board simply won't support wake on
3411 * lan on a particular port
3412 */
3413 switch (pdev->device) {
3414 case E1000_DEV_ID_82575GB_QUAD_COPPER:
3415 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3416 break;
3417 case E1000_DEV_ID_82575EB_FIBER_SERDES:
3418 case E1000_DEV_ID_82576_FIBER:
3419 case E1000_DEV_ID_82576_SERDES:
3420 /* Wake events only supported on port A for dual fiber
3421 * regardless of eeprom setting
3422 */
3423 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
3424 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3425 break;
3426 case E1000_DEV_ID_82576_QUAD_COPPER:
3427 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
3428 /* if quad port adapter, disable WoL on all but port A */
3429 if (global_quad_port_a != 0)
3430 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3431 else
3432 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
3433 /* Reset for multiple quad port adapters */
3434 if (++global_quad_port_a == 4)
3435 global_quad_port_a = 0;
3436 break;
3437 default:
3438 /* If the device can't wake, don't set software support */
3439 if (!device_can_wakeup(&adapter->pdev->dev))
3440 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3441 }
3442
3443 /* initialize the wol settings based on the eeprom settings */
3444 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
3445 adapter->wol |= E1000_WUFC_MAG;
3446
3447 /* Some vendors want WoL disabled by default, but still supported */
3448 if ((hw->mac.type == e1000_i350) &&
3449 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
3450 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3451 adapter->wol = 0;
3452 }
3453
3454 /* Some vendors want the ability to Use the EEPROM setting as
3455 * enable/disable only, and not for capability
3456 */
3457 if (((hw->mac.type == e1000_i350) ||
3458 (hw->mac.type == e1000_i354)) &&
3459 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3460 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3461 adapter->wol = 0;
3462 }
3463 if (hw->mac.type == e1000_i350) {
3464 if (((pdev->subsystem_device == 0x5001) ||
3465 (pdev->subsystem_device == 0x5002)) &&
3466 (hw->bus.func == 0)) {
3467 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3468 adapter->wol = 0;
3469 }
3470 if (pdev->subsystem_device == 0x1F52)
3471 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3472 }
3473
3474 device_set_wakeup_enable(&adapter->pdev->dev,
3475 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3476
3477 /* reset the hardware with the new settings */
3478 igb_reset(adapter);
3479
3480 /* Init the I2C interface */
3481 err = igb_init_i2c(adapter);
3482 if (err) {
3483 dev_err(&pdev->dev, "failed to init i2c interface\n");
3484 goto err_eeprom;
3485 }
3486
3487 /* let the f/w know that the h/w is now under the control of the
3488 * driver.
3489 */
3490 igb_get_hw_control(adapter);
3491
3492 strcpy(netdev->name, "eth%d");
3493 err = register_netdev(netdev);
3494 if (err)
3495 goto err_register;
3496
3497 /* carrier off reporting is important to ethtool even BEFORE open */
3498 netif_carrier_off(netdev);
3499
3500#ifdef CONFIG_IGB_DCA
3501 if (dca_add_requester(&pdev->dev) == 0) {
3502 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3503 dev_info(&pdev->dev, "DCA enabled\n");
3504 igb_setup_dca(adapter);
3505 }
3506
3507#endif
3508#ifdef CONFIG_IGB_HWMON
3509 /* Initialize the thermal sensor on i350 devices. */
3510 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3511 u16 ets_word;
3512
3513 /* Read the NVM to determine if this i350 device supports an
3514 * external thermal sensor.
3515 */
3516 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3517 if (ets_word != 0x0000 && ets_word != 0xFFFF)
3518 adapter->ets = true;
3519 else
3520 adapter->ets = false;
3521 if (igb_sysfs_init(adapter))
3522 dev_err(&pdev->dev,
3523 "failed to allocate sysfs resources\n");
3524 } else {
3525 adapter->ets = false;
3526 }
3527#endif
3528 /* Check if Media Autosense is enabled */
3529 adapter->ei = *ei;
3530 if (hw->dev_spec._82575.mas_capable)
3531 igb_init_mas(adapter);
3532
3533 /* do hw tstamp init after resetting */
3534 igb_ptp_init(adapter);
3535
3536 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3537 /* print bus type/speed/width info, not applicable to i354 */
3538 if (hw->mac.type != e1000_i354) {
3539 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3540 netdev->name,
3541 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3542 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3543 "unknown"),
3544 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3545 "Width x4" :
3546 (hw->bus.width == e1000_bus_width_pcie_x2) ?
3547 "Width x2" :
3548 (hw->bus.width == e1000_bus_width_pcie_x1) ?
3549 "Width x1" : "unknown"), netdev->dev_addr);
3550 }
3551
3552 if ((hw->mac.type == e1000_82576 &&
3553 rd32(E1000_EECD) & E1000_EECD_PRES) ||
3554 (hw->mac.type >= e1000_i210 ||
3555 igb_get_flash_presence_i210(hw))) {
3556 ret_val = igb_read_part_string(hw, part_str,
3557 E1000_PBANUM_LENGTH);
3558 } else {
3559 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3560 }
3561
3562 if (ret_val)
3563 strcpy(part_str, "Unknown");
3564 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3565 dev_info(&pdev->dev,
3566 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3567 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3568 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3569 adapter->num_rx_queues, adapter->num_tx_queues);
3570 if (hw->phy.media_type == e1000_media_type_copper) {
3571 switch (hw->mac.type) {
3572 case e1000_i350:
3573 case e1000_i210:
3574 case e1000_i211:
3575 /* Enable EEE for internal copper PHY devices */
3576 err = igb_set_eee_i350(hw, true, true);
3577 if ((!err) &&
3578 (!hw->dev_spec._82575.eee_disable)) {
3579 adapter->eee_advert =
3580 MDIO_EEE_100TX | MDIO_EEE_1000T;
3581 adapter->flags |= IGB_FLAG_EEE;
3582 }
3583 break;
3584 case e1000_i354:
3585 if ((rd32(E1000_CTRL_EXT) &
3586 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3587 err = igb_set_eee_i354(hw, true, true);
3588 if ((!err) &&
3589 (!hw->dev_spec._82575.eee_disable)) {
3590 adapter->eee_advert =
3591 MDIO_EEE_100TX | MDIO_EEE_1000T;
3592 adapter->flags |= IGB_FLAG_EEE;
3593 }
3594 }
3595 break;
3596 default:
3597 break;
3598 }
3599 }
3600
3601 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
3602
3603 pm_runtime_put_noidle(&pdev->dev);
3604 return 0;
3605
3606err_register:
3607 igb_release_hw_control(adapter);
3608 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3609err_eeprom:
3610 if (!igb_check_reset_block(hw))
3611 igb_reset_phy(hw);
3612
3613 if (hw->flash_address)
3614 iounmap(hw->flash_address);
3615err_sw_init:
3616 kfree(adapter->mac_table);
3617 kfree(adapter->shadow_vfta);
3618 igb_clear_interrupt_scheme(adapter);
3619#ifdef CONFIG_PCI_IOV
3620 igb_disable_sriov(pdev);
3621#endif
3622 pci_iounmap(pdev, adapter->io_addr);
3623err_ioremap:
3624 free_netdev(netdev);
3625err_alloc_etherdev:
3626 pci_disable_pcie_error_reporting(pdev);
3627 pci_release_mem_regions(pdev);
3628err_pci_reg:
3629err_dma:
3630 pci_disable_device(pdev);
3631 return err;
3632}
3633
3634#ifdef CONFIG_PCI_IOV
3635static int igb_disable_sriov(struct pci_dev *pdev)
3636{
3637 struct net_device *netdev = pci_get_drvdata(pdev);
3638 struct igb_adapter *adapter = netdev_priv(netdev);
3639 struct e1000_hw *hw = &adapter->hw;
3640
3641 /* reclaim resources allocated to VFs */
3642 if (adapter->vf_data) {
3643 /* disable iov and allow time for transactions to clear */
3644 if (pci_vfs_assigned(pdev)) {
3645 dev_warn(&pdev->dev,
3646 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3647 return -EPERM;
3648 } else {
3649 pci_disable_sriov(pdev);
3650 msleep(500);
3651 }
3652
3653 kfree(adapter->vf_mac_list);
3654 adapter->vf_mac_list = NULL;
3655 kfree(adapter->vf_data);
3656 adapter->vf_data = NULL;
3657 adapter->vfs_allocated_count = 0;
3658 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3659 wrfl();
3660 msleep(100);
3661 dev_info(&pdev->dev, "IOV Disabled\n");
3662
3663 /* Re-enable DMA Coalescing flag since IOV is turned off */
3664 adapter->flags |= IGB_FLAG_DMAC;
3665 }
3666
3667 return 0;
3668}
3669
3670static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
3671{
3672 struct net_device *netdev = pci_get_drvdata(pdev);
3673 struct igb_adapter *adapter = netdev_priv(netdev);
3674 int old_vfs = pci_num_vf(pdev);
3675 struct vf_mac_filter *mac_list;
3676 int err = 0;
3677 int num_vf_mac_filters, i;
3678
3679 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3680 err = -EPERM;
3681 goto out;
3682 }
3683 if (!num_vfs)
3684 goto out;
3685
3686 if (old_vfs) {
3687 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3688 old_vfs, max_vfs);
3689 adapter->vfs_allocated_count = old_vfs;
3690 } else
3691 adapter->vfs_allocated_count = num_vfs;
3692
3693 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3694 sizeof(struct vf_data_storage), GFP_KERNEL);
3695
3696 /* if allocation failed then we do not support SR-IOV */
3697 if (!adapter->vf_data) {
3698 adapter->vfs_allocated_count = 0;
3699 err = -ENOMEM;
3700 goto out;
3701 }
3702
3703 /* Due to the limited number of RAR entries calculate potential
3704 * number of MAC filters available for the VFs. Reserve entries
3705 * for PF default MAC, PF MAC filters and at least one RAR entry
3706 * for each VF for VF MAC.
3707 */
3708 num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3709 (1 + IGB_PF_MAC_FILTERS_RESERVED +
3710 adapter->vfs_allocated_count);
3711
3712 adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3713 sizeof(struct vf_mac_filter),
3714 GFP_KERNEL);
3715
3716 mac_list = adapter->vf_mac_list;
3717 INIT_LIST_HEAD(&adapter->vf_macs.l);
3718
3719 if (adapter->vf_mac_list) {
3720 /* Initialize list of VF MAC filters */
3721 for (i = 0; i < num_vf_mac_filters; i++) {
3722 mac_list->vf = -1;
3723 mac_list->free = true;
3724 list_add(&mac_list->l, &adapter->vf_macs.l);
3725 mac_list++;
3726 }
3727 } else {
3728 /* If we could not allocate memory for the VF MAC filters
3729 * we can continue without this feature but warn user.
3730 */
3731 dev_err(&pdev->dev,
3732 "Unable to allocate memory for VF MAC filter list\n");
3733 }
3734
3735 /* only call pci_enable_sriov() if no VFs are allocated already */
3736 if (!old_vfs) {
3737 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3738 if (err)
3739 goto err_out;
3740 }
3741 dev_info(&pdev->dev, "%d VFs allocated\n",
3742 adapter->vfs_allocated_count);
3743 for (i = 0; i < adapter->vfs_allocated_count; i++)
3744 igb_vf_configure(adapter, i);
3745
3746 /* DMA Coalescing is not supported in IOV mode. */
3747 adapter->flags &= ~IGB_FLAG_DMAC;
3748 goto out;
3749
3750err_out:
3751 kfree(adapter->vf_mac_list);
3752 adapter->vf_mac_list = NULL;
3753 kfree(adapter->vf_data);
3754 adapter->vf_data = NULL;
3755 adapter->vfs_allocated_count = 0;
3756out:
3757 return err;
3758}
3759
3760#endif
3761/**
3762 * igb_remove_i2c - Cleanup I2C interface
3763 * @adapter: pointer to adapter structure
3764 **/
3765static void igb_remove_i2c(struct igb_adapter *adapter)
3766{
3767 /* free the adapter bus structure */
3768 i2c_del_adapter(&adapter->i2c_adap);
3769}
3770
3771/**
3772 * igb_remove - Device Removal Routine
3773 * @pdev: PCI device information struct
3774 *
3775 * igb_remove is called by the PCI subsystem to alert the driver
3776 * that it should release a PCI device. The could be caused by a
3777 * Hot-Plug event, or because the driver is going to be removed from
3778 * memory.
3779 **/
3780static void igb_remove(struct pci_dev *pdev)
3781{
3782 struct net_device *netdev = pci_get_drvdata(pdev);
3783 struct igb_adapter *adapter = netdev_priv(netdev);
3784 struct e1000_hw *hw = &adapter->hw;
3785
3786 pm_runtime_get_noresume(&pdev->dev);
3787#ifdef CONFIG_IGB_HWMON
3788 igb_sysfs_exit(adapter);
3789#endif
3790 igb_remove_i2c(adapter);
3791 igb_ptp_stop(adapter);
3792 /* The watchdog timer may be rescheduled, so explicitly
3793 * disable watchdog from being rescheduled.
3794 */
3795 set_bit(__IGB_DOWN, &adapter->state);
3796 del_timer_sync(&adapter->watchdog_timer);
3797 del_timer_sync(&adapter->phy_info_timer);
3798
3799 cancel_work_sync(&adapter->reset_task);
3800 cancel_work_sync(&adapter->watchdog_task);
3801
3802#ifdef CONFIG_IGB_DCA
3803 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3804 dev_info(&pdev->dev, "DCA disabled\n");
3805 dca_remove_requester(&pdev->dev);
3806 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3807 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3808 }
3809#endif
3810
3811 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3812 * would have already happened in close and is redundant.
3813 */
3814 igb_release_hw_control(adapter);
3815
3816#ifdef CONFIG_PCI_IOV
3817 igb_disable_sriov(pdev);
3818#endif
3819
3820 unregister_netdev(netdev);
3821
3822 igb_clear_interrupt_scheme(adapter);
3823
3824 pci_iounmap(pdev, adapter->io_addr);
3825 if (hw->flash_address)
3826 iounmap(hw->flash_address);
3827 pci_release_mem_regions(pdev);
3828
3829 kfree(adapter->mac_table);
3830 kfree(adapter->shadow_vfta);
3831 free_netdev(netdev);
3832
3833 pci_disable_pcie_error_reporting(pdev);
3834
3835 pci_disable_device(pdev);
3836}
3837
3838/**
3839 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3840 * @adapter: board private structure to initialize
3841 *
3842 * This function initializes the vf specific data storage and then attempts to
3843 * allocate the VFs. The reason for ordering it this way is because it is much
3844 * mor expensive time wise to disable SR-IOV than it is to allocate and free
3845 * the memory for the VFs.
3846 **/
3847static void igb_probe_vfs(struct igb_adapter *adapter)
3848{
3849#ifdef CONFIG_PCI_IOV
3850 struct pci_dev *pdev = adapter->pdev;
3851 struct e1000_hw *hw = &adapter->hw;
3852
3853 /* Virtualization features not supported on i210 family. */
3854 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
3855 return;
3856
3857 /* Of the below we really only want the effect of getting
3858 * IGB_FLAG_HAS_MSIX set (if available), without which
3859 * igb_enable_sriov() has no effect.
3860 */
3861 igb_set_interrupt_capability(adapter, true);
3862 igb_reset_interrupt_capability(adapter);
3863
3864 pci_sriov_set_totalvfs(pdev, 7);
3865 igb_enable_sriov(pdev, max_vfs);
3866
3867#endif /* CONFIG_PCI_IOV */
3868}
3869
3870unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3871{
3872 struct e1000_hw *hw = &adapter->hw;
3873 unsigned int max_rss_queues;
3874
3875 /* Determine the maximum number of RSS queues supported. */
3876 switch (hw->mac.type) {
3877 case e1000_i211:
3878 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3879 break;
3880 case e1000_82575:
3881 case e1000_i210:
3882 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3883 break;
3884 case e1000_i350:
3885 /* I350 cannot do RSS and SR-IOV at the same time */
3886 if (!!adapter->vfs_allocated_count) {
3887 max_rss_queues = 1;
3888 break;
3889 }
3890 fallthrough;
3891 case e1000_82576:
3892 if (!!adapter->vfs_allocated_count) {
3893 max_rss_queues = 2;
3894 break;
3895 }
3896 fallthrough;
3897 case e1000_82580:
3898 case e1000_i354:
3899 default:
3900 max_rss_queues = IGB_MAX_RX_QUEUES;
3901 break;
3902 }
3903
3904 return max_rss_queues;
3905}
3906
3907static void igb_init_queue_configuration(struct igb_adapter *adapter)
3908{
3909 u32 max_rss_queues;
3910
3911 max_rss_queues = igb_get_max_rss_queues(adapter);
3912 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3913
3914 igb_set_flag_queue_pairs(adapter, max_rss_queues);
3915}
3916
3917void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3918 const u32 max_rss_queues)
3919{
3920 struct e1000_hw *hw = &adapter->hw;
3921
3922 /* Determine if we need to pair queues. */
3923 switch (hw->mac.type) {
3924 case e1000_82575:
3925 case e1000_i211:
3926 /* Device supports enough interrupts without queue pairing. */
3927 break;
3928 case e1000_82576:
3929 case e1000_82580:
3930 case e1000_i350:
3931 case e1000_i354:
3932 case e1000_i210:
3933 default:
3934 /* If rss_queues > half of max_rss_queues, pair the queues in
3935 * order to conserve interrupts due to limited supply.
3936 */
3937 if (adapter->rss_queues > (max_rss_queues / 2))
3938 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
3939 else
3940 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
3941 break;
3942 }
3943}
3944
3945/**
3946 * igb_sw_init - Initialize general software structures (struct igb_adapter)
3947 * @adapter: board private structure to initialize
3948 *
3949 * igb_sw_init initializes the Adapter private data structure.
3950 * Fields are initialized based on PCI device information and
3951 * OS network device settings (MTU size).
3952 **/
3953static int igb_sw_init(struct igb_adapter *adapter)
3954{
3955 struct e1000_hw *hw = &adapter->hw;
3956 struct net_device *netdev = adapter->netdev;
3957 struct pci_dev *pdev = adapter->pdev;
3958
3959 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3960
3961 /* set default ring sizes */
3962 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3963 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3964
3965 /* set default ITR values */
3966 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3967 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3968
3969 /* set default work limits */
3970 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3971
3972 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD;
3973 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3974
3975 spin_lock_init(&adapter->nfc_lock);
3976 spin_lock_init(&adapter->stats64_lock);
3977#ifdef CONFIG_PCI_IOV
3978 switch (hw->mac.type) {
3979 case e1000_82576:
3980 case e1000_i350:
3981 if (max_vfs > 7) {
3982 dev_warn(&pdev->dev,
3983 "Maximum of 7 VFs per PF, using max\n");
3984 max_vfs = adapter->vfs_allocated_count = 7;
3985 } else
3986 adapter->vfs_allocated_count = max_vfs;
3987 if (adapter->vfs_allocated_count)
3988 dev_warn(&pdev->dev,
3989 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3990 break;
3991 default:
3992 break;
3993 }
3994#endif /* CONFIG_PCI_IOV */
3995
3996 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3997 adapter->flags |= IGB_FLAG_HAS_MSIX;
3998
3999 adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
4000 sizeof(struct igb_mac_addr),
4001 GFP_KERNEL);
4002 if (!adapter->mac_table)
4003 return -ENOMEM;
4004
4005 igb_probe_vfs(adapter);
4006
4007 igb_init_queue_configuration(adapter);
4008
4009 /* Setup and initialize a copy of the hw vlan table array */
4010 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
4011 GFP_KERNEL);
4012 if (!adapter->shadow_vfta)
4013 return -ENOMEM;
4014
4015 /* This call may decrease the number of queues */
4016 if (igb_init_interrupt_scheme(adapter, true)) {
4017 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4018 return -ENOMEM;
4019 }
4020
4021 /* Explicitly disable IRQ since the NIC can be in any state. */
4022 igb_irq_disable(adapter);
4023
4024 if (hw->mac.type >= e1000_i350)
4025 adapter->flags &= ~IGB_FLAG_DMAC;
4026
4027 set_bit(__IGB_DOWN, &adapter->state);
4028 return 0;
4029}
4030
4031/**
4032 * __igb_open - Called when a network interface is made active
4033 * @netdev: network interface device structure
4034 * @resuming: indicates whether we are in a resume call
4035 *
4036 * Returns 0 on success, negative value on failure
4037 *
4038 * The open entry point is called when a network interface is made
4039 * active by the system (IFF_UP). At this point all resources needed
4040 * for transmit and receive operations are allocated, the interrupt
4041 * handler is registered with the OS, the watchdog timer is started,
4042 * and the stack is notified that the interface is ready.
4043 **/
4044static int __igb_open(struct net_device *netdev, bool resuming)
4045{
4046 struct igb_adapter *adapter = netdev_priv(netdev);
4047 struct e1000_hw *hw = &adapter->hw;
4048 struct pci_dev *pdev = adapter->pdev;
4049 int err;
4050 int i;
4051
4052 /* disallow open during test */
4053 if (test_bit(__IGB_TESTING, &adapter->state)) {
4054 WARN_ON(resuming);
4055 return -EBUSY;
4056 }
4057
4058 if (!resuming)
4059 pm_runtime_get_sync(&pdev->dev);
4060
4061 netif_carrier_off(netdev);
4062
4063 /* allocate transmit descriptors */
4064 err = igb_setup_all_tx_resources(adapter);
4065 if (err)
4066 goto err_setup_tx;
4067
4068 /* allocate receive descriptors */
4069 err = igb_setup_all_rx_resources(adapter);
4070 if (err)
4071 goto err_setup_rx;
4072
4073 igb_power_up_link(adapter);
4074
4075 /* before we allocate an interrupt, we must be ready to handle it.
4076 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4077 * as soon as we call pci_request_irq, so we have to setup our
4078 * clean_rx handler before we do so.
4079 */
4080 igb_configure(adapter);
4081
4082 err = igb_request_irq(adapter);
4083 if (err)
4084 goto err_req_irq;
4085
4086 /* Notify the stack of the actual queue counts. */
4087 err = netif_set_real_num_tx_queues(adapter->netdev,
4088 adapter->num_tx_queues);
4089 if (err)
4090 goto err_set_queues;
4091
4092 err = netif_set_real_num_rx_queues(adapter->netdev,
4093 adapter->num_rx_queues);
4094 if (err)
4095 goto err_set_queues;
4096
4097 /* From here on the code is the same as igb_up() */
4098 clear_bit(__IGB_DOWN, &adapter->state);
4099
4100 for (i = 0; i < adapter->num_q_vectors; i++)
4101 napi_enable(&(adapter->q_vector[i]->napi));
4102
4103 /* Clear any pending interrupts. */
4104 rd32(E1000_TSICR);
4105 rd32(E1000_ICR);
4106
4107 igb_irq_enable(adapter);
4108
4109 /* notify VFs that reset has been completed */
4110 if (adapter->vfs_allocated_count) {
4111 u32 reg_data = rd32(E1000_CTRL_EXT);
4112
4113 reg_data |= E1000_CTRL_EXT_PFRSTD;
4114 wr32(E1000_CTRL_EXT, reg_data);
4115 }
4116
4117 netif_tx_start_all_queues(netdev);
4118
4119 if (!resuming)
4120 pm_runtime_put(&pdev->dev);
4121
4122 /* start the watchdog. */
4123 hw->mac.get_link_status = 1;
4124 schedule_work(&adapter->watchdog_task);
4125
4126 return 0;
4127
4128err_set_queues:
4129 igb_free_irq(adapter);
4130err_req_irq:
4131 igb_release_hw_control(adapter);
4132 igb_power_down_link(adapter);
4133 igb_free_all_rx_resources(adapter);
4134err_setup_rx:
4135 igb_free_all_tx_resources(adapter);
4136err_setup_tx:
4137 igb_reset(adapter);
4138 if (!resuming)
4139 pm_runtime_put(&pdev->dev);
4140
4141 return err;
4142}
4143
4144int igb_open(struct net_device *netdev)
4145{
4146 return __igb_open(netdev, false);
4147}
4148
4149/**
4150 * __igb_close - Disables a network interface
4151 * @netdev: network interface device structure
4152 * @suspending: indicates we are in a suspend call
4153 *
4154 * Returns 0, this is not allowed to fail
4155 *
4156 * The close entry point is called when an interface is de-activated
4157 * by the OS. The hardware is still under the driver's control, but
4158 * needs to be disabled. A global MAC reset is issued to stop the
4159 * hardware, and all transmit and receive resources are freed.
4160 **/
4161static int __igb_close(struct net_device *netdev, bool suspending)
4162{
4163 struct igb_adapter *adapter = netdev_priv(netdev);
4164 struct pci_dev *pdev = adapter->pdev;
4165
4166 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4167
4168 if (!suspending)
4169 pm_runtime_get_sync(&pdev->dev);
4170
4171 igb_down(adapter);
4172 igb_free_irq(adapter);
4173
4174 igb_free_all_tx_resources(adapter);
4175 igb_free_all_rx_resources(adapter);
4176
4177 if (!suspending)
4178 pm_runtime_put_sync(&pdev->dev);
4179 return 0;
4180}
4181
4182int igb_close(struct net_device *netdev)
4183{
4184 if (netif_device_present(netdev) || netdev->dismantle)
4185 return __igb_close(netdev, false);
4186 return 0;
4187}
4188
4189/**
4190 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
4191 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4192 *
4193 * Return 0 on success, negative on failure
4194 **/
4195int igb_setup_tx_resources(struct igb_ring *tx_ring)
4196{
4197 struct device *dev = tx_ring->dev;
4198 int size;
4199
4200 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
4201
4202 tx_ring->tx_buffer_info = vmalloc(size);
4203 if (!tx_ring->tx_buffer_info)
4204 goto err;
4205
4206 /* round up to nearest 4K */
4207 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
4208 tx_ring->size = ALIGN(tx_ring->size, 4096);
4209
4210 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4211 &tx_ring->dma, GFP_KERNEL);
4212 if (!tx_ring->desc)
4213 goto err;
4214
4215 tx_ring->next_to_use = 0;
4216 tx_ring->next_to_clean = 0;
4217
4218 return 0;
4219
4220err:
4221 vfree(tx_ring->tx_buffer_info);
4222 tx_ring->tx_buffer_info = NULL;
4223 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4224 return -ENOMEM;
4225}
4226
4227/**
4228 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
4229 * (Descriptors) for all queues
4230 * @adapter: board private structure
4231 *
4232 * Return 0 on success, negative on failure
4233 **/
4234static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
4235{
4236 struct pci_dev *pdev = adapter->pdev;
4237 int i, err = 0;
4238
4239 for (i = 0; i < adapter->num_tx_queues; i++) {
4240 err = igb_setup_tx_resources(adapter->tx_ring[i]);
4241 if (err) {
4242 dev_err(&pdev->dev,
4243 "Allocation for Tx Queue %u failed\n", i);
4244 for (i--; i >= 0; i--)
4245 igb_free_tx_resources(adapter->tx_ring[i]);
4246 break;
4247 }
4248 }
4249
4250 return err;
4251}
4252
4253/**
4254 * igb_setup_tctl - configure the transmit control registers
4255 * @adapter: Board private structure
4256 **/
4257void igb_setup_tctl(struct igb_adapter *adapter)
4258{
4259 struct e1000_hw *hw = &adapter->hw;
4260 u32 tctl;
4261
4262 /* disable queue 0 which is enabled by default on 82575 and 82576 */
4263 wr32(E1000_TXDCTL(0), 0);
4264
4265 /* Program the Transmit Control Register */
4266 tctl = rd32(E1000_TCTL);
4267 tctl &= ~E1000_TCTL_CT;
4268 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
4269 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4270
4271 igb_config_collision_dist(hw);
4272
4273 /* Enable transmits */
4274 tctl |= E1000_TCTL_EN;
4275
4276 wr32(E1000_TCTL, tctl);
4277}
4278
4279/**
4280 * igb_configure_tx_ring - Configure transmit ring after Reset
4281 * @adapter: board private structure
4282 * @ring: tx ring to configure
4283 *
4284 * Configure a transmit ring after a reset.
4285 **/
4286void igb_configure_tx_ring(struct igb_adapter *adapter,
4287 struct igb_ring *ring)
4288{
4289 struct e1000_hw *hw = &adapter->hw;
4290 u32 txdctl = 0;
4291 u64 tdba = ring->dma;
4292 int reg_idx = ring->reg_idx;
4293
4294 wr32(E1000_TDLEN(reg_idx),
4295 ring->count * sizeof(union e1000_adv_tx_desc));
4296 wr32(E1000_TDBAL(reg_idx),
4297 tdba & 0x00000000ffffffffULL);
4298 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
4299
4300 ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
4301 wr32(E1000_TDH(reg_idx), 0);
4302 writel(0, ring->tail);
4303
4304 txdctl |= IGB_TX_PTHRESH;
4305 txdctl |= IGB_TX_HTHRESH << 8;
4306 txdctl |= IGB_TX_WTHRESH << 16;
4307
4308 /* reinitialize tx_buffer_info */
4309 memset(ring->tx_buffer_info, 0,
4310 sizeof(struct igb_tx_buffer) * ring->count);
4311
4312 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
4313 wr32(E1000_TXDCTL(reg_idx), txdctl);
4314}
4315
4316/**
4317 * igb_configure_tx - Configure transmit Unit after Reset
4318 * @adapter: board private structure
4319 *
4320 * Configure the Tx unit of the MAC after a reset.
4321 **/
4322static void igb_configure_tx(struct igb_adapter *adapter)
4323{
4324 struct e1000_hw *hw = &adapter->hw;
4325 int i;
4326
4327 /* disable the queues */
4328 for (i = 0; i < adapter->num_tx_queues; i++)
4329 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0);
4330
4331 wrfl();
4332 usleep_range(10000, 20000);
4333
4334 for (i = 0; i < adapter->num_tx_queues; i++)
4335 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
4336}
4337
4338/**
4339 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
4340 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
4341 *
4342 * Returns 0 on success, negative on failure
4343 **/
4344int igb_setup_rx_resources(struct igb_ring *rx_ring)
4345{
4346 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev);
4347 struct device *dev = rx_ring->dev;
4348 int size;
4349
4350 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
4351
4352 rx_ring->rx_buffer_info = vmalloc(size);
4353 if (!rx_ring->rx_buffer_info)
4354 goto err;
4355
4356 /* Round up to nearest 4K */
4357 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
4358 rx_ring->size = ALIGN(rx_ring->size, 4096);
4359
4360 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4361 &rx_ring->dma, GFP_KERNEL);
4362 if (!rx_ring->desc)
4363 goto err;
4364
4365 rx_ring->next_to_alloc = 0;
4366 rx_ring->next_to_clean = 0;
4367 rx_ring->next_to_use = 0;
4368
4369 rx_ring->xdp_prog = adapter->xdp_prog;
4370
4371 /* XDP RX-queue info */
4372 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
4373 rx_ring->queue_index, 0) < 0)
4374 goto err;
4375
4376 return 0;
4377
4378err:
4379 vfree(rx_ring->rx_buffer_info);
4380 rx_ring->rx_buffer_info = NULL;
4381 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4382 return -ENOMEM;
4383}
4384
4385/**
4386 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
4387 * (Descriptors) for all queues
4388 * @adapter: board private structure
4389 *
4390 * Return 0 on success, negative on failure
4391 **/
4392static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
4393{
4394 struct pci_dev *pdev = adapter->pdev;
4395 int i, err = 0;
4396
4397 for (i = 0; i < adapter->num_rx_queues; i++) {
4398 err = igb_setup_rx_resources(adapter->rx_ring[i]);
4399 if (err) {
4400 dev_err(&pdev->dev,
4401 "Allocation for Rx Queue %u failed\n", i);
4402 for (i--; i >= 0; i--)
4403 igb_free_rx_resources(adapter->rx_ring[i]);
4404 break;
4405 }
4406 }
4407
4408 return err;
4409}
4410
4411/**
4412 * igb_setup_mrqc - configure the multiple receive queue control registers
4413 * @adapter: Board private structure
4414 **/
4415static void igb_setup_mrqc(struct igb_adapter *adapter)
4416{
4417 struct e1000_hw *hw = &adapter->hw;
4418 u32 mrqc, rxcsum;
4419 u32 j, num_rx_queues;
4420 u32 rss_key[10];
4421
4422 netdev_rss_key_fill(rss_key, sizeof(rss_key));
4423 for (j = 0; j < 10; j++)
4424 wr32(E1000_RSSRK(j), rss_key[j]);
4425
4426 num_rx_queues = adapter->rss_queues;
4427
4428 switch (hw->mac.type) {
4429 case e1000_82576:
4430 /* 82576 supports 2 RSS queues for SR-IOV */
4431 if (adapter->vfs_allocated_count)
4432 num_rx_queues = 2;
4433 break;
4434 default:
4435 break;
4436 }
4437
4438 if (adapter->rss_indir_tbl_init != num_rx_queues) {
4439 for (j = 0; j < IGB_RETA_SIZE; j++)
4440 adapter->rss_indir_tbl[j] =
4441 (j * num_rx_queues) / IGB_RETA_SIZE;
4442 adapter->rss_indir_tbl_init = num_rx_queues;
4443 }
4444 igb_write_rss_indir_tbl(adapter);
4445
4446 /* Disable raw packet checksumming so that RSS hash is placed in
4447 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
4448 * offloads as they are enabled by default
4449 */
4450 rxcsum = rd32(E1000_RXCSUM);
4451 rxcsum |= E1000_RXCSUM_PCSD;
4452
4453 if (adapter->hw.mac.type >= e1000_82576)
4454 /* Enable Receive Checksum Offload for SCTP */
4455 rxcsum |= E1000_RXCSUM_CRCOFL;
4456
4457 /* Don't need to set TUOFL or IPOFL, they default to 1 */
4458 wr32(E1000_RXCSUM, rxcsum);
4459
4460 /* Generate RSS hash based on packet types, TCP/UDP
4461 * port numbers and/or IPv4/v6 src and dst addresses
4462 */
4463 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
4464 E1000_MRQC_RSS_FIELD_IPV4_TCP |
4465 E1000_MRQC_RSS_FIELD_IPV6 |
4466 E1000_MRQC_RSS_FIELD_IPV6_TCP |
4467 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
4468
4469 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
4470 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
4471 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
4472 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
4473
4474 /* If VMDq is enabled then we set the appropriate mode for that, else
4475 * we default to RSS so that an RSS hash is calculated per packet even
4476 * if we are only using one queue
4477 */
4478 if (adapter->vfs_allocated_count) {
4479 if (hw->mac.type > e1000_82575) {
4480 /* Set the default pool for the PF's first queue */
4481 u32 vtctl = rd32(E1000_VT_CTL);
4482
4483 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4484 E1000_VT_CTL_DISABLE_DEF_POOL);
4485 vtctl |= adapter->vfs_allocated_count <<
4486 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4487 wr32(E1000_VT_CTL, vtctl);
4488 }
4489 if (adapter->rss_queues > 1)
4490 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4491 else
4492 mrqc |= E1000_MRQC_ENABLE_VMDQ;
4493 } else {
4494 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4495 }
4496 igb_vmm_control(adapter);
4497
4498 wr32(E1000_MRQC, mrqc);
4499}
4500
4501/**
4502 * igb_setup_rctl - configure the receive control registers
4503 * @adapter: Board private structure
4504 **/
4505void igb_setup_rctl(struct igb_adapter *adapter)
4506{
4507 struct e1000_hw *hw = &adapter->hw;
4508 u32 rctl;
4509
4510 rctl = rd32(E1000_RCTL);
4511
4512 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4513 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4514
4515 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4516 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4517
4518 /* enable stripping of CRC. It's unlikely this will break BMC
4519 * redirection as it did with e1000. Newer features require
4520 * that the HW strips the CRC.
4521 */
4522 rctl |= E1000_RCTL_SECRC;
4523
4524 /* disable store bad packets and clear size bits. */
4525 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4526
4527 /* enable LPE to allow for reception of jumbo frames */
4528 rctl |= E1000_RCTL_LPE;
4529
4530 /* disable queue 0 to prevent tail write w/o re-config */
4531 wr32(E1000_RXDCTL(0), 0);
4532
4533 /* Attention!!! For SR-IOV PF driver operations you must enable
4534 * queue drop for all VF and PF queues to prevent head of line blocking
4535 * if an un-trusted VF does not provide descriptors to hardware.
4536 */
4537 if (adapter->vfs_allocated_count) {
4538 /* set all queue drop enable bits */
4539 wr32(E1000_QDE, ALL_QUEUES);
4540 }
4541
4542 /* This is useful for sniffing bad packets. */
4543 if (adapter->netdev->features & NETIF_F_RXALL) {
4544 /* UPE and MPE will be handled by normal PROMISC logic
4545 * in e1000e_set_rx_mode
4546 */
4547 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4548 E1000_RCTL_BAM | /* RX All Bcast Pkts */
4549 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4550
4551 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4552 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4553 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4554 * and that breaks VLANs.
4555 */
4556 }
4557
4558 wr32(E1000_RCTL, rctl);
4559}
4560
4561static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4562 int vfn)
4563{
4564 struct e1000_hw *hw = &adapter->hw;
4565 u32 vmolr;
4566
4567 if (size > MAX_JUMBO_FRAME_SIZE)
4568 size = MAX_JUMBO_FRAME_SIZE;
4569
4570 vmolr = rd32(E1000_VMOLR(vfn));
4571 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4572 vmolr |= size | E1000_VMOLR_LPE;
4573 wr32(E1000_VMOLR(vfn), vmolr);
4574
4575 return 0;
4576}
4577
4578static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4579 int vfn, bool enable)
4580{
4581 struct e1000_hw *hw = &adapter->hw;
4582 u32 val, reg;
4583
4584 if (hw->mac.type < e1000_82576)
4585 return;
4586
4587 if (hw->mac.type == e1000_i350)
4588 reg = E1000_DVMOLR(vfn);
4589 else
4590 reg = E1000_VMOLR(vfn);
4591
4592 val = rd32(reg);
4593 if (enable)
4594 val |= E1000_VMOLR_STRVLAN;
4595 else
4596 val &= ~(E1000_VMOLR_STRVLAN);
4597 wr32(reg, val);
4598}
4599
4600static inline void igb_set_vmolr(struct igb_adapter *adapter,
4601 int vfn, bool aupe)
4602{
4603 struct e1000_hw *hw = &adapter->hw;
4604 u32 vmolr;
4605
4606 /* This register exists only on 82576 and newer so if we are older then
4607 * we should exit and do nothing
4608 */
4609 if (hw->mac.type < e1000_82576)
4610 return;
4611
4612 vmolr = rd32(E1000_VMOLR(vfn));
4613 if (aupe)
4614 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4615 else
4616 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4617
4618 /* clear all bits that might not be set */
4619 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4620
4621 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4622 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4623 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
4624 * multicast packets
4625 */
4626 if (vfn <= adapter->vfs_allocated_count)
4627 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4628
4629 wr32(E1000_VMOLR(vfn), vmolr);
4630}
4631
4632/**
4633 * igb_setup_srrctl - configure the split and replication receive control
4634 * registers
4635 * @adapter: Board private structure
4636 * @ring: receive ring to be configured
4637 **/
4638void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring)
4639{
4640 struct e1000_hw *hw = &adapter->hw;
4641 int reg_idx = ring->reg_idx;
4642 u32 srrctl = 0;
4643
4644 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4645 if (ring_uses_large_buffer(ring))
4646 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4647 else
4648 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4649 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4650 if (hw->mac.type >= e1000_82580)
4651 srrctl |= E1000_SRRCTL_TIMESTAMP;
4652 /* Only set Drop Enable if VFs allocated, or we are supporting multiple
4653 * queues and rx flow control is disabled
4654 */
4655 if (adapter->vfs_allocated_count ||
4656 (!(hw->fc.current_mode & e1000_fc_rx_pause) &&
4657 adapter->num_rx_queues > 1))
4658 srrctl |= E1000_SRRCTL_DROP_EN;
4659
4660 wr32(E1000_SRRCTL(reg_idx), srrctl);
4661}
4662
4663/**
4664 * igb_configure_rx_ring - Configure a receive ring after Reset
4665 * @adapter: board private structure
4666 * @ring: receive ring to be configured
4667 *
4668 * Configure the Rx unit of the MAC after a reset.
4669 **/
4670void igb_configure_rx_ring(struct igb_adapter *adapter,
4671 struct igb_ring *ring)
4672{
4673 struct e1000_hw *hw = &adapter->hw;
4674 union e1000_adv_rx_desc *rx_desc;
4675 u64 rdba = ring->dma;
4676 int reg_idx = ring->reg_idx;
4677 u32 rxdctl = 0;
4678
4679 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4680 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4681 MEM_TYPE_PAGE_SHARED, NULL));
4682
4683 /* disable the queue */
4684 wr32(E1000_RXDCTL(reg_idx), 0);
4685
4686 /* Set DMA base address registers */
4687 wr32(E1000_RDBAL(reg_idx),
4688 rdba & 0x00000000ffffffffULL);
4689 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4690 wr32(E1000_RDLEN(reg_idx),
4691 ring->count * sizeof(union e1000_adv_rx_desc));
4692
4693 /* initialize head and tail */
4694 ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4695 wr32(E1000_RDH(reg_idx), 0);
4696 writel(0, ring->tail);
4697
4698 /* set descriptor configuration */
4699 igb_setup_srrctl(adapter, ring);
4700
4701 /* set filtering for VMDQ pools */
4702 igb_set_vmolr(adapter, reg_idx & 0x7, true);
4703
4704 rxdctl |= IGB_RX_PTHRESH;
4705 rxdctl |= IGB_RX_HTHRESH << 8;
4706 rxdctl |= IGB_RX_WTHRESH << 16;
4707
4708 /* initialize rx_buffer_info */
4709 memset(ring->rx_buffer_info, 0,
4710 sizeof(struct igb_rx_buffer) * ring->count);
4711
4712 /* initialize Rx descriptor 0 */
4713 rx_desc = IGB_RX_DESC(ring, 0);
4714 rx_desc->wb.upper.length = 0;
4715
4716 /* enable receive descriptor fetching */
4717 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4718 wr32(E1000_RXDCTL(reg_idx), rxdctl);
4719}
4720
4721static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4722 struct igb_ring *rx_ring)
4723{
4724 /* set build_skb and buffer size flags */
4725 clear_ring_build_skb_enabled(rx_ring);
4726 clear_ring_uses_large_buffer(rx_ring);
4727
4728 if (adapter->flags & IGB_FLAG_RX_LEGACY)
4729 return;
4730
4731 set_ring_build_skb_enabled(rx_ring);
4732
4733#if (PAGE_SIZE < 8192)
4734 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
4735 return;
4736
4737 set_ring_uses_large_buffer(rx_ring);
4738#endif
4739}
4740
4741/**
4742 * igb_configure_rx - Configure receive Unit after Reset
4743 * @adapter: board private structure
4744 *
4745 * Configure the Rx unit of the MAC after a reset.
4746 **/
4747static void igb_configure_rx(struct igb_adapter *adapter)
4748{
4749 int i;
4750
4751 /* set the correct pool for the PF default MAC address in entry 0 */
4752 igb_set_default_mac_filter(adapter);
4753
4754 /* Setup the HW Rx Head and Tail Descriptor Pointers and
4755 * the Base and Length of the Rx Descriptor Ring
4756 */
4757 for (i = 0; i < adapter->num_rx_queues; i++) {
4758 struct igb_ring *rx_ring = adapter->rx_ring[i];
4759
4760 igb_set_rx_buffer_len(adapter, rx_ring);
4761 igb_configure_rx_ring(adapter, rx_ring);
4762 }
4763}
4764
4765/**
4766 * igb_free_tx_resources - Free Tx Resources per Queue
4767 * @tx_ring: Tx descriptor ring for a specific queue
4768 *
4769 * Free all transmit software resources
4770 **/
4771void igb_free_tx_resources(struct igb_ring *tx_ring)
4772{
4773 igb_clean_tx_ring(tx_ring);
4774
4775 vfree(tx_ring->tx_buffer_info);
4776 tx_ring->tx_buffer_info = NULL;
4777
4778 /* if not set, then don't free */
4779 if (!tx_ring->desc)
4780 return;
4781
4782 dma_free_coherent(tx_ring->dev, tx_ring->size,
4783 tx_ring->desc, tx_ring->dma);
4784
4785 tx_ring->desc = NULL;
4786}
4787
4788/**
4789 * igb_free_all_tx_resources - Free Tx Resources for All Queues
4790 * @adapter: board private structure
4791 *
4792 * Free all transmit software resources
4793 **/
4794static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4795{
4796 int i;
4797
4798 for (i = 0; i < adapter->num_tx_queues; i++)
4799 if (adapter->tx_ring[i])
4800 igb_free_tx_resources(adapter->tx_ring[i]);
4801}
4802
4803/**
4804 * igb_clean_tx_ring - Free Tx Buffers
4805 * @tx_ring: ring to be cleaned
4806 **/
4807static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4808{
4809 u16 i = tx_ring->next_to_clean;
4810 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4811
4812 while (i != tx_ring->next_to_use) {
4813 union e1000_adv_tx_desc *eop_desc, *tx_desc;
4814
4815 /* Free all the Tx ring sk_buffs */
4816 dev_kfree_skb_any(tx_buffer->skb);
4817
4818 /* unmap skb header data */
4819 dma_unmap_single(tx_ring->dev,
4820 dma_unmap_addr(tx_buffer, dma),
4821 dma_unmap_len(tx_buffer, len),
4822 DMA_TO_DEVICE);
4823
4824 /* check for eop_desc to determine the end of the packet */
4825 eop_desc = tx_buffer->next_to_watch;
4826 tx_desc = IGB_TX_DESC(tx_ring, i);
4827
4828 /* unmap remaining buffers */
4829 while (tx_desc != eop_desc) {
4830 tx_buffer++;
4831 tx_desc++;
4832 i++;
4833 if (unlikely(i == tx_ring->count)) {
4834 i = 0;
4835 tx_buffer = tx_ring->tx_buffer_info;
4836 tx_desc = IGB_TX_DESC(tx_ring, 0);
4837 }
4838
4839 /* unmap any remaining paged data */
4840 if (dma_unmap_len(tx_buffer, len))
4841 dma_unmap_page(tx_ring->dev,
4842 dma_unmap_addr(tx_buffer, dma),
4843 dma_unmap_len(tx_buffer, len),
4844 DMA_TO_DEVICE);
4845 }
4846
4847 tx_buffer->next_to_watch = NULL;
4848
4849 /* move us one more past the eop_desc for start of next pkt */
4850 tx_buffer++;
4851 i++;
4852 if (unlikely(i == tx_ring->count)) {
4853 i = 0;
4854 tx_buffer = tx_ring->tx_buffer_info;
4855 }
4856 }
4857
4858 /* reset BQL for queue */
4859 netdev_tx_reset_queue(txring_txq(tx_ring));
4860
4861 /* reset next_to_use and next_to_clean */
4862 tx_ring->next_to_use = 0;
4863 tx_ring->next_to_clean = 0;
4864}
4865
4866/**
4867 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
4868 * @adapter: board private structure
4869 **/
4870static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4871{
4872 int i;
4873
4874 for (i = 0; i < adapter->num_tx_queues; i++)
4875 if (adapter->tx_ring[i])
4876 igb_clean_tx_ring(adapter->tx_ring[i]);
4877}
4878
4879/**
4880 * igb_free_rx_resources - Free Rx Resources
4881 * @rx_ring: ring to clean the resources from
4882 *
4883 * Free all receive software resources
4884 **/
4885void igb_free_rx_resources(struct igb_ring *rx_ring)
4886{
4887 igb_clean_rx_ring(rx_ring);
4888
4889 rx_ring->xdp_prog = NULL;
4890 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4891 vfree(rx_ring->rx_buffer_info);
4892 rx_ring->rx_buffer_info = NULL;
4893
4894 /* if not set, then don't free */
4895 if (!rx_ring->desc)
4896 return;
4897
4898 dma_free_coherent(rx_ring->dev, rx_ring->size,
4899 rx_ring->desc, rx_ring->dma);
4900
4901 rx_ring->desc = NULL;
4902}
4903
4904/**
4905 * igb_free_all_rx_resources - Free Rx Resources for All Queues
4906 * @adapter: board private structure
4907 *
4908 * Free all receive software resources
4909 **/
4910static void igb_free_all_rx_resources(struct igb_adapter *adapter)
4911{
4912 int i;
4913
4914 for (i = 0; i < adapter->num_rx_queues; i++)
4915 if (adapter->rx_ring[i])
4916 igb_free_rx_resources(adapter->rx_ring[i]);
4917}
4918
4919/**
4920 * igb_clean_rx_ring - Free Rx Buffers per Queue
4921 * @rx_ring: ring to free buffers from
4922 **/
4923static void igb_clean_rx_ring(struct igb_ring *rx_ring)
4924{
4925 u16 i = rx_ring->next_to_clean;
4926
4927 dev_kfree_skb(rx_ring->skb);
4928 rx_ring->skb = NULL;
4929
4930 /* Free all the Rx ring sk_buffs */
4931 while (i != rx_ring->next_to_alloc) {
4932 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
4933
4934 /* Invalidate cache lines that may have been written to by
4935 * device so that we avoid corrupting memory.
4936 */
4937 dma_sync_single_range_for_cpu(rx_ring->dev,
4938 buffer_info->dma,
4939 buffer_info->page_offset,
4940 igb_rx_bufsz(rx_ring),
4941 DMA_FROM_DEVICE);
4942
4943 /* free resources associated with mapping */
4944 dma_unmap_page_attrs(rx_ring->dev,
4945 buffer_info->dma,
4946 igb_rx_pg_size(rx_ring),
4947 DMA_FROM_DEVICE,
4948 IGB_RX_DMA_ATTR);
4949 __page_frag_cache_drain(buffer_info->page,
4950 buffer_info->pagecnt_bias);
4951
4952 i++;
4953 if (i == rx_ring->count)
4954 i = 0;
4955 }
4956
4957 rx_ring->next_to_alloc = 0;
4958 rx_ring->next_to_clean = 0;
4959 rx_ring->next_to_use = 0;
4960}
4961
4962/**
4963 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
4964 * @adapter: board private structure
4965 **/
4966static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
4967{
4968 int i;
4969
4970 for (i = 0; i < adapter->num_rx_queues; i++)
4971 if (adapter->rx_ring[i])
4972 igb_clean_rx_ring(adapter->rx_ring[i]);
4973}
4974
4975/**
4976 * igb_set_mac - Change the Ethernet Address of the NIC
4977 * @netdev: network interface device structure
4978 * @p: pointer to an address structure
4979 *
4980 * Returns 0 on success, negative on failure
4981 **/
4982static int igb_set_mac(struct net_device *netdev, void *p)
4983{
4984 struct igb_adapter *adapter = netdev_priv(netdev);
4985 struct e1000_hw *hw = &adapter->hw;
4986 struct sockaddr *addr = p;
4987
4988 if (!is_valid_ether_addr(addr->sa_data))
4989 return -EADDRNOTAVAIL;
4990
4991 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4992 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4993
4994 /* set the correct pool for the new PF MAC address in entry 0 */
4995 igb_set_default_mac_filter(adapter);
4996
4997 return 0;
4998}
4999
5000/**
5001 * igb_write_mc_addr_list - write multicast addresses to MTA
5002 * @netdev: network interface device structure
5003 *
5004 * Writes multicast address list to the MTA hash table.
5005 * Returns: -ENOMEM on failure
5006 * 0 on no addresses written
5007 * X on writing X addresses to MTA
5008 **/
5009static int igb_write_mc_addr_list(struct net_device *netdev)
5010{
5011 struct igb_adapter *adapter = netdev_priv(netdev);
5012 struct e1000_hw *hw = &adapter->hw;
5013 struct netdev_hw_addr *ha;
5014 u8 *mta_list;
5015 int i;
5016
5017 if (netdev_mc_empty(netdev)) {
5018 /* nothing to program, so clear mc list */
5019 igb_update_mc_addr_list(hw, NULL, 0);
5020 igb_restore_vf_multicasts(adapter);
5021 return 0;
5022 }
5023
5024 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
5025 if (!mta_list)
5026 return -ENOMEM;
5027
5028 /* The shared function expects a packed array of only addresses. */
5029 i = 0;
5030 netdev_for_each_mc_addr(ha, netdev)
5031 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
5032
5033 igb_update_mc_addr_list(hw, mta_list, i);
5034 kfree(mta_list);
5035
5036 return netdev_mc_count(netdev);
5037}
5038
5039static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
5040{
5041 struct e1000_hw *hw = &adapter->hw;
5042 u32 i, pf_id;
5043
5044 switch (hw->mac.type) {
5045 case e1000_i210:
5046 case e1000_i211:
5047 case e1000_i350:
5048 /* VLAN filtering needed for VLAN prio filter */
5049 if (adapter->netdev->features & NETIF_F_NTUPLE)
5050 break;
5051 fallthrough;
5052 case e1000_82576:
5053 case e1000_82580:
5054 case e1000_i354:
5055 /* VLAN filtering needed for pool filtering */
5056 if (adapter->vfs_allocated_count)
5057 break;
5058 fallthrough;
5059 default:
5060 return 1;
5061 }
5062
5063 /* We are already in VLAN promisc, nothing to do */
5064 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5065 return 0;
5066
5067 if (!adapter->vfs_allocated_count)
5068 goto set_vfta;
5069
5070 /* Add PF to all active pools */
5071 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5072
5073 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5074 u32 vlvf = rd32(E1000_VLVF(i));
5075
5076 vlvf |= BIT(pf_id);
5077 wr32(E1000_VLVF(i), vlvf);
5078 }
5079
5080set_vfta:
5081 /* Set all bits in the VLAN filter table array */
5082 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
5083 hw->mac.ops.write_vfta(hw, i, ~0U);
5084
5085 /* Set flag so we don't redo unnecessary work */
5086 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
5087
5088 return 0;
5089}
5090
5091#define VFTA_BLOCK_SIZE 8
5092static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
5093{
5094 struct e1000_hw *hw = &adapter->hw;
5095 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
5096 u32 vid_start = vfta_offset * 32;
5097 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
5098 u32 i, vid, word, bits, pf_id;
5099
5100 /* guarantee that we don't scrub out management VLAN */
5101 vid = adapter->mng_vlan_id;
5102 if (vid >= vid_start && vid < vid_end)
5103 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5104
5105 if (!adapter->vfs_allocated_count)
5106 goto set_vfta;
5107
5108 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5109
5110 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5111 u32 vlvf = rd32(E1000_VLVF(i));
5112
5113 /* pull VLAN ID from VLVF */
5114 vid = vlvf & VLAN_VID_MASK;
5115
5116 /* only concern ourselves with a certain range */
5117 if (vid < vid_start || vid >= vid_end)
5118 continue;
5119
5120 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
5121 /* record VLAN ID in VFTA */
5122 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5123
5124 /* if PF is part of this then continue */
5125 if (test_bit(vid, adapter->active_vlans))
5126 continue;
5127 }
5128
5129 /* remove PF from the pool */
5130 bits = ~BIT(pf_id);
5131 bits &= rd32(E1000_VLVF(i));
5132 wr32(E1000_VLVF(i), bits);
5133 }
5134
5135set_vfta:
5136 /* extract values from active_vlans and write back to VFTA */
5137 for (i = VFTA_BLOCK_SIZE; i--;) {
5138 vid = (vfta_offset + i) * 32;
5139 word = vid / BITS_PER_LONG;
5140 bits = vid % BITS_PER_LONG;
5141
5142 vfta[i] |= adapter->active_vlans[word] >> bits;
5143
5144 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
5145 }
5146}
5147
5148static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
5149{
5150 u32 i;
5151
5152 /* We are not in VLAN promisc, nothing to do */
5153 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
5154 return;
5155
5156 /* Set flag so we don't redo unnecessary work */
5157 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
5158
5159 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
5160 igb_scrub_vfta(adapter, i);
5161}
5162
5163/**
5164 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
5165 * @netdev: network interface device structure
5166 *
5167 * The set_rx_mode entry point is called whenever the unicast or multicast
5168 * address lists or the network interface flags are updated. This routine is
5169 * responsible for configuring the hardware for proper unicast, multicast,
5170 * promiscuous mode, and all-multi behavior.
5171 **/
5172static void igb_set_rx_mode(struct net_device *netdev)
5173{
5174 struct igb_adapter *adapter = netdev_priv(netdev);
5175 struct e1000_hw *hw = &adapter->hw;
5176 unsigned int vfn = adapter->vfs_allocated_count;
5177 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
5178 int count;
5179
5180 /* Check for Promiscuous and All Multicast modes */
5181 if (netdev->flags & IFF_PROMISC) {
5182 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
5183 vmolr |= E1000_VMOLR_MPME;
5184
5185 /* enable use of UTA filter to force packets to default pool */
5186 if (hw->mac.type == e1000_82576)
5187 vmolr |= E1000_VMOLR_ROPE;
5188 } else {
5189 if (netdev->flags & IFF_ALLMULTI) {
5190 rctl |= E1000_RCTL_MPE;
5191 vmolr |= E1000_VMOLR_MPME;
5192 } else {
5193 /* Write addresses to the MTA, if the attempt fails
5194 * then we should just turn on promiscuous mode so
5195 * that we can at least receive multicast traffic
5196 */
5197 count = igb_write_mc_addr_list(netdev);
5198 if (count < 0) {
5199 rctl |= E1000_RCTL_MPE;
5200 vmolr |= E1000_VMOLR_MPME;
5201 } else if (count) {
5202 vmolr |= E1000_VMOLR_ROMPE;
5203 }
5204 }
5205 }
5206
5207 /* Write addresses to available RAR registers, if there is not
5208 * sufficient space to store all the addresses then enable
5209 * unicast promiscuous mode
5210 */
5211 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
5212 rctl |= E1000_RCTL_UPE;
5213 vmolr |= E1000_VMOLR_ROPE;
5214 }
5215
5216 /* enable VLAN filtering by default */
5217 rctl |= E1000_RCTL_VFE;
5218
5219 /* disable VLAN filtering for modes that require it */
5220 if ((netdev->flags & IFF_PROMISC) ||
5221 (netdev->features & NETIF_F_RXALL)) {
5222 /* if we fail to set all rules then just clear VFE */
5223 if (igb_vlan_promisc_enable(adapter))
5224 rctl &= ~E1000_RCTL_VFE;
5225 } else {
5226 igb_vlan_promisc_disable(adapter);
5227 }
5228
5229 /* update state of unicast, multicast, and VLAN filtering modes */
5230 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
5231 E1000_RCTL_VFE);
5232 wr32(E1000_RCTL, rctl);
5233
5234#if (PAGE_SIZE < 8192)
5235 if (!adapter->vfs_allocated_count) {
5236 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5237 rlpml = IGB_MAX_FRAME_BUILD_SKB;
5238 }
5239#endif
5240 wr32(E1000_RLPML, rlpml);
5241
5242 /* In order to support SR-IOV and eventually VMDq it is necessary to set
5243 * the VMOLR to enable the appropriate modes. Without this workaround
5244 * we will have issues with VLAN tag stripping not being done for frames
5245 * that are only arriving because we are the default pool
5246 */
5247 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
5248 return;
5249
5250 /* set UTA to appropriate mode */
5251 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
5252
5253 vmolr |= rd32(E1000_VMOLR(vfn)) &
5254 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
5255
5256 /* enable Rx jumbo frames, restrict as needed to support build_skb */
5257 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5258#if (PAGE_SIZE < 8192)
5259 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5260 vmolr |= IGB_MAX_FRAME_BUILD_SKB;
5261 else
5262#endif
5263 vmolr |= MAX_JUMBO_FRAME_SIZE;
5264 vmolr |= E1000_VMOLR_LPE;
5265
5266 wr32(E1000_VMOLR(vfn), vmolr);
5267
5268 igb_restore_vf_multicasts(adapter);
5269}
5270
5271static void igb_check_wvbr(struct igb_adapter *adapter)
5272{
5273 struct e1000_hw *hw = &adapter->hw;
5274 u32 wvbr = 0;
5275
5276 switch (hw->mac.type) {
5277 case e1000_82576:
5278 case e1000_i350:
5279 wvbr = rd32(E1000_WVBR);
5280 if (!wvbr)
5281 return;
5282 break;
5283 default:
5284 break;
5285 }
5286
5287 adapter->wvbr |= wvbr;
5288}
5289
5290#define IGB_STAGGERED_QUEUE_OFFSET 8
5291
5292static void igb_spoof_check(struct igb_adapter *adapter)
5293{
5294 int j;
5295
5296 if (!adapter->wvbr)
5297 return;
5298
5299 for (j = 0; j < adapter->vfs_allocated_count; j++) {
5300 if (adapter->wvbr & BIT(j) ||
5301 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
5302 dev_warn(&adapter->pdev->dev,
5303 "Spoof event(s) detected on VF %d\n", j);
5304 adapter->wvbr &=
5305 ~(BIT(j) |
5306 BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
5307 }
5308 }
5309}
5310
5311/* Need to wait a few seconds after link up to get diagnostic information from
5312 * the phy
5313 */
5314static void igb_update_phy_info(struct timer_list *t)
5315{
5316 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5317 igb_get_phy_info(&adapter->hw);
5318}
5319
5320/**
5321 * igb_has_link - check shared code for link and determine up/down
5322 * @adapter: pointer to driver private info
5323 **/
5324bool igb_has_link(struct igb_adapter *adapter)
5325{
5326 struct e1000_hw *hw = &adapter->hw;
5327 bool link_active = false;
5328
5329 /* get_link_status is set on LSC (link status) interrupt or
5330 * rx sequence error interrupt. get_link_status will stay
5331 * false until the e1000_check_for_link establishes link
5332 * for copper adapters ONLY
5333 */
5334 switch (hw->phy.media_type) {
5335 case e1000_media_type_copper:
5336 if (!hw->mac.get_link_status)
5337 return true;
5338 fallthrough;
5339 case e1000_media_type_internal_serdes:
5340 hw->mac.ops.check_for_link(hw);
5341 link_active = !hw->mac.get_link_status;
5342 break;
5343 default:
5344 case e1000_media_type_unknown:
5345 break;
5346 }
5347
5348 if (((hw->mac.type == e1000_i210) ||
5349 (hw->mac.type == e1000_i211)) &&
5350 (hw->phy.id == I210_I_PHY_ID)) {
5351 if (!netif_carrier_ok(adapter->netdev)) {
5352 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5353 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
5354 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
5355 adapter->link_check_timeout = jiffies;
5356 }
5357 }
5358
5359 return link_active;
5360}
5361
5362static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
5363{
5364 bool ret = false;
5365 u32 ctrl_ext, thstat;
5366
5367 /* check for thermal sensor event on i350 copper only */
5368 if (hw->mac.type == e1000_i350) {
5369 thstat = rd32(E1000_THSTAT);
5370 ctrl_ext = rd32(E1000_CTRL_EXT);
5371
5372 if ((hw->phy.media_type == e1000_media_type_copper) &&
5373 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
5374 ret = !!(thstat & event);
5375 }
5376
5377 return ret;
5378}
5379
5380/**
5381 * igb_check_lvmmc - check for malformed packets received
5382 * and indicated in LVMMC register
5383 * @adapter: pointer to adapter
5384 **/
5385static void igb_check_lvmmc(struct igb_adapter *adapter)
5386{
5387 struct e1000_hw *hw = &adapter->hw;
5388 u32 lvmmc;
5389
5390 lvmmc = rd32(E1000_LVMMC);
5391 if (lvmmc) {
5392 if (unlikely(net_ratelimit())) {
5393 netdev_warn(adapter->netdev,
5394 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
5395 lvmmc);
5396 }
5397 }
5398}
5399
5400/**
5401 * igb_watchdog - Timer Call-back
5402 * @t: pointer to timer_list containing our private info pointer
5403 **/
5404static void igb_watchdog(struct timer_list *t)
5405{
5406 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5407 /* Do the rest outside of interrupt context */
5408 schedule_work(&adapter->watchdog_task);
5409}
5410
5411static void igb_watchdog_task(struct work_struct *work)
5412{
5413 struct igb_adapter *adapter = container_of(work,
5414 struct igb_adapter,
5415 watchdog_task);
5416 struct e1000_hw *hw = &adapter->hw;
5417 struct e1000_phy_info *phy = &hw->phy;
5418 struct net_device *netdev = adapter->netdev;
5419 u32 link;
5420 int i;
5421 u32 connsw;
5422 u16 phy_data, retry_count = 20;
5423
5424 link = igb_has_link(adapter);
5425
5426 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
5427 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5428 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5429 else
5430 link = false;
5431 }
5432
5433 /* Force link down if we have fiber to swap to */
5434 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5435 if (hw->phy.media_type == e1000_media_type_copper) {
5436 connsw = rd32(E1000_CONNSW);
5437 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
5438 link = 0;
5439 }
5440 }
5441 if (link) {
5442 /* Perform a reset if the media type changed. */
5443 if (hw->dev_spec._82575.media_changed) {
5444 hw->dev_spec._82575.media_changed = false;
5445 adapter->flags |= IGB_FLAG_MEDIA_RESET;
5446 igb_reset(adapter);
5447 }
5448 /* Cancel scheduled suspend requests. */
5449 pm_runtime_resume(netdev->dev.parent);
5450
5451 if (!netif_carrier_ok(netdev)) {
5452 u32 ctrl;
5453
5454 hw->mac.ops.get_speed_and_duplex(hw,
5455 &adapter->link_speed,
5456 &adapter->link_duplex);
5457
5458 ctrl = rd32(E1000_CTRL);
5459 /* Links status message must follow this format */
5460 netdev_info(netdev,
5461 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5462 netdev->name,
5463 adapter->link_speed,
5464 adapter->link_duplex == FULL_DUPLEX ?
5465 "Full" : "Half",
5466 (ctrl & E1000_CTRL_TFCE) &&
5467 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
5468 (ctrl & E1000_CTRL_RFCE) ? "RX" :
5469 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
5470
5471 /* disable EEE if enabled */
5472 if ((adapter->flags & IGB_FLAG_EEE) &&
5473 (adapter->link_duplex == HALF_DUPLEX)) {
5474 dev_info(&adapter->pdev->dev,
5475 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
5476 adapter->hw.dev_spec._82575.eee_disable = true;
5477 adapter->flags &= ~IGB_FLAG_EEE;
5478 }
5479
5480 /* check if SmartSpeed worked */
5481 igb_check_downshift(hw);
5482 if (phy->speed_downgraded)
5483 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5484
5485 /* check for thermal sensor event */
5486 if (igb_thermal_sensor_event(hw,
5487 E1000_THSTAT_LINK_THROTTLE))
5488 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
5489
5490 /* adjust timeout factor according to speed/duplex */
5491 adapter->tx_timeout_factor = 1;
5492 switch (adapter->link_speed) {
5493 case SPEED_10:
5494 adapter->tx_timeout_factor = 14;
5495 break;
5496 case SPEED_100:
5497 /* maybe add some timeout factor ? */
5498 break;
5499 }
5500
5501 if (adapter->link_speed != SPEED_1000)
5502 goto no_wait;
5503
5504 /* wait for Remote receiver status OK */
5505retry_read_status:
5506 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5507 &phy_data)) {
5508 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5509 retry_count) {
5510 msleep(100);
5511 retry_count--;
5512 goto retry_read_status;
5513 } else if (!retry_count) {
5514 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5515 }
5516 } else {
5517 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5518 }
5519no_wait:
5520 netif_carrier_on(netdev);
5521
5522 igb_ping_all_vfs(adapter);
5523 igb_check_vf_rate_limit(adapter);
5524
5525 /* link state has changed, schedule phy info update */
5526 if (!test_bit(__IGB_DOWN, &adapter->state))
5527 mod_timer(&adapter->phy_info_timer,
5528 round_jiffies(jiffies + 2 * HZ));
5529 }
5530 } else {
5531 if (netif_carrier_ok(netdev)) {
5532 adapter->link_speed = 0;
5533 adapter->link_duplex = 0;
5534
5535 /* check for thermal sensor event */
5536 if (igb_thermal_sensor_event(hw,
5537 E1000_THSTAT_PWR_DOWN)) {
5538 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5539 }
5540
5541 /* Links status message must follow this format */
5542 netdev_info(netdev, "igb: %s NIC Link is Down\n",
5543 netdev->name);
5544 netif_carrier_off(netdev);
5545
5546 igb_ping_all_vfs(adapter);
5547
5548 /* link state has changed, schedule phy info update */
5549 if (!test_bit(__IGB_DOWN, &adapter->state))
5550 mod_timer(&adapter->phy_info_timer,
5551 round_jiffies(jiffies + 2 * HZ));
5552
5553 /* link is down, time to check for alternate media */
5554 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5555 igb_check_swap_media(adapter);
5556 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5557 schedule_work(&adapter->reset_task);
5558 /* return immediately */
5559 return;
5560 }
5561 }
5562 pm_schedule_suspend(netdev->dev.parent,
5563 MSEC_PER_SEC * 5);
5564
5565 /* also check for alternate media here */
5566 } else if (!netif_carrier_ok(netdev) &&
5567 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5568 igb_check_swap_media(adapter);
5569 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5570 schedule_work(&adapter->reset_task);
5571 /* return immediately */
5572 return;
5573 }
5574 }
5575 }
5576
5577 spin_lock(&adapter->stats64_lock);
5578 igb_update_stats(adapter);
5579 spin_unlock(&adapter->stats64_lock);
5580
5581 for (i = 0; i < adapter->num_tx_queues; i++) {
5582 struct igb_ring *tx_ring = adapter->tx_ring[i];
5583 if (!netif_carrier_ok(netdev)) {
5584 /* We've lost link, so the controller stops DMA,
5585 * but we've got queued Tx work that's never going
5586 * to get done, so reset controller to flush Tx.
5587 * (Do the reset outside of interrupt context).
5588 */
5589 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5590 adapter->tx_timeout_count++;
5591 schedule_work(&adapter->reset_task);
5592 /* return immediately since reset is imminent */
5593 return;
5594 }
5595 }
5596
5597 /* Force detection of hung controller every watchdog period */
5598 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5599 }
5600
5601 /* Cause software interrupt to ensure Rx ring is cleaned */
5602 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5603 u32 eics = 0;
5604
5605 for (i = 0; i < adapter->num_q_vectors; i++)
5606 eics |= adapter->q_vector[i]->eims_value;
5607 wr32(E1000_EICS, eics);
5608 } else {
5609 wr32(E1000_ICS, E1000_ICS_RXDMT0);
5610 }
5611
5612 igb_spoof_check(adapter);
5613 igb_ptp_rx_hang(adapter);
5614 igb_ptp_tx_hang(adapter);
5615
5616 /* Check LVMMC register on i350/i354 only */
5617 if ((adapter->hw.mac.type == e1000_i350) ||
5618 (adapter->hw.mac.type == e1000_i354))
5619 igb_check_lvmmc(adapter);
5620
5621 /* Reset the timer */
5622 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5623 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5624 mod_timer(&adapter->watchdog_timer,
5625 round_jiffies(jiffies + HZ));
5626 else
5627 mod_timer(&adapter->watchdog_timer,
5628 round_jiffies(jiffies + 2 * HZ));
5629 }
5630}
5631
5632enum latency_range {
5633 lowest_latency = 0,
5634 low_latency = 1,
5635 bulk_latency = 2,
5636 latency_invalid = 255
5637};
5638
5639/**
5640 * igb_update_ring_itr - update the dynamic ITR value based on packet size
5641 * @q_vector: pointer to q_vector
5642 *
5643 * Stores a new ITR value based on strictly on packet size. This
5644 * algorithm is less sophisticated than that used in igb_update_itr,
5645 * due to the difficulty of synchronizing statistics across multiple
5646 * receive rings. The divisors and thresholds used by this function
5647 * were determined based on theoretical maximum wire speed and testing
5648 * data, in order to minimize response time while increasing bulk
5649 * throughput.
5650 * This functionality is controlled by ethtool's coalescing settings.
5651 * NOTE: This function is called only when operating in a multiqueue
5652 * receive environment.
5653 **/
5654static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5655{
5656 int new_val = q_vector->itr_val;
5657 int avg_wire_size = 0;
5658 struct igb_adapter *adapter = q_vector->adapter;
5659 unsigned int packets;
5660
5661 /* For non-gigabit speeds, just fix the interrupt rate at 4000
5662 * ints/sec - ITR timer value of 120 ticks.
5663 */
5664 if (adapter->link_speed != SPEED_1000) {
5665 new_val = IGB_4K_ITR;
5666 goto set_itr_val;
5667 }
5668
5669 packets = q_vector->rx.total_packets;
5670 if (packets)
5671 avg_wire_size = q_vector->rx.total_bytes / packets;
5672
5673 packets = q_vector->tx.total_packets;
5674 if (packets)
5675 avg_wire_size = max_t(u32, avg_wire_size,
5676 q_vector->tx.total_bytes / packets);
5677
5678 /* if avg_wire_size isn't set no work was done */
5679 if (!avg_wire_size)
5680 goto clear_counts;
5681
5682 /* Add 24 bytes to size to account for CRC, preamble, and gap */
5683 avg_wire_size += 24;
5684
5685 /* Don't starve jumbo frames */
5686 avg_wire_size = min(avg_wire_size, 3000);
5687
5688 /* Give a little boost to mid-size frames */
5689 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5690 new_val = avg_wire_size / 3;
5691 else
5692 new_val = avg_wire_size / 2;
5693
5694 /* conservative mode (itr 3) eliminates the lowest_latency setting */
5695 if (new_val < IGB_20K_ITR &&
5696 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5697 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5698 new_val = IGB_20K_ITR;
5699
5700set_itr_val:
5701 if (new_val != q_vector->itr_val) {
5702 q_vector->itr_val = new_val;
5703 q_vector->set_itr = 1;
5704 }
5705clear_counts:
5706 q_vector->rx.total_bytes = 0;
5707 q_vector->rx.total_packets = 0;
5708 q_vector->tx.total_bytes = 0;
5709 q_vector->tx.total_packets = 0;
5710}
5711
5712/**
5713 * igb_update_itr - update the dynamic ITR value based on statistics
5714 * @q_vector: pointer to q_vector
5715 * @ring_container: ring info to update the itr for
5716 *
5717 * Stores a new ITR value based on packets and byte
5718 * counts during the last interrupt. The advantage of per interrupt
5719 * computation is faster updates and more accurate ITR for the current
5720 * traffic pattern. Constants in this function were computed
5721 * based on theoretical maximum wire speed and thresholds were set based
5722 * on testing data as well as attempting to minimize response time
5723 * while increasing bulk throughput.
5724 * This functionality is controlled by ethtool's coalescing settings.
5725 * NOTE: These calculations are only valid when operating in a single-
5726 * queue environment.
5727 **/
5728static void igb_update_itr(struct igb_q_vector *q_vector,
5729 struct igb_ring_container *ring_container)
5730{
5731 unsigned int packets = ring_container->total_packets;
5732 unsigned int bytes = ring_container->total_bytes;
5733 u8 itrval = ring_container->itr;
5734
5735 /* no packets, exit with status unchanged */
5736 if (packets == 0)
5737 return;
5738
5739 switch (itrval) {
5740 case lowest_latency:
5741 /* handle TSO and jumbo frames */
5742 if (bytes/packets > 8000)
5743 itrval = bulk_latency;
5744 else if ((packets < 5) && (bytes > 512))
5745 itrval = low_latency;
5746 break;
5747 case low_latency: /* 50 usec aka 20000 ints/s */
5748 if (bytes > 10000) {
5749 /* this if handles the TSO accounting */
5750 if (bytes/packets > 8000)
5751 itrval = bulk_latency;
5752 else if ((packets < 10) || ((bytes/packets) > 1200))
5753 itrval = bulk_latency;
5754 else if ((packets > 35))
5755 itrval = lowest_latency;
5756 } else if (bytes/packets > 2000) {
5757 itrval = bulk_latency;
5758 } else if (packets <= 2 && bytes < 512) {
5759 itrval = lowest_latency;
5760 }
5761 break;
5762 case bulk_latency: /* 250 usec aka 4000 ints/s */
5763 if (bytes > 25000) {
5764 if (packets > 35)
5765 itrval = low_latency;
5766 } else if (bytes < 1500) {
5767 itrval = low_latency;
5768 }
5769 break;
5770 }
5771
5772 /* clear work counters since we have the values we need */
5773 ring_container->total_bytes = 0;
5774 ring_container->total_packets = 0;
5775
5776 /* write updated itr to ring container */
5777 ring_container->itr = itrval;
5778}
5779
5780static void igb_set_itr(struct igb_q_vector *q_vector)
5781{
5782 struct igb_adapter *adapter = q_vector->adapter;
5783 u32 new_itr = q_vector->itr_val;
5784 u8 current_itr = 0;
5785
5786 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5787 if (adapter->link_speed != SPEED_1000) {
5788 current_itr = 0;
5789 new_itr = IGB_4K_ITR;
5790 goto set_itr_now;
5791 }
5792
5793 igb_update_itr(q_vector, &q_vector->tx);
5794 igb_update_itr(q_vector, &q_vector->rx);
5795
5796 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5797
5798 /* conservative mode (itr 3) eliminates the lowest_latency setting */
5799 if (current_itr == lowest_latency &&
5800 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5801 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5802 current_itr = low_latency;
5803
5804 switch (current_itr) {
5805 /* counts and packets in update_itr are dependent on these numbers */
5806 case lowest_latency:
5807 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5808 break;
5809 case low_latency:
5810 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5811 break;
5812 case bulk_latency:
5813 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
5814 break;
5815 default:
5816 break;
5817 }
5818
5819set_itr_now:
5820 if (new_itr != q_vector->itr_val) {
5821 /* this attempts to bias the interrupt rate towards Bulk
5822 * by adding intermediate steps when interrupt rate is
5823 * increasing
5824 */
5825 new_itr = new_itr > q_vector->itr_val ?
5826 max((new_itr * q_vector->itr_val) /
5827 (new_itr + (q_vector->itr_val >> 2)),
5828 new_itr) : new_itr;
5829 /* Don't write the value here; it resets the adapter's
5830 * internal timer, and causes us to delay far longer than
5831 * we should between interrupts. Instead, we write the ITR
5832 * value at the beginning of the next interrupt so the timing
5833 * ends up being correct.
5834 */
5835 q_vector->itr_val = new_itr;
5836 q_vector->set_itr = 1;
5837 }
5838}
5839
5840static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5841 struct igb_tx_buffer *first,
5842 u32 vlan_macip_lens, u32 type_tucmd,
5843 u32 mss_l4len_idx)
5844{
5845 struct e1000_adv_tx_context_desc *context_desc;
5846 u16 i = tx_ring->next_to_use;
5847 struct timespec64 ts;
5848
5849 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5850
5851 i++;
5852 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5853
5854 /* set bits to identify this as an advanced context descriptor */
5855 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5856
5857 /* For 82575, context index must be unique per ring. */
5858 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5859 mss_l4len_idx |= tx_ring->reg_idx << 4;
5860
5861 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5862 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
5863 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5864
5865 /* We assume there is always a valid tx time available. Invalid times
5866 * should have been handled by the upper layers.
5867 */
5868 if (tx_ring->launchtime_enable) {
5869 ts = ktime_to_timespec64(first->skb->tstamp);
5870 skb_txtime_consumed(first->skb);
5871 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5872 } else {
5873 context_desc->seqnum_seed = 0;
5874 }
5875}
5876
5877static int igb_tso(struct igb_ring *tx_ring,
5878 struct igb_tx_buffer *first,
5879 u8 *hdr_len)
5880{
5881 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5882 struct sk_buff *skb = first->skb;
5883 union {
5884 struct iphdr *v4;
5885 struct ipv6hdr *v6;
5886 unsigned char *hdr;
5887 } ip;
5888 union {
5889 struct tcphdr *tcp;
5890 struct udphdr *udp;
5891 unsigned char *hdr;
5892 } l4;
5893 u32 paylen, l4_offset;
5894 int err;
5895
5896 if (skb->ip_summed != CHECKSUM_PARTIAL)
5897 return 0;
5898
5899 if (!skb_is_gso(skb))
5900 return 0;
5901
5902 err = skb_cow_head(skb, 0);
5903 if (err < 0)
5904 return err;
5905
5906 ip.hdr = skb_network_header(skb);
5907 l4.hdr = skb_checksum_start(skb);
5908
5909 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5910 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
5911 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP;
5912
5913 /* initialize outer IP header fields */
5914 if (ip.v4->version == 4) {
5915 unsigned char *csum_start = skb_checksum_start(skb);
5916 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
5917
5918 /* IP header will have to cancel out any data that
5919 * is not a part of the outer IP header
5920 */
5921 ip.v4->check = csum_fold(csum_partial(trans_start,
5922 csum_start - trans_start,
5923 0));
5924 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
5925
5926 ip.v4->tot_len = 0;
5927 first->tx_flags |= IGB_TX_FLAGS_TSO |
5928 IGB_TX_FLAGS_CSUM |
5929 IGB_TX_FLAGS_IPV4;
5930 } else {
5931 ip.v6->payload_len = 0;
5932 first->tx_flags |= IGB_TX_FLAGS_TSO |
5933 IGB_TX_FLAGS_CSUM;
5934 }
5935
5936 /* determine offset of inner transport header */
5937 l4_offset = l4.hdr - skb->data;
5938
5939 /* remove payload length from inner checksum */
5940 paylen = skb->len - l4_offset;
5941 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) {
5942 /* compute length of segmentation header */
5943 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
5944 csum_replace_by_diff(&l4.tcp->check,
5945 (__force __wsum)htonl(paylen));
5946 } else {
5947 /* compute length of segmentation header */
5948 *hdr_len = sizeof(*l4.udp) + l4_offset;
5949 csum_replace_by_diff(&l4.udp->check,
5950 (__force __wsum)htonl(paylen));
5951 }
5952
5953 /* update gso size and bytecount with header size */
5954 first->gso_segs = skb_shinfo(skb)->gso_segs;
5955 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5956
5957 /* MSS L4LEN IDX */
5958 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
5959 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
5960
5961 /* VLAN MACLEN IPLEN */
5962 vlan_macip_lens = l4.hdr - ip.hdr;
5963 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
5964 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5965
5966 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
5967 type_tucmd, mss_l4len_idx);
5968
5969 return 1;
5970}
5971
5972static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
5973{
5974 struct sk_buff *skb = first->skb;
5975 u32 vlan_macip_lens = 0;
5976 u32 type_tucmd = 0;
5977
5978 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5979csum_failed:
5980 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) &&
5981 !tx_ring->launchtime_enable)
5982 return;
5983 goto no_csum;
5984 }
5985
5986 switch (skb->csum_offset) {
5987 case offsetof(struct tcphdr, check):
5988 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5989 fallthrough;
5990 case offsetof(struct udphdr, check):
5991 break;
5992 case offsetof(struct sctphdr, checksum):
5993 /* validate that this is actually an SCTP request */
5994 if (skb_csum_is_sctp(skb)) {
5995 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
5996 break;
5997 }
5998 fallthrough;
5999 default:
6000 skb_checksum_help(skb);
6001 goto csum_failed;
6002 }
6003
6004 /* update TX checksum flag */
6005 first->tx_flags |= IGB_TX_FLAGS_CSUM;
6006 vlan_macip_lens = skb_checksum_start_offset(skb) -
6007 skb_network_offset(skb);
6008no_csum:
6009 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
6010 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6011
6012 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
6013}
6014
6015#define IGB_SET_FLAG(_input, _flag, _result) \
6016 ((_flag <= _result) ? \
6017 ((u32)(_input & _flag) * (_result / _flag)) : \
6018 ((u32)(_input & _flag) / (_flag / _result)))
6019
6020static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6021{
6022 /* set type for advanced descriptor with frame checksum insertion */
6023 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
6024 E1000_ADVTXD_DCMD_DEXT |
6025 E1000_ADVTXD_DCMD_IFCS;
6026
6027 /* set HW vlan bit if vlan is present */
6028 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
6029 (E1000_ADVTXD_DCMD_VLE));
6030
6031 /* set segmentation bits for TSO */
6032 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
6033 (E1000_ADVTXD_DCMD_TSE));
6034
6035 /* set timestamp bit if present */
6036 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
6037 (E1000_ADVTXD_MAC_TSTAMP));
6038
6039 /* insert frame checksum */
6040 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
6041
6042 return cmd_type;
6043}
6044
6045static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
6046 union e1000_adv_tx_desc *tx_desc,
6047 u32 tx_flags, unsigned int paylen)
6048{
6049 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
6050
6051 /* 82575 requires a unique index per ring */
6052 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6053 olinfo_status |= tx_ring->reg_idx << 4;
6054
6055 /* insert L4 checksum */
6056 olinfo_status |= IGB_SET_FLAG(tx_flags,
6057 IGB_TX_FLAGS_CSUM,
6058 (E1000_TXD_POPTS_TXSM << 8));
6059
6060 /* insert IPv4 checksum */
6061 olinfo_status |= IGB_SET_FLAG(tx_flags,
6062 IGB_TX_FLAGS_IPV4,
6063 (E1000_TXD_POPTS_IXSM << 8));
6064
6065 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6066}
6067
6068static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6069{
6070 struct net_device *netdev = tx_ring->netdev;
6071
6072 netif_stop_subqueue(netdev, tx_ring->queue_index);
6073
6074 /* Herbert's original patch had:
6075 * smp_mb__after_netif_stop_queue();
6076 * but since that doesn't exist yet, just open code it.
6077 */
6078 smp_mb();
6079
6080 /* We need to check again in a case another CPU has just
6081 * made room available.
6082 */
6083 if (igb_desc_unused(tx_ring) < size)
6084 return -EBUSY;
6085
6086 /* A reprieve! */
6087 netif_wake_subqueue(netdev, tx_ring->queue_index);
6088
6089 u64_stats_update_begin(&tx_ring->tx_syncp2);
6090 tx_ring->tx_stats.restart_queue2++;
6091 u64_stats_update_end(&tx_ring->tx_syncp2);
6092
6093 return 0;
6094}
6095
6096static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6097{
6098 if (igb_desc_unused(tx_ring) >= size)
6099 return 0;
6100 return __igb_maybe_stop_tx(tx_ring, size);
6101}
6102
6103static int igb_tx_map(struct igb_ring *tx_ring,
6104 struct igb_tx_buffer *first,
6105 const u8 hdr_len)
6106{
6107 struct sk_buff *skb = first->skb;
6108 struct igb_tx_buffer *tx_buffer;
6109 union e1000_adv_tx_desc *tx_desc;
6110 skb_frag_t *frag;
6111 dma_addr_t dma;
6112 unsigned int data_len, size;
6113 u32 tx_flags = first->tx_flags;
6114 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
6115 u16 i = tx_ring->next_to_use;
6116
6117 tx_desc = IGB_TX_DESC(tx_ring, i);
6118
6119 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
6120
6121 size = skb_headlen(skb);
6122 data_len = skb->data_len;
6123
6124 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6125
6126 tx_buffer = first;
6127
6128 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6129 if (dma_mapping_error(tx_ring->dev, dma))
6130 goto dma_error;
6131
6132 /* record length, and DMA address */
6133 dma_unmap_len_set(tx_buffer, len, size);
6134 dma_unmap_addr_set(tx_buffer, dma, dma);
6135
6136 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6137
6138 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
6139 tx_desc->read.cmd_type_len =
6140 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
6141
6142 i++;
6143 tx_desc++;
6144 if (i == tx_ring->count) {
6145 tx_desc = IGB_TX_DESC(tx_ring, 0);
6146 i = 0;
6147 }
6148 tx_desc->read.olinfo_status = 0;
6149
6150 dma += IGB_MAX_DATA_PER_TXD;
6151 size -= IGB_MAX_DATA_PER_TXD;
6152
6153 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6154 }
6155
6156 if (likely(!data_len))
6157 break;
6158
6159 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6160
6161 i++;
6162 tx_desc++;
6163 if (i == tx_ring->count) {
6164 tx_desc = IGB_TX_DESC(tx_ring, 0);
6165 i = 0;
6166 }
6167 tx_desc->read.olinfo_status = 0;
6168
6169 size = skb_frag_size(frag);
6170 data_len -= size;
6171
6172 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
6173 size, DMA_TO_DEVICE);
6174
6175 tx_buffer = &tx_ring->tx_buffer_info[i];
6176 }
6177
6178 /* write last descriptor with RS and EOP bits */
6179 cmd_type |= size | IGB_TXD_DCMD;
6180 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6181
6182 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6183
6184 /* set the timestamp */
6185 first->time_stamp = jiffies;
6186
6187 skb_tx_timestamp(skb);
6188
6189 /* Force memory writes to complete before letting h/w know there
6190 * are new descriptors to fetch. (Only applicable for weak-ordered
6191 * memory model archs, such as IA-64).
6192 *
6193 * We also need this memory barrier to make certain all of the
6194 * status bits have been updated before next_to_watch is written.
6195 */
6196 dma_wmb();
6197
6198 /* set next_to_watch value indicating a packet is present */
6199 first->next_to_watch = tx_desc;
6200
6201 i++;
6202 if (i == tx_ring->count)
6203 i = 0;
6204
6205 tx_ring->next_to_use = i;
6206
6207 /* Make sure there is space in the ring for the next send. */
6208 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6209
6210 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
6211 writel(i, tx_ring->tail);
6212 }
6213 return 0;
6214
6215dma_error:
6216 dev_err(tx_ring->dev, "TX DMA map failed\n");
6217 tx_buffer = &tx_ring->tx_buffer_info[i];
6218
6219 /* clear dma mappings for failed tx_buffer_info map */
6220 while (tx_buffer != first) {
6221 if (dma_unmap_len(tx_buffer, len))
6222 dma_unmap_page(tx_ring->dev,
6223 dma_unmap_addr(tx_buffer, dma),
6224 dma_unmap_len(tx_buffer, len),
6225 DMA_TO_DEVICE);
6226 dma_unmap_len_set(tx_buffer, len, 0);
6227
6228 if (i-- == 0)
6229 i += tx_ring->count;
6230 tx_buffer = &tx_ring->tx_buffer_info[i];
6231 }
6232
6233 if (dma_unmap_len(tx_buffer, len))
6234 dma_unmap_single(tx_ring->dev,
6235 dma_unmap_addr(tx_buffer, dma),
6236 dma_unmap_len(tx_buffer, len),
6237 DMA_TO_DEVICE);
6238 dma_unmap_len_set(tx_buffer, len, 0);
6239
6240 dev_kfree_skb_any(tx_buffer->skb);
6241 tx_buffer->skb = NULL;
6242
6243 tx_ring->next_to_use = i;
6244
6245 return -1;
6246}
6247
6248int igb_xmit_xdp_ring(struct igb_adapter *adapter,
6249 struct igb_ring *tx_ring,
6250 struct xdp_frame *xdpf)
6251{
6252 union e1000_adv_tx_desc *tx_desc;
6253 u32 len, cmd_type, olinfo_status;
6254 struct igb_tx_buffer *tx_buffer;
6255 dma_addr_t dma;
6256 u16 i;
6257
6258 len = xdpf->len;
6259
6260 if (unlikely(!igb_desc_unused(tx_ring)))
6261 return IGB_XDP_CONSUMED;
6262
6263 dma = dma_map_single(tx_ring->dev, xdpf->data, len, DMA_TO_DEVICE);
6264 if (dma_mapping_error(tx_ring->dev, dma))
6265 return IGB_XDP_CONSUMED;
6266
6267 /* record the location of the first descriptor for this packet */
6268 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6269 tx_buffer->bytecount = len;
6270 tx_buffer->gso_segs = 1;
6271 tx_buffer->protocol = 0;
6272
6273 i = tx_ring->next_to_use;
6274 tx_desc = IGB_TX_DESC(tx_ring, i);
6275
6276 dma_unmap_len_set(tx_buffer, len, len);
6277 dma_unmap_addr_set(tx_buffer, dma, dma);
6278 tx_buffer->type = IGB_TYPE_XDP;
6279 tx_buffer->xdpf = xdpf;
6280
6281 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6282
6283 /* put descriptor type bits */
6284 cmd_type = E1000_ADVTXD_DTYP_DATA |
6285 E1000_ADVTXD_DCMD_DEXT |
6286 E1000_ADVTXD_DCMD_IFCS;
6287 cmd_type |= len | IGB_TXD_DCMD;
6288 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6289
6290 olinfo_status = len << E1000_ADVTXD_PAYLEN_SHIFT;
6291 /* 82575 requires a unique index per ring */
6292 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6293 olinfo_status |= tx_ring->reg_idx << 4;
6294
6295 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6296
6297 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer->bytecount);
6298
6299 /* set the timestamp */
6300 tx_buffer->time_stamp = jiffies;
6301
6302 /* Avoid any potential race with xdp_xmit and cleanup */
6303 smp_wmb();
6304
6305 /* set next_to_watch value indicating a packet is present */
6306 i++;
6307 if (i == tx_ring->count)
6308 i = 0;
6309
6310 tx_buffer->next_to_watch = tx_desc;
6311 tx_ring->next_to_use = i;
6312
6313 /* Make sure there is space in the ring for the next send. */
6314 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6315
6316 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more())
6317 writel(i, tx_ring->tail);
6318
6319 return IGB_XDP_TX;
6320}
6321
6322netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
6323 struct igb_ring *tx_ring)
6324{
6325 struct igb_tx_buffer *first;
6326 int tso;
6327 u32 tx_flags = 0;
6328 unsigned short f;
6329 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6330 __be16 protocol = vlan_get_protocol(skb);
6331 u8 hdr_len = 0;
6332
6333 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
6334 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
6335 * + 2 desc gap to keep tail from touching head,
6336 * + 1 desc for context descriptor,
6337 * otherwise try next time
6338 */
6339 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6340 count += TXD_USE_COUNT(skb_frag_size(
6341 &skb_shinfo(skb)->frags[f]));
6342
6343 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
6344 /* this is a hard error */
6345 return NETDEV_TX_BUSY;
6346 }
6347
6348 /* record the location of the first descriptor for this packet */
6349 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6350 first->type = IGB_TYPE_SKB;
6351 first->skb = skb;
6352 first->bytecount = skb->len;
6353 first->gso_segs = 1;
6354
6355 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6356 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6357
6358 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
6359 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
6360 &adapter->state)) {
6361 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6362 tx_flags |= IGB_TX_FLAGS_TSTAMP;
6363
6364 adapter->ptp_tx_skb = skb_get(skb);
6365 adapter->ptp_tx_start = jiffies;
6366 if (adapter->hw.mac.type == e1000_82576)
6367 schedule_work(&adapter->ptp_tx_work);
6368 } else {
6369 adapter->tx_hwtstamp_skipped++;
6370 }
6371 }
6372
6373 if (skb_vlan_tag_present(skb)) {
6374 tx_flags |= IGB_TX_FLAGS_VLAN;
6375 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
6376 }
6377
6378 /* record initial flags and protocol */
6379 first->tx_flags = tx_flags;
6380 first->protocol = protocol;
6381
6382 tso = igb_tso(tx_ring, first, &hdr_len);
6383 if (tso < 0)
6384 goto out_drop;
6385 else if (!tso)
6386 igb_tx_csum(tx_ring, first);
6387
6388 if (igb_tx_map(tx_ring, first, hdr_len))
6389 goto cleanup_tx_tstamp;
6390
6391 return NETDEV_TX_OK;
6392
6393out_drop:
6394 dev_kfree_skb_any(first->skb);
6395 first->skb = NULL;
6396cleanup_tx_tstamp:
6397 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
6398 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6399
6400 dev_kfree_skb_any(adapter->ptp_tx_skb);
6401 adapter->ptp_tx_skb = NULL;
6402 if (adapter->hw.mac.type == e1000_82576)
6403 cancel_work_sync(&adapter->ptp_tx_work);
6404 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
6405 }
6406
6407 return NETDEV_TX_OK;
6408}
6409
6410static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
6411 struct sk_buff *skb)
6412{
6413 unsigned int r_idx = skb->queue_mapping;
6414
6415 if (r_idx >= adapter->num_tx_queues)
6416 r_idx = r_idx % adapter->num_tx_queues;
6417
6418 return adapter->tx_ring[r_idx];
6419}
6420
6421static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
6422 struct net_device *netdev)
6423{
6424 struct igb_adapter *adapter = netdev_priv(netdev);
6425
6426 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
6427 * in order to meet this minimum size requirement.
6428 */
6429 if (skb_put_padto(skb, 17))
6430 return NETDEV_TX_OK;
6431
6432 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
6433}
6434
6435/**
6436 * igb_tx_timeout - Respond to a Tx Hang
6437 * @netdev: network interface device structure
6438 * @txqueue: number of the Tx queue that hung (unused)
6439 **/
6440static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6441{
6442 struct igb_adapter *adapter = netdev_priv(netdev);
6443 struct e1000_hw *hw = &adapter->hw;
6444
6445 /* Do the reset outside of interrupt context */
6446 adapter->tx_timeout_count++;
6447
6448 if (hw->mac.type >= e1000_82580)
6449 hw->dev_spec._82575.global_device_reset = true;
6450
6451 schedule_work(&adapter->reset_task);
6452 wr32(E1000_EICS,
6453 (adapter->eims_enable_mask & ~adapter->eims_other));
6454}
6455
6456static void igb_reset_task(struct work_struct *work)
6457{
6458 struct igb_adapter *adapter;
6459 adapter = container_of(work, struct igb_adapter, reset_task);
6460
6461 rtnl_lock();
6462 /* If we're already down or resetting, just bail */
6463 if (test_bit(__IGB_DOWN, &adapter->state) ||
6464 test_bit(__IGB_RESETTING, &adapter->state)) {
6465 rtnl_unlock();
6466 return;
6467 }
6468
6469 igb_dump(adapter);
6470 netdev_err(adapter->netdev, "Reset adapter\n");
6471 igb_reinit_locked(adapter);
6472 rtnl_unlock();
6473}
6474
6475/**
6476 * igb_get_stats64 - Get System Network Statistics
6477 * @netdev: network interface device structure
6478 * @stats: rtnl_link_stats64 pointer
6479 **/
6480static void igb_get_stats64(struct net_device *netdev,
6481 struct rtnl_link_stats64 *stats)
6482{
6483 struct igb_adapter *adapter = netdev_priv(netdev);
6484
6485 spin_lock(&adapter->stats64_lock);
6486 igb_update_stats(adapter);
6487 memcpy(stats, &adapter->stats64, sizeof(*stats));
6488 spin_unlock(&adapter->stats64_lock);
6489}
6490
6491/**
6492 * igb_change_mtu - Change the Maximum Transfer Unit
6493 * @netdev: network interface device structure
6494 * @new_mtu: new value for maximum frame size
6495 *
6496 * Returns 0 on success, negative on failure
6497 **/
6498static int igb_change_mtu(struct net_device *netdev, int new_mtu)
6499{
6500 struct igb_adapter *adapter = netdev_priv(netdev);
6501 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD;
6502
6503 if (adapter->xdp_prog) {
6504 int i;
6505
6506 for (i = 0; i < adapter->num_rx_queues; i++) {
6507 struct igb_ring *ring = adapter->rx_ring[i];
6508
6509 if (max_frame > igb_rx_bufsz(ring)) {
6510 netdev_warn(adapter->netdev,
6511 "Requested MTU size is not supported with XDP. Max frame size is %d\n",
6512 max_frame);
6513 return -EINVAL;
6514 }
6515 }
6516 }
6517
6518 /* adjust max frame to be at least the size of a standard frame */
6519 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
6520 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
6521
6522 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
6523 usleep_range(1000, 2000);
6524
6525 /* igb_down has a dependency on max_frame_size */
6526 adapter->max_frame_size = max_frame;
6527
6528 if (netif_running(netdev))
6529 igb_down(adapter);
6530
6531 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6532 netdev->mtu, new_mtu);
6533 netdev->mtu = new_mtu;
6534
6535 if (netif_running(netdev))
6536 igb_up(adapter);
6537 else
6538 igb_reset(adapter);
6539
6540 clear_bit(__IGB_RESETTING, &adapter->state);
6541
6542 return 0;
6543}
6544
6545/**
6546 * igb_update_stats - Update the board statistics counters
6547 * @adapter: board private structure
6548 **/
6549void igb_update_stats(struct igb_adapter *adapter)
6550{
6551 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
6552 struct e1000_hw *hw = &adapter->hw;
6553 struct pci_dev *pdev = adapter->pdev;
6554 u32 reg, mpc;
6555 int i;
6556 u64 bytes, packets;
6557 unsigned int start;
6558 u64 _bytes, _packets;
6559
6560 /* Prevent stats update while adapter is being reset, or if the pci
6561 * connection is down.
6562 */
6563 if (adapter->link_speed == 0)
6564 return;
6565 if (pci_channel_offline(pdev))
6566 return;
6567
6568 bytes = 0;
6569 packets = 0;
6570
6571 rcu_read_lock();
6572 for (i = 0; i < adapter->num_rx_queues; i++) {
6573 struct igb_ring *ring = adapter->rx_ring[i];
6574 u32 rqdpc = rd32(E1000_RQDPC(i));
6575 if (hw->mac.type >= e1000_i210)
6576 wr32(E1000_RQDPC(i), 0);
6577
6578 if (rqdpc) {
6579 ring->rx_stats.drops += rqdpc;
6580 net_stats->rx_fifo_errors += rqdpc;
6581 }
6582
6583 do {
6584 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
6585 _bytes = ring->rx_stats.bytes;
6586 _packets = ring->rx_stats.packets;
6587 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
6588 bytes += _bytes;
6589 packets += _packets;
6590 }
6591
6592 net_stats->rx_bytes = bytes;
6593 net_stats->rx_packets = packets;
6594
6595 bytes = 0;
6596 packets = 0;
6597 for (i = 0; i < adapter->num_tx_queues; i++) {
6598 struct igb_ring *ring = adapter->tx_ring[i];
6599 do {
6600 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
6601 _bytes = ring->tx_stats.bytes;
6602 _packets = ring->tx_stats.packets;
6603 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
6604 bytes += _bytes;
6605 packets += _packets;
6606 }
6607 net_stats->tx_bytes = bytes;
6608 net_stats->tx_packets = packets;
6609 rcu_read_unlock();
6610
6611 /* read stats registers */
6612 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6613 adapter->stats.gprc += rd32(E1000_GPRC);
6614 adapter->stats.gorc += rd32(E1000_GORCL);
6615 rd32(E1000_GORCH); /* clear GORCL */
6616 adapter->stats.bprc += rd32(E1000_BPRC);
6617 adapter->stats.mprc += rd32(E1000_MPRC);
6618 adapter->stats.roc += rd32(E1000_ROC);
6619
6620 adapter->stats.prc64 += rd32(E1000_PRC64);
6621 adapter->stats.prc127 += rd32(E1000_PRC127);
6622 adapter->stats.prc255 += rd32(E1000_PRC255);
6623 adapter->stats.prc511 += rd32(E1000_PRC511);
6624 adapter->stats.prc1023 += rd32(E1000_PRC1023);
6625 adapter->stats.prc1522 += rd32(E1000_PRC1522);
6626 adapter->stats.symerrs += rd32(E1000_SYMERRS);
6627 adapter->stats.sec += rd32(E1000_SEC);
6628
6629 mpc = rd32(E1000_MPC);
6630 adapter->stats.mpc += mpc;
6631 net_stats->rx_fifo_errors += mpc;
6632 adapter->stats.scc += rd32(E1000_SCC);
6633 adapter->stats.ecol += rd32(E1000_ECOL);
6634 adapter->stats.mcc += rd32(E1000_MCC);
6635 adapter->stats.latecol += rd32(E1000_LATECOL);
6636 adapter->stats.dc += rd32(E1000_DC);
6637 adapter->stats.rlec += rd32(E1000_RLEC);
6638 adapter->stats.xonrxc += rd32(E1000_XONRXC);
6639 adapter->stats.xontxc += rd32(E1000_XONTXC);
6640 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6641 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6642 adapter->stats.fcruc += rd32(E1000_FCRUC);
6643 adapter->stats.gptc += rd32(E1000_GPTC);
6644 adapter->stats.gotc += rd32(E1000_GOTCL);
6645 rd32(E1000_GOTCH); /* clear GOTCL */
6646 adapter->stats.rnbc += rd32(E1000_RNBC);
6647 adapter->stats.ruc += rd32(E1000_RUC);
6648 adapter->stats.rfc += rd32(E1000_RFC);
6649 adapter->stats.rjc += rd32(E1000_RJC);
6650 adapter->stats.tor += rd32(E1000_TORH);
6651 adapter->stats.tot += rd32(E1000_TOTH);
6652 adapter->stats.tpr += rd32(E1000_TPR);
6653
6654 adapter->stats.ptc64 += rd32(E1000_PTC64);
6655 adapter->stats.ptc127 += rd32(E1000_PTC127);
6656 adapter->stats.ptc255 += rd32(E1000_PTC255);
6657 adapter->stats.ptc511 += rd32(E1000_PTC511);
6658 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6659 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6660
6661 adapter->stats.mptc += rd32(E1000_MPTC);
6662 adapter->stats.bptc += rd32(E1000_BPTC);
6663
6664 adapter->stats.tpt += rd32(E1000_TPT);
6665 adapter->stats.colc += rd32(E1000_COLC);
6666
6667 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6668 /* read internal phy specific stats */
6669 reg = rd32(E1000_CTRL_EXT);
6670 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6671 adapter->stats.rxerrc += rd32(E1000_RXERRC);
6672
6673 /* this stat has invalid values on i210/i211 */
6674 if ((hw->mac.type != e1000_i210) &&
6675 (hw->mac.type != e1000_i211))
6676 adapter->stats.tncrs += rd32(E1000_TNCRS);
6677 }
6678
6679 adapter->stats.tsctc += rd32(E1000_TSCTC);
6680 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6681
6682 adapter->stats.iac += rd32(E1000_IAC);
6683 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6684 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6685 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6686 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6687 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6688 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6689 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6690 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6691
6692 /* Fill out the OS statistics structure */
6693 net_stats->multicast = adapter->stats.mprc;
6694 net_stats->collisions = adapter->stats.colc;
6695
6696 /* Rx Errors */
6697
6698 /* RLEC on some newer hardware can be incorrect so build
6699 * our own version based on RUC and ROC
6700 */
6701 net_stats->rx_errors = adapter->stats.rxerrc +
6702 adapter->stats.crcerrs + adapter->stats.algnerrc +
6703 adapter->stats.ruc + adapter->stats.roc +
6704 adapter->stats.cexterr;
6705 net_stats->rx_length_errors = adapter->stats.ruc +
6706 adapter->stats.roc;
6707 net_stats->rx_crc_errors = adapter->stats.crcerrs;
6708 net_stats->rx_frame_errors = adapter->stats.algnerrc;
6709 net_stats->rx_missed_errors = adapter->stats.mpc;
6710
6711 /* Tx Errors */
6712 net_stats->tx_errors = adapter->stats.ecol +
6713 adapter->stats.latecol;
6714 net_stats->tx_aborted_errors = adapter->stats.ecol;
6715 net_stats->tx_window_errors = adapter->stats.latecol;
6716 net_stats->tx_carrier_errors = adapter->stats.tncrs;
6717
6718 /* Tx Dropped needs to be maintained elsewhere */
6719
6720 /* Management Stats */
6721 adapter->stats.mgptc += rd32(E1000_MGTPTC);
6722 adapter->stats.mgprc += rd32(E1000_MGTPRC);
6723 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6724
6725 /* OS2BMC Stats */
6726 reg = rd32(E1000_MANC);
6727 if (reg & E1000_MANC_EN_BMC2OS) {
6728 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6729 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6730 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6731 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6732 }
6733}
6734
6735static void igb_tsync_interrupt(struct igb_adapter *adapter)
6736{
6737 struct e1000_hw *hw = &adapter->hw;
6738 struct ptp_clock_event event;
6739 struct timespec64 ts;
6740 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
6741
6742 if (tsicr & TSINTR_SYS_WRAP) {
6743 event.type = PTP_CLOCK_PPS;
6744 if (adapter->ptp_caps.pps)
6745 ptp_clock_event(adapter->ptp_clock, &event);
6746 ack |= TSINTR_SYS_WRAP;
6747 }
6748
6749 if (tsicr & E1000_TSICR_TXTS) {
6750 /* retrieve hardware timestamp */
6751 schedule_work(&adapter->ptp_tx_work);
6752 ack |= E1000_TSICR_TXTS;
6753 }
6754
6755 if (tsicr & TSINTR_TT0) {
6756 spin_lock(&adapter->tmreg_lock);
6757 ts = timespec64_add(adapter->perout[0].start,
6758 adapter->perout[0].period);
6759 /* u32 conversion of tv_sec is safe until y2106 */
6760 wr32(E1000_TRGTTIML0, ts.tv_nsec);
6761 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
6762 tsauxc = rd32(E1000_TSAUXC);
6763 tsauxc |= TSAUXC_EN_TT0;
6764 wr32(E1000_TSAUXC, tsauxc);
6765 adapter->perout[0].start = ts;
6766 spin_unlock(&adapter->tmreg_lock);
6767 ack |= TSINTR_TT0;
6768 }
6769
6770 if (tsicr & TSINTR_TT1) {
6771 spin_lock(&adapter->tmreg_lock);
6772 ts = timespec64_add(adapter->perout[1].start,
6773 adapter->perout[1].period);
6774 wr32(E1000_TRGTTIML1, ts.tv_nsec);
6775 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
6776 tsauxc = rd32(E1000_TSAUXC);
6777 tsauxc |= TSAUXC_EN_TT1;
6778 wr32(E1000_TSAUXC, tsauxc);
6779 adapter->perout[1].start = ts;
6780 spin_unlock(&adapter->tmreg_lock);
6781 ack |= TSINTR_TT1;
6782 }
6783
6784 if (tsicr & TSINTR_AUTT0) {
6785 nsec = rd32(E1000_AUXSTMPL0);
6786 sec = rd32(E1000_AUXSTMPH0);
6787 event.type = PTP_CLOCK_EXTTS;
6788 event.index = 0;
6789 event.timestamp = sec * 1000000000ULL + nsec;
6790 ptp_clock_event(adapter->ptp_clock, &event);
6791 ack |= TSINTR_AUTT0;
6792 }
6793
6794 if (tsicr & TSINTR_AUTT1) {
6795 nsec = rd32(E1000_AUXSTMPL1);
6796 sec = rd32(E1000_AUXSTMPH1);
6797 event.type = PTP_CLOCK_EXTTS;
6798 event.index = 1;
6799 event.timestamp = sec * 1000000000ULL + nsec;
6800 ptp_clock_event(adapter->ptp_clock, &event);
6801 ack |= TSINTR_AUTT1;
6802 }
6803
6804 /* acknowledge the interrupts */
6805 wr32(E1000_TSICR, ack);
6806}
6807
6808static irqreturn_t igb_msix_other(int irq, void *data)
6809{
6810 struct igb_adapter *adapter = data;
6811 struct e1000_hw *hw = &adapter->hw;
6812 u32 icr = rd32(E1000_ICR);
6813 /* reading ICR causes bit 31 of EICR to be cleared */
6814
6815 if (icr & E1000_ICR_DRSTA)
6816 schedule_work(&adapter->reset_task);
6817
6818 if (icr & E1000_ICR_DOUTSYNC) {
6819 /* HW is reporting DMA is out of sync */
6820 adapter->stats.doosync++;
6821 /* The DMA Out of Sync is also indication of a spoof event
6822 * in IOV mode. Check the Wrong VM Behavior register to
6823 * see if it is really a spoof event.
6824 */
6825 igb_check_wvbr(adapter);
6826 }
6827
6828 /* Check for a mailbox event */
6829 if (icr & E1000_ICR_VMMB)
6830 igb_msg_task(adapter);
6831
6832 if (icr & E1000_ICR_LSC) {
6833 hw->mac.get_link_status = 1;
6834 /* guard against interrupt when we're going down */
6835 if (!test_bit(__IGB_DOWN, &adapter->state))
6836 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6837 }
6838
6839 if (icr & E1000_ICR_TS)
6840 igb_tsync_interrupt(adapter);
6841
6842 wr32(E1000_EIMS, adapter->eims_other);
6843
6844 return IRQ_HANDLED;
6845}
6846
6847static void igb_write_itr(struct igb_q_vector *q_vector)
6848{
6849 struct igb_adapter *adapter = q_vector->adapter;
6850 u32 itr_val = q_vector->itr_val & 0x7FFC;
6851
6852 if (!q_vector->set_itr)
6853 return;
6854
6855 if (!itr_val)
6856 itr_val = 0x4;
6857
6858 if (adapter->hw.mac.type == e1000_82575)
6859 itr_val |= itr_val << 16;
6860 else
6861 itr_val |= E1000_EITR_CNT_IGNR;
6862
6863 writel(itr_val, q_vector->itr_register);
6864 q_vector->set_itr = 0;
6865}
6866
6867static irqreturn_t igb_msix_ring(int irq, void *data)
6868{
6869 struct igb_q_vector *q_vector = data;
6870
6871 /* Write the ITR value calculated from the previous interrupt. */
6872 igb_write_itr(q_vector);
6873
6874 napi_schedule(&q_vector->napi);
6875
6876 return IRQ_HANDLED;
6877}
6878
6879#ifdef CONFIG_IGB_DCA
6880static void igb_update_tx_dca(struct igb_adapter *adapter,
6881 struct igb_ring *tx_ring,
6882 int cpu)
6883{
6884 struct e1000_hw *hw = &adapter->hw;
6885 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
6886
6887 if (hw->mac.type != e1000_82575)
6888 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
6889
6890 /* We can enable relaxed ordering for reads, but not writes when
6891 * DCA is enabled. This is due to a known issue in some chipsets
6892 * which will cause the DCA tag to be cleared.
6893 */
6894 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
6895 E1000_DCA_TXCTRL_DATA_RRO_EN |
6896 E1000_DCA_TXCTRL_DESC_DCA_EN;
6897
6898 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
6899}
6900
6901static void igb_update_rx_dca(struct igb_adapter *adapter,
6902 struct igb_ring *rx_ring,
6903 int cpu)
6904{
6905 struct e1000_hw *hw = &adapter->hw;
6906 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
6907
6908 if (hw->mac.type != e1000_82575)
6909 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
6910
6911 /* We can enable relaxed ordering for reads, but not writes when
6912 * DCA is enabled. This is due to a known issue in some chipsets
6913 * which will cause the DCA tag to be cleared.
6914 */
6915 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
6916 E1000_DCA_RXCTRL_DESC_DCA_EN;
6917
6918 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
6919}
6920
6921static void igb_update_dca(struct igb_q_vector *q_vector)
6922{
6923 struct igb_adapter *adapter = q_vector->adapter;
6924 int cpu = get_cpu();
6925
6926 if (q_vector->cpu == cpu)
6927 goto out_no_update;
6928
6929 if (q_vector->tx.ring)
6930 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
6931
6932 if (q_vector->rx.ring)
6933 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
6934
6935 q_vector->cpu = cpu;
6936out_no_update:
6937 put_cpu();
6938}
6939
6940static void igb_setup_dca(struct igb_adapter *adapter)
6941{
6942 struct e1000_hw *hw = &adapter->hw;
6943 int i;
6944
6945 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
6946 return;
6947
6948 /* Always use CB2 mode, difference is masked in the CB driver. */
6949 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
6950
6951 for (i = 0; i < adapter->num_q_vectors; i++) {
6952 adapter->q_vector[i]->cpu = -1;
6953 igb_update_dca(adapter->q_vector[i]);
6954 }
6955}
6956
6957static int __igb_notify_dca(struct device *dev, void *data)
6958{
6959 struct net_device *netdev = dev_get_drvdata(dev);
6960 struct igb_adapter *adapter = netdev_priv(netdev);
6961 struct pci_dev *pdev = adapter->pdev;
6962 struct e1000_hw *hw = &adapter->hw;
6963 unsigned long event = *(unsigned long *)data;
6964
6965 switch (event) {
6966 case DCA_PROVIDER_ADD:
6967 /* if already enabled, don't do it again */
6968 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
6969 break;
6970 if (dca_add_requester(dev) == 0) {
6971 adapter->flags |= IGB_FLAG_DCA_ENABLED;
6972 dev_info(&pdev->dev, "DCA enabled\n");
6973 igb_setup_dca(adapter);
6974 break;
6975 }
6976 fallthrough; /* since DCA is disabled. */
6977 case DCA_PROVIDER_REMOVE:
6978 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
6979 /* without this a class_device is left
6980 * hanging around in the sysfs model
6981 */
6982 dca_remove_requester(dev);
6983 dev_info(&pdev->dev, "DCA disabled\n");
6984 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
6985 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
6986 }
6987 break;
6988 }
6989
6990 return 0;
6991}
6992
6993static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
6994 void *p)
6995{
6996 int ret_val;
6997
6998 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
6999 __igb_notify_dca);
7000
7001 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7002}
7003#endif /* CONFIG_IGB_DCA */
7004
7005#ifdef CONFIG_PCI_IOV
7006static int igb_vf_configure(struct igb_adapter *adapter, int vf)
7007{
7008 unsigned char mac_addr[ETH_ALEN];
7009
7010 eth_zero_addr(mac_addr);
7011 igb_set_vf_mac(adapter, vf, mac_addr);
7012
7013 /* By default spoof check is enabled for all VFs */
7014 adapter->vf_data[vf].spoofchk_enabled = true;
7015
7016 /* By default VFs are not trusted */
7017 adapter->vf_data[vf].trusted = false;
7018
7019 return 0;
7020}
7021
7022#endif
7023static void igb_ping_all_vfs(struct igb_adapter *adapter)
7024{
7025 struct e1000_hw *hw = &adapter->hw;
7026 u32 ping;
7027 int i;
7028
7029 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
7030 ping = E1000_PF_CONTROL_MSG;
7031 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
7032 ping |= E1000_VT_MSGTYPE_CTS;
7033 igb_write_mbx(hw, &ping, 1, i);
7034 }
7035}
7036
7037static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7038{
7039 struct e1000_hw *hw = &adapter->hw;
7040 u32 vmolr = rd32(E1000_VMOLR(vf));
7041 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7042
7043 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7044 IGB_VF_FLAG_MULTI_PROMISC);
7045 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7046
7047 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
7048 vmolr |= E1000_VMOLR_MPME;
7049 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7050 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
7051 } else {
7052 /* if we have hashes and we are clearing a multicast promisc
7053 * flag we need to write the hashes to the MTA as this step
7054 * was previously skipped
7055 */
7056 if (vf_data->num_vf_mc_hashes > 30) {
7057 vmolr |= E1000_VMOLR_MPME;
7058 } else if (vf_data->num_vf_mc_hashes) {
7059 int j;
7060
7061 vmolr |= E1000_VMOLR_ROMPE;
7062 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7063 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7064 }
7065 }
7066
7067 wr32(E1000_VMOLR(vf), vmolr);
7068
7069 /* there are flags left unprocessed, likely not supported */
7070 if (*msgbuf & E1000_VT_MSGINFO_MASK)
7071 return -EINVAL;
7072
7073 return 0;
7074}
7075
7076static int igb_set_vf_multicasts(struct igb_adapter *adapter,
7077 u32 *msgbuf, u32 vf)
7078{
7079 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7080 u16 *hash_list = (u16 *)&msgbuf[1];
7081 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7082 int i;
7083
7084 /* salt away the number of multicast addresses assigned
7085 * to this VF for later use to restore when the PF multi cast
7086 * list changes
7087 */
7088 vf_data->num_vf_mc_hashes = n;
7089
7090 /* only up to 30 hash values supported */
7091 if (n > 30)
7092 n = 30;
7093
7094 /* store the hashes for later use */
7095 for (i = 0; i < n; i++)
7096 vf_data->vf_mc_hashes[i] = hash_list[i];
7097
7098 /* Flush and reset the mta with the new values */
7099 igb_set_rx_mode(adapter->netdev);
7100
7101 return 0;
7102}
7103
7104static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
7105{
7106 struct e1000_hw *hw = &adapter->hw;
7107 struct vf_data_storage *vf_data;
7108 int i, j;
7109
7110 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7111 u32 vmolr = rd32(E1000_VMOLR(i));
7112
7113 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7114
7115 vf_data = &adapter->vf_data[i];
7116
7117 if ((vf_data->num_vf_mc_hashes > 30) ||
7118 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
7119 vmolr |= E1000_VMOLR_MPME;
7120 } else if (vf_data->num_vf_mc_hashes) {
7121 vmolr |= E1000_VMOLR_ROMPE;
7122 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7123 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7124 }
7125 wr32(E1000_VMOLR(i), vmolr);
7126 }
7127}
7128
7129static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
7130{
7131 struct e1000_hw *hw = &adapter->hw;
7132 u32 pool_mask, vlvf_mask, i;
7133
7134 /* create mask for VF and other pools */
7135 pool_mask = E1000_VLVF_POOLSEL_MASK;
7136 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
7137
7138 /* drop PF from pool bits */
7139 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
7140 adapter->vfs_allocated_count);
7141
7142 /* Find the vlan filter for this id */
7143 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
7144 u32 vlvf = rd32(E1000_VLVF(i));
7145 u32 vfta_mask, vid, vfta;
7146
7147 /* remove the vf from the pool */
7148 if (!(vlvf & vlvf_mask))
7149 continue;
7150
7151 /* clear out bit from VLVF */
7152 vlvf ^= vlvf_mask;
7153
7154 /* if other pools are present, just remove ourselves */
7155 if (vlvf & pool_mask)
7156 goto update_vlvfb;
7157
7158 /* if PF is present, leave VFTA */
7159 if (vlvf & E1000_VLVF_POOLSEL_MASK)
7160 goto update_vlvf;
7161
7162 vid = vlvf & E1000_VLVF_VLANID_MASK;
7163 vfta_mask = BIT(vid % 32);
7164
7165 /* clear bit from VFTA */
7166 vfta = adapter->shadow_vfta[vid / 32];
7167 if (vfta & vfta_mask)
7168 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
7169update_vlvf:
7170 /* clear pool selection enable */
7171 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7172 vlvf &= E1000_VLVF_POOLSEL_MASK;
7173 else
7174 vlvf = 0;
7175update_vlvfb:
7176 /* clear pool bits */
7177 wr32(E1000_VLVF(i), vlvf);
7178 }
7179}
7180
7181static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
7182{
7183 u32 vlvf;
7184 int idx;
7185
7186 /* short cut the special case */
7187 if (vlan == 0)
7188 return 0;
7189
7190 /* Search for the VLAN id in the VLVF entries */
7191 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
7192 vlvf = rd32(E1000_VLVF(idx));
7193 if ((vlvf & VLAN_VID_MASK) == vlan)
7194 break;
7195 }
7196
7197 return idx;
7198}
7199
7200static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
7201{
7202 struct e1000_hw *hw = &adapter->hw;
7203 u32 bits, pf_id;
7204 int idx;
7205
7206 idx = igb_find_vlvf_entry(hw, vid);
7207 if (!idx)
7208 return;
7209
7210 /* See if any other pools are set for this VLAN filter
7211 * entry other than the PF.
7212 */
7213 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
7214 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
7215 bits &= rd32(E1000_VLVF(idx));
7216
7217 /* Disable the filter so this falls into the default pool. */
7218 if (!bits) {
7219 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7220 wr32(E1000_VLVF(idx), BIT(pf_id));
7221 else
7222 wr32(E1000_VLVF(idx), 0);
7223 }
7224}
7225
7226static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
7227 bool add, u32 vf)
7228{
7229 int pf_id = adapter->vfs_allocated_count;
7230 struct e1000_hw *hw = &adapter->hw;
7231 int err;
7232
7233 /* If VLAN overlaps with one the PF is currently monitoring make
7234 * sure that we are able to allocate a VLVF entry. This may be
7235 * redundant but it guarantees PF will maintain visibility to
7236 * the VLAN.
7237 */
7238 if (add && test_bit(vid, adapter->active_vlans)) {
7239 err = igb_vfta_set(hw, vid, pf_id, true, false);
7240 if (err)
7241 return err;
7242 }
7243
7244 err = igb_vfta_set(hw, vid, vf, add, false);
7245
7246 if (add && !err)
7247 return err;
7248
7249 /* If we failed to add the VF VLAN or we are removing the VF VLAN
7250 * we may need to drop the PF pool bit in order to allow us to free
7251 * up the VLVF resources.
7252 */
7253 if (test_bit(vid, adapter->active_vlans) ||
7254 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
7255 igb_update_pf_vlvf(adapter, vid);
7256
7257 return err;
7258}
7259
7260static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
7261{
7262 struct e1000_hw *hw = &adapter->hw;
7263
7264 if (vid)
7265 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
7266 else
7267 wr32(E1000_VMVIR(vf), 0);
7268}
7269
7270static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
7271 u16 vlan, u8 qos)
7272{
7273 int err;
7274
7275 err = igb_set_vf_vlan(adapter, vlan, true, vf);
7276 if (err)
7277 return err;
7278
7279 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
7280 igb_set_vmolr(adapter, vf, !vlan);
7281
7282 /* revoke access to previous VLAN */
7283 if (vlan != adapter->vf_data[vf].pf_vlan)
7284 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7285 false, vf);
7286
7287 adapter->vf_data[vf].pf_vlan = vlan;
7288 adapter->vf_data[vf].pf_qos = qos;
7289 igb_set_vf_vlan_strip(adapter, vf, true);
7290 dev_info(&adapter->pdev->dev,
7291 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
7292 if (test_bit(__IGB_DOWN, &adapter->state)) {
7293 dev_warn(&adapter->pdev->dev,
7294 "The VF VLAN has been set, but the PF device is not up.\n");
7295 dev_warn(&adapter->pdev->dev,
7296 "Bring the PF device up before attempting to use the VF device.\n");
7297 }
7298
7299 return err;
7300}
7301
7302static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
7303{
7304 /* Restore tagless access via VLAN 0 */
7305 igb_set_vf_vlan(adapter, 0, true, vf);
7306
7307 igb_set_vmvir(adapter, 0, vf);
7308 igb_set_vmolr(adapter, vf, true);
7309
7310 /* Remove any PF assigned VLAN */
7311 if (adapter->vf_data[vf].pf_vlan)
7312 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7313 false, vf);
7314
7315 adapter->vf_data[vf].pf_vlan = 0;
7316 adapter->vf_data[vf].pf_qos = 0;
7317 igb_set_vf_vlan_strip(adapter, vf, false);
7318
7319 return 0;
7320}
7321
7322static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
7323 u16 vlan, u8 qos, __be16 vlan_proto)
7324{
7325 struct igb_adapter *adapter = netdev_priv(netdev);
7326
7327 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
7328 return -EINVAL;
7329
7330 if (vlan_proto != htons(ETH_P_8021Q))
7331 return -EPROTONOSUPPORT;
7332
7333 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
7334 igb_disable_port_vlan(adapter, vf);
7335}
7336
7337static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7338{
7339 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7340 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
7341 int ret;
7342
7343 if (adapter->vf_data[vf].pf_vlan)
7344 return -1;
7345
7346 /* VLAN 0 is a special case, don't allow it to be removed */
7347 if (!vid && !add)
7348 return 0;
7349
7350 ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
7351 if (!ret)
7352 igb_set_vf_vlan_strip(adapter, vf, !!vid);
7353 return ret;
7354}
7355
7356static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
7357{
7358 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7359
7360 /* clear flags - except flag that indicates PF has set the MAC */
7361 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
7362 vf_data->last_nack = jiffies;
7363
7364 /* reset vlans for device */
7365 igb_clear_vf_vfta(adapter, vf);
7366 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
7367 igb_set_vmvir(adapter, vf_data->pf_vlan |
7368 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
7369 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
7370 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
7371
7372 /* reset multicast table array for vf */
7373 adapter->vf_data[vf].num_vf_mc_hashes = 0;
7374
7375 /* Flush and reset the mta with the new values */
7376 igb_set_rx_mode(adapter->netdev);
7377}
7378
7379static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
7380{
7381 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7382
7383 /* clear mac address as we were hotplug removed/added */
7384 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7385 eth_zero_addr(vf_mac);
7386
7387 /* process remaining reset events */
7388 igb_vf_reset(adapter, vf);
7389}
7390
7391static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
7392{
7393 struct e1000_hw *hw = &adapter->hw;
7394 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7395 u32 reg, msgbuf[3];
7396 u8 *addr = (u8 *)(&msgbuf[1]);
7397
7398 /* process all the same items cleared in a function level reset */
7399 igb_vf_reset(adapter, vf);
7400
7401 /* set vf mac address */
7402 igb_set_vf_mac(adapter, vf, vf_mac);
7403
7404 /* enable transmit and receive for vf */
7405 reg = rd32(E1000_VFTE);
7406 wr32(E1000_VFTE, reg | BIT(vf));
7407 reg = rd32(E1000_VFRE);
7408 wr32(E1000_VFRE, reg | BIT(vf));
7409
7410 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
7411
7412 /* reply to reset with ack and vf mac address */
7413 if (!is_zero_ether_addr(vf_mac)) {
7414 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
7415 memcpy(addr, vf_mac, ETH_ALEN);
7416 } else {
7417 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
7418 }
7419 igb_write_mbx(hw, msgbuf, 3, vf);
7420}
7421
7422static void igb_flush_mac_table(struct igb_adapter *adapter)
7423{
7424 struct e1000_hw *hw = &adapter->hw;
7425 int i;
7426
7427 for (i = 0; i < hw->mac.rar_entry_count; i++) {
7428 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
7429 eth_zero_addr(adapter->mac_table[i].addr);
7430 adapter->mac_table[i].queue = 0;
7431 igb_rar_set_index(adapter, i);
7432 }
7433}
7434
7435static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
7436{
7437 struct e1000_hw *hw = &adapter->hw;
7438 /* do not count rar entries reserved for VFs MAC addresses */
7439 int rar_entries = hw->mac.rar_entry_count -
7440 adapter->vfs_allocated_count;
7441 int i, count = 0;
7442
7443 for (i = 0; i < rar_entries; i++) {
7444 /* do not count default entries */
7445 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
7446 continue;
7447
7448 /* do not count "in use" entries for different queues */
7449 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
7450 (adapter->mac_table[i].queue != queue))
7451 continue;
7452
7453 count++;
7454 }
7455
7456 return count;
7457}
7458
7459/* Set default MAC address for the PF in the first RAR entry */
7460static void igb_set_default_mac_filter(struct igb_adapter *adapter)
7461{
7462 struct igb_mac_addr *mac_table = &adapter->mac_table[0];
7463
7464 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
7465 mac_table->queue = adapter->vfs_allocated_count;
7466 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7467
7468 igb_rar_set_index(adapter, 0);
7469}
7470
7471/* If the filter to be added and an already existing filter express
7472 * the same address and address type, it should be possible to only
7473 * override the other configurations, for example the queue to steer
7474 * traffic.
7475 */
7476static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry,
7477 const u8 *addr, const u8 flags)
7478{
7479 if (!(entry->state & IGB_MAC_STATE_IN_USE))
7480 return true;
7481
7482 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
7483 (flags & IGB_MAC_STATE_SRC_ADDR))
7484 return false;
7485
7486 if (!ether_addr_equal(addr, entry->addr))
7487 return false;
7488
7489 return true;
7490}
7491
7492/* Add a MAC filter for 'addr' directing matching traffic to 'queue',
7493 * 'flags' is used to indicate what kind of match is made, match is by
7494 * default for the destination address, if matching by source address
7495 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used.
7496 */
7497static int igb_add_mac_filter_flags(struct igb_adapter *adapter,
7498 const u8 *addr, const u8 queue,
7499 const u8 flags)
7500{
7501 struct e1000_hw *hw = &adapter->hw;
7502 int rar_entries = hw->mac.rar_entry_count -
7503 adapter->vfs_allocated_count;
7504 int i;
7505
7506 if (is_zero_ether_addr(addr))
7507 return -EINVAL;
7508
7509 /* Search for the first empty entry in the MAC table.
7510 * Do not touch entries at the end of the table reserved for the VF MAC
7511 * addresses.
7512 */
7513 for (i = 0; i < rar_entries; i++) {
7514 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i],
7515 addr, flags))
7516 continue;
7517
7518 ether_addr_copy(adapter->mac_table[i].addr, addr);
7519 adapter->mac_table[i].queue = queue;
7520 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags;
7521
7522 igb_rar_set_index(adapter, i);
7523 return i;
7524 }
7525
7526 return -ENOSPC;
7527}
7528
7529static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7530 const u8 queue)
7531{
7532 return igb_add_mac_filter_flags(adapter, addr, queue, 0);
7533}
7534
7535/* Remove a MAC filter for 'addr' directing matching traffic to
7536 * 'queue', 'flags' is used to indicate what kind of match need to be
7537 * removed, match is by default for the destination address, if
7538 * matching by source address is to be removed the flag
7539 * IGB_MAC_STATE_SRC_ADDR can be used.
7540 */
7541static int igb_del_mac_filter_flags(struct igb_adapter *adapter,
7542 const u8 *addr, const u8 queue,
7543 const u8 flags)
7544{
7545 struct e1000_hw *hw = &adapter->hw;
7546 int rar_entries = hw->mac.rar_entry_count -
7547 adapter->vfs_allocated_count;
7548 int i;
7549
7550 if (is_zero_ether_addr(addr))
7551 return -EINVAL;
7552
7553 /* Search for matching entry in the MAC table based on given address
7554 * and queue. Do not touch entries at the end of the table reserved
7555 * for the VF MAC addresses.
7556 */
7557 for (i = 0; i < rar_entries; i++) {
7558 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
7559 continue;
7560 if ((adapter->mac_table[i].state & flags) != flags)
7561 continue;
7562 if (adapter->mac_table[i].queue != queue)
7563 continue;
7564 if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
7565 continue;
7566
7567 /* When a filter for the default address is "deleted",
7568 * we return it to its initial configuration
7569 */
7570 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
7571 adapter->mac_table[i].state =
7572 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7573 adapter->mac_table[i].queue =
7574 adapter->vfs_allocated_count;
7575 } else {
7576 adapter->mac_table[i].state = 0;
7577 adapter->mac_table[i].queue = 0;
7578 eth_zero_addr(adapter->mac_table[i].addr);
7579 }
7580
7581 igb_rar_set_index(adapter, i);
7582 return 0;
7583 }
7584
7585 return -ENOENT;
7586}
7587
7588static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7589 const u8 queue)
7590{
7591 return igb_del_mac_filter_flags(adapter, addr, queue, 0);
7592}
7593
7594int igb_add_mac_steering_filter(struct igb_adapter *adapter,
7595 const u8 *addr, u8 queue, u8 flags)
7596{
7597 struct e1000_hw *hw = &adapter->hw;
7598
7599 /* In theory, this should be supported on 82575 as well, but
7600 * that part wasn't easily accessible during development.
7601 */
7602 if (hw->mac.type != e1000_i210)
7603 return -EOPNOTSUPP;
7604
7605 return igb_add_mac_filter_flags(adapter, addr, queue,
7606 IGB_MAC_STATE_QUEUE_STEERING | flags);
7607}
7608
7609int igb_del_mac_steering_filter(struct igb_adapter *adapter,
7610 const u8 *addr, u8 queue, u8 flags)
7611{
7612 return igb_del_mac_filter_flags(adapter, addr, queue,
7613 IGB_MAC_STATE_QUEUE_STEERING | flags);
7614}
7615
7616static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
7617{
7618 struct igb_adapter *adapter = netdev_priv(netdev);
7619 int ret;
7620
7621 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7622
7623 return min_t(int, ret, 0);
7624}
7625
7626static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
7627{
7628 struct igb_adapter *adapter = netdev_priv(netdev);
7629
7630 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7631
7632 return 0;
7633}
7634
7635static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
7636 const u32 info, const u8 *addr)
7637{
7638 struct pci_dev *pdev = adapter->pdev;
7639 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7640 struct list_head *pos;
7641 struct vf_mac_filter *entry = NULL;
7642 int ret = 0;
7643
7644 switch (info) {
7645 case E1000_VF_MAC_FILTER_CLR:
7646 /* remove all unicast MAC filters related to the current VF */
7647 list_for_each(pos, &adapter->vf_macs.l) {
7648 entry = list_entry(pos, struct vf_mac_filter, l);
7649 if (entry->vf == vf) {
7650 entry->vf = -1;
7651 entry->free = true;
7652 igb_del_mac_filter(adapter, entry->vf_mac, vf);
7653 }
7654 }
7655 break;
7656 case E1000_VF_MAC_FILTER_ADD:
7657 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7658 !vf_data->trusted) {
7659 dev_warn(&pdev->dev,
7660 "VF %d requested MAC filter but is administratively denied\n",
7661 vf);
7662 return -EINVAL;
7663 }
7664 if (!is_valid_ether_addr(addr)) {
7665 dev_warn(&pdev->dev,
7666 "VF %d attempted to set invalid MAC filter\n",
7667 vf);
7668 return -EINVAL;
7669 }
7670
7671 /* try to find empty slot in the list */
7672 list_for_each(pos, &adapter->vf_macs.l) {
7673 entry = list_entry(pos, struct vf_mac_filter, l);
7674 if (entry->free)
7675 break;
7676 }
7677
7678 if (entry && entry->free) {
7679 entry->free = false;
7680 entry->vf = vf;
7681 ether_addr_copy(entry->vf_mac, addr);
7682
7683 ret = igb_add_mac_filter(adapter, addr, vf);
7684 ret = min_t(int, ret, 0);
7685 } else {
7686 ret = -ENOSPC;
7687 }
7688
7689 if (ret == -ENOSPC)
7690 dev_warn(&pdev->dev,
7691 "VF %d has requested MAC filter but there is no space for it\n",
7692 vf);
7693 break;
7694 default:
7695 ret = -EINVAL;
7696 break;
7697 }
7698
7699 return ret;
7700}
7701
7702static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7703{
7704 struct pci_dev *pdev = adapter->pdev;
7705 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7706 u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7707
7708 /* The VF MAC Address is stored in a packed array of bytes
7709 * starting at the second 32 bit word of the msg array
7710 */
7711 unsigned char *addr = (unsigned char *)&msg[1];
7712 int ret = 0;
7713
7714 if (!info) {
7715 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7716 !vf_data->trusted) {
7717 dev_warn(&pdev->dev,
7718 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7719 vf);
7720 return -EINVAL;
7721 }
7722
7723 if (!is_valid_ether_addr(addr)) {
7724 dev_warn(&pdev->dev,
7725 "VF %d attempted to set invalid MAC\n",
7726 vf);
7727 return -EINVAL;
7728 }
7729
7730 ret = igb_set_vf_mac(adapter, vf, addr);
7731 } else {
7732 ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7733 }
7734
7735 return ret;
7736}
7737
7738static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7739{
7740 struct e1000_hw *hw = &adapter->hw;
7741 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7742 u32 msg = E1000_VT_MSGTYPE_NACK;
7743
7744 /* if device isn't clear to send it shouldn't be reading either */
7745 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7746 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7747 igb_write_mbx(hw, &msg, 1, vf);
7748 vf_data->last_nack = jiffies;
7749 }
7750}
7751
7752static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7753{
7754 struct pci_dev *pdev = adapter->pdev;
7755 u32 msgbuf[E1000_VFMAILBOX_SIZE];
7756 struct e1000_hw *hw = &adapter->hw;
7757 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7758 s32 retval;
7759
7760 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7761
7762 if (retval) {
7763 /* if receive failed revoke VF CTS stats and restart init */
7764 dev_err(&pdev->dev, "Error receiving message from VF\n");
7765 vf_data->flags &= ~IGB_VF_FLAG_CTS;
7766 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7767 goto unlock;
7768 goto out;
7769 }
7770
7771 /* this is a message we already processed, do nothing */
7772 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7773 goto unlock;
7774
7775 /* until the vf completes a reset it should not be
7776 * allowed to start any configuration.
7777 */
7778 if (msgbuf[0] == E1000_VF_RESET) {
7779 /* unlocks mailbox */
7780 igb_vf_reset_msg(adapter, vf);
7781 return;
7782 }
7783
7784 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7785 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7786 goto unlock;
7787 retval = -1;
7788 goto out;
7789 }
7790
7791 switch ((msgbuf[0] & 0xFFFF)) {
7792 case E1000_VF_SET_MAC_ADDR:
7793 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
7794 break;
7795 case E1000_VF_SET_PROMISC:
7796 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
7797 break;
7798 case E1000_VF_SET_MULTICAST:
7799 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
7800 break;
7801 case E1000_VF_SET_LPE:
7802 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
7803 break;
7804 case E1000_VF_SET_VLAN:
7805 retval = -1;
7806 if (vf_data->pf_vlan)
7807 dev_warn(&pdev->dev,
7808 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
7809 vf);
7810 else
7811 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
7812 break;
7813 default:
7814 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
7815 retval = -1;
7816 break;
7817 }
7818
7819 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
7820out:
7821 /* notify the VF of the results of what it sent us */
7822 if (retval)
7823 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
7824 else
7825 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
7826
7827 /* unlocks mailbox */
7828 igb_write_mbx(hw, msgbuf, 1, vf);
7829 return;
7830
7831unlock:
7832 igb_unlock_mbx(hw, vf);
7833}
7834
7835static void igb_msg_task(struct igb_adapter *adapter)
7836{
7837 struct e1000_hw *hw = &adapter->hw;
7838 u32 vf;
7839
7840 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
7841 /* process any reset requests */
7842 if (!igb_check_for_rst(hw, vf))
7843 igb_vf_reset_event(adapter, vf);
7844
7845 /* process any messages pending */
7846 if (!igb_check_for_msg(hw, vf))
7847 igb_rcv_msg_from_vf(adapter, vf);
7848
7849 /* process any acks */
7850 if (!igb_check_for_ack(hw, vf))
7851 igb_rcv_ack_from_vf(adapter, vf);
7852 }
7853}
7854
7855/**
7856 * igb_set_uta - Set unicast filter table address
7857 * @adapter: board private structure
7858 * @set: boolean indicating if we are setting or clearing bits
7859 *
7860 * The unicast table address is a register array of 32-bit registers.
7861 * The table is meant to be used in a way similar to how the MTA is used
7862 * however due to certain limitations in the hardware it is necessary to
7863 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
7864 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
7865 **/
7866static void igb_set_uta(struct igb_adapter *adapter, bool set)
7867{
7868 struct e1000_hw *hw = &adapter->hw;
7869 u32 uta = set ? ~0 : 0;
7870 int i;
7871
7872 /* we only need to do this if VMDq is enabled */
7873 if (!adapter->vfs_allocated_count)
7874 return;
7875
7876 for (i = hw->mac.uta_reg_count; i--;)
7877 array_wr32(E1000_UTA, i, uta);
7878}
7879
7880/**
7881 * igb_intr_msi - Interrupt Handler
7882 * @irq: interrupt number
7883 * @data: pointer to a network interface device structure
7884 **/
7885static irqreturn_t igb_intr_msi(int irq, void *data)
7886{
7887 struct igb_adapter *adapter = data;
7888 struct igb_q_vector *q_vector = adapter->q_vector[0];
7889 struct e1000_hw *hw = &adapter->hw;
7890 /* read ICR disables interrupts using IAM */
7891 u32 icr = rd32(E1000_ICR);
7892
7893 igb_write_itr(q_vector);
7894
7895 if (icr & E1000_ICR_DRSTA)
7896 schedule_work(&adapter->reset_task);
7897
7898 if (icr & E1000_ICR_DOUTSYNC) {
7899 /* HW is reporting DMA is out of sync */
7900 adapter->stats.doosync++;
7901 }
7902
7903 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7904 hw->mac.get_link_status = 1;
7905 if (!test_bit(__IGB_DOWN, &adapter->state))
7906 mod_timer(&adapter->watchdog_timer, jiffies + 1);
7907 }
7908
7909 if (icr & E1000_ICR_TS)
7910 igb_tsync_interrupt(adapter);
7911
7912 napi_schedule(&q_vector->napi);
7913
7914 return IRQ_HANDLED;
7915}
7916
7917/**
7918 * igb_intr - Legacy Interrupt Handler
7919 * @irq: interrupt number
7920 * @data: pointer to a network interface device structure
7921 **/
7922static irqreturn_t igb_intr(int irq, void *data)
7923{
7924 struct igb_adapter *adapter = data;
7925 struct igb_q_vector *q_vector = adapter->q_vector[0];
7926 struct e1000_hw *hw = &adapter->hw;
7927 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
7928 * need for the IMC write
7929 */
7930 u32 icr = rd32(E1000_ICR);
7931
7932 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
7933 * not set, then the adapter didn't send an interrupt
7934 */
7935 if (!(icr & E1000_ICR_INT_ASSERTED))
7936 return IRQ_NONE;
7937
7938 igb_write_itr(q_vector);
7939
7940 if (icr & E1000_ICR_DRSTA)
7941 schedule_work(&adapter->reset_task);
7942
7943 if (icr & E1000_ICR_DOUTSYNC) {
7944 /* HW is reporting DMA is out of sync */
7945 adapter->stats.doosync++;
7946 }
7947
7948 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7949 hw->mac.get_link_status = 1;
7950 /* guard against interrupt when we're going down */
7951 if (!test_bit(__IGB_DOWN, &adapter->state))
7952 mod_timer(&adapter->watchdog_timer, jiffies + 1);
7953 }
7954
7955 if (icr & E1000_ICR_TS)
7956 igb_tsync_interrupt(adapter);
7957
7958 napi_schedule(&q_vector->napi);
7959
7960 return IRQ_HANDLED;
7961}
7962
7963static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
7964{
7965 struct igb_adapter *adapter = q_vector->adapter;
7966 struct e1000_hw *hw = &adapter->hw;
7967
7968 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
7969 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
7970 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
7971 igb_set_itr(q_vector);
7972 else
7973 igb_update_ring_itr(q_vector);
7974 }
7975
7976 if (!test_bit(__IGB_DOWN, &adapter->state)) {
7977 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7978 wr32(E1000_EIMS, q_vector->eims_value);
7979 else
7980 igb_irq_enable(adapter);
7981 }
7982}
7983
7984/**
7985 * igb_poll - NAPI Rx polling callback
7986 * @napi: napi polling structure
7987 * @budget: count of how many packets we should handle
7988 **/
7989static int igb_poll(struct napi_struct *napi, int budget)
7990{
7991 struct igb_q_vector *q_vector = container_of(napi,
7992 struct igb_q_vector,
7993 napi);
7994 bool clean_complete = true;
7995 int work_done = 0;
7996
7997#ifdef CONFIG_IGB_DCA
7998 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
7999 igb_update_dca(q_vector);
8000#endif
8001 if (q_vector->tx.ring)
8002 clean_complete = igb_clean_tx_irq(q_vector, budget);
8003
8004 if (q_vector->rx.ring) {
8005 int cleaned = igb_clean_rx_irq(q_vector, budget);
8006
8007 work_done += cleaned;
8008 if (cleaned >= budget)
8009 clean_complete = false;
8010 }
8011
8012 /* If all work not completed, return budget and keep polling */
8013 if (!clean_complete)
8014 return budget;
8015
8016 /* Exit the polling mode, but don't re-enable interrupts if stack might
8017 * poll us due to busy-polling
8018 */
8019 if (likely(napi_complete_done(napi, work_done)))
8020 igb_ring_irq_enable(q_vector);
8021
8022 return min(work_done, budget - 1);
8023}
8024
8025/**
8026 * igb_clean_tx_irq - Reclaim resources after transmit completes
8027 * @q_vector: pointer to q_vector containing needed info
8028 * @napi_budget: Used to determine if we are in netpoll
8029 *
8030 * returns true if ring is completely cleaned
8031 **/
8032static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
8033{
8034 struct igb_adapter *adapter = q_vector->adapter;
8035 struct igb_ring *tx_ring = q_vector->tx.ring;
8036 struct igb_tx_buffer *tx_buffer;
8037 union e1000_adv_tx_desc *tx_desc;
8038 unsigned int total_bytes = 0, total_packets = 0;
8039 unsigned int budget = q_vector->tx.work_limit;
8040 unsigned int i = tx_ring->next_to_clean;
8041
8042 if (test_bit(__IGB_DOWN, &adapter->state))
8043 return true;
8044
8045 tx_buffer = &tx_ring->tx_buffer_info[i];
8046 tx_desc = IGB_TX_DESC(tx_ring, i);
8047 i -= tx_ring->count;
8048
8049 do {
8050 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8051
8052 /* if next_to_watch is not set then there is no work pending */
8053 if (!eop_desc)
8054 break;
8055
8056 /* prevent any other reads prior to eop_desc */
8057 smp_rmb();
8058
8059 /* if DD is not set pending work has not been completed */
8060 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
8061 break;
8062
8063 /* clear next_to_watch to prevent false hangs */
8064 tx_buffer->next_to_watch = NULL;
8065
8066 /* update the statistics for this packet */
8067 total_bytes += tx_buffer->bytecount;
8068 total_packets += tx_buffer->gso_segs;
8069
8070 /* free the skb */
8071 if (tx_buffer->type == IGB_TYPE_SKB)
8072 napi_consume_skb(tx_buffer->skb, napi_budget);
8073 else
8074 xdp_return_frame(tx_buffer->xdpf);
8075
8076 /* unmap skb header data */
8077 dma_unmap_single(tx_ring->dev,
8078 dma_unmap_addr(tx_buffer, dma),
8079 dma_unmap_len(tx_buffer, len),
8080 DMA_TO_DEVICE);
8081
8082 /* clear tx_buffer data */
8083 dma_unmap_len_set(tx_buffer, len, 0);
8084
8085 /* clear last DMA location and unmap remaining buffers */
8086 while (tx_desc != eop_desc) {
8087 tx_buffer++;
8088 tx_desc++;
8089 i++;
8090 if (unlikely(!i)) {
8091 i -= tx_ring->count;
8092 tx_buffer = tx_ring->tx_buffer_info;
8093 tx_desc = IGB_TX_DESC(tx_ring, 0);
8094 }
8095
8096 /* unmap any remaining paged data */
8097 if (dma_unmap_len(tx_buffer, len)) {
8098 dma_unmap_page(tx_ring->dev,
8099 dma_unmap_addr(tx_buffer, dma),
8100 dma_unmap_len(tx_buffer, len),
8101 DMA_TO_DEVICE);
8102 dma_unmap_len_set(tx_buffer, len, 0);
8103 }
8104 }
8105
8106 /* move us one more past the eop_desc for start of next pkt */
8107 tx_buffer++;
8108 tx_desc++;
8109 i++;
8110 if (unlikely(!i)) {
8111 i -= tx_ring->count;
8112 tx_buffer = tx_ring->tx_buffer_info;
8113 tx_desc = IGB_TX_DESC(tx_ring, 0);
8114 }
8115
8116 /* issue prefetch for next Tx descriptor */
8117 prefetch(tx_desc);
8118
8119 /* update budget accounting */
8120 budget--;
8121 } while (likely(budget));
8122
8123 netdev_tx_completed_queue(txring_txq(tx_ring),
8124 total_packets, total_bytes);
8125 i += tx_ring->count;
8126 tx_ring->next_to_clean = i;
8127 u64_stats_update_begin(&tx_ring->tx_syncp);
8128 tx_ring->tx_stats.bytes += total_bytes;
8129 tx_ring->tx_stats.packets += total_packets;
8130 u64_stats_update_end(&tx_ring->tx_syncp);
8131 q_vector->tx.total_bytes += total_bytes;
8132 q_vector->tx.total_packets += total_packets;
8133
8134 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
8135 struct e1000_hw *hw = &adapter->hw;
8136
8137 /* Detect a transmit hang in hardware, this serializes the
8138 * check with the clearing of time_stamp and movement of i
8139 */
8140 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
8141 if (tx_buffer->next_to_watch &&
8142 time_after(jiffies, tx_buffer->time_stamp +
8143 (adapter->tx_timeout_factor * HZ)) &&
8144 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
8145
8146 /* detected Tx unit hang */
8147 dev_err(tx_ring->dev,
8148 "Detected Tx Unit Hang\n"
8149 " Tx Queue <%d>\n"
8150 " TDH <%x>\n"
8151 " TDT <%x>\n"
8152 " next_to_use <%x>\n"
8153 " next_to_clean <%x>\n"
8154 "buffer_info[next_to_clean]\n"
8155 " time_stamp <%lx>\n"
8156 " next_to_watch <%p>\n"
8157 " jiffies <%lx>\n"
8158 " desc.status <%x>\n",
8159 tx_ring->queue_index,
8160 rd32(E1000_TDH(tx_ring->reg_idx)),
8161 readl(tx_ring->tail),
8162 tx_ring->next_to_use,
8163 tx_ring->next_to_clean,
8164 tx_buffer->time_stamp,
8165 tx_buffer->next_to_watch,
8166 jiffies,
8167 tx_buffer->next_to_watch->wb.status);
8168 netif_stop_subqueue(tx_ring->netdev,
8169 tx_ring->queue_index);
8170
8171 /* we are about to reset, no point in enabling stuff */
8172 return true;
8173 }
8174 }
8175
8176#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
8177 if (unlikely(total_packets &&
8178 netif_carrier_ok(tx_ring->netdev) &&
8179 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
8180 /* Make sure that anybody stopping the queue after this
8181 * sees the new next_to_clean.
8182 */
8183 smp_mb();
8184 if (__netif_subqueue_stopped(tx_ring->netdev,
8185 tx_ring->queue_index) &&
8186 !(test_bit(__IGB_DOWN, &adapter->state))) {
8187 netif_wake_subqueue(tx_ring->netdev,
8188 tx_ring->queue_index);
8189
8190 u64_stats_update_begin(&tx_ring->tx_syncp);
8191 tx_ring->tx_stats.restart_queue++;
8192 u64_stats_update_end(&tx_ring->tx_syncp);
8193 }
8194 }
8195
8196 return !!budget;
8197}
8198
8199/**
8200 * igb_reuse_rx_page - page flip buffer and store it back on the ring
8201 * @rx_ring: rx descriptor ring to store buffers on
8202 * @old_buff: donor buffer to have page reused
8203 *
8204 * Synchronizes page for reuse by the adapter
8205 **/
8206static void igb_reuse_rx_page(struct igb_ring *rx_ring,
8207 struct igb_rx_buffer *old_buff)
8208{
8209 struct igb_rx_buffer *new_buff;
8210 u16 nta = rx_ring->next_to_alloc;
8211
8212 new_buff = &rx_ring->rx_buffer_info[nta];
8213
8214 /* update, and store next to alloc */
8215 nta++;
8216 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
8217
8218 /* Transfer page from old buffer to new buffer.
8219 * Move each member individually to avoid possible store
8220 * forwarding stalls.
8221 */
8222 new_buff->dma = old_buff->dma;
8223 new_buff->page = old_buff->page;
8224 new_buff->page_offset = old_buff->page_offset;
8225 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
8226}
8227
8228static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
8229 int rx_buf_pgcnt)
8230{
8231 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
8232 struct page *page = rx_buffer->page;
8233
8234 /* avoid re-using remote and pfmemalloc pages */
8235 if (!dev_page_is_reusable(page))
8236 return false;
8237
8238#if (PAGE_SIZE < 8192)
8239 /* if we are only owner of page we can reuse it */
8240 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1))
8241 return false;
8242#else
8243#define IGB_LAST_OFFSET \
8244 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
8245
8246 if (rx_buffer->page_offset > IGB_LAST_OFFSET)
8247 return false;
8248#endif
8249
8250 /* If we have drained the page fragment pool we need to update
8251 * the pagecnt_bias and page count so that we fully restock the
8252 * number of references the driver holds.
8253 */
8254 if (unlikely(pagecnt_bias == 1)) {
8255 page_ref_add(page, USHRT_MAX - 1);
8256 rx_buffer->pagecnt_bias = USHRT_MAX;
8257 }
8258
8259 return true;
8260}
8261
8262/**
8263 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
8264 * @rx_ring: rx descriptor ring to transact packets on
8265 * @rx_buffer: buffer containing page to add
8266 * @skb: sk_buff to place the data into
8267 * @size: size of buffer to be added
8268 *
8269 * This function will add the data contained in rx_buffer->page to the skb.
8270 **/
8271static void igb_add_rx_frag(struct igb_ring *rx_ring,
8272 struct igb_rx_buffer *rx_buffer,
8273 struct sk_buff *skb,
8274 unsigned int size)
8275{
8276#if (PAGE_SIZE < 8192)
8277 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8278#else
8279 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
8280 SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
8281 SKB_DATA_ALIGN(size);
8282#endif
8283 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
8284 rx_buffer->page_offset, size, truesize);
8285#if (PAGE_SIZE < 8192)
8286 rx_buffer->page_offset ^= truesize;
8287#else
8288 rx_buffer->page_offset += truesize;
8289#endif
8290}
8291
8292static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
8293 struct igb_rx_buffer *rx_buffer,
8294 struct xdp_buff *xdp,
8295 ktime_t timestamp)
8296{
8297#if (PAGE_SIZE < 8192)
8298 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8299#else
8300 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
8301 xdp->data_hard_start);
8302#endif
8303 unsigned int size = xdp->data_end - xdp->data;
8304 unsigned int headlen;
8305 struct sk_buff *skb;
8306
8307 /* prefetch first cache line of first page */
8308 net_prefetch(xdp->data);
8309
8310 /* allocate a skb to store the frags */
8311 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
8312 if (unlikely(!skb))
8313 return NULL;
8314
8315 if (timestamp)
8316 skb_hwtstamps(skb)->hwtstamp = timestamp;
8317
8318 /* Determine available headroom for copy */
8319 headlen = size;
8320 if (headlen > IGB_RX_HDR_LEN)
8321 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN);
8322
8323 /* align pull length to size of long to optimize memcpy performance */
8324 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long)));
8325
8326 /* update all of the pointers */
8327 size -= headlen;
8328 if (size) {
8329 skb_add_rx_frag(skb, 0, rx_buffer->page,
8330 (xdp->data + headlen) - page_address(rx_buffer->page),
8331 size, truesize);
8332#if (PAGE_SIZE < 8192)
8333 rx_buffer->page_offset ^= truesize;
8334#else
8335 rx_buffer->page_offset += truesize;
8336#endif
8337 } else {
8338 rx_buffer->pagecnt_bias++;
8339 }
8340
8341 return skb;
8342}
8343
8344static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
8345 struct igb_rx_buffer *rx_buffer,
8346 struct xdp_buff *xdp,
8347 ktime_t timestamp)
8348{
8349#if (PAGE_SIZE < 8192)
8350 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8351#else
8352 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
8353 SKB_DATA_ALIGN(xdp->data_end -
8354 xdp->data_hard_start);
8355#endif
8356 unsigned int metasize = xdp->data - xdp->data_meta;
8357 struct sk_buff *skb;
8358
8359 /* prefetch first cache line of first page */
8360 net_prefetch(xdp->data_meta);
8361
8362 /* build an skb around the page buffer */
8363 skb = build_skb(xdp->data_hard_start, truesize);
8364 if (unlikely(!skb))
8365 return NULL;
8366
8367 /* update pointers within the skb to store the data */
8368 skb_reserve(skb, xdp->data - xdp->data_hard_start);
8369 __skb_put(skb, xdp->data_end - xdp->data);
8370
8371 if (metasize)
8372 skb_metadata_set(skb, metasize);
8373
8374 if (timestamp)
8375 skb_hwtstamps(skb)->hwtstamp = timestamp;
8376
8377 /* update buffer offset */
8378#if (PAGE_SIZE < 8192)
8379 rx_buffer->page_offset ^= truesize;
8380#else
8381 rx_buffer->page_offset += truesize;
8382#endif
8383
8384 return skb;
8385}
8386
8387static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter,
8388 struct igb_ring *rx_ring,
8389 struct xdp_buff *xdp)
8390{
8391 int err, result = IGB_XDP_PASS;
8392 struct bpf_prog *xdp_prog;
8393 u32 act;
8394
8395 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
8396
8397 if (!xdp_prog)
8398 goto xdp_out;
8399
8400 prefetchw(xdp->data_hard_start); /* xdp_frame write */
8401
8402 act = bpf_prog_run_xdp(xdp_prog, xdp);
8403 switch (act) {
8404 case XDP_PASS:
8405 break;
8406 case XDP_TX:
8407 result = igb_xdp_xmit_back(adapter, xdp);
8408 if (result == IGB_XDP_CONSUMED)
8409 goto out_failure;
8410 break;
8411 case XDP_REDIRECT:
8412 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
8413 if (err)
8414 goto out_failure;
8415 result = IGB_XDP_REDIR;
8416 break;
8417 default:
8418 bpf_warn_invalid_xdp_action(act);
8419 fallthrough;
8420 case XDP_ABORTED:
8421out_failure:
8422 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
8423 fallthrough;
8424 case XDP_DROP:
8425 result = IGB_XDP_CONSUMED;
8426 break;
8427 }
8428xdp_out:
8429 return ERR_PTR(-result);
8430}
8431
8432static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring,
8433 unsigned int size)
8434{
8435 unsigned int truesize;
8436
8437#if (PAGE_SIZE < 8192)
8438 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
8439#else
8440 truesize = ring_uses_build_skb(rx_ring) ?
8441 SKB_DATA_ALIGN(IGB_SKB_PAD + size) +
8442 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
8443 SKB_DATA_ALIGN(size);
8444#endif
8445 return truesize;
8446}
8447
8448static void igb_rx_buffer_flip(struct igb_ring *rx_ring,
8449 struct igb_rx_buffer *rx_buffer,
8450 unsigned int size)
8451{
8452 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size);
8453#if (PAGE_SIZE < 8192)
8454 rx_buffer->page_offset ^= truesize;
8455#else
8456 rx_buffer->page_offset += truesize;
8457#endif
8458}
8459
8460static inline void igb_rx_checksum(struct igb_ring *ring,
8461 union e1000_adv_rx_desc *rx_desc,
8462 struct sk_buff *skb)
8463{
8464 skb_checksum_none_assert(skb);
8465
8466 /* Ignore Checksum bit is set */
8467 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
8468 return;
8469
8470 /* Rx checksum disabled via ethtool */
8471 if (!(ring->netdev->features & NETIF_F_RXCSUM))
8472 return;
8473
8474 /* TCP/UDP checksum error bit is set */
8475 if (igb_test_staterr(rx_desc,
8476 E1000_RXDEXT_STATERR_TCPE |
8477 E1000_RXDEXT_STATERR_IPE)) {
8478 /* work around errata with sctp packets where the TCPE aka
8479 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
8480 * packets, (aka let the stack check the crc32c)
8481 */
8482 if (!((skb->len == 60) &&
8483 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
8484 u64_stats_update_begin(&ring->rx_syncp);
8485 ring->rx_stats.csum_err++;
8486 u64_stats_update_end(&ring->rx_syncp);
8487 }
8488 /* let the stack verify checksum errors */
8489 return;
8490 }
8491 /* It must be a TCP or UDP packet with a valid checksum */
8492 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
8493 E1000_RXD_STAT_UDPCS))
8494 skb->ip_summed = CHECKSUM_UNNECESSARY;
8495
8496 dev_dbg(ring->dev, "cksum success: bits %08X\n",
8497 le32_to_cpu(rx_desc->wb.upper.status_error));
8498}
8499
8500static inline void igb_rx_hash(struct igb_ring *ring,
8501 union e1000_adv_rx_desc *rx_desc,
8502 struct sk_buff *skb)
8503{
8504 if (ring->netdev->features & NETIF_F_RXHASH)
8505 skb_set_hash(skb,
8506 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
8507 PKT_HASH_TYPE_L3);
8508}
8509
8510/**
8511 * igb_is_non_eop - process handling of non-EOP buffers
8512 * @rx_ring: Rx ring being processed
8513 * @rx_desc: Rx descriptor for current buffer
8514 *
8515 * This function updates next to clean. If the buffer is an EOP buffer
8516 * this function exits returning false, otherwise it will place the
8517 * sk_buff in the next buffer to be chained and return true indicating
8518 * that this is in fact a non-EOP buffer.
8519 **/
8520static bool igb_is_non_eop(struct igb_ring *rx_ring,
8521 union e1000_adv_rx_desc *rx_desc)
8522{
8523 u32 ntc = rx_ring->next_to_clean + 1;
8524
8525 /* fetch, update, and store next to clean */
8526 ntc = (ntc < rx_ring->count) ? ntc : 0;
8527 rx_ring->next_to_clean = ntc;
8528
8529 prefetch(IGB_RX_DESC(rx_ring, ntc));
8530
8531 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
8532 return false;
8533
8534 return true;
8535}
8536
8537/**
8538 * igb_cleanup_headers - Correct corrupted or empty headers
8539 * @rx_ring: rx descriptor ring packet is being transacted on
8540 * @rx_desc: pointer to the EOP Rx descriptor
8541 * @skb: pointer to current skb being fixed
8542 *
8543 * Address the case where we are pulling data in on pages only
8544 * and as such no data is present in the skb header.
8545 *
8546 * In addition if skb is not at least 60 bytes we need to pad it so that
8547 * it is large enough to qualify as a valid Ethernet frame.
8548 *
8549 * Returns true if an error was encountered and skb was freed.
8550 **/
8551static bool igb_cleanup_headers(struct igb_ring *rx_ring,
8552 union e1000_adv_rx_desc *rx_desc,
8553 struct sk_buff *skb)
8554{
8555 /* XDP packets use error pointer so abort at this point */
8556 if (IS_ERR(skb))
8557 return true;
8558
8559 if (unlikely((igb_test_staterr(rx_desc,
8560 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
8561 struct net_device *netdev = rx_ring->netdev;
8562 if (!(netdev->features & NETIF_F_RXALL)) {
8563 dev_kfree_skb_any(skb);
8564 return true;
8565 }
8566 }
8567
8568 /* if eth_skb_pad returns an error the skb was freed */
8569 if (eth_skb_pad(skb))
8570 return true;
8571
8572 return false;
8573}
8574
8575/**
8576 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
8577 * @rx_ring: rx descriptor ring packet is being transacted on
8578 * @rx_desc: pointer to the EOP Rx descriptor
8579 * @skb: pointer to current skb being populated
8580 *
8581 * This function checks the ring, descriptor, and packet information in
8582 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
8583 * other fields within the skb.
8584 **/
8585static void igb_process_skb_fields(struct igb_ring *rx_ring,
8586 union e1000_adv_rx_desc *rx_desc,
8587 struct sk_buff *skb)
8588{
8589 struct net_device *dev = rx_ring->netdev;
8590
8591 igb_rx_hash(rx_ring, rx_desc, skb);
8592
8593 igb_rx_checksum(rx_ring, rx_desc, skb);
8594
8595 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
8596 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
8597 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
8598
8599 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
8600 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
8601 u16 vid;
8602
8603 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
8604 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
8605 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);
8606 else
8607 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
8608
8609 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
8610 }
8611
8612 skb_record_rx_queue(skb, rx_ring->queue_index);
8613
8614 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8615}
8616
8617static unsigned int igb_rx_offset(struct igb_ring *rx_ring)
8618{
8619 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
8620}
8621
8622static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
8623 const unsigned int size, int *rx_buf_pgcnt)
8624{
8625 struct igb_rx_buffer *rx_buffer;
8626
8627 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
8628 *rx_buf_pgcnt =
8629#if (PAGE_SIZE < 8192)
8630 page_count(rx_buffer->page);
8631#else
8632 0;
8633#endif
8634 prefetchw(rx_buffer->page);
8635
8636 /* we are reusing so sync this buffer for CPU use */
8637 dma_sync_single_range_for_cpu(rx_ring->dev,
8638 rx_buffer->dma,
8639 rx_buffer->page_offset,
8640 size,
8641 DMA_FROM_DEVICE);
8642
8643 rx_buffer->pagecnt_bias--;
8644
8645 return rx_buffer;
8646}
8647
8648static void igb_put_rx_buffer(struct igb_ring *rx_ring,
8649 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt)
8650{
8651 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) {
8652 /* hand second half of page back to the ring */
8653 igb_reuse_rx_page(rx_ring, rx_buffer);
8654 } else {
8655 /* We are not reusing the buffer so unmap it and free
8656 * any references we are holding to it
8657 */
8658 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
8659 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
8660 IGB_RX_DMA_ATTR);
8661 __page_frag_cache_drain(rx_buffer->page,
8662 rx_buffer->pagecnt_bias);
8663 }
8664
8665 /* clear contents of rx_buffer */
8666 rx_buffer->page = NULL;
8667}
8668
8669static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8670{
8671 struct igb_adapter *adapter = q_vector->adapter;
8672 struct igb_ring *rx_ring = q_vector->rx.ring;
8673 struct sk_buff *skb = rx_ring->skb;
8674 unsigned int total_bytes = 0, total_packets = 0;
8675 u16 cleaned_count = igb_desc_unused(rx_ring);
8676 unsigned int xdp_xmit = 0;
8677 struct xdp_buff xdp;
8678 u32 frame_sz = 0;
8679 int rx_buf_pgcnt;
8680
8681 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
8682#if (PAGE_SIZE < 8192)
8683 frame_sz = igb_rx_frame_truesize(rx_ring, 0);
8684#endif
8685 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
8686
8687 while (likely(total_packets < budget)) {
8688 union e1000_adv_rx_desc *rx_desc;
8689 struct igb_rx_buffer *rx_buffer;
8690 ktime_t timestamp = 0;
8691 int pkt_offset = 0;
8692 unsigned int size;
8693 void *pktbuf;
8694
8695 /* return some buffers to hardware, one at a time is too slow */
8696 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
8697 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8698 cleaned_count = 0;
8699 }
8700
8701 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
8702 size = le16_to_cpu(rx_desc->wb.upper.length);
8703 if (!size)
8704 break;
8705
8706 /* This memory barrier is needed to keep us from reading
8707 * any other fields out of the rx_desc until we know the
8708 * descriptor has been written back
8709 */
8710 dma_rmb();
8711
8712 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt);
8713 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;
8714
8715 /* pull rx packet timestamp if available and valid */
8716 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
8717 int ts_hdr_len;
8718
8719 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector,
8720 pktbuf, ×tamp);
8721
8722 pkt_offset += ts_hdr_len;
8723 size -= ts_hdr_len;
8724 }
8725
8726 /* retrieve a buffer from the ring */
8727 if (!skb) {
8728 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring);
8729 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring);
8730
8731 xdp_prepare_buff(&xdp, hard_start, offset, size, true);
8732#if (PAGE_SIZE > 4096)
8733 /* At larger PAGE_SIZE, frame_sz depend on len size */
8734 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size);
8735#endif
8736 skb = igb_run_xdp(adapter, rx_ring, &xdp);
8737 }
8738
8739 if (IS_ERR(skb)) {
8740 unsigned int xdp_res = -PTR_ERR(skb);
8741
8742 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) {
8743 xdp_xmit |= xdp_res;
8744 igb_rx_buffer_flip(rx_ring, rx_buffer, size);
8745 } else {
8746 rx_buffer->pagecnt_bias++;
8747 }
8748 total_packets++;
8749 total_bytes += size;
8750 } else if (skb)
8751 igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
8752 else if (ring_uses_build_skb(rx_ring))
8753 skb = igb_build_skb(rx_ring, rx_buffer, &xdp,
8754 timestamp);
8755 else
8756 skb = igb_construct_skb(rx_ring, rx_buffer,
8757 &xdp, timestamp);
8758
8759 /* exit if we failed to retrieve a buffer */
8760 if (!skb) {
8761 rx_ring->rx_stats.alloc_failed++;
8762 rx_buffer->pagecnt_bias++;
8763 break;
8764 }
8765
8766 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt);
8767 cleaned_count++;
8768
8769 /* fetch next buffer in frame if non-eop */
8770 if (igb_is_non_eop(rx_ring, rx_desc))
8771 continue;
8772
8773 /* verify the packet layout is correct */
8774 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
8775 skb = NULL;
8776 continue;
8777 }
8778
8779 /* probably a little skewed due to removing CRC */
8780 total_bytes += skb->len;
8781
8782 /* populate checksum, timestamp, VLAN, and protocol */
8783 igb_process_skb_fields(rx_ring, rx_desc, skb);
8784
8785 napi_gro_receive(&q_vector->napi, skb);
8786
8787 /* reset skb pointer */
8788 skb = NULL;
8789
8790 /* update budget accounting */
8791 total_packets++;
8792 }
8793
8794 /* place incomplete frames back on ring for completion */
8795 rx_ring->skb = skb;
8796
8797 if (xdp_xmit & IGB_XDP_REDIR)
8798 xdp_do_flush();
8799
8800 if (xdp_xmit & IGB_XDP_TX) {
8801 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
8802
8803 igb_xdp_ring_update_tail(tx_ring);
8804 }
8805
8806 u64_stats_update_begin(&rx_ring->rx_syncp);
8807 rx_ring->rx_stats.packets += total_packets;
8808 rx_ring->rx_stats.bytes += total_bytes;
8809 u64_stats_update_end(&rx_ring->rx_syncp);
8810 q_vector->rx.total_packets += total_packets;
8811 q_vector->rx.total_bytes += total_bytes;
8812
8813 if (cleaned_count)
8814 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8815
8816 return total_packets;
8817}
8818
8819static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
8820 struct igb_rx_buffer *bi)
8821{
8822 struct page *page = bi->page;
8823 dma_addr_t dma;
8824
8825 /* since we are recycling buffers we should seldom need to alloc */
8826 if (likely(page))
8827 return true;
8828
8829 /* alloc new page for storage */
8830 page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
8831 if (unlikely(!page)) {
8832 rx_ring->rx_stats.alloc_failed++;
8833 return false;
8834 }
8835
8836 /* map page for use */
8837 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
8838 igb_rx_pg_size(rx_ring),
8839 DMA_FROM_DEVICE,
8840 IGB_RX_DMA_ATTR);
8841
8842 /* if mapping failed free memory back to system since
8843 * there isn't much point in holding memory we can't use
8844 */
8845 if (dma_mapping_error(rx_ring->dev, dma)) {
8846 __free_pages(page, igb_rx_pg_order(rx_ring));
8847
8848 rx_ring->rx_stats.alloc_failed++;
8849 return false;
8850 }
8851
8852 bi->dma = dma;
8853 bi->page = page;
8854 bi->page_offset = igb_rx_offset(rx_ring);
8855 page_ref_add(page, USHRT_MAX - 1);
8856 bi->pagecnt_bias = USHRT_MAX;
8857
8858 return true;
8859}
8860
8861/**
8862 * igb_alloc_rx_buffers - Replace used receive buffers
8863 * @rx_ring: rx descriptor ring to allocate new receive buffers
8864 * @cleaned_count: count of buffers to allocate
8865 **/
8866void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
8867{
8868 union e1000_adv_rx_desc *rx_desc;
8869 struct igb_rx_buffer *bi;
8870 u16 i = rx_ring->next_to_use;
8871 u16 bufsz;
8872
8873 /* nothing to do */
8874 if (!cleaned_count)
8875 return;
8876
8877 rx_desc = IGB_RX_DESC(rx_ring, i);
8878 bi = &rx_ring->rx_buffer_info[i];
8879 i -= rx_ring->count;
8880
8881 bufsz = igb_rx_bufsz(rx_ring);
8882
8883 do {
8884 if (!igb_alloc_mapped_page(rx_ring, bi))
8885 break;
8886
8887 /* sync the buffer for use by the device */
8888 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
8889 bi->page_offset, bufsz,
8890 DMA_FROM_DEVICE);
8891
8892 /* Refresh the desc even if buffer_addrs didn't change
8893 * because each write-back erases this info.
8894 */
8895 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
8896
8897 rx_desc++;
8898 bi++;
8899 i++;
8900 if (unlikely(!i)) {
8901 rx_desc = IGB_RX_DESC(rx_ring, 0);
8902 bi = rx_ring->rx_buffer_info;
8903 i -= rx_ring->count;
8904 }
8905
8906 /* clear the length for the next_to_use descriptor */
8907 rx_desc->wb.upper.length = 0;
8908
8909 cleaned_count--;
8910 } while (cleaned_count);
8911
8912 i += rx_ring->count;
8913
8914 if (rx_ring->next_to_use != i) {
8915 /* record the next descriptor to use */
8916 rx_ring->next_to_use = i;
8917
8918 /* update next to alloc since we have filled the ring */
8919 rx_ring->next_to_alloc = i;
8920
8921 /* Force memory writes to complete before letting h/w
8922 * know there are new descriptors to fetch. (Only
8923 * applicable for weak-ordered memory model archs,
8924 * such as IA-64).
8925 */
8926 dma_wmb();
8927 writel(i, rx_ring->tail);
8928 }
8929}
8930
8931/**
8932 * igb_mii_ioctl -
8933 * @netdev: pointer to netdev struct
8934 * @ifr: interface structure
8935 * @cmd: ioctl command to execute
8936 **/
8937static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8938{
8939 struct igb_adapter *adapter = netdev_priv(netdev);
8940 struct mii_ioctl_data *data = if_mii(ifr);
8941
8942 if (adapter->hw.phy.media_type != e1000_media_type_copper)
8943 return -EOPNOTSUPP;
8944
8945 switch (cmd) {
8946 case SIOCGMIIPHY:
8947 data->phy_id = adapter->hw.phy.addr;
8948 break;
8949 case SIOCGMIIREG:
8950 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
8951 &data->val_out))
8952 return -EIO;
8953 break;
8954 case SIOCSMIIREG:
8955 default:
8956 return -EOPNOTSUPP;
8957 }
8958 return 0;
8959}
8960
8961/**
8962 * igb_ioctl -
8963 * @netdev: pointer to netdev struct
8964 * @ifr: interface structure
8965 * @cmd: ioctl command to execute
8966 **/
8967static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8968{
8969 switch (cmd) {
8970 case SIOCGMIIPHY:
8971 case SIOCGMIIREG:
8972 case SIOCSMIIREG:
8973 return igb_mii_ioctl(netdev, ifr, cmd);
8974 case SIOCGHWTSTAMP:
8975 return igb_ptp_get_ts_config(netdev, ifr);
8976 case SIOCSHWTSTAMP:
8977 return igb_ptp_set_ts_config(netdev, ifr);
8978 default:
8979 return -EOPNOTSUPP;
8980 }
8981}
8982
8983void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8984{
8985 struct igb_adapter *adapter = hw->back;
8986
8987 pci_read_config_word(adapter->pdev, reg, value);
8988}
8989
8990void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8991{
8992 struct igb_adapter *adapter = hw->back;
8993
8994 pci_write_config_word(adapter->pdev, reg, *value);
8995}
8996
8997s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
8998{
8999 struct igb_adapter *adapter = hw->back;
9000
9001 if (pcie_capability_read_word(adapter->pdev, reg, value))
9002 return -E1000_ERR_CONFIG;
9003
9004 return 0;
9005}
9006
9007s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9008{
9009 struct igb_adapter *adapter = hw->back;
9010
9011 if (pcie_capability_write_word(adapter->pdev, reg, *value))
9012 return -E1000_ERR_CONFIG;
9013
9014 return 0;
9015}
9016
9017static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9018{
9019 struct igb_adapter *adapter = netdev_priv(netdev);
9020 struct e1000_hw *hw = &adapter->hw;
9021 u32 ctrl, rctl;
9022 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9023
9024 if (enable) {
9025 /* enable VLAN tag insert/strip */
9026 ctrl = rd32(E1000_CTRL);
9027 ctrl |= E1000_CTRL_VME;
9028 wr32(E1000_CTRL, ctrl);
9029
9030 /* Disable CFI check */
9031 rctl = rd32(E1000_RCTL);
9032 rctl &= ~E1000_RCTL_CFIEN;
9033 wr32(E1000_RCTL, rctl);
9034 } else {
9035 /* disable VLAN tag insert/strip */
9036 ctrl = rd32(E1000_CTRL);
9037 ctrl &= ~E1000_CTRL_VME;
9038 wr32(E1000_CTRL, ctrl);
9039 }
9040
9041 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9042}
9043
9044static int igb_vlan_rx_add_vid(struct net_device *netdev,
9045 __be16 proto, u16 vid)
9046{
9047 struct igb_adapter *adapter = netdev_priv(netdev);
9048 struct e1000_hw *hw = &adapter->hw;
9049 int pf_id = adapter->vfs_allocated_count;
9050
9051 /* add the filter since PF can receive vlans w/o entry in vlvf */
9052 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9053 igb_vfta_set(hw, vid, pf_id, true, !!vid);
9054
9055 set_bit(vid, adapter->active_vlans);
9056
9057 return 0;
9058}
9059
9060static int igb_vlan_rx_kill_vid(struct net_device *netdev,
9061 __be16 proto, u16 vid)
9062{
9063 struct igb_adapter *adapter = netdev_priv(netdev);
9064 int pf_id = adapter->vfs_allocated_count;
9065 struct e1000_hw *hw = &adapter->hw;
9066
9067 /* remove VID from filter table */
9068 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9069 igb_vfta_set(hw, vid, pf_id, false, true);
9070
9071 clear_bit(vid, adapter->active_vlans);
9072
9073 return 0;
9074}
9075
9076static void igb_restore_vlan(struct igb_adapter *adapter)
9077{
9078 u16 vid = 1;
9079
9080 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
9081 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
9082
9083 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
9084 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9085}
9086
9087int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9088{
9089 struct pci_dev *pdev = adapter->pdev;
9090 struct e1000_mac_info *mac = &adapter->hw.mac;
9091
9092 mac->autoneg = 0;
9093
9094 /* Make sure dplx is at most 1 bit and lsb of speed is not set
9095 * for the switch() below to work
9096 */
9097 if ((spd & 1) || (dplx & ~1))
9098 goto err_inval;
9099
9100 /* Fiber NIC's only allow 1000 gbps Full duplex
9101 * and 100Mbps Full duplex for 100baseFx sfp
9102 */
9103 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
9104 switch (spd + dplx) {
9105 case SPEED_10 + DUPLEX_HALF:
9106 case SPEED_10 + DUPLEX_FULL:
9107 case SPEED_100 + DUPLEX_HALF:
9108 goto err_inval;
9109 default:
9110 break;
9111 }
9112 }
9113
9114 switch (spd + dplx) {
9115 case SPEED_10 + DUPLEX_HALF:
9116 mac->forced_speed_duplex = ADVERTISE_10_HALF;
9117 break;
9118 case SPEED_10 + DUPLEX_FULL:
9119 mac->forced_speed_duplex = ADVERTISE_10_FULL;
9120 break;
9121 case SPEED_100 + DUPLEX_HALF:
9122 mac->forced_speed_duplex = ADVERTISE_100_HALF;
9123 break;
9124 case SPEED_100 + DUPLEX_FULL:
9125 mac->forced_speed_duplex = ADVERTISE_100_FULL;
9126 break;
9127 case SPEED_1000 + DUPLEX_FULL:
9128 mac->autoneg = 1;
9129 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
9130 break;
9131 case SPEED_1000 + DUPLEX_HALF: /* not supported */
9132 default:
9133 goto err_inval;
9134 }
9135
9136 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
9137 adapter->hw.phy.mdix = AUTO_ALL_MODES;
9138
9139 return 0;
9140
9141err_inval:
9142 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9143 return -EINVAL;
9144}
9145
9146static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
9147 bool runtime)
9148{
9149 struct net_device *netdev = pci_get_drvdata(pdev);
9150 struct igb_adapter *adapter = netdev_priv(netdev);
9151 struct e1000_hw *hw = &adapter->hw;
9152 u32 ctrl, rctl, status;
9153 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9154 bool wake;
9155
9156 rtnl_lock();
9157 netif_device_detach(netdev);
9158
9159 if (netif_running(netdev))
9160 __igb_close(netdev, true);
9161
9162 igb_ptp_suspend(adapter);
9163
9164 igb_clear_interrupt_scheme(adapter);
9165 rtnl_unlock();
9166
9167 status = rd32(E1000_STATUS);
9168 if (status & E1000_STATUS_LU)
9169 wufc &= ~E1000_WUFC_LNKC;
9170
9171 if (wufc) {
9172 igb_setup_rctl(adapter);
9173 igb_set_rx_mode(netdev);
9174
9175 /* turn on all-multi mode if wake on multicast is enabled */
9176 if (wufc & E1000_WUFC_MC) {
9177 rctl = rd32(E1000_RCTL);
9178 rctl |= E1000_RCTL_MPE;
9179 wr32(E1000_RCTL, rctl);
9180 }
9181
9182 ctrl = rd32(E1000_CTRL);
9183 ctrl |= E1000_CTRL_ADVD3WUC;
9184 wr32(E1000_CTRL, ctrl);
9185
9186 /* Allow time for pending master requests to run */
9187 igb_disable_pcie_master(hw);
9188
9189 wr32(E1000_WUC, E1000_WUC_PME_EN);
9190 wr32(E1000_WUFC, wufc);
9191 } else {
9192 wr32(E1000_WUC, 0);
9193 wr32(E1000_WUFC, 0);
9194 }
9195
9196 wake = wufc || adapter->en_mng_pt;
9197 if (!wake)
9198 igb_power_down_link(adapter);
9199 else
9200 igb_power_up_link(adapter);
9201
9202 if (enable_wake)
9203 *enable_wake = wake;
9204
9205 /* Release control of h/w to f/w. If f/w is AMT enabled, this
9206 * would have already happened in close and is redundant.
9207 */
9208 igb_release_hw_control(adapter);
9209
9210 pci_disable_device(pdev);
9211
9212 return 0;
9213}
9214
9215static void igb_deliver_wake_packet(struct net_device *netdev)
9216{
9217 struct igb_adapter *adapter = netdev_priv(netdev);
9218 struct e1000_hw *hw = &adapter->hw;
9219 struct sk_buff *skb;
9220 u32 wupl;
9221
9222 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
9223
9224 /* WUPM stores only the first 128 bytes of the wake packet.
9225 * Read the packet only if we have the whole thing.
9226 */
9227 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
9228 return;
9229
9230 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
9231 if (!skb)
9232 return;
9233
9234 skb_put(skb, wupl);
9235
9236 /* Ensure reads are 32-bit aligned */
9237 wupl = roundup(wupl, 4);
9238
9239 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
9240
9241 skb->protocol = eth_type_trans(skb, netdev);
9242 netif_rx(skb);
9243}
9244
9245static int __maybe_unused igb_suspend(struct device *dev)
9246{
9247 return __igb_shutdown(to_pci_dev(dev), NULL, 0);
9248}
9249
9250static int __maybe_unused igb_resume(struct device *dev)
9251{
9252 struct pci_dev *pdev = to_pci_dev(dev);
9253 struct net_device *netdev = pci_get_drvdata(pdev);
9254 struct igb_adapter *adapter = netdev_priv(netdev);
9255 struct e1000_hw *hw = &adapter->hw;
9256 u32 err, val;
9257
9258 pci_set_power_state(pdev, PCI_D0);
9259 pci_restore_state(pdev);
9260 pci_save_state(pdev);
9261
9262 if (!pci_device_is_present(pdev))
9263 return -ENODEV;
9264 err = pci_enable_device_mem(pdev);
9265 if (err) {
9266 dev_err(&pdev->dev,
9267 "igb: Cannot enable PCI device from suspend\n");
9268 return err;
9269 }
9270 pci_set_master(pdev);
9271
9272 pci_enable_wake(pdev, PCI_D3hot, 0);
9273 pci_enable_wake(pdev, PCI_D3cold, 0);
9274
9275 if (igb_init_interrupt_scheme(adapter, true)) {
9276 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9277 return -ENOMEM;
9278 }
9279
9280 igb_reset(adapter);
9281
9282 /* let the f/w know that the h/w is now under the control of the
9283 * driver.
9284 */
9285 igb_get_hw_control(adapter);
9286
9287 val = rd32(E1000_WUS);
9288 if (val & WAKE_PKT_WUS)
9289 igb_deliver_wake_packet(netdev);
9290
9291 wr32(E1000_WUS, ~0);
9292
9293 rtnl_lock();
9294 if (!err && netif_running(netdev))
9295 err = __igb_open(netdev, true);
9296
9297 if (!err)
9298 netif_device_attach(netdev);
9299 rtnl_unlock();
9300
9301 return err;
9302}
9303
9304static int __maybe_unused igb_runtime_idle(struct device *dev)
9305{
9306 struct net_device *netdev = dev_get_drvdata(dev);
9307 struct igb_adapter *adapter = netdev_priv(netdev);
9308
9309 if (!igb_has_link(adapter))
9310 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
9311
9312 return -EBUSY;
9313}
9314
9315static int __maybe_unused igb_runtime_suspend(struct device *dev)
9316{
9317 return __igb_shutdown(to_pci_dev(dev), NULL, 1);
9318}
9319
9320static int __maybe_unused igb_runtime_resume(struct device *dev)
9321{
9322 return igb_resume(dev);
9323}
9324
9325static void igb_shutdown(struct pci_dev *pdev)
9326{
9327 bool wake;
9328
9329 __igb_shutdown(pdev, &wake, 0);
9330
9331 if (system_state == SYSTEM_POWER_OFF) {
9332 pci_wake_from_d3(pdev, wake);
9333 pci_set_power_state(pdev, PCI_D3hot);
9334 }
9335}
9336
9337#ifdef CONFIG_PCI_IOV
9338static int igb_sriov_reinit(struct pci_dev *dev)
9339{
9340 struct net_device *netdev = pci_get_drvdata(dev);
9341 struct igb_adapter *adapter = netdev_priv(netdev);
9342 struct pci_dev *pdev = adapter->pdev;
9343
9344 rtnl_lock();
9345
9346 if (netif_running(netdev))
9347 igb_close(netdev);
9348 else
9349 igb_reset(adapter);
9350
9351 igb_clear_interrupt_scheme(adapter);
9352
9353 igb_init_queue_configuration(adapter);
9354
9355 if (igb_init_interrupt_scheme(adapter, true)) {
9356 rtnl_unlock();
9357 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9358 return -ENOMEM;
9359 }
9360
9361 if (netif_running(netdev))
9362 igb_open(netdev);
9363
9364 rtnl_unlock();
9365
9366 return 0;
9367}
9368
9369static int igb_pci_disable_sriov(struct pci_dev *dev)
9370{
9371 int err = igb_disable_sriov(dev);
9372
9373 if (!err)
9374 err = igb_sriov_reinit(dev);
9375
9376 return err;
9377}
9378
9379static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
9380{
9381 int err = igb_enable_sriov(dev, num_vfs);
9382
9383 if (err)
9384 goto out;
9385
9386 err = igb_sriov_reinit(dev);
9387 if (!err)
9388 return num_vfs;
9389
9390out:
9391 return err;
9392}
9393
9394#endif
9395static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
9396{
9397#ifdef CONFIG_PCI_IOV
9398 if (num_vfs == 0)
9399 return igb_pci_disable_sriov(dev);
9400 else
9401 return igb_pci_enable_sriov(dev, num_vfs);
9402#endif
9403 return 0;
9404}
9405
9406/**
9407 * igb_io_error_detected - called when PCI error is detected
9408 * @pdev: Pointer to PCI device
9409 * @state: The current pci connection state
9410 *
9411 * This function is called after a PCI bus error affecting
9412 * this device has been detected.
9413 **/
9414static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
9415 pci_channel_state_t state)
9416{
9417 struct net_device *netdev = pci_get_drvdata(pdev);
9418 struct igb_adapter *adapter = netdev_priv(netdev);
9419
9420 netif_device_detach(netdev);
9421
9422 if (state == pci_channel_io_perm_failure)
9423 return PCI_ERS_RESULT_DISCONNECT;
9424
9425 if (netif_running(netdev))
9426 igb_down(adapter);
9427 pci_disable_device(pdev);
9428
9429 /* Request a slot slot reset. */
9430 return PCI_ERS_RESULT_NEED_RESET;
9431}
9432
9433/**
9434 * igb_io_slot_reset - called after the pci bus has been reset.
9435 * @pdev: Pointer to PCI device
9436 *
9437 * Restart the card from scratch, as if from a cold-boot. Implementation
9438 * resembles the first-half of the igb_resume routine.
9439 **/
9440static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
9441{
9442 struct net_device *netdev = pci_get_drvdata(pdev);
9443 struct igb_adapter *adapter = netdev_priv(netdev);
9444 struct e1000_hw *hw = &adapter->hw;
9445 pci_ers_result_t result;
9446
9447 if (pci_enable_device_mem(pdev)) {
9448 dev_err(&pdev->dev,
9449 "Cannot re-enable PCI device after reset.\n");
9450 result = PCI_ERS_RESULT_DISCONNECT;
9451 } else {
9452 pci_set_master(pdev);
9453 pci_restore_state(pdev);
9454 pci_save_state(pdev);
9455
9456 pci_enable_wake(pdev, PCI_D3hot, 0);
9457 pci_enable_wake(pdev, PCI_D3cold, 0);
9458
9459 /* In case of PCI error, adapter lose its HW address
9460 * so we should re-assign it here.
9461 */
9462 hw->hw_addr = adapter->io_addr;
9463
9464 igb_reset(adapter);
9465 wr32(E1000_WUS, ~0);
9466 result = PCI_ERS_RESULT_RECOVERED;
9467 }
9468
9469 return result;
9470}
9471
9472/**
9473 * igb_io_resume - called when traffic can start flowing again.
9474 * @pdev: Pointer to PCI device
9475 *
9476 * This callback is called when the error recovery driver tells us that
9477 * its OK to resume normal operation. Implementation resembles the
9478 * second-half of the igb_resume routine.
9479 */
9480static void igb_io_resume(struct pci_dev *pdev)
9481{
9482 struct net_device *netdev = pci_get_drvdata(pdev);
9483 struct igb_adapter *adapter = netdev_priv(netdev);
9484
9485 if (netif_running(netdev)) {
9486 if (igb_up(adapter)) {
9487 dev_err(&pdev->dev, "igb_up failed after reset\n");
9488 return;
9489 }
9490 }
9491
9492 netif_device_attach(netdev);
9493
9494 /* let the f/w know that the h/w is now under the control of the
9495 * driver.
9496 */
9497 igb_get_hw_control(adapter);
9498}
9499
9500/**
9501 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
9502 * @adapter: Pointer to adapter structure
9503 * @index: Index of the RAR entry which need to be synced with MAC table
9504 **/
9505static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
9506{
9507 struct e1000_hw *hw = &adapter->hw;
9508 u32 rar_low, rar_high;
9509 u8 *addr = adapter->mac_table[index].addr;
9510
9511 /* HW expects these to be in network order when they are plugged
9512 * into the registers which are little endian. In order to guarantee
9513 * that ordering we need to do an leXX_to_cpup here in order to be
9514 * ready for the byteswap that occurs with writel
9515 */
9516 rar_low = le32_to_cpup((__le32 *)(addr));
9517 rar_high = le16_to_cpup((__le16 *)(addr + 4));
9518
9519 /* Indicate to hardware the Address is Valid. */
9520 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
9521 if (is_valid_ether_addr(addr))
9522 rar_high |= E1000_RAH_AV;
9523
9524 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
9525 rar_high |= E1000_RAH_ASEL_SRC_ADDR;
9526
9527 switch (hw->mac.type) {
9528 case e1000_82575:
9529 case e1000_i210:
9530 if (adapter->mac_table[index].state &
9531 IGB_MAC_STATE_QUEUE_STEERING)
9532 rar_high |= E1000_RAH_QSEL_ENABLE;
9533
9534 rar_high |= E1000_RAH_POOL_1 *
9535 adapter->mac_table[index].queue;
9536 break;
9537 default:
9538 rar_high |= E1000_RAH_POOL_1 <<
9539 adapter->mac_table[index].queue;
9540 break;
9541 }
9542 }
9543
9544 wr32(E1000_RAL(index), rar_low);
9545 wrfl();
9546 wr32(E1000_RAH(index), rar_high);
9547 wrfl();
9548}
9549
9550static int igb_set_vf_mac(struct igb_adapter *adapter,
9551 int vf, unsigned char *mac_addr)
9552{
9553 struct e1000_hw *hw = &adapter->hw;
9554 /* VF MAC addresses start at end of receive addresses and moves
9555 * towards the first, as a result a collision should not be possible
9556 */
9557 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
9558 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
9559
9560 ether_addr_copy(vf_mac_addr, mac_addr);
9561 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
9562 adapter->mac_table[rar_entry].queue = vf;
9563 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
9564 igb_rar_set_index(adapter, rar_entry);
9565
9566 return 0;
9567}
9568
9569static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
9570{
9571 struct igb_adapter *adapter = netdev_priv(netdev);
9572
9573 if (vf >= adapter->vfs_allocated_count)
9574 return -EINVAL;
9575
9576 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
9577 * flag and allows to overwrite the MAC via VF netdev. This
9578 * is necessary to allow libvirt a way to restore the original
9579 * MAC after unbinding vfio-pci and reloading igbvf after shutting
9580 * down a VM.
9581 */
9582 if (is_zero_ether_addr(mac)) {
9583 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
9584 dev_info(&adapter->pdev->dev,
9585 "remove administratively set MAC on VF %d\n",
9586 vf);
9587 } else if (is_valid_ether_addr(mac)) {
9588 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
9589 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
9590 mac, vf);
9591 dev_info(&adapter->pdev->dev,
9592 "Reload the VF driver to make this change effective.");
9593 /* Generate additional warning if PF is down */
9594 if (test_bit(__IGB_DOWN, &adapter->state)) {
9595 dev_warn(&adapter->pdev->dev,
9596 "The VF MAC address has been set, but the PF device is not up.\n");
9597 dev_warn(&adapter->pdev->dev,
9598 "Bring the PF device up before attempting to use the VF device.\n");
9599 }
9600 } else {
9601 return -EINVAL;
9602 }
9603 return igb_set_vf_mac(adapter, vf, mac);
9604}
9605
9606static int igb_link_mbps(int internal_link_speed)
9607{
9608 switch (internal_link_speed) {
9609 case SPEED_100:
9610 return 100;
9611 case SPEED_1000:
9612 return 1000;
9613 default:
9614 return 0;
9615 }
9616}
9617
9618static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
9619 int link_speed)
9620{
9621 int rf_dec, rf_int;
9622 u32 bcnrc_val;
9623
9624 if (tx_rate != 0) {
9625 /* Calculate the rate factor values to set */
9626 rf_int = link_speed / tx_rate;
9627 rf_dec = (link_speed - (rf_int * tx_rate));
9628 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
9629 tx_rate;
9630
9631 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
9632 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
9633 E1000_RTTBCNRC_RF_INT_MASK);
9634 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
9635 } else {
9636 bcnrc_val = 0;
9637 }
9638
9639 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
9640 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
9641 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
9642 */
9643 wr32(E1000_RTTBCNRM, 0x14);
9644 wr32(E1000_RTTBCNRC, bcnrc_val);
9645}
9646
9647static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
9648{
9649 int actual_link_speed, i;
9650 bool reset_rate = false;
9651
9652 /* VF TX rate limit was not set or not supported */
9653 if ((adapter->vf_rate_link_speed == 0) ||
9654 (adapter->hw.mac.type != e1000_82576))
9655 return;
9656
9657 actual_link_speed = igb_link_mbps(adapter->link_speed);
9658 if (actual_link_speed != adapter->vf_rate_link_speed) {
9659 reset_rate = true;
9660 adapter->vf_rate_link_speed = 0;
9661 dev_info(&adapter->pdev->dev,
9662 "Link speed has been changed. VF Transmit rate is disabled\n");
9663 }
9664
9665 for (i = 0; i < adapter->vfs_allocated_count; i++) {
9666 if (reset_rate)
9667 adapter->vf_data[i].tx_rate = 0;
9668
9669 igb_set_vf_rate_limit(&adapter->hw, i,
9670 adapter->vf_data[i].tx_rate,
9671 actual_link_speed);
9672 }
9673}
9674
9675static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
9676 int min_tx_rate, int max_tx_rate)
9677{
9678 struct igb_adapter *adapter = netdev_priv(netdev);
9679 struct e1000_hw *hw = &adapter->hw;
9680 int actual_link_speed;
9681
9682 if (hw->mac.type != e1000_82576)
9683 return -EOPNOTSUPP;
9684
9685 if (min_tx_rate)
9686 return -EINVAL;
9687
9688 actual_link_speed = igb_link_mbps(adapter->link_speed);
9689 if ((vf >= adapter->vfs_allocated_count) ||
9690 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
9691 (max_tx_rate < 0) ||
9692 (max_tx_rate > actual_link_speed))
9693 return -EINVAL;
9694
9695 adapter->vf_rate_link_speed = actual_link_speed;
9696 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
9697 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
9698
9699 return 0;
9700}
9701
9702static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
9703 bool setting)
9704{
9705 struct igb_adapter *adapter = netdev_priv(netdev);
9706 struct e1000_hw *hw = &adapter->hw;
9707 u32 reg_val, reg_offset;
9708
9709 if (!adapter->vfs_allocated_count)
9710 return -EOPNOTSUPP;
9711
9712 if (vf >= adapter->vfs_allocated_count)
9713 return -EINVAL;
9714
9715 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
9716 reg_val = rd32(reg_offset);
9717 if (setting)
9718 reg_val |= (BIT(vf) |
9719 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9720 else
9721 reg_val &= ~(BIT(vf) |
9722 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9723 wr32(reg_offset, reg_val);
9724
9725 adapter->vf_data[vf].spoofchk_enabled = setting;
9726 return 0;
9727}
9728
9729static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
9730{
9731 struct igb_adapter *adapter = netdev_priv(netdev);
9732
9733 if (vf >= adapter->vfs_allocated_count)
9734 return -EINVAL;
9735 if (adapter->vf_data[vf].trusted == setting)
9736 return 0;
9737
9738 adapter->vf_data[vf].trusted = setting;
9739
9740 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
9741 vf, setting ? "" : "not ");
9742 return 0;
9743}
9744
9745static int igb_ndo_get_vf_config(struct net_device *netdev,
9746 int vf, struct ifla_vf_info *ivi)
9747{
9748 struct igb_adapter *adapter = netdev_priv(netdev);
9749 if (vf >= adapter->vfs_allocated_count)
9750 return -EINVAL;
9751 ivi->vf = vf;
9752 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
9753 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
9754 ivi->min_tx_rate = 0;
9755 ivi->vlan = adapter->vf_data[vf].pf_vlan;
9756 ivi->qos = adapter->vf_data[vf].pf_qos;
9757 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
9758 ivi->trusted = adapter->vf_data[vf].trusted;
9759 return 0;
9760}
9761
9762static void igb_vmm_control(struct igb_adapter *adapter)
9763{
9764 struct e1000_hw *hw = &adapter->hw;
9765 u32 reg;
9766
9767 switch (hw->mac.type) {
9768 case e1000_82575:
9769 case e1000_i210:
9770 case e1000_i211:
9771 case e1000_i354:
9772 default:
9773 /* replication is not supported for 82575 */
9774 return;
9775 case e1000_82576:
9776 /* notify HW that the MAC is adding vlan tags */
9777 reg = rd32(E1000_DTXCTL);
9778 reg |= E1000_DTXCTL_VLAN_ADDED;
9779 wr32(E1000_DTXCTL, reg);
9780 fallthrough;
9781 case e1000_82580:
9782 /* enable replication vlan tag stripping */
9783 reg = rd32(E1000_RPLOLR);
9784 reg |= E1000_RPLOLR_STRVLAN;
9785 wr32(E1000_RPLOLR, reg);
9786 fallthrough;
9787 case e1000_i350:
9788 /* none of the above registers are supported by i350 */
9789 break;
9790 }
9791
9792 if (adapter->vfs_allocated_count) {
9793 igb_vmdq_set_loopback_pf(hw, true);
9794 igb_vmdq_set_replication_pf(hw, true);
9795 igb_vmdq_set_anti_spoofing_pf(hw, true,
9796 adapter->vfs_allocated_count);
9797 } else {
9798 igb_vmdq_set_loopback_pf(hw, false);
9799 igb_vmdq_set_replication_pf(hw, false);
9800 }
9801}
9802
9803static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9804{
9805 struct e1000_hw *hw = &adapter->hw;
9806 u32 dmac_thr;
9807 u16 hwm;
9808
9809 if (hw->mac.type > e1000_82580) {
9810 if (adapter->flags & IGB_FLAG_DMAC) {
9811 u32 reg;
9812
9813 /* force threshold to 0. */
9814 wr32(E1000_DMCTXTH, 0);
9815
9816 /* DMA Coalescing high water mark needs to be greater
9817 * than the Rx threshold. Set hwm to PBA - max frame
9818 * size in 16B units, capping it at PBA - 6KB.
9819 */
9820 hwm = 64 * (pba - 6);
9821 reg = rd32(E1000_FCRTC);
9822 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9823 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
9824 & E1000_FCRTC_RTH_COAL_MASK);
9825 wr32(E1000_FCRTC, reg);
9826
9827 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
9828 * frame size, capping it at PBA - 10KB.
9829 */
9830 dmac_thr = pba - 10;
9831 reg = rd32(E1000_DMACR);
9832 reg &= ~E1000_DMACR_DMACTHR_MASK;
9833 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
9834 & E1000_DMACR_DMACTHR_MASK);
9835
9836 /* transition to L0x or L1 if available..*/
9837 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
9838
9839 /* watchdog timer= +-1000 usec in 32usec intervals */
9840 reg |= (1000 >> 5);
9841
9842 /* Disable BMC-to-OS Watchdog Enable */
9843 if (hw->mac.type != e1000_i354)
9844 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
9845
9846 wr32(E1000_DMACR, reg);
9847
9848 /* no lower threshold to disable
9849 * coalescing(smart fifb)-UTRESH=0
9850 */
9851 wr32(E1000_DMCRTRH, 0);
9852
9853 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
9854
9855 wr32(E1000_DMCTLX, reg);
9856
9857 /* free space in tx packet buffer to wake from
9858 * DMA coal
9859 */
9860 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
9861 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
9862
9863 /* make low power state decision controlled
9864 * by DMA coal
9865 */
9866 reg = rd32(E1000_PCIEMISC);
9867 reg &= ~E1000_PCIEMISC_LX_DECISION;
9868 wr32(E1000_PCIEMISC, reg);
9869 } /* endif adapter->dmac is not disabled */
9870 } else if (hw->mac.type == e1000_82580) {
9871 u32 reg = rd32(E1000_PCIEMISC);
9872
9873 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
9874 wr32(E1000_DMACR, 0);
9875 }
9876}
9877
9878/**
9879 * igb_read_i2c_byte - Reads 8 bit word over I2C
9880 * @hw: pointer to hardware structure
9881 * @byte_offset: byte offset to read
9882 * @dev_addr: device address
9883 * @data: value read
9884 *
9885 * Performs byte read operation over I2C interface at
9886 * a specified device address.
9887 **/
9888s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9889 u8 dev_addr, u8 *data)
9890{
9891 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9892 struct i2c_client *this_client = adapter->i2c_client;
9893 s32 status;
9894 u16 swfw_mask = 0;
9895
9896 if (!this_client)
9897 return E1000_ERR_I2C;
9898
9899 swfw_mask = E1000_SWFW_PHY0_SM;
9900
9901 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9902 return E1000_ERR_SWFW_SYNC;
9903
9904 status = i2c_smbus_read_byte_data(this_client, byte_offset);
9905 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9906
9907 if (status < 0)
9908 return E1000_ERR_I2C;
9909 else {
9910 *data = status;
9911 return 0;
9912 }
9913}
9914
9915/**
9916 * igb_write_i2c_byte - Writes 8 bit word over I2C
9917 * @hw: pointer to hardware structure
9918 * @byte_offset: byte offset to write
9919 * @dev_addr: device address
9920 * @data: value to write
9921 *
9922 * Performs byte write operation over I2C interface at
9923 * a specified device address.
9924 **/
9925s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9926 u8 dev_addr, u8 data)
9927{
9928 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9929 struct i2c_client *this_client = adapter->i2c_client;
9930 s32 status;
9931 u16 swfw_mask = E1000_SWFW_PHY0_SM;
9932
9933 if (!this_client)
9934 return E1000_ERR_I2C;
9935
9936 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9937 return E1000_ERR_SWFW_SYNC;
9938 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
9939 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9940
9941 if (status)
9942 return E1000_ERR_I2C;
9943 else
9944 return 0;
9945
9946}
9947
9948int igb_reinit_queues(struct igb_adapter *adapter)
9949{
9950 struct net_device *netdev = adapter->netdev;
9951 struct pci_dev *pdev = adapter->pdev;
9952 int err = 0;
9953
9954 if (netif_running(netdev))
9955 igb_close(netdev);
9956
9957 igb_reset_interrupt_capability(adapter);
9958
9959 if (igb_init_interrupt_scheme(adapter, true)) {
9960 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9961 return -ENOMEM;
9962 }
9963
9964 if (netif_running(netdev))
9965 err = igb_open(netdev);
9966
9967 return err;
9968}
9969
9970static void igb_nfc_filter_exit(struct igb_adapter *adapter)
9971{
9972 struct igb_nfc_filter *rule;
9973
9974 spin_lock(&adapter->nfc_lock);
9975
9976 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9977 igb_erase_filter(adapter, rule);
9978
9979 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node)
9980 igb_erase_filter(adapter, rule);
9981
9982 spin_unlock(&adapter->nfc_lock);
9983}
9984
9985static void igb_nfc_filter_restore(struct igb_adapter *adapter)
9986{
9987 struct igb_nfc_filter *rule;
9988
9989 spin_lock(&adapter->nfc_lock);
9990
9991 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9992 igb_add_filter(adapter, rule);
9993
9994 spin_unlock(&adapter->nfc_lock);
9995}
9996/* igb_main.c */