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1/*
2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 *
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
8
9/*
10 * Handle hardware traps and faults.
11 */
12#include <linux/interrupt.h>
13#include <linux/kallsyms.h>
14#include <linux/spinlock.h>
15#include <linux/kprobes.h>
16#include <linux/uaccess.h>
17#include <linux/kdebug.h>
18#include <linux/kgdb.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/ptrace.h>
22#include <linux/string.h>
23#include <linux/delay.h>
24#include <linux/errno.h>
25#include <linux/kexec.h>
26#include <linux/sched.h>
27#include <linux/timer.h>
28#include <linux/init.h>
29#include <linux/bug.h>
30#include <linux/nmi.h>
31#include <linux/mm.h>
32#include <linux/smp.h>
33#include <linux/io.h>
34
35#ifdef CONFIG_EISA
36#include <linux/ioport.h>
37#include <linux/eisa.h>
38#endif
39
40#if defined(CONFIG_EDAC)
41#include <linux/edac.h>
42#endif
43
44#include <asm/kmemcheck.h>
45#include <asm/stacktrace.h>
46#include <asm/processor.h>
47#include <asm/debugreg.h>
48#include <linux/atomic.h>
49#include <asm/ftrace.h>
50#include <asm/traps.h>
51#include <asm/desc.h>
52#include <asm/i387.h>
53#include <asm/fpu-internal.h>
54#include <asm/mce.h>
55
56#include <asm/mach_traps.h>
57
58#ifdef CONFIG_X86_64
59#include <asm/x86_init.h>
60#include <asm/pgalloc.h>
61#include <asm/proto.h>
62#else
63#include <asm/processor-flags.h>
64#include <asm/setup.h>
65
66asmlinkage int system_call(void);
67
68/* Do we ignore FPU interrupts ? */
69char ignore_fpu_irq;
70
71/*
72 * The IDT has to be page-aligned to simplify the Pentium
73 * F0 0F bug workaround.
74 */
75gate_desc idt_table[NR_VECTORS] __page_aligned_data = { { { { 0, 0 } } }, };
76#endif
77
78DECLARE_BITMAP(used_vectors, NR_VECTORS);
79EXPORT_SYMBOL_GPL(used_vectors);
80
81static inline void conditional_sti(struct pt_regs *regs)
82{
83 if (regs->flags & X86_EFLAGS_IF)
84 local_irq_enable();
85}
86
87static inline void preempt_conditional_sti(struct pt_regs *regs)
88{
89 inc_preempt_count();
90 if (regs->flags & X86_EFLAGS_IF)
91 local_irq_enable();
92}
93
94static inline void conditional_cli(struct pt_regs *regs)
95{
96 if (regs->flags & X86_EFLAGS_IF)
97 local_irq_disable();
98}
99
100static inline void preempt_conditional_cli(struct pt_regs *regs)
101{
102 if (regs->flags & X86_EFLAGS_IF)
103 local_irq_disable();
104 dec_preempt_count();
105}
106
107static void __kprobes
108do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
109 long error_code, siginfo_t *info)
110{
111 struct task_struct *tsk = current;
112
113#ifdef CONFIG_X86_32
114 if (regs->flags & X86_VM_MASK) {
115 /*
116 * traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
117 * On nmi (interrupt 2), do_trap should not be called.
118 */
119 if (trapnr < X86_TRAP_UD)
120 goto vm86_trap;
121 goto trap_signal;
122 }
123#endif
124
125 if (!user_mode(regs))
126 goto kernel_trap;
127
128#ifdef CONFIG_X86_32
129trap_signal:
130#endif
131 /*
132 * We want error_code and trap_nr set for userspace faults and
133 * kernelspace faults which result in die(), but not
134 * kernelspace faults which are fixed up. die() gives the
135 * process no chance to handle the signal and notice the
136 * kernel fault information, so that won't result in polluting
137 * the information about previously queued, but not yet
138 * delivered, faults. See also do_general_protection below.
139 */
140 tsk->thread.error_code = error_code;
141 tsk->thread.trap_nr = trapnr;
142
143#ifdef CONFIG_X86_64
144 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
145 printk_ratelimit()) {
146 printk(KERN_INFO
147 "%s[%d] trap %s ip:%lx sp:%lx error:%lx",
148 tsk->comm, tsk->pid, str,
149 regs->ip, regs->sp, error_code);
150 print_vma_addr(" in ", regs->ip);
151 printk("\n");
152 }
153#endif
154
155 if (info)
156 force_sig_info(signr, info, tsk);
157 else
158 force_sig(signr, tsk);
159 return;
160
161kernel_trap:
162 if (!fixup_exception(regs)) {
163 tsk->thread.error_code = error_code;
164 tsk->thread.trap_nr = trapnr;
165 die(str, regs, error_code);
166 }
167 return;
168
169#ifdef CONFIG_X86_32
170vm86_trap:
171 if (handle_vm86_trap((struct kernel_vm86_regs *) regs,
172 error_code, trapnr))
173 goto trap_signal;
174 return;
175#endif
176}
177
178#define DO_ERROR(trapnr, signr, str, name) \
179dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \
180{ \
181 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
182 == NOTIFY_STOP) \
183 return; \
184 conditional_sti(regs); \
185 do_trap(trapnr, signr, str, regs, error_code, NULL); \
186}
187
188#define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \
189dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \
190{ \
191 siginfo_t info; \
192 info.si_signo = signr; \
193 info.si_errno = 0; \
194 info.si_code = sicode; \
195 info.si_addr = (void __user *)siaddr; \
196 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \
197 == NOTIFY_STOP) \
198 return; \
199 conditional_sti(regs); \
200 do_trap(trapnr, signr, str, regs, error_code, &info); \
201}
202
203DO_ERROR_INFO(X86_TRAP_DE, SIGFPE, "divide error", divide_error, FPE_INTDIV,
204 regs->ip)
205DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow)
206DO_ERROR(X86_TRAP_BR, SIGSEGV, "bounds", bounds)
207DO_ERROR_INFO(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op, ILL_ILLOPN,
208 regs->ip)
209DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",
210 coprocessor_segment_overrun)
211DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS)
212DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present)
213#ifdef CONFIG_X86_32
214DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment)
215#endif
216DO_ERROR_INFO(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check,
217 BUS_ADRALN, 0)
218
219#ifdef CONFIG_X86_64
220/* Runs on IST stack */
221dotraplinkage void do_stack_segment(struct pt_regs *regs, long error_code)
222{
223 if (notify_die(DIE_TRAP, "stack segment", regs, error_code,
224 X86_TRAP_SS, SIGBUS) == NOTIFY_STOP)
225 return;
226 preempt_conditional_sti(regs);
227 do_trap(X86_TRAP_SS, SIGBUS, "stack segment", regs, error_code, NULL);
228 preempt_conditional_cli(regs);
229}
230
231dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
232{
233 static const char str[] = "double fault";
234 struct task_struct *tsk = current;
235
236 /* Return not checked because double check cannot be ignored */
237 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
238
239 tsk->thread.error_code = error_code;
240 tsk->thread.trap_nr = X86_TRAP_DF;
241
242 /*
243 * This is always a kernel trap and never fixable (and thus must
244 * never return).
245 */
246 for (;;)
247 die(str, regs, error_code);
248}
249#endif
250
251dotraplinkage void __kprobes
252do_general_protection(struct pt_regs *regs, long error_code)
253{
254 struct task_struct *tsk;
255
256 conditional_sti(regs);
257
258#ifdef CONFIG_X86_32
259 if (regs->flags & X86_VM_MASK)
260 goto gp_in_vm86;
261#endif
262
263 tsk = current;
264 if (!user_mode(regs))
265 goto gp_in_kernel;
266
267 tsk->thread.error_code = error_code;
268 tsk->thread.trap_nr = X86_TRAP_GP;
269
270 if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
271 printk_ratelimit()) {
272 printk(KERN_INFO
273 "%s[%d] general protection ip:%lx sp:%lx error:%lx",
274 tsk->comm, task_pid_nr(tsk),
275 regs->ip, regs->sp, error_code);
276 print_vma_addr(" in ", regs->ip);
277 printk("\n");
278 }
279
280 force_sig(SIGSEGV, tsk);
281 return;
282
283#ifdef CONFIG_X86_32
284gp_in_vm86:
285 local_irq_enable();
286 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
287 return;
288#endif
289
290gp_in_kernel:
291 if (fixup_exception(regs))
292 return;
293
294 tsk->thread.error_code = error_code;
295 tsk->thread.trap_nr = X86_TRAP_GP;
296 if (notify_die(DIE_GPF, "general protection fault", regs, error_code,
297 X86_TRAP_GP, SIGSEGV) == NOTIFY_STOP)
298 return;
299 die("general protection fault", regs, error_code);
300}
301
302/* May run on IST stack. */
303dotraplinkage void __kprobes notrace do_int3(struct pt_regs *regs, long error_code)
304{
305#ifdef CONFIG_DYNAMIC_FTRACE
306 /*
307 * ftrace must be first, everything else may cause a recursive crash.
308 * See note by declaration of modifying_ftrace_code in ftrace.c
309 */
310 if (unlikely(atomic_read(&modifying_ftrace_code)) &&
311 ftrace_int3_handler(regs))
312 return;
313#endif
314#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
315 if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
316 SIGTRAP) == NOTIFY_STOP)
317 return;
318#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
319
320 if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
321 SIGTRAP) == NOTIFY_STOP)
322 return;
323
324 /*
325 * Let others (NMI) know that the debug stack is in use
326 * as we may switch to the interrupt stack.
327 */
328 debug_stack_usage_inc();
329 preempt_conditional_sti(regs);
330 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL);
331 preempt_conditional_cli(regs);
332 debug_stack_usage_dec();
333}
334
335#ifdef CONFIG_X86_64
336/*
337 * Help handler running on IST stack to switch back to user stack
338 * for scheduling or signal handling. The actual stack switch is done in
339 * entry.S
340 */
341asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs)
342{
343 struct pt_regs *regs = eregs;
344 /* Did already sync */
345 if (eregs == (struct pt_regs *)eregs->sp)
346 ;
347 /* Exception from user space */
348 else if (user_mode(eregs))
349 regs = task_pt_regs(current);
350 /*
351 * Exception from kernel and interrupts are enabled. Move to
352 * kernel process stack.
353 */
354 else if (eregs->flags & X86_EFLAGS_IF)
355 regs = (struct pt_regs *)(eregs->sp -= sizeof(struct pt_regs));
356 if (eregs != regs)
357 *regs = *eregs;
358 return regs;
359}
360#endif
361
362/*
363 * Our handling of the processor debug registers is non-trivial.
364 * We do not clear them on entry and exit from the kernel. Therefore
365 * it is possible to get a watchpoint trap here from inside the kernel.
366 * However, the code in ./ptrace.c has ensured that the user can
367 * only set watchpoints on userspace addresses. Therefore the in-kernel
368 * watchpoint trap can only occur in code which is reading/writing
369 * from user space. Such code must not hold kernel locks (since it
370 * can equally take a page fault), therefore it is safe to call
371 * force_sig_info even though that claims and releases locks.
372 *
373 * Code in ./signal.c ensures that the debug control register
374 * is restored before we deliver any signal, and therefore that
375 * user code runs with the correct debug control register even though
376 * we clear it here.
377 *
378 * Being careful here means that we don't have to be as careful in a
379 * lot of more complicated places (task switching can be a bit lazy
380 * about restoring all the debug state, and ptrace doesn't have to
381 * find every occurrence of the TF bit that could be saved away even
382 * by user code)
383 *
384 * May run on IST stack.
385 */
386dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code)
387{
388 struct task_struct *tsk = current;
389 int user_icebp = 0;
390 unsigned long dr6;
391 int si_code;
392
393 get_debugreg(dr6, 6);
394
395 /* Filter out all the reserved bits which are preset to 1 */
396 dr6 &= ~DR6_RESERVED;
397
398 /*
399 * If dr6 has no reason to give us about the origin of this trap,
400 * then it's very likely the result of an icebp/int01 trap.
401 * User wants a sigtrap for that.
402 */
403 if (!dr6 && user_mode(regs))
404 user_icebp = 1;
405
406 /* Catch kmemcheck conditions first of all! */
407 if ((dr6 & DR_STEP) && kmemcheck_trap(regs))
408 return;
409
410 /* DR6 may or may not be cleared by the CPU */
411 set_debugreg(0, 6);
412
413 /*
414 * The processor cleared BTF, so don't mark that we need it set.
415 */
416 clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP);
417
418 /* Store the virtualized DR6 value */
419 tsk->thread.debugreg6 = dr6;
420
421 if (notify_die(DIE_DEBUG, "debug", regs, PTR_ERR(&dr6), error_code,
422 SIGTRAP) == NOTIFY_STOP)
423 return;
424
425 /*
426 * Let others (NMI) know that the debug stack is in use
427 * as we may switch to the interrupt stack.
428 */
429 debug_stack_usage_inc();
430
431 /* It's safe to allow irq's after DR6 has been saved */
432 preempt_conditional_sti(regs);
433
434 if (regs->flags & X86_VM_MASK) {
435 handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code,
436 X86_TRAP_DB);
437 preempt_conditional_cli(regs);
438 debug_stack_usage_dec();
439 return;
440 }
441
442 /*
443 * Single-stepping through system calls: ignore any exceptions in
444 * kernel space, but re-enable TF when returning to user mode.
445 *
446 * We already checked v86 mode above, so we can check for kernel mode
447 * by just checking the CPL of CS.
448 */
449 if ((dr6 & DR_STEP) && !user_mode(regs)) {
450 tsk->thread.debugreg6 &= ~DR_STEP;
451 set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
452 regs->flags &= ~X86_EFLAGS_TF;
453 }
454 si_code = get_si_code(tsk->thread.debugreg6);
455 if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
456 send_sigtrap(tsk, regs, error_code, si_code);
457 preempt_conditional_cli(regs);
458 debug_stack_usage_dec();
459
460 return;
461}
462
463/*
464 * Note that we play around with the 'TS' bit in an attempt to get
465 * the correct behaviour even in the presence of the asynchronous
466 * IRQ13 behaviour
467 */
468void math_error(struct pt_regs *regs, int error_code, int trapnr)
469{
470 struct task_struct *task = current;
471 siginfo_t info;
472 unsigned short err;
473 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
474 "simd exception";
475
476 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP)
477 return;
478 conditional_sti(regs);
479
480 if (!user_mode_vm(regs))
481 {
482 if (!fixup_exception(regs)) {
483 task->thread.error_code = error_code;
484 task->thread.trap_nr = trapnr;
485 die(str, regs, error_code);
486 }
487 return;
488 }
489
490 /*
491 * Save the info for the exception handler and clear the error.
492 */
493 save_init_fpu(task);
494 task->thread.trap_nr = trapnr;
495 task->thread.error_code = error_code;
496 info.si_signo = SIGFPE;
497 info.si_errno = 0;
498 info.si_addr = (void __user *)regs->ip;
499 if (trapnr == X86_TRAP_MF) {
500 unsigned short cwd, swd;
501 /*
502 * (~cwd & swd) will mask out exceptions that are not set to unmasked
503 * status. 0x3f is the exception bits in these regs, 0x200 is the
504 * C1 reg you need in case of a stack fault, 0x040 is the stack
505 * fault bit. We should only be taking one exception at a time,
506 * so if this combination doesn't produce any single exception,
507 * then we have a bad program that isn't synchronizing its FPU usage
508 * and it will suffer the consequences since we won't be able to
509 * fully reproduce the context of the exception
510 */
511 cwd = get_fpu_cwd(task);
512 swd = get_fpu_swd(task);
513
514 err = swd & ~cwd;
515 } else {
516 /*
517 * The SIMD FPU exceptions are handled a little differently, as there
518 * is only a single status/control register. Thus, to determine which
519 * unmasked exception was caught we must mask the exception mask bits
520 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
521 */
522 unsigned short mxcsr = get_fpu_mxcsr(task);
523 err = ~(mxcsr >> 7) & mxcsr;
524 }
525
526 if (err & 0x001) { /* Invalid op */
527 /*
528 * swd & 0x240 == 0x040: Stack Underflow
529 * swd & 0x240 == 0x240: Stack Overflow
530 * User must clear the SF bit (0x40) if set
531 */
532 info.si_code = FPE_FLTINV;
533 } else if (err & 0x004) { /* Divide by Zero */
534 info.si_code = FPE_FLTDIV;
535 } else if (err & 0x008) { /* Overflow */
536 info.si_code = FPE_FLTOVF;
537 } else if (err & 0x012) { /* Denormal, Underflow */
538 info.si_code = FPE_FLTUND;
539 } else if (err & 0x020) { /* Precision */
540 info.si_code = FPE_FLTRES;
541 } else {
542 /*
543 * If we're using IRQ 13, or supposedly even some trap
544 * X86_TRAP_MF implementations, it's possible
545 * we get a spurious trap, which is not an error.
546 */
547 return;
548 }
549 force_sig_info(SIGFPE, &info, task);
550}
551
552dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code)
553{
554#ifdef CONFIG_X86_32
555 ignore_fpu_irq = 1;
556#endif
557
558 math_error(regs, error_code, X86_TRAP_MF);
559}
560
561dotraplinkage void
562do_simd_coprocessor_error(struct pt_regs *regs, long error_code)
563{
564 math_error(regs, error_code, X86_TRAP_XF);
565}
566
567dotraplinkage void
568do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
569{
570 conditional_sti(regs);
571#if 0
572 /* No need to warn about this any longer. */
573 printk(KERN_INFO "Ignoring P6 Local APIC Spurious Interrupt Bug...\n");
574#endif
575}
576
577asmlinkage void __attribute__((weak)) smp_thermal_interrupt(void)
578{
579}
580
581asmlinkage void __attribute__((weak)) smp_threshold_interrupt(void)
582{
583}
584
585/*
586 * 'math_state_restore()' saves the current math information in the
587 * old math state array, and gets the new ones from the current task
588 *
589 * Careful.. There are problems with IBM-designed IRQ13 behaviour.
590 * Don't touch unless you *really* know how it works.
591 *
592 * Must be called with kernel preemption disabled (eg with local
593 * local interrupts as in the case of do_device_not_available).
594 */
595void math_state_restore(void)
596{
597 struct task_struct *tsk = current;
598
599 if (!tsk_used_math(tsk)) {
600 local_irq_enable();
601 /*
602 * does a slab alloc which can sleep
603 */
604 if (init_fpu(tsk)) {
605 /*
606 * ran out of memory!
607 */
608 do_group_exit(SIGKILL);
609 return;
610 }
611 local_irq_disable();
612 }
613
614 __thread_fpu_begin(tsk);
615 /*
616 * Paranoid restore. send a SIGSEGV if we fail to restore the state.
617 */
618 if (unlikely(restore_fpu_checking(tsk))) {
619 __thread_fpu_end(tsk);
620 force_sig(SIGSEGV, tsk);
621 return;
622 }
623
624 tsk->fpu_counter++;
625}
626EXPORT_SYMBOL_GPL(math_state_restore);
627
628dotraplinkage void __kprobes
629do_device_not_available(struct pt_regs *regs, long error_code)
630{
631#ifdef CONFIG_MATH_EMULATION
632 if (read_cr0() & X86_CR0_EM) {
633 struct math_emu_info info = { };
634
635 conditional_sti(regs);
636
637 info.regs = regs;
638 math_emulate(&info);
639 return;
640 }
641#endif
642 math_state_restore(); /* interrupts still off */
643#ifdef CONFIG_X86_32
644 conditional_sti(regs);
645#endif
646}
647
648#ifdef CONFIG_X86_32
649dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code)
650{
651 siginfo_t info;
652 local_irq_enable();
653
654 info.si_signo = SIGILL;
655 info.si_errno = 0;
656 info.si_code = ILL_BADSTK;
657 info.si_addr = NULL;
658 if (notify_die(DIE_TRAP, "iret exception", regs, error_code,
659 X86_TRAP_IRET, SIGILL) == NOTIFY_STOP)
660 return;
661 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code,
662 &info);
663}
664#endif
665
666/* Set of traps needed for early debugging. */
667void __init early_trap_init(void)
668{
669 set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK);
670 /* int3 can be called from all */
671 set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK);
672 set_intr_gate(X86_TRAP_PF, &page_fault);
673 load_idt(&idt_descr);
674}
675
676void __init trap_init(void)
677{
678 int i;
679
680#ifdef CONFIG_EISA
681 void __iomem *p = early_ioremap(0x0FFFD9, 4);
682
683 if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24))
684 EISA_bus = 1;
685 early_iounmap(p, 4);
686#endif
687
688 set_intr_gate(X86_TRAP_DE, ÷_error);
689 set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK);
690 /* int4 can be called from all */
691 set_system_intr_gate(X86_TRAP_OF, &overflow);
692 set_intr_gate(X86_TRAP_BR, &bounds);
693 set_intr_gate(X86_TRAP_UD, &invalid_op);
694 set_intr_gate(X86_TRAP_NM, &device_not_available);
695#ifdef CONFIG_X86_32
696 set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS);
697#else
698 set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK);
699#endif
700 set_intr_gate(X86_TRAP_OLD_MF, &coprocessor_segment_overrun);
701 set_intr_gate(X86_TRAP_TS, &invalid_TSS);
702 set_intr_gate(X86_TRAP_NP, &segment_not_present);
703 set_intr_gate_ist(X86_TRAP_SS, &stack_segment, STACKFAULT_STACK);
704 set_intr_gate(X86_TRAP_GP, &general_protection);
705 set_intr_gate(X86_TRAP_SPURIOUS, &spurious_interrupt_bug);
706 set_intr_gate(X86_TRAP_MF, &coprocessor_error);
707 set_intr_gate(X86_TRAP_AC, &alignment_check);
708#ifdef CONFIG_X86_MCE
709 set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK);
710#endif
711 set_intr_gate(X86_TRAP_XF, &simd_coprocessor_error);
712
713 /* Reserve all the builtin and the syscall vector: */
714 for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++)
715 set_bit(i, used_vectors);
716
717#ifdef CONFIG_IA32_EMULATION
718 set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall);
719 set_bit(IA32_SYSCALL_VECTOR, used_vectors);
720#endif
721
722#ifdef CONFIG_X86_32
723 set_system_trap_gate(SYSCALL_VECTOR, &system_call);
724 set_bit(SYSCALL_VECTOR, used_vectors);
725#endif
726
727 /*
728 * Should be a barrier for any external CPU state:
729 */
730 cpu_init();
731
732 x86_init.irqs.trap_init();
733
734#ifdef CONFIG_X86_64
735 memcpy(&nmi_idt_table, &idt_table, IDT_ENTRIES * 16);
736 set_nmi_gate(X86_TRAP_DB, &debug);
737 set_nmi_gate(X86_TRAP_BP, &int3);
738#endif
739}
1/*
2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 *
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
8
9/*
10 * Handle hardware traps and faults.
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/context_tracking.h>
16#include <linux/interrupt.h>
17#include <linux/kallsyms.h>
18#include <linux/spinlock.h>
19#include <linux/kprobes.h>
20#include <linux/uaccess.h>
21#include <linux/kdebug.h>
22#include <linux/kgdb.h>
23#include <linux/kernel.h>
24#include <linux/export.h>
25#include <linux/ptrace.h>
26#include <linux/uprobes.h>
27#include <linux/string.h>
28#include <linux/delay.h>
29#include <linux/errno.h>
30#include <linux/kexec.h>
31#include <linux/sched.h>
32#include <linux/sched/task_stack.h>
33#include <linux/timer.h>
34#include <linux/init.h>
35#include <linux/bug.h>
36#include <linux/nmi.h>
37#include <linux/mm.h>
38#include <linux/smp.h>
39#include <linux/io.h>
40#include <linux/hardirq.h>
41#include <linux/atomic.h>
42
43#include <asm/stacktrace.h>
44#include <asm/processor.h>
45#include <asm/debugreg.h>
46#include <asm/realmode.h>
47#include <asm/text-patching.h>
48#include <asm/ftrace.h>
49#include <asm/traps.h>
50#include <asm/desc.h>
51#include <asm/fpu/internal.h>
52#include <asm/cpu.h>
53#include <asm/cpu_entry_area.h>
54#include <asm/mce.h>
55#include <asm/fixmap.h>
56#include <asm/mach_traps.h>
57#include <asm/alternative.h>
58#include <asm/fpu/xstate.h>
59#include <asm/vm86.h>
60#include <asm/umip.h>
61#include <asm/insn.h>
62#include <asm/insn-eval.h>
63#include <asm/vdso.h>
64
65#ifdef CONFIG_X86_64
66#include <asm/x86_init.h>
67#include <asm/proto.h>
68#else
69#include <asm/processor-flags.h>
70#include <asm/setup.h>
71#include <asm/proto.h>
72#endif
73
74DECLARE_BITMAP(system_vectors, NR_VECTORS);
75
76static inline void cond_local_irq_enable(struct pt_regs *regs)
77{
78 if (regs->flags & X86_EFLAGS_IF)
79 local_irq_enable();
80}
81
82static inline void cond_local_irq_disable(struct pt_regs *regs)
83{
84 if (regs->flags & X86_EFLAGS_IF)
85 local_irq_disable();
86}
87
88__always_inline int is_valid_bugaddr(unsigned long addr)
89{
90 if (addr < TASK_SIZE_MAX)
91 return 0;
92
93 /*
94 * We got #UD, if the text isn't readable we'd have gotten
95 * a different exception.
96 */
97 return *(unsigned short *)addr == INSN_UD2;
98}
99
100static nokprobe_inline int
101do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str,
102 struct pt_regs *regs, long error_code)
103{
104 if (v8086_mode(regs)) {
105 /*
106 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
107 * On nmi (interrupt 2), do_trap should not be called.
108 */
109 if (trapnr < X86_TRAP_UD) {
110 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
111 error_code, trapnr))
112 return 0;
113 }
114 } else if (!user_mode(regs)) {
115 if (fixup_exception(regs, trapnr, error_code, 0))
116 return 0;
117
118 tsk->thread.error_code = error_code;
119 tsk->thread.trap_nr = trapnr;
120 die(str, regs, error_code);
121 } else {
122 if (fixup_vdso_exception(regs, trapnr, error_code, 0))
123 return 0;
124 }
125
126 /*
127 * We want error_code and trap_nr set for userspace faults and
128 * kernelspace faults which result in die(), but not
129 * kernelspace faults which are fixed up. die() gives the
130 * process no chance to handle the signal and notice the
131 * kernel fault information, so that won't result in polluting
132 * the information about previously queued, but not yet
133 * delivered, faults. See also exc_general_protection below.
134 */
135 tsk->thread.error_code = error_code;
136 tsk->thread.trap_nr = trapnr;
137
138 return -1;
139}
140
141static void show_signal(struct task_struct *tsk, int signr,
142 const char *type, const char *desc,
143 struct pt_regs *regs, long error_code)
144{
145 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
146 printk_ratelimit()) {
147 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx",
148 tsk->comm, task_pid_nr(tsk), type, desc,
149 regs->ip, regs->sp, error_code);
150 print_vma_addr(KERN_CONT " in ", regs->ip);
151 pr_cont("\n");
152 }
153}
154
155static void
156do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
157 long error_code, int sicode, void __user *addr)
158{
159 struct task_struct *tsk = current;
160
161 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
162 return;
163
164 show_signal(tsk, signr, "trap ", str, regs, error_code);
165
166 if (!sicode)
167 force_sig(signr);
168 else
169 force_sig_fault(signr, sicode, addr);
170}
171NOKPROBE_SYMBOL(do_trap);
172
173static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
174 unsigned long trapnr, int signr, int sicode, void __user *addr)
175{
176 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
177
178 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
179 NOTIFY_STOP) {
180 cond_local_irq_enable(regs);
181 do_trap(trapnr, signr, str, regs, error_code, sicode, addr);
182 cond_local_irq_disable(regs);
183 }
184}
185
186/*
187 * Posix requires to provide the address of the faulting instruction for
188 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t.
189 *
190 * This address is usually regs->ip, but when an uprobe moved the code out
191 * of line then regs->ip points to the XOL code which would confuse
192 * anything which analyzes the fault address vs. the unmodified binary. If
193 * a trap happened in XOL code then uprobe maps regs->ip back to the
194 * original instruction address.
195 */
196static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs)
197{
198 return (void __user *)uprobe_get_trap_addr(regs);
199}
200
201DEFINE_IDTENTRY(exc_divide_error)
202{
203 do_error_trap(regs, 0, "divide error", X86_TRAP_DE, SIGFPE,
204 FPE_INTDIV, error_get_trap_addr(regs));
205}
206
207DEFINE_IDTENTRY(exc_overflow)
208{
209 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL);
210}
211
212#ifdef CONFIG_X86_F00F_BUG
213void handle_invalid_op(struct pt_regs *regs)
214#else
215static inline void handle_invalid_op(struct pt_regs *regs)
216#endif
217{
218 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL,
219 ILL_ILLOPN, error_get_trap_addr(regs));
220}
221
222static noinstr bool handle_bug(struct pt_regs *regs)
223{
224 bool handled = false;
225
226 if (!is_valid_bugaddr(regs->ip))
227 return handled;
228
229 /*
230 * All lies, just get the WARN/BUG out.
231 */
232 instrumentation_begin();
233 /*
234 * Since we're emulating a CALL with exceptions, restore the interrupt
235 * state to what it was at the exception site.
236 */
237 if (regs->flags & X86_EFLAGS_IF)
238 raw_local_irq_enable();
239 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN) {
240 regs->ip += LEN_UD2;
241 handled = true;
242 }
243 if (regs->flags & X86_EFLAGS_IF)
244 raw_local_irq_disable();
245 instrumentation_end();
246
247 return handled;
248}
249
250DEFINE_IDTENTRY_RAW(exc_invalid_op)
251{
252 irqentry_state_t state;
253
254 /*
255 * We use UD2 as a short encoding for 'CALL __WARN', as such
256 * handle it before exception entry to avoid recursive WARN
257 * in case exception entry is the one triggering WARNs.
258 */
259 if (!user_mode(regs) && handle_bug(regs))
260 return;
261
262 state = irqentry_enter(regs);
263 instrumentation_begin();
264 handle_invalid_op(regs);
265 instrumentation_end();
266 irqentry_exit(regs, state);
267}
268
269DEFINE_IDTENTRY(exc_coproc_segment_overrun)
270{
271 do_error_trap(regs, 0, "coprocessor segment overrun",
272 X86_TRAP_OLD_MF, SIGFPE, 0, NULL);
273}
274
275DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss)
276{
277 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV,
278 0, NULL);
279}
280
281DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present)
282{
283 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP,
284 SIGBUS, 0, NULL);
285}
286
287DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment)
288{
289 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS,
290 0, NULL);
291}
292
293DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check)
294{
295 char *str = "alignment check";
296
297 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP)
298 return;
299
300 if (!user_mode(regs))
301 die("Split lock detected\n", regs, error_code);
302
303 local_irq_enable();
304
305 if (handle_user_split_lock(regs, error_code))
306 goto out;
307
308 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs,
309 error_code, BUS_ADRALN, NULL);
310
311out:
312 local_irq_disable();
313}
314
315#ifdef CONFIG_VMAP_STACK
316__visible void __noreturn handle_stack_overflow(const char *message,
317 struct pt_regs *regs,
318 unsigned long fault_address)
319{
320 printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n",
321 (void *)fault_address, current->stack,
322 (char *)current->stack + THREAD_SIZE - 1);
323 die(message, regs, 0);
324
325 /* Be absolutely certain we don't return. */
326 panic("%s", message);
327}
328#endif
329
330/*
331 * Runs on an IST stack for x86_64 and on a special task stack for x86_32.
332 *
333 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the
334 * SDM's warnings about double faults being unrecoverable, returning works as
335 * expected. Presumably what the SDM actually means is that the CPU may get
336 * the register state wrong on entry, so returning could be a bad idea.
337 *
338 * Various CPU engineers have promised that double faults due to an IRET fault
339 * while the stack is read-only are, in fact, recoverable.
340 *
341 * On x86_32, this is entered through a task gate, and regs are synthesized
342 * from the TSS. Returning is, in principle, okay, but changes to regs will
343 * be lost. If, for some reason, we need to return to a context with modified
344 * regs, the shim code could be adjusted to synchronize the registers.
345 *
346 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs
347 * to be read before doing anything else.
348 */
349DEFINE_IDTENTRY_DF(exc_double_fault)
350{
351 static const char str[] = "double fault";
352 struct task_struct *tsk = current;
353
354#ifdef CONFIG_VMAP_STACK
355 unsigned long address = read_cr2();
356#endif
357
358#ifdef CONFIG_X86_ESPFIX64
359 extern unsigned char native_irq_return_iret[];
360
361 /*
362 * If IRET takes a non-IST fault on the espfix64 stack, then we
363 * end up promoting it to a doublefault. In that case, take
364 * advantage of the fact that we're not using the normal (TSS.sp0)
365 * stack right now. We can write a fake #GP(0) frame at TSS.sp0
366 * and then modify our own IRET frame so that, when we return,
367 * we land directly at the #GP(0) vector with the stack already
368 * set up according to its expectations.
369 *
370 * The net result is that our #GP handler will think that we
371 * entered from usermode with the bad user context.
372 *
373 * No need for nmi_enter() here because we don't use RCU.
374 */
375 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY &&
376 regs->cs == __KERNEL_CS &&
377 regs->ip == (unsigned long)native_irq_return_iret)
378 {
379 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
380 unsigned long *p = (unsigned long *)regs->sp;
381
382 /*
383 * regs->sp points to the failing IRET frame on the
384 * ESPFIX64 stack. Copy it to the entry stack. This fills
385 * in gpregs->ss through gpregs->ip.
386 *
387 */
388 gpregs->ip = p[0];
389 gpregs->cs = p[1];
390 gpregs->flags = p[2];
391 gpregs->sp = p[3];
392 gpregs->ss = p[4];
393 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */
394
395 /*
396 * Adjust our frame so that we return straight to the #GP
397 * vector with the expected RSP value. This is safe because
398 * we won't enable interrupts or schedule before we invoke
399 * general_protection, so nothing will clobber the stack
400 * frame we just set up.
401 *
402 * We will enter general_protection with kernel GSBASE,
403 * which is what the stub expects, given that the faulting
404 * RIP will be the IRET instruction.
405 */
406 regs->ip = (unsigned long)asm_exc_general_protection;
407 regs->sp = (unsigned long)&gpregs->orig_ax;
408
409 return;
410 }
411#endif
412
413 irqentry_nmi_enter(regs);
414 instrumentation_begin();
415 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
416
417 tsk->thread.error_code = error_code;
418 tsk->thread.trap_nr = X86_TRAP_DF;
419
420#ifdef CONFIG_VMAP_STACK
421 /*
422 * If we overflow the stack into a guard page, the CPU will fail
423 * to deliver #PF and will send #DF instead. Similarly, if we
424 * take any non-IST exception while too close to the bottom of
425 * the stack, the processor will get a page fault while
426 * delivering the exception and will generate a double fault.
427 *
428 * According to the SDM (footnote in 6.15 under "Interrupt 14 -
429 * Page-Fault Exception (#PF):
430 *
431 * Processors update CR2 whenever a page fault is detected. If a
432 * second page fault occurs while an earlier page fault is being
433 * delivered, the faulting linear address of the second fault will
434 * overwrite the contents of CR2 (replacing the previous
435 * address). These updates to CR2 occur even if the page fault
436 * results in a double fault or occurs during the delivery of a
437 * double fault.
438 *
439 * The logic below has a small possibility of incorrectly diagnosing
440 * some errors as stack overflows. For example, if the IDT or GDT
441 * gets corrupted such that #GP delivery fails due to a bad descriptor
442 * causing #GP and we hit this condition while CR2 coincidentally
443 * points to the stack guard page, we'll think we overflowed the
444 * stack. Given that we're going to panic one way or another
445 * if this happens, this isn't necessarily worth fixing.
446 *
447 * If necessary, we could improve the test by only diagnosing
448 * a stack overflow if the saved RSP points within 47 bytes of
449 * the bottom of the stack: if RSP == tsk_stack + 48 and we
450 * take an exception, the stack is already aligned and there
451 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a
452 * possible error code, so a stack overflow would *not* double
453 * fault. With any less space left, exception delivery could
454 * fail, and, as a practical matter, we've overflowed the
455 * stack even if the actual trigger for the double fault was
456 * something else.
457 */
458 if ((unsigned long)task_stack_page(tsk) - 1 - address < PAGE_SIZE) {
459 handle_stack_overflow("kernel stack overflow (double-fault)",
460 regs, address);
461 }
462#endif
463
464 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code);
465 die("double fault", regs, error_code);
466 panic("Machine halted.");
467 instrumentation_end();
468}
469
470DEFINE_IDTENTRY(exc_bounds)
471{
472 if (notify_die(DIE_TRAP, "bounds", regs, 0,
473 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
474 return;
475 cond_local_irq_enable(regs);
476
477 if (!user_mode(regs))
478 die("bounds", regs, 0);
479
480 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL);
481
482 cond_local_irq_disable(regs);
483}
484
485enum kernel_gp_hint {
486 GP_NO_HINT,
487 GP_NON_CANONICAL,
488 GP_CANONICAL
489};
490
491/*
492 * When an uncaught #GP occurs, try to determine the memory address accessed by
493 * the instruction and return that address to the caller. Also, try to figure
494 * out whether any part of the access to that address was non-canonical.
495 */
496static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs,
497 unsigned long *addr)
498{
499 u8 insn_buf[MAX_INSN_SIZE];
500 struct insn insn;
501 int ret;
502
503 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip,
504 MAX_INSN_SIZE))
505 return GP_NO_HINT;
506
507 ret = insn_decode_kernel(&insn, insn_buf);
508 if (ret < 0)
509 return GP_NO_HINT;
510
511 *addr = (unsigned long)insn_get_addr_ref(&insn, regs);
512 if (*addr == -1UL)
513 return GP_NO_HINT;
514
515#ifdef CONFIG_X86_64
516 /*
517 * Check that:
518 * - the operand is not in the kernel half
519 * - the last byte of the operand is not in the user canonical half
520 */
521 if (*addr < ~__VIRTUAL_MASK &&
522 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK)
523 return GP_NON_CANONICAL;
524#endif
525
526 return GP_CANONICAL;
527}
528
529#define GPFSTR "general protection fault"
530
531DEFINE_IDTENTRY_ERRORCODE(exc_general_protection)
532{
533 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR;
534 enum kernel_gp_hint hint = GP_NO_HINT;
535 struct task_struct *tsk;
536 unsigned long gp_addr;
537 int ret;
538
539 cond_local_irq_enable(regs);
540
541 if (static_cpu_has(X86_FEATURE_UMIP)) {
542 if (user_mode(regs) && fixup_umip_exception(regs))
543 goto exit;
544 }
545
546 if (v8086_mode(regs)) {
547 local_irq_enable();
548 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
549 local_irq_disable();
550 return;
551 }
552
553 tsk = current;
554
555 if (user_mode(regs)) {
556 tsk->thread.error_code = error_code;
557 tsk->thread.trap_nr = X86_TRAP_GP;
558
559 if (fixup_vdso_exception(regs, X86_TRAP_GP, error_code, 0))
560 goto exit;
561
562 show_signal(tsk, SIGSEGV, "", desc, regs, error_code);
563 force_sig(SIGSEGV);
564 goto exit;
565 }
566
567 if (fixup_exception(regs, X86_TRAP_GP, error_code, 0))
568 goto exit;
569
570 tsk->thread.error_code = error_code;
571 tsk->thread.trap_nr = X86_TRAP_GP;
572
573 /*
574 * To be potentially processing a kprobe fault and to trust the result
575 * from kprobe_running(), we have to be non-preemptible.
576 */
577 if (!preemptible() &&
578 kprobe_running() &&
579 kprobe_fault_handler(regs, X86_TRAP_GP))
580 goto exit;
581
582 ret = notify_die(DIE_GPF, desc, regs, error_code, X86_TRAP_GP, SIGSEGV);
583 if (ret == NOTIFY_STOP)
584 goto exit;
585
586 if (error_code)
587 snprintf(desc, sizeof(desc), "segment-related " GPFSTR);
588 else
589 hint = get_kernel_gp_address(regs, &gp_addr);
590
591 if (hint != GP_NO_HINT)
592 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx",
593 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address"
594 : "maybe for address",
595 gp_addr);
596
597 /*
598 * KASAN is interested only in the non-canonical case, clear it
599 * otherwise.
600 */
601 if (hint != GP_NON_CANONICAL)
602 gp_addr = 0;
603
604 die_addr(desc, regs, error_code, gp_addr);
605
606exit:
607 cond_local_irq_disable(regs);
608}
609
610static bool do_int3(struct pt_regs *regs)
611{
612 int res;
613
614#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
615 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP,
616 SIGTRAP) == NOTIFY_STOP)
617 return true;
618#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
619
620#ifdef CONFIG_KPROBES
621 if (kprobe_int3_handler(regs))
622 return true;
623#endif
624 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP);
625
626 return res == NOTIFY_STOP;
627}
628
629static void do_int3_user(struct pt_regs *regs)
630{
631 if (do_int3(regs))
632 return;
633
634 cond_local_irq_enable(regs);
635 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL);
636 cond_local_irq_disable(regs);
637}
638
639DEFINE_IDTENTRY_RAW(exc_int3)
640{
641 /*
642 * poke_int3_handler() is completely self contained code; it does (and
643 * must) *NOT* call out to anything, lest it hits upon yet another
644 * INT3.
645 */
646 if (poke_int3_handler(regs))
647 return;
648
649 /*
650 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely()
651 * and therefore can trigger INT3, hence poke_int3_handler() must
652 * be done before. If the entry came from kernel mode, then use
653 * nmi_enter() because the INT3 could have been hit in any context
654 * including NMI.
655 */
656 if (user_mode(regs)) {
657 irqentry_enter_from_user_mode(regs);
658 instrumentation_begin();
659 do_int3_user(regs);
660 instrumentation_end();
661 irqentry_exit_to_user_mode(regs);
662 } else {
663 irqentry_state_t irq_state = irqentry_nmi_enter(regs);
664
665 instrumentation_begin();
666 if (!do_int3(regs))
667 die("int3", regs, 0);
668 instrumentation_end();
669 irqentry_nmi_exit(regs, irq_state);
670 }
671}
672
673#ifdef CONFIG_X86_64
674/*
675 * Help handler running on a per-cpu (IST or entry trampoline) stack
676 * to switch to the normal thread stack if the interrupted code was in
677 * user mode. The actual stack switch is done in entry_64.S
678 */
679asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs)
680{
681 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1;
682 if (regs != eregs)
683 *regs = *eregs;
684 return regs;
685}
686
687#ifdef CONFIG_AMD_MEM_ENCRYPT
688asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *regs)
689{
690 unsigned long sp, *stack;
691 struct stack_info info;
692 struct pt_regs *regs_ret;
693
694 /*
695 * In the SYSCALL entry path the RSP value comes from user-space - don't
696 * trust it and switch to the current kernel stack
697 */
698 if (ip_within_syscall_gap(regs)) {
699 sp = this_cpu_read(cpu_current_top_of_stack);
700 goto sync;
701 }
702
703 /*
704 * From here on the RSP value is trusted. Now check whether entry
705 * happened from a safe stack. Not safe are the entry or unknown stacks,
706 * use the fall-back stack instead in this case.
707 */
708 sp = regs->sp;
709 stack = (unsigned long *)sp;
710
711 if (!get_stack_info_noinstr(stack, current, &info) || info.type == STACK_TYPE_ENTRY ||
712 info.type >= STACK_TYPE_EXCEPTION_LAST)
713 sp = __this_cpu_ist_top_va(VC2);
714
715sync:
716 /*
717 * Found a safe stack - switch to it as if the entry didn't happen via
718 * IST stack. The code below only copies pt_regs, the real switch happens
719 * in assembly code.
720 */
721 sp = ALIGN_DOWN(sp, 8) - sizeof(*regs_ret);
722
723 regs_ret = (struct pt_regs *)sp;
724 *regs_ret = *regs;
725
726 return regs_ret;
727}
728#endif
729
730struct bad_iret_stack {
731 void *error_entry_ret;
732 struct pt_regs regs;
733};
734
735asmlinkage __visible noinstr
736struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
737{
738 /*
739 * This is called from entry_64.S early in handling a fault
740 * caused by a bad iret to user mode. To handle the fault
741 * correctly, we want to move our stack frame to where it would
742 * be had we entered directly on the entry stack (rather than
743 * just below the IRET frame) and we want to pretend that the
744 * exception came from the IRET target.
745 */
746 struct bad_iret_stack tmp, *new_stack =
747 (struct bad_iret_stack *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1;
748
749 /* Copy the IRET target to the temporary storage. */
750 __memcpy(&tmp.regs.ip, (void *)s->regs.sp, 5*8);
751
752 /* Copy the remainder of the stack from the current stack. */
753 __memcpy(&tmp, s, offsetof(struct bad_iret_stack, regs.ip));
754
755 /* Update the entry stack */
756 __memcpy(new_stack, &tmp, sizeof(tmp));
757
758 BUG_ON(!user_mode(&new_stack->regs));
759 return new_stack;
760}
761#endif
762
763static bool is_sysenter_singlestep(struct pt_regs *regs)
764{
765 /*
766 * We don't try for precision here. If we're anywhere in the region of
767 * code that can be single-stepped in the SYSENTER entry path, then
768 * assume that this is a useless single-step trap due to SYSENTER
769 * being invoked with TF set. (We don't know in advance exactly
770 * which instructions will be hit because BTF could plausibly
771 * be set.)
772 */
773#ifdef CONFIG_X86_32
774 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) <
775 (unsigned long)__end_SYSENTER_singlestep_region -
776 (unsigned long)__begin_SYSENTER_singlestep_region;
777#elif defined(CONFIG_IA32_EMULATION)
778 return (regs->ip - (unsigned long)entry_SYSENTER_compat) <
779 (unsigned long)__end_entry_SYSENTER_compat -
780 (unsigned long)entry_SYSENTER_compat;
781#else
782 return false;
783#endif
784}
785
786static __always_inline unsigned long debug_read_clear_dr6(void)
787{
788 unsigned long dr6;
789
790 /*
791 * The Intel SDM says:
792 *
793 * Certain debug exceptions may clear bits 0-3. The remaining
794 * contents of the DR6 register are never cleared by the
795 * processor. To avoid confusion in identifying debug
796 * exceptions, debug handlers should clear the register before
797 * returning to the interrupted task.
798 *
799 * Keep it simple: clear DR6 immediately.
800 */
801 get_debugreg(dr6, 6);
802 set_debugreg(DR6_RESERVED, 6);
803 dr6 ^= DR6_RESERVED; /* Flip to positive polarity */
804
805 return dr6;
806}
807
808/*
809 * Our handling of the processor debug registers is non-trivial.
810 * We do not clear them on entry and exit from the kernel. Therefore
811 * it is possible to get a watchpoint trap here from inside the kernel.
812 * However, the code in ./ptrace.c has ensured that the user can
813 * only set watchpoints on userspace addresses. Therefore the in-kernel
814 * watchpoint trap can only occur in code which is reading/writing
815 * from user space. Such code must not hold kernel locks (since it
816 * can equally take a page fault), therefore it is safe to call
817 * force_sig_info even though that claims and releases locks.
818 *
819 * Code in ./signal.c ensures that the debug control register
820 * is restored before we deliver any signal, and therefore that
821 * user code runs with the correct debug control register even though
822 * we clear it here.
823 *
824 * Being careful here means that we don't have to be as careful in a
825 * lot of more complicated places (task switching can be a bit lazy
826 * about restoring all the debug state, and ptrace doesn't have to
827 * find every occurrence of the TF bit that could be saved away even
828 * by user code)
829 *
830 * May run on IST stack.
831 */
832
833static bool notify_debug(struct pt_regs *regs, unsigned long *dr6)
834{
835 /*
836 * Notifiers will clear bits in @dr6 to indicate the event has been
837 * consumed - hw_breakpoint_handler(), single_stop_cont().
838 *
839 * Notifiers will set bits in @virtual_dr6 to indicate the desire
840 * for signals - ptrace_triggered(), kgdb_hw_overflow_handler().
841 */
842 if (notify_die(DIE_DEBUG, "debug", regs, (long)dr6, 0, SIGTRAP) == NOTIFY_STOP)
843 return true;
844
845 return false;
846}
847
848static __always_inline void exc_debug_kernel(struct pt_regs *regs,
849 unsigned long dr6)
850{
851 /*
852 * Disable breakpoints during exception handling; recursive exceptions
853 * are exceedingly 'fun'.
854 *
855 * Since this function is NOKPROBE, and that also applies to
856 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a
857 * HW_BREAKPOINT_W on our stack)
858 *
859 * Entry text is excluded for HW_BP_X and cpu_entry_area, which
860 * includes the entry stack is excluded for everything.
861 */
862 unsigned long dr7 = local_db_save();
863 irqentry_state_t irq_state = irqentry_nmi_enter(regs);
864 instrumentation_begin();
865
866 /*
867 * If something gets miswired and we end up here for a user mode
868 * #DB, we will malfunction.
869 */
870 WARN_ON_ONCE(user_mode(regs));
871
872 if (test_thread_flag(TIF_BLOCKSTEP)) {
873 /*
874 * The SDM says "The processor clears the BTF flag when it
875 * generates a debug exception." but PTRACE_BLOCKSTEP requested
876 * it for userspace, but we just took a kernel #DB, so re-set
877 * BTF.
878 */
879 unsigned long debugctl;
880
881 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
882 debugctl |= DEBUGCTLMSR_BTF;
883 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
884 }
885
886 /*
887 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a
888 * watchpoint at the same time then that will still be handled.
889 */
890 if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs))
891 dr6 &= ~DR_STEP;
892
893 /*
894 * The kernel doesn't use INT1
895 */
896 if (!dr6)
897 goto out;
898
899 if (notify_debug(regs, &dr6))
900 goto out;
901
902 /*
903 * The kernel doesn't use TF single-step outside of:
904 *
905 * - Kprobes, consumed through kprobe_debug_handler()
906 * - KGDB, consumed through notify_debug()
907 *
908 * So if we get here with DR_STEP set, something is wonky.
909 *
910 * A known way to trigger this is through QEMU's GDB stub,
911 * which leaks #DB into the guest and causes IST recursion.
912 */
913 if (WARN_ON_ONCE(dr6 & DR_STEP))
914 regs->flags &= ~X86_EFLAGS_TF;
915out:
916 instrumentation_end();
917 irqentry_nmi_exit(regs, irq_state);
918
919 local_db_restore(dr7);
920}
921
922static __always_inline void exc_debug_user(struct pt_regs *regs,
923 unsigned long dr6)
924{
925 bool icebp;
926
927 /*
928 * If something gets miswired and we end up here for a kernel mode
929 * #DB, we will malfunction.
930 */
931 WARN_ON_ONCE(!user_mode(regs));
932
933 /*
934 * NB: We can't easily clear DR7 here because
935 * irqentry_exit_to_usermode() can invoke ptrace, schedule, access
936 * user memory, etc. This means that a recursive #DB is possible. If
937 * this happens, that #DB will hit exc_debug_kernel() and clear DR7.
938 * Since we're not on the IST stack right now, everything will be
939 * fine.
940 */
941
942 irqentry_enter_from_user_mode(regs);
943 instrumentation_begin();
944
945 /*
946 * Start the virtual/ptrace DR6 value with just the DR_STEP mask
947 * of the real DR6. ptrace_triggered() will set the DR_TRAPn bits.
948 *
949 * Userspace expects DR_STEP to be visible in ptrace_get_debugreg(6)
950 * even if it is not the result of PTRACE_SINGLESTEP.
951 */
952 current->thread.virtual_dr6 = (dr6 & DR_STEP);
953
954 /*
955 * The SDM says "The processor clears the BTF flag when it
956 * generates a debug exception." Clear TIF_BLOCKSTEP to keep
957 * TIF_BLOCKSTEP in sync with the hardware BTF flag.
958 */
959 clear_thread_flag(TIF_BLOCKSTEP);
960
961 /*
962 * If dr6 has no reason to give us about the origin of this trap,
963 * then it's very likely the result of an icebp/int01 trap.
964 * User wants a sigtrap for that.
965 */
966 icebp = !dr6;
967
968 if (notify_debug(regs, &dr6))
969 goto out;
970
971 /* It's safe to allow irq's after DR6 has been saved */
972 local_irq_enable();
973
974 if (v8086_mode(regs)) {
975 handle_vm86_trap((struct kernel_vm86_regs *)regs, 0, X86_TRAP_DB);
976 goto out_irq;
977 }
978
979 /* #DB for bus lock can only be triggered from userspace. */
980 if (dr6 & DR_BUS_LOCK)
981 handle_bus_lock(regs);
982
983 /* Add the virtual_dr6 bits for signals. */
984 dr6 |= current->thread.virtual_dr6;
985 if (dr6 & (DR_STEP | DR_TRAP_BITS) || icebp)
986 send_sigtrap(regs, 0, get_si_code(dr6));
987
988out_irq:
989 local_irq_disable();
990out:
991 instrumentation_end();
992 irqentry_exit_to_user_mode(regs);
993}
994
995#ifdef CONFIG_X86_64
996/* IST stack entry */
997DEFINE_IDTENTRY_DEBUG(exc_debug)
998{
999 exc_debug_kernel(regs, debug_read_clear_dr6());
1000}
1001
1002/* User entry, runs on regular task stack */
1003DEFINE_IDTENTRY_DEBUG_USER(exc_debug)
1004{
1005 exc_debug_user(regs, debug_read_clear_dr6());
1006}
1007#else
1008/* 32 bit does not have separate entry points. */
1009DEFINE_IDTENTRY_RAW(exc_debug)
1010{
1011 unsigned long dr6 = debug_read_clear_dr6();
1012
1013 if (user_mode(regs))
1014 exc_debug_user(regs, dr6);
1015 else
1016 exc_debug_kernel(regs, dr6);
1017}
1018#endif
1019
1020/*
1021 * Note that we play around with the 'TS' bit in an attempt to get
1022 * the correct behaviour even in the presence of the asynchronous
1023 * IRQ13 behaviour
1024 */
1025static void math_error(struct pt_regs *regs, int trapnr)
1026{
1027 struct task_struct *task = current;
1028 struct fpu *fpu = &task->thread.fpu;
1029 int si_code;
1030 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
1031 "simd exception";
1032
1033 cond_local_irq_enable(regs);
1034
1035 if (!user_mode(regs)) {
1036 if (fixup_exception(regs, trapnr, 0, 0))
1037 goto exit;
1038
1039 task->thread.error_code = 0;
1040 task->thread.trap_nr = trapnr;
1041
1042 if (notify_die(DIE_TRAP, str, regs, 0, trapnr,
1043 SIGFPE) != NOTIFY_STOP)
1044 die(str, regs, 0);
1045 goto exit;
1046 }
1047
1048 /*
1049 * Synchronize the FPU register state to the memory register state
1050 * if necessary. This allows the exception handler to inspect it.
1051 */
1052 fpu_sync_fpstate(fpu);
1053
1054 task->thread.trap_nr = trapnr;
1055 task->thread.error_code = 0;
1056
1057 si_code = fpu__exception_code(fpu, trapnr);
1058 /* Retry when we get spurious exceptions: */
1059 if (!si_code)
1060 goto exit;
1061
1062 if (fixup_vdso_exception(regs, trapnr, 0, 0))
1063 goto exit;
1064
1065 force_sig_fault(SIGFPE, si_code,
1066 (void __user *)uprobe_get_trap_addr(regs));
1067exit:
1068 cond_local_irq_disable(regs);
1069}
1070
1071DEFINE_IDTENTRY(exc_coprocessor_error)
1072{
1073 math_error(regs, X86_TRAP_MF);
1074}
1075
1076DEFINE_IDTENTRY(exc_simd_coprocessor_error)
1077{
1078 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) {
1079 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */
1080 if (!static_cpu_has(X86_FEATURE_XMM)) {
1081 __exc_general_protection(regs, 0);
1082 return;
1083 }
1084 }
1085 math_error(regs, X86_TRAP_XF);
1086}
1087
1088DEFINE_IDTENTRY(exc_spurious_interrupt_bug)
1089{
1090 /*
1091 * This addresses a Pentium Pro Erratum:
1092 *
1093 * PROBLEM: If the APIC subsystem is configured in mixed mode with
1094 * Virtual Wire mode implemented through the local APIC, an
1095 * interrupt vector of 0Fh (Intel reserved encoding) may be
1096 * generated by the local APIC (Int 15). This vector may be
1097 * generated upon receipt of a spurious interrupt (an interrupt
1098 * which is removed before the system receives the INTA sequence)
1099 * instead of the programmed 8259 spurious interrupt vector.
1100 *
1101 * IMPLICATION: The spurious interrupt vector programmed in the
1102 * 8259 is normally handled by an operating system's spurious
1103 * interrupt handler. However, a vector of 0Fh is unknown to some
1104 * operating systems, which would crash if this erratum occurred.
1105 *
1106 * In theory this could be limited to 32bit, but the handler is not
1107 * hurting and who knows which other CPUs suffer from this.
1108 */
1109}
1110
1111DEFINE_IDTENTRY(exc_device_not_available)
1112{
1113 unsigned long cr0 = read_cr0();
1114
1115#ifdef CONFIG_MATH_EMULATION
1116 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) {
1117 struct math_emu_info info = { };
1118
1119 cond_local_irq_enable(regs);
1120
1121 info.regs = regs;
1122 math_emulate(&info);
1123
1124 cond_local_irq_disable(regs);
1125 return;
1126 }
1127#endif
1128
1129 /* This should not happen. */
1130 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) {
1131 /* Try to fix it up and carry on. */
1132 write_cr0(cr0 & ~X86_CR0_TS);
1133 } else {
1134 /*
1135 * Something terrible happened, and we're better off trying
1136 * to kill the task than getting stuck in a never-ending
1137 * loop of #NM faults.
1138 */
1139 die("unexpected #NM exception", regs, 0);
1140 }
1141}
1142
1143#ifdef CONFIG_X86_32
1144DEFINE_IDTENTRY_SW(iret_error)
1145{
1146 local_irq_enable();
1147 if (notify_die(DIE_TRAP, "iret exception", regs, 0,
1148 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
1149 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0,
1150 ILL_BADSTK, (void __user *)NULL);
1151 }
1152 local_irq_disable();
1153}
1154#endif
1155
1156void __init trap_init(void)
1157{
1158 /* Init cpu_entry_area before IST entries are set up */
1159 setup_cpu_entry_areas();
1160
1161 /* Init GHCB memory pages when running as an SEV-ES guest */
1162 sev_es_init_vc_handling();
1163
1164 /* Initialize TSS before setting up traps so ISTs work */
1165 cpu_init_exception_handling();
1166 /* Setup traps as cpu_init() might #GP */
1167 idt_setup_traps();
1168 cpu_init();
1169}