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1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/irq.h>
14#include <linux/spi/spi.h>
15#include <linux/platform_device.h>
16#include <linux/fsl_devices.h>
17#include <linux/mm.h>
18#include <linux/of.h>
19#include <linux/of_platform.h>
20#include <linux/interrupt.h>
21#include <linux/err.h>
22#include <sysdev/fsl_soc.h>
23
24#include "spi-fsl-lib.h"
25
26/* eSPI Controller registers */
27struct fsl_espi_reg {
28 __be32 mode; /* 0x000 - eSPI mode register */
29 __be32 event; /* 0x004 - eSPI event register */
30 __be32 mask; /* 0x008 - eSPI mask register */
31 __be32 command; /* 0x00c - eSPI command register */
32 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
33 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
34 u8 res[8]; /* 0x018 - 0x01c reserved */
35 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
36};
37
38struct fsl_espi_transfer {
39 const void *tx_buf;
40 void *rx_buf;
41 unsigned len;
42 unsigned n_tx;
43 unsigned n_rx;
44 unsigned actual_length;
45 int status;
46};
47
48/* eSPI Controller mode register definitions */
49#define SPMODE_ENABLE (1 << 31)
50#define SPMODE_LOOP (1 << 30)
51#define SPMODE_TXTHR(x) ((x) << 8)
52#define SPMODE_RXTHR(x) ((x) << 0)
53
54/* eSPI Controller CS mode register definitions */
55#define CSMODE_CI_INACTIVEHIGH (1 << 31)
56#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
57#define CSMODE_REV (1 << 29)
58#define CSMODE_DIV16 (1 << 28)
59#define CSMODE_PM(x) ((x) << 24)
60#define CSMODE_POL_1 (1 << 20)
61#define CSMODE_LEN(x) ((x) << 16)
62#define CSMODE_BEF(x) ((x) << 12)
63#define CSMODE_AFT(x) ((x) << 8)
64#define CSMODE_CG(x) ((x) << 3)
65
66/* Default mode/csmode for eSPI controller */
67#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
68#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
69 | CSMODE_AFT(0) | CSMODE_CG(1))
70
71/* SPIE register values */
72#define SPIE_NE 0x00000200 /* Not empty */
73#define SPIE_NF 0x00000100 /* Not full */
74
75/* SPIM register values */
76#define SPIM_NE 0x00000200 /* Not empty */
77#define SPIM_NF 0x00000100 /* Not full */
78#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
79#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
80
81/* SPCOM register values */
82#define SPCOM_CS(x) ((x) << 30)
83#define SPCOM_TRANLEN(x) ((x) << 0)
84#define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
85
86static void fsl_espi_change_mode(struct spi_device *spi)
87{
88 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
89 struct spi_mpc8xxx_cs *cs = spi->controller_state;
90 struct fsl_espi_reg *reg_base = mspi->reg_base;
91 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
92 __be32 __iomem *espi_mode = ®_base->mode;
93 u32 tmp;
94 unsigned long flags;
95
96 /* Turn off IRQs locally to minimize time that SPI is disabled. */
97 local_irq_save(flags);
98
99 /* Turn off SPI unit prior changing mode */
100 tmp = mpc8xxx_spi_read_reg(espi_mode);
101 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
102 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
103 mpc8xxx_spi_write_reg(espi_mode, tmp);
104
105 local_irq_restore(flags);
106}
107
108static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
109{
110 u32 data;
111 u16 data_h;
112 u16 data_l;
113 const u32 *tx = mpc8xxx_spi->tx;
114
115 if (!tx)
116 return 0;
117
118 data = *tx++ << mpc8xxx_spi->tx_shift;
119 data_l = data & 0xffff;
120 data_h = (data >> 16) & 0xffff;
121 swab16s(&data_l);
122 swab16s(&data_h);
123 data = data_h | data_l;
124
125 mpc8xxx_spi->tx = tx;
126 return data;
127}
128
129static int fsl_espi_setup_transfer(struct spi_device *spi,
130 struct spi_transfer *t)
131{
132 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
133 int bits_per_word = 0;
134 u8 pm;
135 u32 hz = 0;
136 struct spi_mpc8xxx_cs *cs = spi->controller_state;
137
138 if (t) {
139 bits_per_word = t->bits_per_word;
140 hz = t->speed_hz;
141 }
142
143 /* spi_transfer level calls that work per-word */
144 if (!bits_per_word)
145 bits_per_word = spi->bits_per_word;
146
147 /* Make sure its a bit width we support [4..16] */
148 if ((bits_per_word < 4) || (bits_per_word > 16))
149 return -EINVAL;
150
151 if (!hz)
152 hz = spi->max_speed_hz;
153
154 cs->rx_shift = 0;
155 cs->tx_shift = 0;
156 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
157 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
158 if (bits_per_word <= 8) {
159 cs->rx_shift = 8 - bits_per_word;
160 } else if (bits_per_word <= 16) {
161 cs->rx_shift = 16 - bits_per_word;
162 if (spi->mode & SPI_LSB_FIRST)
163 cs->get_tx = fsl_espi_tx_buf_lsb;
164 } else {
165 return -EINVAL;
166 }
167
168 mpc8xxx_spi->rx_shift = cs->rx_shift;
169 mpc8xxx_spi->tx_shift = cs->tx_shift;
170 mpc8xxx_spi->get_rx = cs->get_rx;
171 mpc8xxx_spi->get_tx = cs->get_tx;
172
173 bits_per_word = bits_per_word - 1;
174
175 /* mask out bits we are going to set */
176 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
177
178 cs->hw_mode |= CSMODE_LEN(bits_per_word);
179
180 if ((mpc8xxx_spi->spibrg / hz) > 64) {
181 cs->hw_mode |= CSMODE_DIV16;
182 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
183
184 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
185 "Will use %d Hz instead.\n", dev_name(&spi->dev),
186 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
187 if (pm > 33)
188 pm = 33;
189 } else {
190 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
191 }
192 if (pm)
193 pm--;
194 if (pm < 2)
195 pm = 2;
196
197 cs->hw_mode |= CSMODE_PM(pm);
198
199 fsl_espi_change_mode(spi);
200 return 0;
201}
202
203static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
204 unsigned int len)
205{
206 u32 word;
207 struct fsl_espi_reg *reg_base = mspi->reg_base;
208
209 mspi->count = len;
210
211 /* enable rx ints */
212 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
213
214 /* transmit word */
215 word = mspi->get_tx(mspi);
216 mpc8xxx_spi_write_reg(®_base->transmit, word);
217
218 return 0;
219}
220
221static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
222{
223 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
224 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
225 unsigned int len = t->len;
226 u8 bits_per_word;
227 int ret;
228
229 bits_per_word = spi->bits_per_word;
230 if (t->bits_per_word)
231 bits_per_word = t->bits_per_word;
232
233 mpc8xxx_spi->len = t->len;
234 len = roundup(len, 4) / 4;
235
236 mpc8xxx_spi->tx = t->tx_buf;
237 mpc8xxx_spi->rx = t->rx_buf;
238
239 INIT_COMPLETION(mpc8xxx_spi->done);
240
241 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
242 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
243 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
244 " beyond the SPCOM[TRANLEN] field\n", t->len);
245 return -EINVAL;
246 }
247 mpc8xxx_spi_write_reg(®_base->command,
248 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
249
250 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
251 if (ret)
252 return ret;
253
254 wait_for_completion(&mpc8xxx_spi->done);
255
256 /* disable rx ints */
257 mpc8xxx_spi_write_reg(®_base->mask, 0);
258
259 return mpc8xxx_spi->count;
260}
261
262static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
263{
264 if (cmd) {
265 cmd[1] = (u8)(addr >> 16);
266 cmd[2] = (u8)(addr >> 8);
267 cmd[3] = (u8)(addr >> 0);
268 }
269}
270
271static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
272{
273 if (cmd)
274 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
275
276 return 0;
277}
278
279static void fsl_espi_do_trans(struct spi_message *m,
280 struct fsl_espi_transfer *tr)
281{
282 struct spi_device *spi = m->spi;
283 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
284 struct fsl_espi_transfer *espi_trans = tr;
285 struct spi_message message;
286 struct spi_transfer *t, *first, trans;
287 int status = 0;
288
289 spi_message_init(&message);
290 memset(&trans, 0, sizeof(trans));
291
292 first = list_first_entry(&m->transfers, struct spi_transfer,
293 transfer_list);
294 list_for_each_entry(t, &m->transfers, transfer_list) {
295 if ((first->bits_per_word != t->bits_per_word) ||
296 (first->speed_hz != t->speed_hz)) {
297 espi_trans->status = -EINVAL;
298 dev_err(mspi->dev, "bits_per_word/speed_hz should be"
299 " same for the same SPI transfer\n");
300 return;
301 }
302
303 trans.speed_hz = t->speed_hz;
304 trans.bits_per_word = t->bits_per_word;
305 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
306 }
307
308 trans.len = espi_trans->len;
309 trans.tx_buf = espi_trans->tx_buf;
310 trans.rx_buf = espi_trans->rx_buf;
311 spi_message_add_tail(&trans, &message);
312
313 list_for_each_entry(t, &message.transfers, transfer_list) {
314 if (t->bits_per_word || t->speed_hz) {
315 status = -EINVAL;
316
317 status = fsl_espi_setup_transfer(spi, t);
318 if (status < 0)
319 break;
320 }
321
322 if (t->len)
323 status = fsl_espi_bufs(spi, t);
324
325 if (status) {
326 status = -EMSGSIZE;
327 break;
328 }
329
330 if (t->delay_usecs)
331 udelay(t->delay_usecs);
332 }
333
334 espi_trans->status = status;
335 fsl_espi_setup_transfer(spi, NULL);
336}
337
338static void fsl_espi_cmd_trans(struct spi_message *m,
339 struct fsl_espi_transfer *trans, u8 *rx_buff)
340{
341 struct spi_transfer *t;
342 u8 *local_buf;
343 int i = 0;
344 struct fsl_espi_transfer *espi_trans = trans;
345
346 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
347 if (!local_buf) {
348 espi_trans->status = -ENOMEM;
349 return;
350 }
351
352 list_for_each_entry(t, &m->transfers, transfer_list) {
353 if (t->tx_buf) {
354 memcpy(local_buf + i, t->tx_buf, t->len);
355 i += t->len;
356 }
357 }
358
359 espi_trans->tx_buf = local_buf;
360 espi_trans->rx_buf = local_buf + espi_trans->n_tx;
361 fsl_espi_do_trans(m, espi_trans);
362
363 espi_trans->actual_length = espi_trans->len;
364 kfree(local_buf);
365}
366
367static void fsl_espi_rw_trans(struct spi_message *m,
368 struct fsl_espi_transfer *trans, u8 *rx_buff)
369{
370 struct fsl_espi_transfer *espi_trans = trans;
371 unsigned int n_tx = espi_trans->n_tx;
372 unsigned int n_rx = espi_trans->n_rx;
373 struct spi_transfer *t;
374 u8 *local_buf;
375 u8 *rx_buf = rx_buff;
376 unsigned int trans_len;
377 unsigned int addr;
378 int i, pos, loop;
379
380 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
381 if (!local_buf) {
382 espi_trans->status = -ENOMEM;
383 return;
384 }
385
386 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
387 trans_len = n_rx - pos;
388 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
389 trans_len = SPCOM_TRANLEN_MAX - n_tx;
390
391 i = 0;
392 list_for_each_entry(t, &m->transfers, transfer_list) {
393 if (t->tx_buf) {
394 memcpy(local_buf + i, t->tx_buf, t->len);
395 i += t->len;
396 }
397 }
398
399 if (pos > 0) {
400 addr = fsl_espi_cmd2addr(local_buf);
401 addr += pos;
402 fsl_espi_addr2cmd(addr, local_buf);
403 }
404
405 espi_trans->n_tx = n_tx;
406 espi_trans->n_rx = trans_len;
407 espi_trans->len = trans_len + n_tx;
408 espi_trans->tx_buf = local_buf;
409 espi_trans->rx_buf = local_buf + n_tx;
410 fsl_espi_do_trans(m, espi_trans);
411
412 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
413
414 if (loop > 0)
415 espi_trans->actual_length += espi_trans->len - n_tx;
416 else
417 espi_trans->actual_length += espi_trans->len;
418 }
419
420 kfree(local_buf);
421}
422
423static void fsl_espi_do_one_msg(struct spi_message *m)
424{
425 struct spi_transfer *t;
426 u8 *rx_buf = NULL;
427 unsigned int n_tx = 0;
428 unsigned int n_rx = 0;
429 struct fsl_espi_transfer espi_trans;
430
431 list_for_each_entry(t, &m->transfers, transfer_list) {
432 if (t->tx_buf)
433 n_tx += t->len;
434 if (t->rx_buf) {
435 n_rx += t->len;
436 rx_buf = t->rx_buf;
437 }
438 }
439
440 espi_trans.n_tx = n_tx;
441 espi_trans.n_rx = n_rx;
442 espi_trans.len = n_tx + n_rx;
443 espi_trans.actual_length = 0;
444 espi_trans.status = 0;
445
446 if (!rx_buf)
447 fsl_espi_cmd_trans(m, &espi_trans, NULL);
448 else
449 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
450
451 m->actual_length = espi_trans.actual_length;
452 m->status = espi_trans.status;
453 m->complete(m->context);
454}
455
456static int fsl_espi_setup(struct spi_device *spi)
457{
458 struct mpc8xxx_spi *mpc8xxx_spi;
459 struct fsl_espi_reg *reg_base;
460 int retval;
461 u32 hw_mode;
462 u32 loop_mode;
463 struct spi_mpc8xxx_cs *cs = spi->controller_state;
464
465 if (!spi->max_speed_hz)
466 return -EINVAL;
467
468 if (!cs) {
469 cs = kzalloc(sizeof *cs, GFP_KERNEL);
470 if (!cs)
471 return -ENOMEM;
472 spi->controller_state = cs;
473 }
474
475 mpc8xxx_spi = spi_master_get_devdata(spi->master);
476 reg_base = mpc8xxx_spi->reg_base;
477
478 hw_mode = cs->hw_mode; /* Save original settings */
479 cs->hw_mode = mpc8xxx_spi_read_reg(
480 ®_base->csmode[spi->chip_select]);
481 /* mask out bits we are going to set */
482 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
483 | CSMODE_REV);
484
485 if (spi->mode & SPI_CPHA)
486 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
487 if (spi->mode & SPI_CPOL)
488 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
489 if (!(spi->mode & SPI_LSB_FIRST))
490 cs->hw_mode |= CSMODE_REV;
491
492 /* Handle the loop mode */
493 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
494 loop_mode &= ~SPMODE_LOOP;
495 if (spi->mode & SPI_LOOP)
496 loop_mode |= SPMODE_LOOP;
497 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
498
499 retval = fsl_espi_setup_transfer(spi, NULL);
500 if (retval < 0) {
501 cs->hw_mode = hw_mode; /* Restore settings */
502 return retval;
503 }
504 return 0;
505}
506
507void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
508{
509 struct fsl_espi_reg *reg_base = mspi->reg_base;
510
511 /* We need handle RX first */
512 if (events & SPIE_NE) {
513 u32 rx_data, tmp;
514 u8 rx_data_8;
515
516 /* Spin until RX is done */
517 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
518 cpu_relax();
519 events = mpc8xxx_spi_read_reg(®_base->event);
520 }
521
522 if (mspi->len >= 4) {
523 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
524 } else {
525 tmp = mspi->len;
526 rx_data = 0;
527 while (tmp--) {
528 rx_data_8 = in_8((u8 *)®_base->receive);
529 rx_data |= (rx_data_8 << (tmp * 8));
530 }
531
532 rx_data <<= (4 - mspi->len) * 8;
533 }
534
535 mspi->len -= 4;
536
537 if (mspi->rx)
538 mspi->get_rx(rx_data, mspi);
539 }
540
541 if (!(events & SPIE_NF)) {
542 int ret;
543
544 /* spin until TX is done */
545 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
546 ®_base->event)) & SPIE_NF) == 0, 1000, 0);
547 if (!ret) {
548 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
549 return;
550 }
551 }
552
553 /* Clear the events */
554 mpc8xxx_spi_write_reg(®_base->event, events);
555
556 mspi->count -= 1;
557 if (mspi->count) {
558 u32 word = mspi->get_tx(mspi);
559
560 mpc8xxx_spi_write_reg(®_base->transmit, word);
561 } else {
562 complete(&mspi->done);
563 }
564}
565
566static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
567{
568 struct mpc8xxx_spi *mspi = context_data;
569 struct fsl_espi_reg *reg_base = mspi->reg_base;
570 irqreturn_t ret = IRQ_NONE;
571 u32 events;
572
573 /* Get interrupt events(tx/rx) */
574 events = mpc8xxx_spi_read_reg(®_base->event);
575 if (events)
576 ret = IRQ_HANDLED;
577
578 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
579
580 fsl_espi_cpu_irq(mspi, events);
581
582 return ret;
583}
584
585static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
586{
587 iounmap(mspi->reg_base);
588}
589
590static struct spi_master * __devinit fsl_espi_probe(struct device *dev,
591 struct resource *mem, unsigned int irq)
592{
593 struct fsl_spi_platform_data *pdata = dev->platform_data;
594 struct spi_master *master;
595 struct mpc8xxx_spi *mpc8xxx_spi;
596 struct fsl_espi_reg *reg_base;
597 u32 regval;
598 int i, ret = 0;
599
600 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
601 if (!master) {
602 ret = -ENOMEM;
603 goto err;
604 }
605
606 dev_set_drvdata(dev, master);
607
608 ret = mpc8xxx_spi_probe(dev, mem, irq);
609 if (ret)
610 goto err_probe;
611
612 master->setup = fsl_espi_setup;
613
614 mpc8xxx_spi = spi_master_get_devdata(master);
615 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
616 mpc8xxx_spi->spi_remove = fsl_espi_remove;
617
618 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
619 if (!mpc8xxx_spi->reg_base) {
620 ret = -ENOMEM;
621 goto err_probe;
622 }
623
624 reg_base = mpc8xxx_spi->reg_base;
625
626 /* Register for SPI Interrupt */
627 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
628 0, "fsl_espi", mpc8xxx_spi);
629 if (ret)
630 goto free_irq;
631
632 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
633 mpc8xxx_spi->rx_shift = 16;
634 mpc8xxx_spi->tx_shift = 24;
635 }
636
637 /* SPI controller initializations */
638 mpc8xxx_spi_write_reg(®_base->mode, 0);
639 mpc8xxx_spi_write_reg(®_base->mask, 0);
640 mpc8xxx_spi_write_reg(®_base->command, 0);
641 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
642
643 /* Init eSPI CS mode register */
644 for (i = 0; i < pdata->max_chipselect; i++)
645 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
646
647 /* Enable SPI interface */
648 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
649
650 mpc8xxx_spi_write_reg(®_base->mode, regval);
651
652 ret = spi_register_master(master);
653 if (ret < 0)
654 goto unreg_master;
655
656 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
657
658 return master;
659
660unreg_master:
661 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
662free_irq:
663 iounmap(mpc8xxx_spi->reg_base);
664err_probe:
665 spi_master_put(master);
666err:
667 return ERR_PTR(ret);
668}
669
670static int of_fsl_espi_get_chipselects(struct device *dev)
671{
672 struct device_node *np = dev->of_node;
673 struct fsl_spi_platform_data *pdata = dev->platform_data;
674 const u32 *prop;
675 int len;
676
677 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
678 if (!prop || len < sizeof(*prop)) {
679 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
680 return -EINVAL;
681 }
682
683 pdata->max_chipselect = *prop;
684 pdata->cs_control = NULL;
685
686 return 0;
687}
688
689static int __devinit of_fsl_espi_probe(struct platform_device *ofdev)
690{
691 struct device *dev = &ofdev->dev;
692 struct device_node *np = ofdev->dev.of_node;
693 struct spi_master *master;
694 struct resource mem;
695 struct resource irq;
696 int ret = -ENOMEM;
697
698 ret = of_mpc8xxx_spi_probe(ofdev);
699 if (ret)
700 return ret;
701
702 ret = of_fsl_espi_get_chipselects(dev);
703 if (ret)
704 goto err;
705
706 ret = of_address_to_resource(np, 0, &mem);
707 if (ret)
708 goto err;
709
710 ret = of_irq_to_resource(np, 0, &irq);
711 if (!ret) {
712 ret = -EINVAL;
713 goto err;
714 }
715
716 master = fsl_espi_probe(dev, &mem, irq.start);
717 if (IS_ERR(master)) {
718 ret = PTR_ERR(master);
719 goto err;
720 }
721
722 return 0;
723
724err:
725 return ret;
726}
727
728static int __devexit of_fsl_espi_remove(struct platform_device *dev)
729{
730 return mpc8xxx_spi_remove(&dev->dev);
731}
732
733static const struct of_device_id of_fsl_espi_match[] = {
734 { .compatible = "fsl,mpc8536-espi" },
735 {}
736};
737MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
738
739static struct platform_driver fsl_espi_driver = {
740 .driver = {
741 .name = "fsl_espi",
742 .owner = THIS_MODULE,
743 .of_match_table = of_fsl_espi_match,
744 },
745 .probe = of_fsl_espi_probe,
746 .remove = __devexit_p(of_fsl_espi_remove),
747};
748module_platform_driver(fsl_espi_driver);
749
750MODULE_AUTHOR("Mingkai Hu");
751MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
752MODULE_LICENSE("GPL");
1/*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/fsl_devices.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/module.h>
17#include <linux/mm.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/of_platform.h>
22#include <linux/platform_device.h>
23#include <linux/spi/spi.h>
24#include <linux/pm_runtime.h>
25#include <sysdev/fsl_soc.h>
26
27#include "spi-fsl-lib.h"
28
29/* eSPI Controller registers */
30struct fsl_espi_reg {
31 __be32 mode; /* 0x000 - eSPI mode register */
32 __be32 event; /* 0x004 - eSPI event register */
33 __be32 mask; /* 0x008 - eSPI mask register */
34 __be32 command; /* 0x00c - eSPI command register */
35 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
36 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
37 u8 res[8]; /* 0x018 - 0x01c reserved */
38 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
39};
40
41struct fsl_espi_transfer {
42 const void *tx_buf;
43 void *rx_buf;
44 unsigned len;
45 unsigned n_tx;
46 unsigned n_rx;
47 unsigned actual_length;
48 int status;
49};
50
51/* eSPI Controller mode register definitions */
52#define SPMODE_ENABLE (1 << 31)
53#define SPMODE_LOOP (1 << 30)
54#define SPMODE_TXTHR(x) ((x) << 8)
55#define SPMODE_RXTHR(x) ((x) << 0)
56
57/* eSPI Controller CS mode register definitions */
58#define CSMODE_CI_INACTIVEHIGH (1 << 31)
59#define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
60#define CSMODE_REV (1 << 29)
61#define CSMODE_DIV16 (1 << 28)
62#define CSMODE_PM(x) ((x) << 24)
63#define CSMODE_POL_1 (1 << 20)
64#define CSMODE_LEN(x) ((x) << 16)
65#define CSMODE_BEF(x) ((x) << 12)
66#define CSMODE_AFT(x) ((x) << 8)
67#define CSMODE_CG(x) ((x) << 3)
68
69/* Default mode/csmode for eSPI controller */
70#define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
71#define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
72 | CSMODE_AFT(0) | CSMODE_CG(1))
73
74/* SPIE register values */
75#define SPIE_NE 0x00000200 /* Not empty */
76#define SPIE_NF 0x00000100 /* Not full */
77
78/* SPIM register values */
79#define SPIM_NE 0x00000200 /* Not empty */
80#define SPIM_NF 0x00000100 /* Not full */
81#define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
82#define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
83
84/* SPCOM register values */
85#define SPCOM_CS(x) ((x) << 30)
86#define SPCOM_TRANLEN(x) ((x) << 0)
87#define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
88
89#define AUTOSUSPEND_TIMEOUT 2000
90
91static void fsl_espi_change_mode(struct spi_device *spi)
92{
93 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
94 struct spi_mpc8xxx_cs *cs = spi->controller_state;
95 struct fsl_espi_reg *reg_base = mspi->reg_base;
96 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
97 __be32 __iomem *espi_mode = ®_base->mode;
98 u32 tmp;
99 unsigned long flags;
100
101 /* Turn off IRQs locally to minimize time that SPI is disabled. */
102 local_irq_save(flags);
103
104 /* Turn off SPI unit prior changing mode */
105 tmp = mpc8xxx_spi_read_reg(espi_mode);
106 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
107 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
108 mpc8xxx_spi_write_reg(espi_mode, tmp);
109
110 local_irq_restore(flags);
111}
112
113static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
114{
115 u32 data;
116 u16 data_h;
117 u16 data_l;
118 const u32 *tx = mpc8xxx_spi->tx;
119
120 if (!tx)
121 return 0;
122
123 data = *tx++ << mpc8xxx_spi->tx_shift;
124 data_l = data & 0xffff;
125 data_h = (data >> 16) & 0xffff;
126 swab16s(&data_l);
127 swab16s(&data_h);
128 data = data_h | data_l;
129
130 mpc8xxx_spi->tx = tx;
131 return data;
132}
133
134static int fsl_espi_setup_transfer(struct spi_device *spi,
135 struct spi_transfer *t)
136{
137 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
138 int bits_per_word = 0;
139 u8 pm;
140 u32 hz = 0;
141 struct spi_mpc8xxx_cs *cs = spi->controller_state;
142
143 if (t) {
144 bits_per_word = t->bits_per_word;
145 hz = t->speed_hz;
146 }
147
148 /* spi_transfer level calls that work per-word */
149 if (!bits_per_word)
150 bits_per_word = spi->bits_per_word;
151
152 if (!hz)
153 hz = spi->max_speed_hz;
154
155 cs->rx_shift = 0;
156 cs->tx_shift = 0;
157 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
158 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
159 if (bits_per_word <= 8) {
160 cs->rx_shift = 8 - bits_per_word;
161 } else {
162 cs->rx_shift = 16 - bits_per_word;
163 if (spi->mode & SPI_LSB_FIRST)
164 cs->get_tx = fsl_espi_tx_buf_lsb;
165 }
166
167 mpc8xxx_spi->rx_shift = cs->rx_shift;
168 mpc8xxx_spi->tx_shift = cs->tx_shift;
169 mpc8xxx_spi->get_rx = cs->get_rx;
170 mpc8xxx_spi->get_tx = cs->get_tx;
171
172 bits_per_word = bits_per_word - 1;
173
174 /* mask out bits we are going to set */
175 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
176
177 cs->hw_mode |= CSMODE_LEN(bits_per_word);
178
179 if ((mpc8xxx_spi->spibrg / hz) > 64) {
180 cs->hw_mode |= CSMODE_DIV16;
181 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
182
183 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
184 "Will use %d Hz instead.\n", dev_name(&spi->dev),
185 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
186 if (pm > 33)
187 pm = 33;
188 } else {
189 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
190 }
191 if (pm)
192 pm--;
193 if (pm < 2)
194 pm = 2;
195
196 cs->hw_mode |= CSMODE_PM(pm);
197
198 fsl_espi_change_mode(spi);
199 return 0;
200}
201
202static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
203 unsigned int len)
204{
205 u32 word;
206 struct fsl_espi_reg *reg_base = mspi->reg_base;
207
208 mspi->count = len;
209
210 /* enable rx ints */
211 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
212
213 /* transmit word */
214 word = mspi->get_tx(mspi);
215 mpc8xxx_spi_write_reg(®_base->transmit, word);
216
217 return 0;
218}
219
220static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
221{
222 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
223 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
224 unsigned int len = t->len;
225 int ret;
226
227 mpc8xxx_spi->len = t->len;
228 len = roundup(len, 4) / 4;
229
230 mpc8xxx_spi->tx = t->tx_buf;
231 mpc8xxx_spi->rx = t->rx_buf;
232
233 reinit_completion(&mpc8xxx_spi->done);
234
235 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
236 if (t->len > SPCOM_TRANLEN_MAX) {
237 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
238 " beyond the SPCOM[TRANLEN] field\n", t->len);
239 return -EINVAL;
240 }
241 mpc8xxx_spi_write_reg(®_base->command,
242 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
243
244 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
245 if (ret)
246 return ret;
247
248 wait_for_completion(&mpc8xxx_spi->done);
249
250 /* disable rx ints */
251 mpc8xxx_spi_write_reg(®_base->mask, 0);
252
253 return mpc8xxx_spi->count;
254}
255
256static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
257{
258 if (cmd) {
259 cmd[1] = (u8)(addr >> 16);
260 cmd[2] = (u8)(addr >> 8);
261 cmd[3] = (u8)(addr >> 0);
262 }
263}
264
265static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
266{
267 if (cmd)
268 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
269
270 return 0;
271}
272
273static void fsl_espi_do_trans(struct spi_message *m,
274 struct fsl_espi_transfer *tr)
275{
276 struct spi_device *spi = m->spi;
277 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
278 struct fsl_espi_transfer *espi_trans = tr;
279 struct spi_message message;
280 struct spi_transfer *t, *first, trans;
281 int status = 0;
282
283 spi_message_init(&message);
284 memset(&trans, 0, sizeof(trans));
285
286 first = list_first_entry(&m->transfers, struct spi_transfer,
287 transfer_list);
288 list_for_each_entry(t, &m->transfers, transfer_list) {
289 if ((first->bits_per_word != t->bits_per_word) ||
290 (first->speed_hz != t->speed_hz)) {
291 espi_trans->status = -EINVAL;
292 dev_err(mspi->dev,
293 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
294 return;
295 }
296
297 trans.speed_hz = t->speed_hz;
298 trans.bits_per_word = t->bits_per_word;
299 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
300 }
301
302 trans.len = espi_trans->len;
303 trans.tx_buf = espi_trans->tx_buf;
304 trans.rx_buf = espi_trans->rx_buf;
305 spi_message_add_tail(&trans, &message);
306
307 list_for_each_entry(t, &message.transfers, transfer_list) {
308 if (t->bits_per_word || t->speed_hz) {
309 status = -EINVAL;
310
311 status = fsl_espi_setup_transfer(spi, t);
312 if (status < 0)
313 break;
314 }
315
316 if (t->len)
317 status = fsl_espi_bufs(spi, t);
318
319 if (status) {
320 status = -EMSGSIZE;
321 break;
322 }
323
324 if (t->delay_usecs)
325 udelay(t->delay_usecs);
326 }
327
328 espi_trans->status = status;
329 fsl_espi_setup_transfer(spi, NULL);
330}
331
332static void fsl_espi_cmd_trans(struct spi_message *m,
333 struct fsl_espi_transfer *trans, u8 *rx_buff)
334{
335 struct spi_transfer *t;
336 u8 *local_buf;
337 int i = 0;
338 struct fsl_espi_transfer *espi_trans = trans;
339
340 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
341 if (!local_buf) {
342 espi_trans->status = -ENOMEM;
343 return;
344 }
345
346 list_for_each_entry(t, &m->transfers, transfer_list) {
347 if (t->tx_buf) {
348 memcpy(local_buf + i, t->tx_buf, t->len);
349 i += t->len;
350 }
351 }
352
353 espi_trans->tx_buf = local_buf;
354 espi_trans->rx_buf = local_buf;
355 fsl_espi_do_trans(m, espi_trans);
356
357 espi_trans->actual_length = espi_trans->len;
358 kfree(local_buf);
359}
360
361static void fsl_espi_rw_trans(struct spi_message *m,
362 struct fsl_espi_transfer *trans, u8 *rx_buff)
363{
364 struct fsl_espi_transfer *espi_trans = trans;
365 unsigned int total_len = espi_trans->len;
366 struct spi_transfer *t;
367 u8 *local_buf;
368 u8 *rx_buf = rx_buff;
369 unsigned int trans_len;
370 unsigned int addr;
371 unsigned int tx_only;
372 unsigned int rx_pos = 0;
373 unsigned int pos;
374 int i, loop;
375
376 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
377 if (!local_buf) {
378 espi_trans->status = -ENOMEM;
379 return;
380 }
381
382 for (pos = 0, loop = 0; pos < total_len; pos += trans_len, loop++) {
383 trans_len = total_len - pos;
384
385 i = 0;
386 tx_only = 0;
387 list_for_each_entry(t, &m->transfers, transfer_list) {
388 if (t->tx_buf) {
389 memcpy(local_buf + i, t->tx_buf, t->len);
390 i += t->len;
391 if (!t->rx_buf)
392 tx_only += t->len;
393 }
394 }
395
396 /* Add additional TX bytes to compensate SPCOM_TRANLEN_MAX */
397 if (loop > 0)
398 trans_len += tx_only;
399
400 if (trans_len > SPCOM_TRANLEN_MAX)
401 trans_len = SPCOM_TRANLEN_MAX;
402
403 /* Update device offset */
404 if (pos > 0) {
405 addr = fsl_espi_cmd2addr(local_buf);
406 addr += rx_pos;
407 fsl_espi_addr2cmd(addr, local_buf);
408 }
409
410 espi_trans->len = trans_len;
411 espi_trans->tx_buf = local_buf;
412 espi_trans->rx_buf = local_buf;
413 fsl_espi_do_trans(m, espi_trans);
414
415 /* If there is at least one RX byte then copy it to rx_buf */
416 if (tx_only < SPCOM_TRANLEN_MAX)
417 memcpy(rx_buf + rx_pos, espi_trans->rx_buf + tx_only,
418 trans_len - tx_only);
419
420 rx_pos += trans_len - tx_only;
421
422 if (loop > 0)
423 espi_trans->actual_length += espi_trans->len - tx_only;
424 else
425 espi_trans->actual_length += espi_trans->len;
426 }
427
428 kfree(local_buf);
429}
430
431static int fsl_espi_do_one_msg(struct spi_master *master,
432 struct spi_message *m)
433{
434 struct spi_transfer *t;
435 u8 *rx_buf = NULL;
436 unsigned int n_tx = 0;
437 unsigned int n_rx = 0;
438 unsigned int xfer_len = 0;
439 struct fsl_espi_transfer espi_trans;
440
441 list_for_each_entry(t, &m->transfers, transfer_list) {
442 if (t->tx_buf)
443 n_tx += t->len;
444 if (t->rx_buf) {
445 n_rx += t->len;
446 rx_buf = t->rx_buf;
447 }
448 if ((t->tx_buf) || (t->rx_buf))
449 xfer_len += t->len;
450 }
451
452 espi_trans.n_tx = n_tx;
453 espi_trans.n_rx = n_rx;
454 espi_trans.len = xfer_len;
455 espi_trans.actual_length = 0;
456 espi_trans.status = 0;
457
458 if (!rx_buf)
459 fsl_espi_cmd_trans(m, &espi_trans, NULL);
460 else
461 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
462
463 m->actual_length = espi_trans.actual_length;
464 m->status = espi_trans.status;
465 spi_finalize_current_message(master);
466 return 0;
467}
468
469static int fsl_espi_setup(struct spi_device *spi)
470{
471 struct mpc8xxx_spi *mpc8xxx_spi;
472 struct fsl_espi_reg *reg_base;
473 int retval;
474 u32 hw_mode;
475 u32 loop_mode;
476 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
477
478 if (!spi->max_speed_hz)
479 return -EINVAL;
480
481 if (!cs) {
482 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
483 if (!cs)
484 return -ENOMEM;
485 spi_set_ctldata(spi, cs);
486 }
487
488 mpc8xxx_spi = spi_master_get_devdata(spi->master);
489 reg_base = mpc8xxx_spi->reg_base;
490
491 pm_runtime_get_sync(mpc8xxx_spi->dev);
492
493 hw_mode = cs->hw_mode; /* Save original settings */
494 cs->hw_mode = mpc8xxx_spi_read_reg(
495 ®_base->csmode[spi->chip_select]);
496 /* mask out bits we are going to set */
497 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
498 | CSMODE_REV);
499
500 if (spi->mode & SPI_CPHA)
501 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
502 if (spi->mode & SPI_CPOL)
503 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
504 if (!(spi->mode & SPI_LSB_FIRST))
505 cs->hw_mode |= CSMODE_REV;
506
507 /* Handle the loop mode */
508 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
509 loop_mode &= ~SPMODE_LOOP;
510 if (spi->mode & SPI_LOOP)
511 loop_mode |= SPMODE_LOOP;
512 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
513
514 retval = fsl_espi_setup_transfer(spi, NULL);
515
516 pm_runtime_mark_last_busy(mpc8xxx_spi->dev);
517 pm_runtime_put_autosuspend(mpc8xxx_spi->dev);
518
519 if (retval < 0) {
520 cs->hw_mode = hw_mode; /* Restore settings */
521 return retval;
522 }
523 return 0;
524}
525
526static void fsl_espi_cleanup(struct spi_device *spi)
527{
528 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
529
530 kfree(cs);
531 spi_set_ctldata(spi, NULL);
532}
533
534void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
535{
536 struct fsl_espi_reg *reg_base = mspi->reg_base;
537
538 /* We need handle RX first */
539 if (events & SPIE_NE) {
540 u32 rx_data, tmp;
541 u8 rx_data_8;
542
543 /* Spin until RX is done */
544 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
545 cpu_relax();
546 events = mpc8xxx_spi_read_reg(®_base->event);
547 }
548
549 if (mspi->len >= 4) {
550 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
551 } else {
552 tmp = mspi->len;
553 rx_data = 0;
554 while (tmp--) {
555 rx_data_8 = in_8((u8 *)®_base->receive);
556 rx_data |= (rx_data_8 << (tmp * 8));
557 }
558
559 rx_data <<= (4 - mspi->len) * 8;
560 }
561
562 mspi->len -= 4;
563
564 if (mspi->rx)
565 mspi->get_rx(rx_data, mspi);
566 }
567
568 if (!(events & SPIE_NF)) {
569 int ret;
570
571 /* spin until TX is done */
572 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
573 ®_base->event)) & SPIE_NF), 1000, 0);
574 if (!ret) {
575 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
576
577 /* Clear the SPIE bits */
578 mpc8xxx_spi_write_reg(®_base->event, events);
579 complete(&mspi->done);
580 return;
581 }
582 }
583
584 /* Clear the events */
585 mpc8xxx_spi_write_reg(®_base->event, events);
586
587 mspi->count -= 1;
588 if (mspi->count) {
589 u32 word = mspi->get_tx(mspi);
590
591 mpc8xxx_spi_write_reg(®_base->transmit, word);
592 } else {
593 complete(&mspi->done);
594 }
595}
596
597static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
598{
599 struct mpc8xxx_spi *mspi = context_data;
600 struct fsl_espi_reg *reg_base = mspi->reg_base;
601 irqreturn_t ret = IRQ_NONE;
602 u32 events;
603
604 /* Get interrupt events(tx/rx) */
605 events = mpc8xxx_spi_read_reg(®_base->event);
606 if (events)
607 ret = IRQ_HANDLED;
608
609 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
610
611 fsl_espi_cpu_irq(mspi, events);
612
613 return ret;
614}
615
616#ifdef CONFIG_PM
617static int fsl_espi_runtime_suspend(struct device *dev)
618{
619 struct spi_master *master = dev_get_drvdata(dev);
620 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
621 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
622 u32 regval;
623
624 regval = mpc8xxx_spi_read_reg(®_base->mode);
625 regval &= ~SPMODE_ENABLE;
626 mpc8xxx_spi_write_reg(®_base->mode, regval);
627
628 return 0;
629}
630
631static int fsl_espi_runtime_resume(struct device *dev)
632{
633 struct spi_master *master = dev_get_drvdata(dev);
634 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
635 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
636 u32 regval;
637
638 regval = mpc8xxx_spi_read_reg(®_base->mode);
639 regval |= SPMODE_ENABLE;
640 mpc8xxx_spi_write_reg(®_base->mode, regval);
641
642 return 0;
643}
644#endif
645
646static size_t fsl_espi_max_transfer_size(struct spi_device *spi)
647{
648 return SPCOM_TRANLEN_MAX;
649}
650
651static struct spi_master * fsl_espi_probe(struct device *dev,
652 struct resource *mem, unsigned int irq)
653{
654 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
655 struct spi_master *master;
656 struct mpc8xxx_spi *mpc8xxx_spi;
657 struct fsl_espi_reg *reg_base;
658 struct device_node *nc;
659 const __be32 *prop;
660 u32 regval, csmode;
661 int i, len, ret = 0;
662
663 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
664 if (!master) {
665 ret = -ENOMEM;
666 goto err;
667 }
668
669 dev_set_drvdata(dev, master);
670
671 mpc8xxx_spi_probe(dev, mem, irq);
672
673 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
674 master->setup = fsl_espi_setup;
675 master->cleanup = fsl_espi_cleanup;
676 master->transfer_one_message = fsl_espi_do_one_msg;
677 master->auto_runtime_pm = true;
678 master->max_transfer_size = fsl_espi_max_transfer_size;
679
680 mpc8xxx_spi = spi_master_get_devdata(master);
681
682 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
683 if (IS_ERR(mpc8xxx_spi->reg_base)) {
684 ret = PTR_ERR(mpc8xxx_spi->reg_base);
685 goto err_probe;
686 }
687
688 reg_base = mpc8xxx_spi->reg_base;
689
690 /* Register for SPI Interrupt */
691 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_espi_irq,
692 0, "fsl_espi", mpc8xxx_spi);
693 if (ret)
694 goto err_probe;
695
696 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
697 mpc8xxx_spi->rx_shift = 16;
698 mpc8xxx_spi->tx_shift = 24;
699 }
700
701 /* SPI controller initializations */
702 mpc8xxx_spi_write_reg(®_base->mode, 0);
703 mpc8xxx_spi_write_reg(®_base->mask, 0);
704 mpc8xxx_spi_write_reg(®_base->command, 0);
705 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
706
707 /* Init eSPI CS mode register */
708 for_each_available_child_of_node(master->dev.of_node, nc) {
709 /* get chip select */
710 prop = of_get_property(nc, "reg", &len);
711 if (!prop || len < sizeof(*prop))
712 continue;
713 i = be32_to_cpup(prop);
714 if (i < 0 || i >= pdata->max_chipselect)
715 continue;
716
717 csmode = CSMODE_INIT_VAL;
718 /* check if CSBEF is set in device tree */
719 prop = of_get_property(nc, "fsl,csbef", &len);
720 if (prop && len >= sizeof(*prop)) {
721 csmode &= ~(CSMODE_BEF(0xf));
722 csmode |= CSMODE_BEF(be32_to_cpup(prop));
723 }
724 /* check if CSAFT is set in device tree */
725 prop = of_get_property(nc, "fsl,csaft", &len);
726 if (prop && len >= sizeof(*prop)) {
727 csmode &= ~(CSMODE_AFT(0xf));
728 csmode |= CSMODE_AFT(be32_to_cpup(prop));
729 }
730 mpc8xxx_spi_write_reg(®_base->csmode[i], csmode);
731
732 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
733 }
734
735 /* Enable SPI interface */
736 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
737
738 mpc8xxx_spi_write_reg(®_base->mode, regval);
739
740 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
741 pm_runtime_use_autosuspend(dev);
742 pm_runtime_set_active(dev);
743 pm_runtime_enable(dev);
744 pm_runtime_get_sync(dev);
745
746 ret = devm_spi_register_master(dev, master);
747 if (ret < 0)
748 goto err_pm;
749
750 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
751
752 pm_runtime_mark_last_busy(dev);
753 pm_runtime_put_autosuspend(dev);
754
755 return master;
756
757err_pm:
758 pm_runtime_put_noidle(dev);
759 pm_runtime_disable(dev);
760 pm_runtime_set_suspended(dev);
761err_probe:
762 spi_master_put(master);
763err:
764 return ERR_PTR(ret);
765}
766
767static int of_fsl_espi_get_chipselects(struct device *dev)
768{
769 struct device_node *np = dev->of_node;
770 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
771 const u32 *prop;
772 int len;
773
774 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
775 if (!prop || len < sizeof(*prop)) {
776 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
777 return -EINVAL;
778 }
779
780 pdata->max_chipselect = *prop;
781 pdata->cs_control = NULL;
782
783 return 0;
784}
785
786static int of_fsl_espi_probe(struct platform_device *ofdev)
787{
788 struct device *dev = &ofdev->dev;
789 struct device_node *np = ofdev->dev.of_node;
790 struct spi_master *master;
791 struct resource mem;
792 unsigned int irq;
793 int ret = -ENOMEM;
794
795 ret = of_mpc8xxx_spi_probe(ofdev);
796 if (ret)
797 return ret;
798
799 ret = of_fsl_espi_get_chipselects(dev);
800 if (ret)
801 goto err;
802
803 ret = of_address_to_resource(np, 0, &mem);
804 if (ret)
805 goto err;
806
807 irq = irq_of_parse_and_map(np, 0);
808 if (!irq) {
809 ret = -EINVAL;
810 goto err;
811 }
812
813 master = fsl_espi_probe(dev, &mem, irq);
814 if (IS_ERR(master)) {
815 ret = PTR_ERR(master);
816 goto err;
817 }
818
819 return 0;
820
821err:
822 return ret;
823}
824
825static int of_fsl_espi_remove(struct platform_device *dev)
826{
827 pm_runtime_disable(&dev->dev);
828
829 return 0;
830}
831
832#ifdef CONFIG_PM_SLEEP
833static int of_fsl_espi_suspend(struct device *dev)
834{
835 struct spi_master *master = dev_get_drvdata(dev);
836 int ret;
837
838 ret = spi_master_suspend(master);
839 if (ret) {
840 dev_warn(dev, "cannot suspend master\n");
841 return ret;
842 }
843
844 ret = pm_runtime_force_suspend(dev);
845 if (ret < 0)
846 return ret;
847
848 return 0;
849}
850
851static int of_fsl_espi_resume(struct device *dev)
852{
853 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
854 struct spi_master *master = dev_get_drvdata(dev);
855 struct mpc8xxx_spi *mpc8xxx_spi;
856 struct fsl_espi_reg *reg_base;
857 u32 regval;
858 int i, ret;
859
860 mpc8xxx_spi = spi_master_get_devdata(master);
861 reg_base = mpc8xxx_spi->reg_base;
862
863 /* SPI controller initializations */
864 mpc8xxx_spi_write_reg(®_base->mode, 0);
865 mpc8xxx_spi_write_reg(®_base->mask, 0);
866 mpc8xxx_spi_write_reg(®_base->command, 0);
867 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
868
869 /* Init eSPI CS mode register */
870 for (i = 0; i < pdata->max_chipselect; i++)
871 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
872
873 /* Enable SPI interface */
874 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
875
876 mpc8xxx_spi_write_reg(®_base->mode, regval);
877
878 ret = pm_runtime_force_resume(dev);
879 if (ret < 0)
880 return ret;
881
882 return spi_master_resume(master);
883}
884#endif /* CONFIG_PM_SLEEP */
885
886static const struct dev_pm_ops espi_pm = {
887 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
888 fsl_espi_runtime_resume, NULL)
889 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
890};
891
892static const struct of_device_id of_fsl_espi_match[] = {
893 { .compatible = "fsl,mpc8536-espi" },
894 {}
895};
896MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
897
898static struct platform_driver fsl_espi_driver = {
899 .driver = {
900 .name = "fsl_espi",
901 .of_match_table = of_fsl_espi_match,
902 .pm = &espi_pm,
903 },
904 .probe = of_fsl_espi_probe,
905 .remove = of_fsl_espi_remove,
906};
907module_platform_driver(fsl_espi_driver);
908
909MODULE_AUTHOR("Mingkai Hu");
910MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
911MODULE_LICENSE("GPL");