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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11#include <linux/init.h>
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/smp.h>
16#include <linux/interrupt.h>
17#include <linux/spinlock.h>
18#include <linux/cpu.h>
19#include <linux/cpumask.h>
20#include <linux/reboot.h>
21#include <linux/io.h>
22#include <linux/compiler.h>
23#include <linux/linkage.h>
24#include <linux/bug.h>
25#include <linux/kernel.h>
26
27#include <asm/time.h>
28#include <asm/pgtable.h>
29#include <asm/processor.h>
30#include <asm/bootinfo.h>
31#include <asm/pmon.h>
32#include <asm/cacheflush.h>
33#include <asm/tlbflush.h>
34#include <asm/mipsregs.h>
35#include <asm/bmips.h>
36#include <asm/traps.h>
37#include <asm/barrier.h>
38
39static int __maybe_unused max_cpus = 1;
40
41/* these may be configured by the platform code */
42int bmips_smp_enabled = 1;
43int bmips_cpu_offset;
44cpumask_t bmips_booted_mask;
45
46#ifdef CONFIG_SMP
47
48/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
49unsigned long bmips_smp_boot_sp;
50unsigned long bmips_smp_boot_gp;
51
52static void bmips_send_ipi_single(int cpu, unsigned int action);
53static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
54
55/* SW interrupts 0,1 are used for interprocessor signaling */
56#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
57#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
58
59#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
60#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
61#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
62#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
63
64static void __init bmips_smp_setup(void)
65{
66 int i;
67
68#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
69 /* arbitration priority */
70 clear_c0_brcm_cmt_ctrl(0x30);
71
72 /* NBK and weak order flags */
73 set_c0_brcm_config_0(0x30000);
74
75 /*
76 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
77 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
78 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
79 */
80 change_c0_brcm_cmt_intr(0xf8018000,
81 (0x02 << 27) | (0x03 << 15));
82
83 /* single core, 2 threads (2 pipelines) */
84 max_cpus = 2;
85#elif defined(CONFIG_CPU_BMIPS5000)
86 /* enable raceless SW interrupts */
87 set_c0_brcm_config(0x03 << 22);
88
89 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
90 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
91
92 /* N cores, 2 threads per core */
93 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
94
95 /* clear any pending SW interrupts */
96 for (i = 0; i < max_cpus; i++) {
97 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
98 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
99 }
100#endif
101
102 if (!bmips_smp_enabled)
103 max_cpus = 1;
104
105 /* this can be overridden by the BSP */
106 if (!board_ebase_setup)
107 board_ebase_setup = &bmips_ebase_setup;
108
109 for (i = 0; i < max_cpus; i++) {
110 __cpu_number_map[i] = 1;
111 __cpu_logical_map[i] = 1;
112 set_cpu_possible(i, 1);
113 set_cpu_present(i, 1);
114 }
115}
116
117/*
118 * IPI IRQ setup - runs on CPU0
119 */
120static void bmips_prepare_cpus(unsigned int max_cpus)
121{
122 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
123 "smp_ipi0", NULL))
124 panic("Can't request IPI0 interrupt\n");
125 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
126 "smp_ipi1", NULL))
127 panic("Can't request IPI1 interrupt\n");
128}
129
130/*
131 * Tell the hardware to boot CPUx - runs on CPU0
132 */
133static void bmips_boot_secondary(int cpu, struct task_struct *idle)
134{
135 bmips_smp_boot_sp = __KSTK_TOS(idle);
136 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
137 mb();
138
139 /*
140 * Initial boot sequence for secondary CPU:
141 * bmips_reset_nmi_vec @ a000_0000 ->
142 * bmips_smp_entry ->
143 * plat_wired_tlb_setup (cached function call; optional) ->
144 * start_secondary (cached jump)
145 *
146 * Warm restart sequence:
147 * play_dead WAIT loop ->
148 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
149 * eret to play_dead ->
150 * bmips_secondary_reentry ->
151 * start_secondary
152 */
153
154 pr_info("SMP: Booting CPU%d...\n", cpu);
155
156 if (cpumask_test_cpu(cpu, &bmips_booted_mask))
157 bmips_send_ipi_single(cpu, 0);
158 else {
159#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
160 set_c0_brcm_cmt_ctrl(0x01);
161#elif defined(CONFIG_CPU_BMIPS5000)
162 if (cpu & 0x01)
163 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
164 else {
165 /*
166 * core N thread 0 was already booted; just
167 * pulse the NMI line
168 */
169 bmips_write_zscm_reg(0x210, 0xc0000000);
170 udelay(10);
171 bmips_write_zscm_reg(0x210, 0x00);
172 }
173#endif
174 cpumask_set_cpu(cpu, &bmips_booted_mask);
175 }
176}
177
178/*
179 * Early setup - runs on secondary CPU after cache probe
180 */
181static void bmips_init_secondary(void)
182{
183 /* move NMI vector to kseg0, in case XKS01 is enabled */
184
185#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
186 void __iomem *cbr = BMIPS_GET_CBR();
187 unsigned long old_vec;
188
189 old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
190 __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
191
192 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
193#elif defined(CONFIG_CPU_BMIPS5000)
194 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
195 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
196
197 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
198#endif
199}
200
201/*
202 * Late setup - runs on secondary CPU before entering the idle loop
203 */
204static void bmips_smp_finish(void)
205{
206 pr_info("SMP: CPU%d is running\n", smp_processor_id());
207
208 /* make sure there won't be a timer interrupt for a little while */
209 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
210
211 irq_enable_hazard();
212 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
213 irq_enable_hazard();
214}
215
216/*
217 * Runs on CPU0 after all CPUs have been booted
218 */
219static void bmips_cpus_done(void)
220{
221}
222
223#if defined(CONFIG_CPU_BMIPS5000)
224
225/*
226 * BMIPS5000 raceless IPIs
227 *
228 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
229 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
230 * IPI1 is used for SMP_CALL_FUNCTION
231 */
232
233static void bmips_send_ipi_single(int cpu, unsigned int action)
234{
235 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
236}
237
238static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
239{
240 int action = irq - IPI0_IRQ;
241
242 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
243
244 if (action == 0)
245 scheduler_ipi();
246 else
247 smp_call_function_interrupt();
248
249 return IRQ_HANDLED;
250}
251
252#else
253
254/*
255 * BMIPS43xx racey IPIs
256 *
257 * We use one inbound SW IRQ for each CPU.
258 *
259 * A spinlock must be held in order to keep CPUx from accidentally clearing
260 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
261 * same spinlock is used to protect the action masks.
262 */
263
264static DEFINE_SPINLOCK(ipi_lock);
265static DEFINE_PER_CPU(int, ipi_action_mask);
266
267static void bmips_send_ipi_single(int cpu, unsigned int action)
268{
269 unsigned long flags;
270
271 spin_lock_irqsave(&ipi_lock, flags);
272 set_c0_cause(cpu ? C_SW1 : C_SW0);
273 per_cpu(ipi_action_mask, cpu) |= action;
274 irq_enable_hazard();
275 spin_unlock_irqrestore(&ipi_lock, flags);
276}
277
278static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
279{
280 unsigned long flags;
281 int action, cpu = irq - IPI0_IRQ;
282
283 spin_lock_irqsave(&ipi_lock, flags);
284 action = __get_cpu_var(ipi_action_mask);
285 per_cpu(ipi_action_mask, cpu) = 0;
286 clear_c0_cause(cpu ? C_SW1 : C_SW0);
287 spin_unlock_irqrestore(&ipi_lock, flags);
288
289 if (action & SMP_RESCHEDULE_YOURSELF)
290 scheduler_ipi();
291 if (action & SMP_CALL_FUNCTION)
292 smp_call_function_interrupt();
293
294 return IRQ_HANDLED;
295}
296
297#endif /* BMIPS type */
298
299static void bmips_send_ipi_mask(const struct cpumask *mask,
300 unsigned int action)
301{
302 unsigned int i;
303
304 for_each_cpu(i, mask)
305 bmips_send_ipi_single(i, action);
306}
307
308#ifdef CONFIG_HOTPLUG_CPU
309
310static int bmips_cpu_disable(void)
311{
312 unsigned int cpu = smp_processor_id();
313
314 if (cpu == 0)
315 return -EBUSY;
316
317 pr_info("SMP: CPU%d is offline\n", cpu);
318
319 set_cpu_online(cpu, false);
320 cpu_clear(cpu, cpu_callin_map);
321
322 local_flush_tlb_all();
323 local_flush_icache_range(0, ~0);
324
325 return 0;
326}
327
328static void bmips_cpu_die(unsigned int cpu)
329{
330}
331
332void __ref play_dead(void)
333{
334 idle_task_exit();
335
336 /* flush data cache */
337 _dma_cache_wback_inv(0, ~0);
338
339 /*
340 * Wakeup is on SW0 or SW1; disable everything else
341 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
342 * IRQ handlers; this clears ST0_IE and returns immediately.
343 */
344 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
345 change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
346 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
347 irq_disable_hazard();
348
349 /*
350 * wait for SW interrupt from bmips_boot_secondary(), then jump
351 * back to start_secondary()
352 */
353 __asm__ __volatile__(
354 " wait\n"
355 " j bmips_secondary_reentry\n"
356 : : : "memory");
357}
358
359#endif /* CONFIG_HOTPLUG_CPU */
360
361struct plat_smp_ops bmips_smp_ops = {
362 .smp_setup = bmips_smp_setup,
363 .prepare_cpus = bmips_prepare_cpus,
364 .boot_secondary = bmips_boot_secondary,
365 .smp_finish = bmips_smp_finish,
366 .init_secondary = bmips_init_secondary,
367 .cpus_done = bmips_cpus_done,
368 .send_ipi_single = bmips_send_ipi_single,
369 .send_ipi_mask = bmips_send_ipi_mask,
370#ifdef CONFIG_HOTPLUG_CPU
371 .cpu_disable = bmips_cpu_disable,
372 .cpu_die = bmips_cpu_die,
373#endif
374};
375
376#endif /* CONFIG_SMP */
377
378/***********************************************************************
379 * BMIPS vector relocation
380 * This is primarily used for SMP boot, but it is applicable to some
381 * UP BMIPS systems as well.
382 ***********************************************************************/
383
384static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end)
385{
386 memcpy((void *)dst, start, end - start);
387 dma_cache_wback((unsigned long)start, end - start);
388 local_flush_icache_range(dst, dst + (end - start));
389 instruction_hazard();
390}
391
392static inline void __cpuinit bmips_nmi_handler_setup(void)
393{
394 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
395 &bmips_reset_nmi_vec_end);
396 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
397 &bmips_smp_int_vec_end);
398}
399
400void __cpuinit bmips_ebase_setup(void)
401{
402 unsigned long new_ebase = ebase;
403 void __iomem __maybe_unused *cbr;
404
405 BUG_ON(ebase != CKSEG0);
406
407#if defined(CONFIG_CPU_BMIPS4350)
408 /*
409 * BMIPS4350 cannot relocate the normal vectors, but it
410 * can relocate the BEV=1 vectors. So CPU1 starts up at
411 * the relocated BEV=1, IV=0 general exception vector @
412 * 0xa000_0380.
413 *
414 * set_uncached_handler() is used here because:
415 * - CPU1 will run this from uncached space
416 * - None of the cacheflush functions are set up yet
417 */
418 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
419 &bmips_smp_int_vec, 0x80);
420 __sync();
421 return;
422#elif defined(CONFIG_CPU_BMIPS4380)
423 /*
424 * 0x8000_0000: reset/NMI (initially in kseg1)
425 * 0x8000_0400: normal vectors
426 */
427 new_ebase = 0x80000400;
428 cbr = BMIPS_GET_CBR();
429 __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
430 __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
431#elif defined(CONFIG_CPU_BMIPS5000)
432 /*
433 * 0x8000_0000: reset/NMI (initially in kseg1)
434 * 0x8000_1000: normal vectors
435 */
436 new_ebase = 0x80001000;
437 write_c0_brcm_bootvec(0xa0088008);
438 write_c0_ebase(new_ebase);
439 if (max_cpus > 2)
440 bmips_write_zscm_reg(0xa0, 0xa008a008);
441#else
442 return;
443#endif
444 board_nmi_handler_setup = &bmips_nmi_handler_setup;
445 ebase = new_ebase;
446}
447
448asmlinkage void __weak plat_wired_tlb_setup(void)
449{
450 /*
451 * Called when starting/restarting a secondary CPU.
452 * Kernel stacks and other important data might only be accessible
453 * once the wired entries are present.
454 */
455}
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11#include <linux/init.h>
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/smp.h>
16#include <linux/interrupt.h>
17#include <linux/spinlock.h>
18#include <linux/cpu.h>
19#include <linux/cpumask.h>
20#include <linux/reboot.h>
21#include <linux/io.h>
22#include <linux/compiler.h>
23#include <linux/linkage.h>
24#include <linux/bug.h>
25#include <linux/kernel.h>
26
27#include <asm/time.h>
28#include <asm/pgtable.h>
29#include <asm/processor.h>
30#include <asm/bootinfo.h>
31#include <asm/pmon.h>
32#include <asm/cacheflush.h>
33#include <asm/tlbflush.h>
34#include <asm/mipsregs.h>
35#include <asm/bmips.h>
36#include <asm/traps.h>
37#include <asm/barrier.h>
38#include <asm/cpu-features.h>
39
40static int __maybe_unused max_cpus = 1;
41
42/* these may be configured by the platform code */
43int bmips_smp_enabled = 1;
44int bmips_cpu_offset;
45cpumask_t bmips_booted_mask;
46unsigned long bmips_tp1_irqs = IE_IRQ1;
47
48#define RESET_FROM_KSEG0 0x80080800
49#define RESET_FROM_KSEG1 0xa0080800
50
51static void bmips_set_reset_vec(int cpu, u32 val);
52
53#ifdef CONFIG_SMP
54
55/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
56unsigned long bmips_smp_boot_sp;
57unsigned long bmips_smp_boot_gp;
58
59static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
60static void bmips5000_send_ipi_single(int cpu, unsigned int action);
61static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
62static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
63
64/* SW interrupts 0,1 are used for interprocessor signaling */
65#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
66#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
67
68#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
69#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
70#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
71#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
72
73static void __init bmips_smp_setup(void)
74{
75 int i, cpu = 1, boot_cpu = 0;
76 int cpu_hw_intr;
77
78 switch (current_cpu_type()) {
79 case CPU_BMIPS4350:
80 case CPU_BMIPS4380:
81 /* arbitration priority */
82 clear_c0_brcm_cmt_ctrl(0x30);
83
84 /* NBK and weak order flags */
85 set_c0_brcm_config_0(0x30000);
86
87 /* Find out if we are running on TP0 or TP1 */
88 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
89
90 /*
91 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
92 * thread
93 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
94 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
95 */
96 if (boot_cpu == 0)
97 cpu_hw_intr = 0x02;
98 else
99 cpu_hw_intr = 0x1d;
100
101 change_c0_brcm_cmt_intr(0xf8018000,
102 (cpu_hw_intr << 27) | (0x03 << 15));
103
104 /* single core, 2 threads (2 pipelines) */
105 max_cpus = 2;
106
107 break;
108 case CPU_BMIPS5000:
109 /* enable raceless SW interrupts */
110 set_c0_brcm_config(0x03 << 22);
111
112 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
113 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
114
115 /* N cores, 2 threads per core */
116 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
117
118 /* clear any pending SW interrupts */
119 for (i = 0; i < max_cpus; i++) {
120 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
121 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
122 }
123
124 break;
125 default:
126 max_cpus = 1;
127 }
128
129 if (!bmips_smp_enabled)
130 max_cpus = 1;
131
132 /* this can be overridden by the BSP */
133 if (!board_ebase_setup)
134 board_ebase_setup = &bmips_ebase_setup;
135
136 __cpu_number_map[boot_cpu] = 0;
137 __cpu_logical_map[0] = boot_cpu;
138
139 for (i = 0; i < max_cpus; i++) {
140 if (i != boot_cpu) {
141 __cpu_number_map[i] = cpu;
142 __cpu_logical_map[cpu] = i;
143 cpu++;
144 }
145 set_cpu_possible(i, 1);
146 set_cpu_present(i, 1);
147 }
148}
149
150/*
151 * IPI IRQ setup - runs on CPU0
152 */
153static void bmips_prepare_cpus(unsigned int max_cpus)
154{
155 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
156
157 switch (current_cpu_type()) {
158 case CPU_BMIPS4350:
159 case CPU_BMIPS4380:
160 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
161 break;
162 case CPU_BMIPS5000:
163 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
164 break;
165 default:
166 return;
167 }
168
169 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
170 "smp_ipi0", NULL))
171 panic("Can't request IPI0 interrupt");
172 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
173 "smp_ipi1", NULL))
174 panic("Can't request IPI1 interrupt");
175}
176
177/*
178 * Tell the hardware to boot CPUx - runs on CPU0
179 */
180static void bmips_boot_secondary(int cpu, struct task_struct *idle)
181{
182 bmips_smp_boot_sp = __KSTK_TOS(idle);
183 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
184 mb();
185
186 /*
187 * Initial boot sequence for secondary CPU:
188 * bmips_reset_nmi_vec @ a000_0000 ->
189 * bmips_smp_entry ->
190 * plat_wired_tlb_setup (cached function call; optional) ->
191 * start_secondary (cached jump)
192 *
193 * Warm restart sequence:
194 * play_dead WAIT loop ->
195 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
196 * eret to play_dead ->
197 * bmips_secondary_reentry ->
198 * start_secondary
199 */
200
201 pr_info("SMP: Booting CPU%d...\n", cpu);
202
203 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
204 /* kseg1 might not exist if this CPU enabled XKS01 */
205 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
206
207 switch (current_cpu_type()) {
208 case CPU_BMIPS4350:
209 case CPU_BMIPS4380:
210 bmips43xx_send_ipi_single(cpu, 0);
211 break;
212 case CPU_BMIPS5000:
213 bmips5000_send_ipi_single(cpu, 0);
214 break;
215 }
216 } else {
217 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
218
219 switch (current_cpu_type()) {
220 case CPU_BMIPS4350:
221 case CPU_BMIPS4380:
222 /* Reset slave TP1 if booting from TP0 */
223 if (cpu_logical_map(cpu) == 1)
224 set_c0_brcm_cmt_ctrl(0x01);
225 break;
226 case CPU_BMIPS5000:
227 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
228 break;
229 }
230 cpumask_set_cpu(cpu, &bmips_booted_mask);
231 }
232}
233
234/*
235 * Early setup - runs on secondary CPU after cache probe
236 */
237static void bmips_init_secondary(void)
238{
239 switch (current_cpu_type()) {
240 case CPU_BMIPS4350:
241 case CPU_BMIPS4380:
242 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
243 break;
244 case CPU_BMIPS5000:
245 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
246 break;
247 }
248}
249
250/*
251 * Late setup - runs on secondary CPU before entering the idle loop
252 */
253static void bmips_smp_finish(void)
254{
255 pr_info("SMP: CPU%d is running\n", smp_processor_id());
256
257 /* make sure there won't be a timer interrupt for a little while */
258 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
259
260 irq_enable_hazard();
261 set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
262 irq_enable_hazard();
263}
264
265/*
266 * BMIPS5000 raceless IPIs
267 *
268 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
269 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
270 * IPI1 is used for SMP_CALL_FUNCTION
271 */
272
273static void bmips5000_send_ipi_single(int cpu, unsigned int action)
274{
275 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
276}
277
278static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
279{
280 int action = irq - IPI0_IRQ;
281
282 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
283
284 if (action == 0)
285 scheduler_ipi();
286 else
287 generic_smp_call_function_interrupt();
288
289 return IRQ_HANDLED;
290}
291
292static void bmips5000_send_ipi_mask(const struct cpumask *mask,
293 unsigned int action)
294{
295 unsigned int i;
296
297 for_each_cpu(i, mask)
298 bmips5000_send_ipi_single(i, action);
299}
300
301/*
302 * BMIPS43xx racey IPIs
303 *
304 * We use one inbound SW IRQ for each CPU.
305 *
306 * A spinlock must be held in order to keep CPUx from accidentally clearing
307 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
308 * same spinlock is used to protect the action masks.
309 */
310
311static DEFINE_SPINLOCK(ipi_lock);
312static DEFINE_PER_CPU(int, ipi_action_mask);
313
314static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
315{
316 unsigned long flags;
317
318 spin_lock_irqsave(&ipi_lock, flags);
319 set_c0_cause(cpu ? C_SW1 : C_SW0);
320 per_cpu(ipi_action_mask, cpu) |= action;
321 irq_enable_hazard();
322 spin_unlock_irqrestore(&ipi_lock, flags);
323}
324
325static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
326{
327 unsigned long flags;
328 int action, cpu = irq - IPI0_IRQ;
329
330 spin_lock_irqsave(&ipi_lock, flags);
331 action = __this_cpu_read(ipi_action_mask);
332 per_cpu(ipi_action_mask, cpu) = 0;
333 clear_c0_cause(cpu ? C_SW1 : C_SW0);
334 spin_unlock_irqrestore(&ipi_lock, flags);
335
336 if (action & SMP_RESCHEDULE_YOURSELF)
337 scheduler_ipi();
338 if (action & SMP_CALL_FUNCTION)
339 generic_smp_call_function_interrupt();
340
341 return IRQ_HANDLED;
342}
343
344static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
345 unsigned int action)
346{
347 unsigned int i;
348
349 for_each_cpu(i, mask)
350 bmips43xx_send_ipi_single(i, action);
351}
352
353#ifdef CONFIG_HOTPLUG_CPU
354
355static int bmips_cpu_disable(void)
356{
357 unsigned int cpu = smp_processor_id();
358
359 if (cpu == 0)
360 return -EBUSY;
361
362 pr_info("SMP: CPU%d is offline\n", cpu);
363
364 set_cpu_online(cpu, false);
365 cpumask_clear_cpu(cpu, &cpu_callin_map);
366 clear_c0_status(IE_IRQ5);
367
368 local_flush_tlb_all();
369 local_flush_icache_range(0, ~0);
370
371 return 0;
372}
373
374static void bmips_cpu_die(unsigned int cpu)
375{
376}
377
378void __ref play_dead(void)
379{
380 idle_task_exit();
381
382 /* flush data cache */
383 _dma_cache_wback_inv(0, ~0);
384
385 /*
386 * Wakeup is on SW0 or SW1; disable everything else
387 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
388 * IRQ handlers; this clears ST0_IE and returns immediately.
389 */
390 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
391 change_c0_status(
392 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
393 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
394 irq_disable_hazard();
395
396 /*
397 * wait for SW interrupt from bmips_boot_secondary(), then jump
398 * back to start_secondary()
399 */
400 __asm__ __volatile__(
401 " wait\n"
402 " j bmips_secondary_reentry\n"
403 : : : "memory");
404}
405
406#endif /* CONFIG_HOTPLUG_CPU */
407
408struct plat_smp_ops bmips43xx_smp_ops = {
409 .smp_setup = bmips_smp_setup,
410 .prepare_cpus = bmips_prepare_cpus,
411 .boot_secondary = bmips_boot_secondary,
412 .smp_finish = bmips_smp_finish,
413 .init_secondary = bmips_init_secondary,
414 .send_ipi_single = bmips43xx_send_ipi_single,
415 .send_ipi_mask = bmips43xx_send_ipi_mask,
416#ifdef CONFIG_HOTPLUG_CPU
417 .cpu_disable = bmips_cpu_disable,
418 .cpu_die = bmips_cpu_die,
419#endif
420};
421
422struct plat_smp_ops bmips5000_smp_ops = {
423 .smp_setup = bmips_smp_setup,
424 .prepare_cpus = bmips_prepare_cpus,
425 .boot_secondary = bmips_boot_secondary,
426 .smp_finish = bmips_smp_finish,
427 .init_secondary = bmips_init_secondary,
428 .send_ipi_single = bmips5000_send_ipi_single,
429 .send_ipi_mask = bmips5000_send_ipi_mask,
430#ifdef CONFIG_HOTPLUG_CPU
431 .cpu_disable = bmips_cpu_disable,
432 .cpu_die = bmips_cpu_die,
433#endif
434};
435
436#endif /* CONFIG_SMP */
437
438/***********************************************************************
439 * BMIPS vector relocation
440 * This is primarily used for SMP boot, but it is applicable to some
441 * UP BMIPS systems as well.
442 ***********************************************************************/
443
444static void bmips_wr_vec(unsigned long dst, char *start, char *end)
445{
446 memcpy((void *)dst, start, end - start);
447 dma_cache_wback(dst, end - start);
448 local_flush_icache_range(dst, dst + (end - start));
449 instruction_hazard();
450}
451
452static inline void bmips_nmi_handler_setup(void)
453{
454 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
455 &bmips_reset_nmi_vec_end);
456 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
457 &bmips_smp_int_vec_end);
458}
459
460struct reset_vec_info {
461 int cpu;
462 u32 val;
463};
464
465static void bmips_set_reset_vec_remote(void *vinfo)
466{
467 struct reset_vec_info *info = vinfo;
468 int shift = info->cpu & 0x01 ? 16 : 0;
469 u32 mask = ~(0xffff << shift), val = info->val >> 16;
470
471 preempt_disable();
472 if (smp_processor_id() > 0) {
473 smp_call_function_single(0, &bmips_set_reset_vec_remote,
474 info, 1);
475 } else {
476 if (info->cpu & 0x02) {
477 /* BMIPS5200 "should" use mask/shift, but it's buggy */
478 bmips_write_zscm_reg(0xa0, (val << 16) | val);
479 bmips_read_zscm_reg(0xa0);
480 } else {
481 write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
482 (val << shift));
483 }
484 }
485 preempt_enable();
486}
487
488static void bmips_set_reset_vec(int cpu, u32 val)
489{
490 struct reset_vec_info info;
491
492 if (current_cpu_type() == CPU_BMIPS5000) {
493 /* this needs to run from CPU0 (which is always online) */
494 info.cpu = cpu;
495 info.val = val;
496 bmips_set_reset_vec_remote(&info);
497 } else {
498 void __iomem *cbr = BMIPS_GET_CBR();
499
500 if (cpu == 0)
501 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
502 else {
503 if (current_cpu_type() != CPU_BMIPS4380)
504 return;
505 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
506 }
507 }
508 __sync();
509 back_to_back_c0_hazard();
510}
511
512void bmips_ebase_setup(void)
513{
514 unsigned long new_ebase = ebase;
515
516 BUG_ON(ebase != CKSEG0);
517
518 switch (current_cpu_type()) {
519 case CPU_BMIPS4350:
520 /*
521 * BMIPS4350 cannot relocate the normal vectors, but it
522 * can relocate the BEV=1 vectors. So CPU1 starts up at
523 * the relocated BEV=1, IV=0 general exception vector @
524 * 0xa000_0380.
525 *
526 * set_uncached_handler() is used here because:
527 * - CPU1 will run this from uncached space
528 * - None of the cacheflush functions are set up yet
529 */
530 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
531 &bmips_smp_int_vec, 0x80);
532 __sync();
533 return;
534 case CPU_BMIPS3300:
535 case CPU_BMIPS4380:
536 /*
537 * 0x8000_0000: reset/NMI (initially in kseg1)
538 * 0x8000_0400: normal vectors
539 */
540 new_ebase = 0x80000400;
541 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
542 break;
543 case CPU_BMIPS5000:
544 /*
545 * 0x8000_0000: reset/NMI (initially in kseg1)
546 * 0x8000_1000: normal vectors
547 */
548 new_ebase = 0x80001000;
549 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
550 write_c0_ebase(new_ebase);
551 break;
552 default:
553 return;
554 }
555
556 board_nmi_handler_setup = &bmips_nmi_handler_setup;
557 ebase = new_ebase;
558}
559
560asmlinkage void __weak plat_wired_tlb_setup(void)
561{
562 /*
563 * Called when starting/restarting a secondary CPU.
564 * Kernel stacks and other important data might only be accessible
565 * once the wired entries are present.
566 */
567}