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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11#include <linux/init.h>
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/smp.h>
16#include <linux/interrupt.h>
17#include <linux/spinlock.h>
18#include <linux/cpu.h>
19#include <linux/cpumask.h>
20#include <linux/reboot.h>
21#include <linux/io.h>
22#include <linux/compiler.h>
23#include <linux/linkage.h>
24#include <linux/bug.h>
25#include <linux/kernel.h>
26
27#include <asm/time.h>
28#include <asm/pgtable.h>
29#include <asm/processor.h>
30#include <asm/bootinfo.h>
31#include <asm/pmon.h>
32#include <asm/cacheflush.h>
33#include <asm/tlbflush.h>
34#include <asm/mipsregs.h>
35#include <asm/bmips.h>
36#include <asm/traps.h>
37#include <asm/barrier.h>
38
39static int __maybe_unused max_cpus = 1;
40
41/* these may be configured by the platform code */
42int bmips_smp_enabled = 1;
43int bmips_cpu_offset;
44cpumask_t bmips_booted_mask;
45
46#ifdef CONFIG_SMP
47
48/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
49unsigned long bmips_smp_boot_sp;
50unsigned long bmips_smp_boot_gp;
51
52static void bmips_send_ipi_single(int cpu, unsigned int action);
53static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
54
55/* SW interrupts 0,1 are used for interprocessor signaling */
56#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
57#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
58
59#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
60#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
61#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
62#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
63
64static void __init bmips_smp_setup(void)
65{
66 int i;
67
68#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
69 /* arbitration priority */
70 clear_c0_brcm_cmt_ctrl(0x30);
71
72 /* NBK and weak order flags */
73 set_c0_brcm_config_0(0x30000);
74
75 /*
76 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
77 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
78 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
79 */
80 change_c0_brcm_cmt_intr(0xf8018000,
81 (0x02 << 27) | (0x03 << 15));
82
83 /* single core, 2 threads (2 pipelines) */
84 max_cpus = 2;
85#elif defined(CONFIG_CPU_BMIPS5000)
86 /* enable raceless SW interrupts */
87 set_c0_brcm_config(0x03 << 22);
88
89 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
90 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
91
92 /* N cores, 2 threads per core */
93 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
94
95 /* clear any pending SW interrupts */
96 for (i = 0; i < max_cpus; i++) {
97 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
98 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
99 }
100#endif
101
102 if (!bmips_smp_enabled)
103 max_cpus = 1;
104
105 /* this can be overridden by the BSP */
106 if (!board_ebase_setup)
107 board_ebase_setup = &bmips_ebase_setup;
108
109 for (i = 0; i < max_cpus; i++) {
110 __cpu_number_map[i] = 1;
111 __cpu_logical_map[i] = 1;
112 set_cpu_possible(i, 1);
113 set_cpu_present(i, 1);
114 }
115}
116
117/*
118 * IPI IRQ setup - runs on CPU0
119 */
120static void bmips_prepare_cpus(unsigned int max_cpus)
121{
122 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
123 "smp_ipi0", NULL))
124 panic("Can't request IPI0 interrupt\n");
125 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
126 "smp_ipi1", NULL))
127 panic("Can't request IPI1 interrupt\n");
128}
129
130/*
131 * Tell the hardware to boot CPUx - runs on CPU0
132 */
133static void bmips_boot_secondary(int cpu, struct task_struct *idle)
134{
135 bmips_smp_boot_sp = __KSTK_TOS(idle);
136 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
137 mb();
138
139 /*
140 * Initial boot sequence for secondary CPU:
141 * bmips_reset_nmi_vec @ a000_0000 ->
142 * bmips_smp_entry ->
143 * plat_wired_tlb_setup (cached function call; optional) ->
144 * start_secondary (cached jump)
145 *
146 * Warm restart sequence:
147 * play_dead WAIT loop ->
148 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
149 * eret to play_dead ->
150 * bmips_secondary_reentry ->
151 * start_secondary
152 */
153
154 pr_info("SMP: Booting CPU%d...\n", cpu);
155
156 if (cpumask_test_cpu(cpu, &bmips_booted_mask))
157 bmips_send_ipi_single(cpu, 0);
158 else {
159#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
160 set_c0_brcm_cmt_ctrl(0x01);
161#elif defined(CONFIG_CPU_BMIPS5000)
162 if (cpu & 0x01)
163 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
164 else {
165 /*
166 * core N thread 0 was already booted; just
167 * pulse the NMI line
168 */
169 bmips_write_zscm_reg(0x210, 0xc0000000);
170 udelay(10);
171 bmips_write_zscm_reg(0x210, 0x00);
172 }
173#endif
174 cpumask_set_cpu(cpu, &bmips_booted_mask);
175 }
176}
177
178/*
179 * Early setup - runs on secondary CPU after cache probe
180 */
181static void bmips_init_secondary(void)
182{
183 /* move NMI vector to kseg0, in case XKS01 is enabled */
184
185#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
186 void __iomem *cbr = BMIPS_GET_CBR();
187 unsigned long old_vec;
188
189 old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
190 __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
191
192 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
193#elif defined(CONFIG_CPU_BMIPS5000)
194 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
195 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
196
197 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
198#endif
199}
200
201/*
202 * Late setup - runs on secondary CPU before entering the idle loop
203 */
204static void bmips_smp_finish(void)
205{
206 pr_info("SMP: CPU%d is running\n", smp_processor_id());
207
208 /* make sure there won't be a timer interrupt for a little while */
209 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
210
211 irq_enable_hazard();
212 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
213 irq_enable_hazard();
214}
215
216/*
217 * Runs on CPU0 after all CPUs have been booted
218 */
219static void bmips_cpus_done(void)
220{
221}
222
223#if defined(CONFIG_CPU_BMIPS5000)
224
225/*
226 * BMIPS5000 raceless IPIs
227 *
228 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
229 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
230 * IPI1 is used for SMP_CALL_FUNCTION
231 */
232
233static void bmips_send_ipi_single(int cpu, unsigned int action)
234{
235 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
236}
237
238static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
239{
240 int action = irq - IPI0_IRQ;
241
242 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
243
244 if (action == 0)
245 scheduler_ipi();
246 else
247 smp_call_function_interrupt();
248
249 return IRQ_HANDLED;
250}
251
252#else
253
254/*
255 * BMIPS43xx racey IPIs
256 *
257 * We use one inbound SW IRQ for each CPU.
258 *
259 * A spinlock must be held in order to keep CPUx from accidentally clearing
260 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
261 * same spinlock is used to protect the action masks.
262 */
263
264static DEFINE_SPINLOCK(ipi_lock);
265static DEFINE_PER_CPU(int, ipi_action_mask);
266
267static void bmips_send_ipi_single(int cpu, unsigned int action)
268{
269 unsigned long flags;
270
271 spin_lock_irqsave(&ipi_lock, flags);
272 set_c0_cause(cpu ? C_SW1 : C_SW0);
273 per_cpu(ipi_action_mask, cpu) |= action;
274 irq_enable_hazard();
275 spin_unlock_irqrestore(&ipi_lock, flags);
276}
277
278static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
279{
280 unsigned long flags;
281 int action, cpu = irq - IPI0_IRQ;
282
283 spin_lock_irqsave(&ipi_lock, flags);
284 action = __get_cpu_var(ipi_action_mask);
285 per_cpu(ipi_action_mask, cpu) = 0;
286 clear_c0_cause(cpu ? C_SW1 : C_SW0);
287 spin_unlock_irqrestore(&ipi_lock, flags);
288
289 if (action & SMP_RESCHEDULE_YOURSELF)
290 scheduler_ipi();
291 if (action & SMP_CALL_FUNCTION)
292 smp_call_function_interrupt();
293
294 return IRQ_HANDLED;
295}
296
297#endif /* BMIPS type */
298
299static void bmips_send_ipi_mask(const struct cpumask *mask,
300 unsigned int action)
301{
302 unsigned int i;
303
304 for_each_cpu(i, mask)
305 bmips_send_ipi_single(i, action);
306}
307
308#ifdef CONFIG_HOTPLUG_CPU
309
310static int bmips_cpu_disable(void)
311{
312 unsigned int cpu = smp_processor_id();
313
314 if (cpu == 0)
315 return -EBUSY;
316
317 pr_info("SMP: CPU%d is offline\n", cpu);
318
319 set_cpu_online(cpu, false);
320 cpu_clear(cpu, cpu_callin_map);
321
322 local_flush_tlb_all();
323 local_flush_icache_range(0, ~0);
324
325 return 0;
326}
327
328static void bmips_cpu_die(unsigned int cpu)
329{
330}
331
332void __ref play_dead(void)
333{
334 idle_task_exit();
335
336 /* flush data cache */
337 _dma_cache_wback_inv(0, ~0);
338
339 /*
340 * Wakeup is on SW0 or SW1; disable everything else
341 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
342 * IRQ handlers; this clears ST0_IE and returns immediately.
343 */
344 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
345 change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
346 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
347 irq_disable_hazard();
348
349 /*
350 * wait for SW interrupt from bmips_boot_secondary(), then jump
351 * back to start_secondary()
352 */
353 __asm__ __volatile__(
354 " wait\n"
355 " j bmips_secondary_reentry\n"
356 : : : "memory");
357}
358
359#endif /* CONFIG_HOTPLUG_CPU */
360
361struct plat_smp_ops bmips_smp_ops = {
362 .smp_setup = bmips_smp_setup,
363 .prepare_cpus = bmips_prepare_cpus,
364 .boot_secondary = bmips_boot_secondary,
365 .smp_finish = bmips_smp_finish,
366 .init_secondary = bmips_init_secondary,
367 .cpus_done = bmips_cpus_done,
368 .send_ipi_single = bmips_send_ipi_single,
369 .send_ipi_mask = bmips_send_ipi_mask,
370#ifdef CONFIG_HOTPLUG_CPU
371 .cpu_disable = bmips_cpu_disable,
372 .cpu_die = bmips_cpu_die,
373#endif
374};
375
376#endif /* CONFIG_SMP */
377
378/***********************************************************************
379 * BMIPS vector relocation
380 * This is primarily used for SMP boot, but it is applicable to some
381 * UP BMIPS systems as well.
382 ***********************************************************************/
383
384static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end)
385{
386 memcpy((void *)dst, start, end - start);
387 dma_cache_wback((unsigned long)start, end - start);
388 local_flush_icache_range(dst, dst + (end - start));
389 instruction_hazard();
390}
391
392static inline void __cpuinit bmips_nmi_handler_setup(void)
393{
394 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
395 &bmips_reset_nmi_vec_end);
396 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
397 &bmips_smp_int_vec_end);
398}
399
400void __cpuinit bmips_ebase_setup(void)
401{
402 unsigned long new_ebase = ebase;
403 void __iomem __maybe_unused *cbr;
404
405 BUG_ON(ebase != CKSEG0);
406
407#if defined(CONFIG_CPU_BMIPS4350)
408 /*
409 * BMIPS4350 cannot relocate the normal vectors, but it
410 * can relocate the BEV=1 vectors. So CPU1 starts up at
411 * the relocated BEV=1, IV=0 general exception vector @
412 * 0xa000_0380.
413 *
414 * set_uncached_handler() is used here because:
415 * - CPU1 will run this from uncached space
416 * - None of the cacheflush functions are set up yet
417 */
418 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
419 &bmips_smp_int_vec, 0x80);
420 __sync();
421 return;
422#elif defined(CONFIG_CPU_BMIPS4380)
423 /*
424 * 0x8000_0000: reset/NMI (initially in kseg1)
425 * 0x8000_0400: normal vectors
426 */
427 new_ebase = 0x80000400;
428 cbr = BMIPS_GET_CBR();
429 __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
430 __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
431#elif defined(CONFIG_CPU_BMIPS5000)
432 /*
433 * 0x8000_0000: reset/NMI (initially in kseg1)
434 * 0x8000_1000: normal vectors
435 */
436 new_ebase = 0x80001000;
437 write_c0_brcm_bootvec(0xa0088008);
438 write_c0_ebase(new_ebase);
439 if (max_cpus > 2)
440 bmips_write_zscm_reg(0xa0, 0xa008a008);
441#else
442 return;
443#endif
444 board_nmi_handler_setup = &bmips_nmi_handler_setup;
445 ebase = new_ebase;
446}
447
448asmlinkage void __weak plat_wired_tlb_setup(void)
449{
450 /*
451 * Called when starting/restarting a secondary CPU.
452 * Kernel stacks and other important data might only be accessible
453 * once the wired entries are present.
454 */
455}
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11#include <linux/init.h>
12#include <linux/sched.h>
13#include <linux/sched/hotplug.h>
14#include <linux/sched/task_stack.h>
15#include <linux/mm.h>
16#include <linux/delay.h>
17#include <linux/smp.h>
18#include <linux/interrupt.h>
19#include <linux/spinlock.h>
20#include <linux/cpu.h>
21#include <linux/cpumask.h>
22#include <linux/reboot.h>
23#include <linux/io.h>
24#include <linux/compiler.h>
25#include <linux/linkage.h>
26#include <linux/bug.h>
27#include <linux/kernel.h>
28#include <linux/kexec.h>
29#include <linux/irq.h>
30
31#include <asm/time.h>
32#include <asm/processor.h>
33#include <asm/bootinfo.h>
34#include <asm/cacheflush.h>
35#include <asm/tlbflush.h>
36#include <asm/mipsregs.h>
37#include <asm/bmips.h>
38#include <asm/traps.h>
39#include <asm/barrier.h>
40#include <asm/cpu-features.h>
41
42static int __maybe_unused max_cpus = 1;
43
44/* these may be configured by the platform code */
45int bmips_smp_enabled = 1;
46int bmips_cpu_offset;
47cpumask_t bmips_booted_mask;
48unsigned long bmips_tp1_irqs = IE_IRQ1;
49
50#define RESET_FROM_KSEG0 0x80080800
51#define RESET_FROM_KSEG1 0xa0080800
52
53static void bmips_set_reset_vec(int cpu, u32 val);
54
55#ifdef CONFIG_SMP
56
57#include <asm/smp.h>
58
59/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
60unsigned long bmips_smp_boot_sp;
61unsigned long bmips_smp_boot_gp;
62
63static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
64static void bmips5000_send_ipi_single(int cpu, unsigned int action);
65static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
66static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
67
68/* SW interrupts 0,1 are used for interprocessor signaling */
69#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
70#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
71
72#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
73#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
74#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
75#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
76
77static void __init bmips_smp_setup(void)
78{
79 int i, cpu = 1, boot_cpu = 0;
80 int cpu_hw_intr;
81
82 switch (current_cpu_type()) {
83 case CPU_BMIPS4350:
84 case CPU_BMIPS4380:
85 /* arbitration priority */
86 clear_c0_brcm_cmt_ctrl(0x30);
87
88 /* NBK and weak order flags */
89 set_c0_brcm_config_0(0x30000);
90
91 /* Find out if we are running on TP0 or TP1 */
92 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
93
94 /*
95 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
96 * thread
97 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
98 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
99 */
100 if (boot_cpu == 0)
101 cpu_hw_intr = 0x02;
102 else
103 cpu_hw_intr = 0x1d;
104
105 change_c0_brcm_cmt_intr(0xf8018000,
106 (cpu_hw_intr << 27) | (0x03 << 15));
107
108 /* single core, 2 threads (2 pipelines) */
109 max_cpus = 2;
110
111 break;
112 case CPU_BMIPS5000:
113 /* enable raceless SW interrupts */
114 set_c0_brcm_config(0x03 << 22);
115
116 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
117 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
118
119 /* N cores, 2 threads per core */
120 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
121
122 /* clear any pending SW interrupts */
123 for (i = 0; i < max_cpus; i++) {
124 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
125 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
126 }
127
128 break;
129 default:
130 max_cpus = 1;
131 }
132
133 if (!bmips_smp_enabled)
134 max_cpus = 1;
135
136 /* this can be overridden by the BSP */
137 if (!board_ebase_setup)
138 board_ebase_setup = &bmips_ebase_setup;
139
140 if (max_cpus > 1) {
141 __cpu_number_map[boot_cpu] = 0;
142 __cpu_logical_map[0] = boot_cpu;
143
144 for (i = 0; i < max_cpus; i++) {
145 if (i != boot_cpu) {
146 __cpu_number_map[i] = cpu;
147 __cpu_logical_map[cpu] = i;
148 cpu++;
149 }
150 set_cpu_possible(i, 1);
151 set_cpu_present(i, 1);
152 }
153 } else {
154 __cpu_number_map[0] = boot_cpu;
155 __cpu_logical_map[0] = 0;
156 set_cpu_possible(0, 1);
157 set_cpu_present(0, 1);
158 }
159}
160
161/*
162 * IPI IRQ setup - runs on CPU0
163 */
164static void bmips_prepare_cpus(unsigned int max_cpus)
165{
166 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
167
168 switch (current_cpu_type()) {
169 case CPU_BMIPS4350:
170 case CPU_BMIPS4380:
171 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
172 break;
173 case CPU_BMIPS5000:
174 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
175 break;
176 default:
177 return;
178 }
179
180 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt,
181 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL))
182 panic("Can't request IPI0 interrupt");
183 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt,
184 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL))
185 panic("Can't request IPI1 interrupt");
186}
187
188/*
189 * Tell the hardware to boot CPUx - runs on CPU0
190 */
191static int bmips_boot_secondary(int cpu, struct task_struct *idle)
192{
193 bmips_smp_boot_sp = __KSTK_TOS(idle);
194 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
195 mb();
196
197 /*
198 * Initial boot sequence for secondary CPU:
199 * bmips_reset_nmi_vec @ a000_0000 ->
200 * bmips_smp_entry ->
201 * plat_wired_tlb_setup (cached function call; optional) ->
202 * start_secondary (cached jump)
203 *
204 * Warm restart sequence:
205 * play_dead WAIT loop ->
206 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
207 * eret to play_dead ->
208 * bmips_secondary_reentry ->
209 * start_secondary
210 */
211
212 pr_info("SMP: Booting CPU%d...\n", cpu);
213
214 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
215 /* kseg1 might not exist if this CPU enabled XKS01 */
216 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
217
218 switch (current_cpu_type()) {
219 case CPU_BMIPS4350:
220 case CPU_BMIPS4380:
221 bmips43xx_send_ipi_single(cpu, 0);
222 break;
223 case CPU_BMIPS5000:
224 bmips5000_send_ipi_single(cpu, 0);
225 break;
226 }
227 } else {
228 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
229
230 switch (current_cpu_type()) {
231 case CPU_BMIPS4350:
232 case CPU_BMIPS4380:
233 /* Reset slave TP1 if booting from TP0 */
234 if (cpu_logical_map(cpu) == 1)
235 set_c0_brcm_cmt_ctrl(0x01);
236 break;
237 case CPU_BMIPS5000:
238 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
239 break;
240 }
241 cpumask_set_cpu(cpu, &bmips_booted_mask);
242 }
243
244 return 0;
245}
246
247/*
248 * Early setup - runs on secondary CPU after cache probe
249 */
250static void bmips_init_secondary(void)
251{
252 bmips_cpu_setup();
253
254 switch (current_cpu_type()) {
255 case CPU_BMIPS4350:
256 case CPU_BMIPS4380:
257 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
258 break;
259 case CPU_BMIPS5000:
260 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
261 cpu_set_core(¤t_cpu_data, (read_c0_brcm_config() >> 25) & 3);
262 break;
263 }
264}
265
266/*
267 * Late setup - runs on secondary CPU before entering the idle loop
268 */
269static void bmips_smp_finish(void)
270{
271 pr_info("SMP: CPU%d is running\n", smp_processor_id());
272
273 /* make sure there won't be a timer interrupt for a little while */
274 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
275
276 irq_enable_hazard();
277 set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
278 irq_enable_hazard();
279}
280
281/*
282 * BMIPS5000 raceless IPIs
283 *
284 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
285 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
286 * IPI1 is used for SMP_CALL_FUNCTION
287 */
288
289static void bmips5000_send_ipi_single(int cpu, unsigned int action)
290{
291 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
292}
293
294static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
295{
296 int action = irq - IPI0_IRQ;
297
298 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
299
300 if (action == 0)
301 scheduler_ipi();
302 else
303 generic_smp_call_function_interrupt();
304
305 return IRQ_HANDLED;
306}
307
308static void bmips5000_send_ipi_mask(const struct cpumask *mask,
309 unsigned int action)
310{
311 unsigned int i;
312
313 for_each_cpu(i, mask)
314 bmips5000_send_ipi_single(i, action);
315}
316
317/*
318 * BMIPS43xx racey IPIs
319 *
320 * We use one inbound SW IRQ for each CPU.
321 *
322 * A spinlock must be held in order to keep CPUx from accidentally clearing
323 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
324 * same spinlock is used to protect the action masks.
325 */
326
327static DEFINE_SPINLOCK(ipi_lock);
328static DEFINE_PER_CPU(int, ipi_action_mask);
329
330static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
331{
332 unsigned long flags;
333
334 spin_lock_irqsave(&ipi_lock, flags);
335 set_c0_cause(cpu ? C_SW1 : C_SW0);
336 per_cpu(ipi_action_mask, cpu) |= action;
337 irq_enable_hazard();
338 spin_unlock_irqrestore(&ipi_lock, flags);
339}
340
341static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
342{
343 unsigned long flags;
344 int action, cpu = irq - IPI0_IRQ;
345
346 spin_lock_irqsave(&ipi_lock, flags);
347 action = __this_cpu_read(ipi_action_mask);
348 per_cpu(ipi_action_mask, cpu) = 0;
349 clear_c0_cause(cpu ? C_SW1 : C_SW0);
350 spin_unlock_irqrestore(&ipi_lock, flags);
351
352 if (action & SMP_RESCHEDULE_YOURSELF)
353 scheduler_ipi();
354 if (action & SMP_CALL_FUNCTION)
355 generic_smp_call_function_interrupt();
356
357 return IRQ_HANDLED;
358}
359
360static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
361 unsigned int action)
362{
363 unsigned int i;
364
365 for_each_cpu(i, mask)
366 bmips43xx_send_ipi_single(i, action);
367}
368
369#ifdef CONFIG_HOTPLUG_CPU
370
371static int bmips_cpu_disable(void)
372{
373 unsigned int cpu = smp_processor_id();
374
375 pr_info("SMP: CPU%d is offline\n", cpu);
376
377 set_cpu_online(cpu, false);
378 calculate_cpu_foreign_map();
379 irq_migrate_all_off_this_cpu();
380 clear_c0_status(IE_IRQ5);
381
382 local_flush_tlb_all();
383 local_flush_icache_range(0, ~0);
384
385 return 0;
386}
387
388static void bmips_cpu_die(unsigned int cpu)
389{
390}
391
392void __ref play_dead(void)
393{
394 idle_task_exit();
395 cpuhp_ap_report_dead();
396
397 /* flush data cache */
398 _dma_cache_wback_inv(0, ~0);
399
400 /*
401 * Wakeup is on SW0 or SW1; disable everything else
402 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
403 * IRQ handlers; this clears ST0_IE and returns immediately.
404 */
405 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
406 change_c0_status(
407 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
408 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
409 irq_disable_hazard();
410
411 /*
412 * wait for SW interrupt from bmips_boot_secondary(), then jump
413 * back to start_secondary()
414 */
415 __asm__ __volatile__(
416 " wait\n"
417 " j bmips_secondary_reentry\n"
418 : : : "memory");
419
420 BUG();
421}
422
423#endif /* CONFIG_HOTPLUG_CPU */
424
425const struct plat_smp_ops bmips43xx_smp_ops = {
426 .smp_setup = bmips_smp_setup,
427 .prepare_cpus = bmips_prepare_cpus,
428 .boot_secondary = bmips_boot_secondary,
429 .smp_finish = bmips_smp_finish,
430 .init_secondary = bmips_init_secondary,
431 .send_ipi_single = bmips43xx_send_ipi_single,
432 .send_ipi_mask = bmips43xx_send_ipi_mask,
433#ifdef CONFIG_HOTPLUG_CPU
434 .cpu_disable = bmips_cpu_disable,
435 .cpu_die = bmips_cpu_die,
436#endif
437#ifdef CONFIG_KEXEC_CORE
438 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
439#endif
440};
441
442const struct plat_smp_ops bmips5000_smp_ops = {
443 .smp_setup = bmips_smp_setup,
444 .prepare_cpus = bmips_prepare_cpus,
445 .boot_secondary = bmips_boot_secondary,
446 .smp_finish = bmips_smp_finish,
447 .init_secondary = bmips_init_secondary,
448 .send_ipi_single = bmips5000_send_ipi_single,
449 .send_ipi_mask = bmips5000_send_ipi_mask,
450#ifdef CONFIG_HOTPLUG_CPU
451 .cpu_disable = bmips_cpu_disable,
452 .cpu_die = bmips_cpu_die,
453#endif
454#ifdef CONFIG_KEXEC_CORE
455 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
456#endif
457};
458
459#endif /* CONFIG_SMP */
460
461/***********************************************************************
462 * BMIPS vector relocation
463 * This is primarily used for SMP boot, but it is applicable to some
464 * UP BMIPS systems as well.
465 ***********************************************************************/
466
467static void bmips_wr_vec(unsigned long dst, char *start, char *end)
468{
469 memcpy((void *)dst, start, end - start);
470 dma_cache_wback(dst, end - start);
471 local_flush_icache_range(dst, dst + (end - start));
472 instruction_hazard();
473}
474
475static inline void bmips_nmi_handler_setup(void)
476{
477 bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec,
478 bmips_reset_nmi_vec_end);
479 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec,
480 bmips_smp_int_vec_end);
481}
482
483struct reset_vec_info {
484 int cpu;
485 u32 val;
486};
487
488static void bmips_set_reset_vec_remote(void *vinfo)
489{
490 struct reset_vec_info *info = vinfo;
491 int shift = info->cpu & 0x01 ? 16 : 0;
492 u32 mask = ~(0xffff << shift), val = info->val >> 16;
493
494 preempt_disable();
495 if (smp_processor_id() > 0) {
496 smp_call_function_single(0, &bmips_set_reset_vec_remote,
497 info, 1);
498 } else {
499 if (info->cpu & 0x02) {
500 /* BMIPS5200 "should" use mask/shift, but it's buggy */
501 bmips_write_zscm_reg(0xa0, (val << 16) | val);
502 bmips_read_zscm_reg(0xa0);
503 } else {
504 write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
505 (val << shift));
506 }
507 }
508 preempt_enable();
509}
510
511static void bmips_set_reset_vec(int cpu, u32 val)
512{
513 struct reset_vec_info info;
514
515 if (current_cpu_type() == CPU_BMIPS5000) {
516 /* this needs to run from CPU0 (which is always online) */
517 info.cpu = cpu;
518 info.val = val;
519 bmips_set_reset_vec_remote(&info);
520 } else {
521 void __iomem *cbr = BMIPS_GET_CBR();
522
523 if (cpu == 0)
524 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
525 else {
526 if (current_cpu_type() != CPU_BMIPS4380)
527 return;
528 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
529 }
530 }
531 __sync();
532 back_to_back_c0_hazard();
533}
534
535void bmips_ebase_setup(void)
536{
537 unsigned long new_ebase = ebase;
538
539 BUG_ON(ebase != CKSEG0);
540
541 switch (current_cpu_type()) {
542 case CPU_BMIPS4350:
543 /*
544 * BMIPS4350 cannot relocate the normal vectors, but it
545 * can relocate the BEV=1 vectors. So CPU1 starts up at
546 * the relocated BEV=1, IV=0 general exception vector @
547 * 0xa000_0380.
548 *
549 * set_uncached_handler() is used here because:
550 * - CPU1 will run this from uncached space
551 * - None of the cacheflush functions are set up yet
552 */
553 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
554 &bmips_smp_int_vec, 0x80);
555 __sync();
556 return;
557 case CPU_BMIPS3300:
558 case CPU_BMIPS4380:
559 /*
560 * 0x8000_0000: reset/NMI (initially in kseg1)
561 * 0x8000_0400: normal vectors
562 */
563 new_ebase = 0x80000400;
564 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
565 break;
566 case CPU_BMIPS5000:
567 /*
568 * 0x8000_0000: reset/NMI (initially in kseg1)
569 * 0x8000_1000: normal vectors
570 */
571 new_ebase = 0x80001000;
572 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
573 write_c0_ebase(new_ebase);
574 break;
575 default:
576 return;
577 }
578
579 board_nmi_handler_setup = &bmips_nmi_handler_setup;
580 ebase = new_ebase;
581}
582
583asmlinkage void __weak plat_wired_tlb_setup(void)
584{
585 /*
586 * Called when starting/restarting a secondary CPU.
587 * Kernel stacks and other important data might only be accessible
588 * once the wired entries are present.
589 */
590}
591
592void bmips_cpu_setup(void)
593{
594 void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
595 u32 __maybe_unused cfg;
596
597 switch (current_cpu_type()) {
598 case CPU_BMIPS3300:
599 /* Set BIU to async mode */
600 set_c0_brcm_bus_pll(BIT(22));
601 __sync();
602
603 /* put the BIU back in sync mode */
604 clear_c0_brcm_bus_pll(BIT(22));
605
606 /* clear BHTD to enable branch history table */
607 clear_c0_brcm_reset(BIT(16));
608
609 /* Flush and enable RAC */
610 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
611 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
612 __raw_readl(cbr + BMIPS_RAC_CONFIG);
613
614 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
615 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG);
616 __raw_readl(cbr + BMIPS_RAC_CONFIG);
617
618 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
619 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
620 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
621 break;
622
623 case CPU_BMIPS4380:
624 /* CBG workaround for early BMIPS4380 CPUs */
625 switch (read_c0_prid()) {
626 case 0x2a040:
627 case 0x2a042:
628 case 0x2a044:
629 case 0x2a060:
630 cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
631 __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
632 __raw_readl(cbr + BMIPS_L2_CONFIG);
633 }
634
635 /* clear BHTD to enable branch history table */
636 clear_c0_brcm_config_0(BIT(21));
637
638 /* XI/ROTR enable */
639 set_c0_brcm_config_0(BIT(23));
640 set_c0_brcm_cmt_ctrl(BIT(15));
641 break;
642
643 case CPU_BMIPS5000:
644 /* enable RDHWR, BRDHWR */
645 set_c0_brcm_config(BIT(17) | BIT(21));
646
647 /* Disable JTB */
648 __asm__ __volatile__(
649 " .set noreorder\n"
650 " li $8, 0x5a455048\n"
651 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
652 " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */
653 " li $9, 0x00008000\n"
654 " or $8, $8, $9\n"
655 " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */
656 " sync\n"
657 " li $8, 0x0\n"
658 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
659 " .set reorder\n"
660 : : : "$8", "$9");
661
662 /* XI enable */
663 set_c0_brcm_config(BIT(27));
664
665 /* enable MIPS32R2 ROR instruction for XI TLB handlers */
666 __asm__ __volatile__(
667 " li $8, 0x5a455048\n"
668 " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */
669 " nop; nop; nop\n"
670 " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
671 " lui $9, 0x0100\n"
672 " or $8, $9\n"
673 " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
674 : : : "$8", "$9");
675 break;
676 }
677}