Loading...
1/*
2 * linux/arch/arm/mach-omap2/gpmc-onenand.c
3 *
4 * Copyright (C) 2006 - 2009 Nokia Corporation
5 * Contacts: Juha Yrjola
6 * Tony Lindgren
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/string.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/onenand_regs.h>
17#include <linux/io.h>
18
19#include <asm/mach/flash.h>
20
21#include <plat/cpu.h>
22#include <plat/onenand.h>
23#include <plat/board.h>
24#include <plat/gpmc.h>
25
26static struct omap_onenand_platform_data *gpmc_onenand_data;
27
28static struct platform_device gpmc_onenand_device = {
29 .name = "omap2-onenand",
30 .id = -1,
31};
32
33static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
34{
35 struct gpmc_timings t;
36 u32 reg;
37 int err;
38
39 const int t_cer = 15;
40 const int t_avdp = 12;
41 const int t_aavdh = 7;
42 const int t_ce = 76;
43 const int t_aa = 76;
44 const int t_oe = 20;
45 const int t_cez = 20; /* max of t_cez, t_oez */
46 const int t_ds = 30;
47 const int t_wpl = 40;
48 const int t_wph = 30;
49
50 /* Ensure sync read and sync write are disabled */
51 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
52 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
53 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
54
55 memset(&t, 0, sizeof(t));
56 t.sync_clk = 0;
57 t.cs_on = 0;
58 t.adv_on = 0;
59
60 /* Read */
61 t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
62 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
63 t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
64 t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
65 t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
66 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
67 t.cs_rd_off = t.oe_off;
68 t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
69
70 /* Write */
71 t.adv_wr_off = t.adv_rd_off;
72 t.we_on = t.oe_on;
73 if (cpu_is_omap34xx()) {
74 t.wr_data_mux_bus = t.we_on;
75 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
76 }
77 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
78 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
79 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
80
81 /* Configure GPMC for asynchronous read */
82 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
83 GPMC_CONFIG1_DEVICESIZE_16 |
84 GPMC_CONFIG1_MUXADDDATA);
85
86 err = gpmc_cs_set_timings(cs, &t);
87 if (err)
88 return err;
89
90 /* Ensure sync read and sync write are disabled */
91 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
92 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
93 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
94
95 return 0;
96}
97
98static void set_onenand_cfg(void __iomem *onenand_base, int latency,
99 int sync_read, int sync_write, int hf, int vhf)
100{
101 u32 reg;
102
103 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
104 reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
105 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
106 ONENAND_SYS_CFG1_BL_16;
107 if (sync_read)
108 reg |= ONENAND_SYS_CFG1_SYNC_READ;
109 else
110 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
111 if (sync_write)
112 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
113 else
114 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
115 if (hf)
116 reg |= ONENAND_SYS_CFG1_HF;
117 else
118 reg &= ~ONENAND_SYS_CFG1_HF;
119 if (vhf)
120 reg |= ONENAND_SYS_CFG1_VHF;
121 else
122 reg &= ~ONENAND_SYS_CFG1_VHF;
123 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
124}
125
126static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
127 void __iomem *onenand_base, bool *clk_dep)
128{
129 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
130 int freq = 0;
131
132 if (cfg->get_freq) {
133 struct onenand_freq_info fi;
134
135 fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
136 fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
137 fi.ver_id = ver;
138 freq = cfg->get_freq(&fi, clk_dep);
139 if (freq)
140 return freq;
141 }
142
143 switch ((ver >> 4) & 0xf) {
144 case 0:
145 freq = 40;
146 break;
147 case 1:
148 freq = 54;
149 break;
150 case 2:
151 freq = 66;
152 break;
153 case 3:
154 freq = 83;
155 break;
156 case 4:
157 freq = 104;
158 break;
159 default:
160 freq = 54;
161 break;
162 }
163
164 return freq;
165}
166
167static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
168 void __iomem *onenand_base,
169 int *freq_ptr)
170{
171 struct gpmc_timings t;
172 const int t_cer = 15;
173 const int t_avdp = 12;
174 const int t_cez = 20; /* max of t_cez, t_oez */
175 const int t_ds = 30;
176 const int t_wpl = 40;
177 const int t_wph = 30;
178 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
179 int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
180 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
181 int err, ticks_cez;
182 int cs = cfg->cs, freq = *freq_ptr;
183 u32 reg;
184 bool clk_dep = false;
185
186 if (cfg->flags & ONENAND_SYNC_READ) {
187 sync_read = 1;
188 } else if (cfg->flags & ONENAND_SYNC_READWRITE) {
189 sync_read = 1;
190 sync_write = 1;
191 } else
192 return omap2_onenand_set_async_mode(cs, onenand_base);
193
194 if (!freq) {
195 /* Very first call freq is not known */
196 err = omap2_onenand_set_async_mode(cs, onenand_base);
197 if (err)
198 return err;
199 freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
200 first_time = 1;
201 }
202
203 switch (freq) {
204 case 104:
205 min_gpmc_clk_period = 9600; /* 104 MHz */
206 t_ces = 3;
207 t_avds = 4;
208 t_avdh = 2;
209 t_ach = 3;
210 t_aavdh = 6;
211 t_rdyo = 6;
212 break;
213 case 83:
214 min_gpmc_clk_period = 12000; /* 83 MHz */
215 t_ces = 5;
216 t_avds = 4;
217 t_avdh = 2;
218 t_ach = 6;
219 t_aavdh = 6;
220 t_rdyo = 9;
221 break;
222 case 66:
223 min_gpmc_clk_period = 15000; /* 66 MHz */
224 t_ces = 6;
225 t_avds = 5;
226 t_avdh = 2;
227 t_ach = 6;
228 t_aavdh = 6;
229 t_rdyo = 11;
230 break;
231 default:
232 min_gpmc_clk_period = 18500; /* 54 MHz */
233 t_ces = 7;
234 t_avds = 7;
235 t_avdh = 7;
236 t_ach = 9;
237 t_aavdh = 7;
238 t_rdyo = 15;
239 sync_write = 0;
240 break;
241 }
242
243 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
244 gpmc_clk_ns = gpmc_ticks_to_ns(div);
245 if (gpmc_clk_ns < 15) /* >66Mhz */
246 hf = 1;
247 if (gpmc_clk_ns < 12) /* >83Mhz */
248 vhf = 1;
249 if (vhf)
250 latency = 8;
251 else if (hf)
252 latency = 6;
253 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
254 latency = 3;
255 else
256 latency = 4;
257
258 if (clk_dep) {
259 if (gpmc_clk_ns < 12) { /* >83Mhz */
260 t_ces = 3;
261 t_avds = 4;
262 } else if (gpmc_clk_ns < 15) { /* >66Mhz */
263 t_ces = 5;
264 t_avds = 4;
265 } else if (gpmc_clk_ns < 25) { /* >40Mhz */
266 t_ces = 6;
267 t_avds = 5;
268 } else {
269 t_ces = 7;
270 t_avds = 7;
271 }
272 }
273
274 if (first_time)
275 set_onenand_cfg(onenand_base, latency,
276 sync_read, sync_write, hf, vhf);
277
278 if (div == 1) {
279 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
280 reg |= (1 << 7);
281 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
282 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
283 reg |= (1 << 7);
284 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
285 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
286 reg |= (1 << 7);
287 reg |= (1 << 23);
288 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
289 } else {
290 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
291 reg &= ~(1 << 7);
292 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
293 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
294 reg &= ~(1 << 7);
295 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
296 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
297 reg &= ~(1 << 7);
298 reg &= ~(1 << 23);
299 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
300 }
301
302 /* Set synchronous read timings */
303 memset(&t, 0, sizeof(t));
304 t.sync_clk = min_gpmc_clk_period;
305 t.cs_on = 0;
306 t.adv_on = 0;
307 fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
308 fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
309 t.page_burst_access = gpmc_clk_ns;
310
311 /* Read */
312 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
313 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
314 /* Force at least 1 clk between AVD High to OE Low */
315 if (t.oe_on <= t.adv_rd_off)
316 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
317 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
318 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
319 t.cs_rd_off = t.oe_off;
320 ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;
321 t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
322 ticks_cez);
323
324 /* Write */
325 if (sync_write) {
326 t.adv_wr_off = t.adv_rd_off;
327 t.we_on = 0;
328 t.we_off = t.cs_rd_off;
329 t.cs_wr_off = t.cs_rd_off;
330 t.wr_cycle = t.rd_cycle;
331 if (cpu_is_omap34xx()) {
332 t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
333 gpmc_ps_to_ticks(min_gpmc_clk_period +
334 t_rdyo * 1000));
335 t.wr_access = t.access;
336 }
337 } else {
338 t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int,
339 t_avdp, t_cer));
340 t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);
341 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
342 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
343 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
344 if (cpu_is_omap34xx()) {
345 t.wr_data_mux_bus = t.we_on;
346 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
347 }
348 }
349
350 /* Configure GPMC for synchronous read */
351 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
352 GPMC_CONFIG1_WRAPBURST_SUPP |
353 GPMC_CONFIG1_READMULTIPLE_SUPP |
354 (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
355 (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
356 (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
357 GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
358 GPMC_CONFIG1_PAGE_LEN(2) |
359 (cpu_is_omap34xx() ? 0 :
360 (GPMC_CONFIG1_WAIT_READ_MON |
361 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
362 GPMC_CONFIG1_DEVICESIZE_16 |
363 GPMC_CONFIG1_DEVICETYPE_NOR |
364 GPMC_CONFIG1_MUXADDDATA);
365
366 err = gpmc_cs_set_timings(cs, &t);
367 if (err)
368 return err;
369
370 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
371
372 *freq_ptr = freq;
373
374 return 0;
375}
376
377static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
378{
379 struct device *dev = &gpmc_onenand_device.dev;
380
381 /* Set sync timings in GPMC */
382 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
383 freq_ptr) < 0) {
384 dev_err(dev, "Unable to set synchronous mode\n");
385 return -EINVAL;
386 }
387
388 return 0;
389}
390
391void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
392{
393 gpmc_onenand_data = _onenand_data;
394 gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
395 gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
396
397 if (cpu_is_omap24xx() &&
398 (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
399 printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
400 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
401 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
402 }
403
404 if (platform_device_register(&gpmc_onenand_device) < 0) {
405 printk(KERN_ERR "Unable to register OneNAND device\n");
406 return;
407 }
408}
1/*
2 * linux/arch/arm/mach-omap2/gpmc-onenand.c
3 *
4 * Copyright (C) 2006 - 2009 Nokia Corporation
5 * Contacts: Juha Yrjola
6 * Tony Lindgren
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/string.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/onenand_regs.h>
17#include <linux/io.h>
18#include <linux/omap-gpmc.h>
19#include <linux/platform_data/mtd-onenand-omap2.h>
20#include <linux/err.h>
21
22#include <asm/mach/flash.h>
23
24#include "soc.h"
25
26#define ONENAND_IO_SIZE SZ_128K
27
28#define ONENAND_FLAG_SYNCREAD (1 << 0)
29#define ONENAND_FLAG_SYNCWRITE (1 << 1)
30#define ONENAND_FLAG_HF (1 << 2)
31#define ONENAND_FLAG_VHF (1 << 3)
32
33static unsigned onenand_flags;
34static unsigned latency;
35
36static struct omap_onenand_platform_data *gpmc_onenand_data;
37
38static struct resource gpmc_onenand_resource = {
39 .flags = IORESOURCE_MEM,
40};
41
42static struct platform_device gpmc_onenand_device = {
43 .name = "omap2-onenand",
44 .id = -1,
45 .num_resources = 1,
46 .resource = &gpmc_onenand_resource,
47};
48
49static struct gpmc_settings onenand_async = {
50 .device_width = GPMC_DEVWIDTH_16BIT,
51 .mux_add_data = GPMC_MUX_AD,
52};
53
54static struct gpmc_settings onenand_sync = {
55 .burst_read = true,
56 .burst_wrap = true,
57 .burst_len = GPMC_BURST_16,
58 .device_width = GPMC_DEVWIDTH_16BIT,
59 .mux_add_data = GPMC_MUX_AD,
60 .wait_pin = 0,
61};
62
63static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
64{
65 struct gpmc_device_timings dev_t;
66 const int t_cer = 15;
67 const int t_avdp = 12;
68 const int t_aavdh = 7;
69 const int t_ce = 76;
70 const int t_aa = 76;
71 const int t_oe = 20;
72 const int t_cez = 20; /* max of t_cez, t_oez */
73 const int t_wpl = 40;
74 const int t_wph = 30;
75
76 memset(&dev_t, 0, sizeof(dev_t));
77
78 dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
79 dev_t.t_avdp_w = dev_t.t_avdp_r;
80 dev_t.t_aavdh = t_aavdh * 1000;
81 dev_t.t_aa = t_aa * 1000;
82 dev_t.t_ce = t_ce * 1000;
83 dev_t.t_oe = t_oe * 1000;
84 dev_t.t_cez_r = t_cez * 1000;
85 dev_t.t_cez_w = dev_t.t_cez_r;
86 dev_t.t_wpl = t_wpl * 1000;
87 dev_t.t_wph = t_wph * 1000;
88
89 gpmc_calc_timings(t, &onenand_async, &dev_t);
90}
91
92static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
93{
94 u32 reg;
95
96 /* Ensure sync read and sync write are disabled */
97 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
98 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
99 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
100}
101
102static void set_onenand_cfg(void __iomem *onenand_base)
103{
104 u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
105
106 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
107 ONENAND_SYS_CFG1_BL_16;
108 if (onenand_flags & ONENAND_FLAG_SYNCREAD)
109 reg |= ONENAND_SYS_CFG1_SYNC_READ;
110 else
111 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
112 if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
113 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
114 else
115 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
116 if (onenand_flags & ONENAND_FLAG_HF)
117 reg |= ONENAND_SYS_CFG1_HF;
118 else
119 reg &= ~ONENAND_SYS_CFG1_HF;
120 if (onenand_flags & ONENAND_FLAG_VHF)
121 reg |= ONENAND_SYS_CFG1_VHF;
122 else
123 reg &= ~ONENAND_SYS_CFG1_VHF;
124
125 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
126}
127
128static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
129 void __iomem *onenand_base)
130{
131 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
132 int freq;
133
134 switch ((ver >> 4) & 0xf) {
135 case 0:
136 freq = 40;
137 break;
138 case 1:
139 freq = 54;
140 break;
141 case 2:
142 freq = 66;
143 break;
144 case 3:
145 freq = 83;
146 break;
147 case 4:
148 freq = 104;
149 break;
150 default:
151 pr_err("onenand rate not detected, bad GPMC async timings?\n");
152 freq = 0;
153 }
154
155 return freq;
156}
157
158static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
159 unsigned int flags,
160 int freq)
161{
162 struct gpmc_device_timings dev_t;
163 const int t_cer = 15;
164 const int t_avdp = 12;
165 const int t_cez = 20; /* max of t_cez, t_oez */
166 const int t_wpl = 40;
167 const int t_wph = 30;
168 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
169 int div, gpmc_clk_ns;
170
171 if (flags & ONENAND_SYNC_READ)
172 onenand_flags = ONENAND_FLAG_SYNCREAD;
173 else if (flags & ONENAND_SYNC_READWRITE)
174 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
175
176 switch (freq) {
177 case 104:
178 min_gpmc_clk_period = 9600; /* 104 MHz */
179 t_ces = 3;
180 t_avds = 4;
181 t_avdh = 2;
182 t_ach = 3;
183 t_aavdh = 6;
184 t_rdyo = 6;
185 break;
186 case 83:
187 min_gpmc_clk_period = 12000; /* 83 MHz */
188 t_ces = 5;
189 t_avds = 4;
190 t_avdh = 2;
191 t_ach = 6;
192 t_aavdh = 6;
193 t_rdyo = 9;
194 break;
195 case 66:
196 min_gpmc_clk_period = 15000; /* 66 MHz */
197 t_ces = 6;
198 t_avds = 5;
199 t_avdh = 2;
200 t_ach = 6;
201 t_aavdh = 6;
202 t_rdyo = 11;
203 break;
204 default:
205 min_gpmc_clk_period = 18500; /* 54 MHz */
206 t_ces = 7;
207 t_avds = 7;
208 t_avdh = 7;
209 t_ach = 9;
210 t_aavdh = 7;
211 t_rdyo = 15;
212 onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
213 break;
214 }
215
216 div = gpmc_calc_divider(min_gpmc_clk_period);
217 gpmc_clk_ns = gpmc_ticks_to_ns(div);
218 if (gpmc_clk_ns < 15) /* >66MHz */
219 onenand_flags |= ONENAND_FLAG_HF;
220 else
221 onenand_flags &= ~ONENAND_FLAG_HF;
222 if (gpmc_clk_ns < 12) /* >83MHz */
223 onenand_flags |= ONENAND_FLAG_VHF;
224 else
225 onenand_flags &= ~ONENAND_FLAG_VHF;
226 if (onenand_flags & ONENAND_FLAG_VHF)
227 latency = 8;
228 else if (onenand_flags & ONENAND_FLAG_HF)
229 latency = 6;
230 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
231 latency = 3;
232 else
233 latency = 4;
234
235 /* Set synchronous read timings */
236 memset(&dev_t, 0, sizeof(dev_t));
237
238 if (onenand_flags & ONENAND_FLAG_SYNCREAD)
239 onenand_sync.sync_read = true;
240 if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
241 onenand_sync.sync_write = true;
242 onenand_sync.burst_write = true;
243 } else {
244 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
245 dev_t.t_wpl = t_wpl * 1000;
246 dev_t.t_wph = t_wph * 1000;
247 dev_t.t_aavdh = t_aavdh * 1000;
248 }
249 dev_t.ce_xdelay = true;
250 dev_t.avd_xdelay = true;
251 dev_t.oe_xdelay = true;
252 dev_t.we_xdelay = true;
253 dev_t.clk = min_gpmc_clk_period;
254 dev_t.t_bacc = dev_t.clk;
255 dev_t.t_ces = t_ces * 1000;
256 dev_t.t_avds = t_avds * 1000;
257 dev_t.t_avdh = t_avdh * 1000;
258 dev_t.t_ach = t_ach * 1000;
259 dev_t.cyc_iaa = (latency + 1);
260 dev_t.t_cez_r = t_cez * 1000;
261 dev_t.t_cez_w = dev_t.t_cez_r;
262 dev_t.cyc_aavdh_oe = 1;
263 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
264
265 gpmc_calc_timings(t, &onenand_sync, &dev_t);
266}
267
268static int omap2_onenand_setup_async(void __iomem *onenand_base)
269{
270 struct gpmc_timings t;
271 int ret;
272
273 /*
274 * Note that we need to keep sync_write set for the call to
275 * omap2_onenand_set_async_mode() to work to detect the onenand
276 * supported clock rate for the sync timings.
277 */
278 if (gpmc_onenand_data->of_node) {
279 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
280 &onenand_async);
281 if (onenand_async.sync_read || onenand_async.sync_write) {
282 if (onenand_async.sync_write)
283 gpmc_onenand_data->flags |=
284 ONENAND_SYNC_READWRITE;
285 else
286 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
287 onenand_async.sync_read = false;
288 }
289 }
290
291 onenand_async.sync_write = true;
292 omap2_onenand_calc_async_timings(&t);
293
294 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
295 if (ret < 0)
296 return ret;
297
298 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async);
299 if (ret < 0)
300 return ret;
301
302 omap2_onenand_set_async_mode(onenand_base);
303
304 return 0;
305}
306
307static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
308{
309 int ret, freq = *freq_ptr;
310 struct gpmc_timings t;
311
312 if (!freq) {
313 /* Very first call freq is not known */
314 freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
315 if (!freq)
316 return -ENODEV;
317 set_onenand_cfg(onenand_base);
318 }
319
320 if (gpmc_onenand_data->of_node) {
321 gpmc_read_settings_dt(gpmc_onenand_data->of_node,
322 &onenand_sync);
323 } else {
324 /*
325 * FIXME: Appears to be legacy code from initial ONENAND commit.
326 * Unclear what boards this is for and if this can be removed.
327 */
328 if (!cpu_is_omap34xx())
329 onenand_sync.wait_on_read = true;
330 }
331
332 omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
333
334 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
335 if (ret < 0)
336 return ret;
337
338 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync);
339 if (ret < 0)
340 return ret;
341
342 set_onenand_cfg(onenand_base);
343
344 *freq_ptr = freq;
345
346 return 0;
347}
348
349static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
350{
351 struct device *dev = &gpmc_onenand_device.dev;
352 unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
353 int ret;
354
355 ret = omap2_onenand_setup_async(onenand_base);
356 if (ret) {
357 dev_err(dev, "unable to set to async mode\n");
358 return ret;
359 }
360
361 if (!(gpmc_onenand_data->flags & l))
362 return 0;
363
364 ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
365 if (ret)
366 dev_err(dev, "unable to set to sync mode\n");
367 return ret;
368}
369
370void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
371{
372 int err;
373 struct device *dev = &gpmc_onenand_device.dev;
374
375 gpmc_onenand_data = _onenand_data;
376 gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
377 gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
378
379 if (cpu_is_omap24xx() &&
380 (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
381 dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
382 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
383 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
384 }
385
386 if (cpu_is_omap34xx())
387 gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
388 else
389 gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
390
391 err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
392 (unsigned long *)&gpmc_onenand_resource.start);
393 if (err < 0) {
394 dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
395 gpmc_onenand_data->cs, err);
396 return;
397 }
398
399 gpmc_onenand_resource.end = gpmc_onenand_resource.start +
400 ONENAND_IO_SIZE - 1;
401
402 if (platform_device_register(&gpmc_onenand_device) < 0) {
403 dev_err(dev, "Unable to register OneNAND device\n");
404 gpmc_cs_free(gpmc_onenand_data->cs);
405 return;
406 }
407}