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1/*
2 * linux/arch/arm/mach-omap2/gpmc-onenand.c
3 *
4 * Copyright (C) 2006 - 2009 Nokia Corporation
5 * Contacts: Juha Yrjola
6 * Tony Lindgren
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/string.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/onenand_regs.h>
17#include <linux/io.h>
18
19#include <asm/mach/flash.h>
20
21#include <plat/cpu.h>
22#include <plat/onenand.h>
23#include <plat/board.h>
24#include <plat/gpmc.h>
25
26static struct omap_onenand_platform_data *gpmc_onenand_data;
27
28static struct platform_device gpmc_onenand_device = {
29 .name = "omap2-onenand",
30 .id = -1,
31};
32
33static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
34{
35 struct gpmc_timings t;
36 u32 reg;
37 int err;
38
39 const int t_cer = 15;
40 const int t_avdp = 12;
41 const int t_aavdh = 7;
42 const int t_ce = 76;
43 const int t_aa = 76;
44 const int t_oe = 20;
45 const int t_cez = 20; /* max of t_cez, t_oez */
46 const int t_ds = 30;
47 const int t_wpl = 40;
48 const int t_wph = 30;
49
50 /* Ensure sync read and sync write are disabled */
51 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
52 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
53 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
54
55 memset(&t, 0, sizeof(t));
56 t.sync_clk = 0;
57 t.cs_on = 0;
58 t.adv_on = 0;
59
60 /* Read */
61 t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
62 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
63 t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
64 t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
65 t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
66 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
67 t.cs_rd_off = t.oe_off;
68 t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
69
70 /* Write */
71 t.adv_wr_off = t.adv_rd_off;
72 t.we_on = t.oe_on;
73 if (cpu_is_omap34xx()) {
74 t.wr_data_mux_bus = t.we_on;
75 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
76 }
77 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
78 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
79 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
80
81 /* Configure GPMC for asynchronous read */
82 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
83 GPMC_CONFIG1_DEVICESIZE_16 |
84 GPMC_CONFIG1_MUXADDDATA);
85
86 err = gpmc_cs_set_timings(cs, &t);
87 if (err)
88 return err;
89
90 /* Ensure sync read and sync write are disabled */
91 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
92 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
93 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
94
95 return 0;
96}
97
98static void set_onenand_cfg(void __iomem *onenand_base, int latency,
99 int sync_read, int sync_write, int hf, int vhf)
100{
101 u32 reg;
102
103 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
104 reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
105 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
106 ONENAND_SYS_CFG1_BL_16;
107 if (sync_read)
108 reg |= ONENAND_SYS_CFG1_SYNC_READ;
109 else
110 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
111 if (sync_write)
112 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
113 else
114 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
115 if (hf)
116 reg |= ONENAND_SYS_CFG1_HF;
117 else
118 reg &= ~ONENAND_SYS_CFG1_HF;
119 if (vhf)
120 reg |= ONENAND_SYS_CFG1_VHF;
121 else
122 reg &= ~ONENAND_SYS_CFG1_VHF;
123 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
124}
125
126static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
127 void __iomem *onenand_base, bool *clk_dep)
128{
129 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
130 int freq = 0;
131
132 if (cfg->get_freq) {
133 struct onenand_freq_info fi;
134
135 fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
136 fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
137 fi.ver_id = ver;
138 freq = cfg->get_freq(&fi, clk_dep);
139 if (freq)
140 return freq;
141 }
142
143 switch ((ver >> 4) & 0xf) {
144 case 0:
145 freq = 40;
146 break;
147 case 1:
148 freq = 54;
149 break;
150 case 2:
151 freq = 66;
152 break;
153 case 3:
154 freq = 83;
155 break;
156 case 4:
157 freq = 104;
158 break;
159 default:
160 freq = 54;
161 break;
162 }
163
164 return freq;
165}
166
167static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
168 void __iomem *onenand_base,
169 int *freq_ptr)
170{
171 struct gpmc_timings t;
172 const int t_cer = 15;
173 const int t_avdp = 12;
174 const int t_cez = 20; /* max of t_cez, t_oez */
175 const int t_ds = 30;
176 const int t_wpl = 40;
177 const int t_wph = 30;
178 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
179 int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
180 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
181 int err, ticks_cez;
182 int cs = cfg->cs, freq = *freq_ptr;
183 u32 reg;
184 bool clk_dep = false;
185
186 if (cfg->flags & ONENAND_SYNC_READ) {
187 sync_read = 1;
188 } else if (cfg->flags & ONENAND_SYNC_READWRITE) {
189 sync_read = 1;
190 sync_write = 1;
191 } else
192 return omap2_onenand_set_async_mode(cs, onenand_base);
193
194 if (!freq) {
195 /* Very first call freq is not known */
196 err = omap2_onenand_set_async_mode(cs, onenand_base);
197 if (err)
198 return err;
199 freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
200 first_time = 1;
201 }
202
203 switch (freq) {
204 case 104:
205 min_gpmc_clk_period = 9600; /* 104 MHz */
206 t_ces = 3;
207 t_avds = 4;
208 t_avdh = 2;
209 t_ach = 3;
210 t_aavdh = 6;
211 t_rdyo = 6;
212 break;
213 case 83:
214 min_gpmc_clk_period = 12000; /* 83 MHz */
215 t_ces = 5;
216 t_avds = 4;
217 t_avdh = 2;
218 t_ach = 6;
219 t_aavdh = 6;
220 t_rdyo = 9;
221 break;
222 case 66:
223 min_gpmc_clk_period = 15000; /* 66 MHz */
224 t_ces = 6;
225 t_avds = 5;
226 t_avdh = 2;
227 t_ach = 6;
228 t_aavdh = 6;
229 t_rdyo = 11;
230 break;
231 default:
232 min_gpmc_clk_period = 18500; /* 54 MHz */
233 t_ces = 7;
234 t_avds = 7;
235 t_avdh = 7;
236 t_ach = 9;
237 t_aavdh = 7;
238 t_rdyo = 15;
239 sync_write = 0;
240 break;
241 }
242
243 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
244 gpmc_clk_ns = gpmc_ticks_to_ns(div);
245 if (gpmc_clk_ns < 15) /* >66Mhz */
246 hf = 1;
247 if (gpmc_clk_ns < 12) /* >83Mhz */
248 vhf = 1;
249 if (vhf)
250 latency = 8;
251 else if (hf)
252 latency = 6;
253 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
254 latency = 3;
255 else
256 latency = 4;
257
258 if (clk_dep) {
259 if (gpmc_clk_ns < 12) { /* >83Mhz */
260 t_ces = 3;
261 t_avds = 4;
262 } else if (gpmc_clk_ns < 15) { /* >66Mhz */
263 t_ces = 5;
264 t_avds = 4;
265 } else if (gpmc_clk_ns < 25) { /* >40Mhz */
266 t_ces = 6;
267 t_avds = 5;
268 } else {
269 t_ces = 7;
270 t_avds = 7;
271 }
272 }
273
274 if (first_time)
275 set_onenand_cfg(onenand_base, latency,
276 sync_read, sync_write, hf, vhf);
277
278 if (div == 1) {
279 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
280 reg |= (1 << 7);
281 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
282 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
283 reg |= (1 << 7);
284 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
285 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
286 reg |= (1 << 7);
287 reg |= (1 << 23);
288 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
289 } else {
290 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
291 reg &= ~(1 << 7);
292 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
293 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
294 reg &= ~(1 << 7);
295 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
296 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
297 reg &= ~(1 << 7);
298 reg &= ~(1 << 23);
299 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
300 }
301
302 /* Set synchronous read timings */
303 memset(&t, 0, sizeof(t));
304 t.sync_clk = min_gpmc_clk_period;
305 t.cs_on = 0;
306 t.adv_on = 0;
307 fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
308 fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
309 t.page_burst_access = gpmc_clk_ns;
310
311 /* Read */
312 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
313 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
314 /* Force at least 1 clk between AVD High to OE Low */
315 if (t.oe_on <= t.adv_rd_off)
316 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
317 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
318 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
319 t.cs_rd_off = t.oe_off;
320 ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;
321 t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
322 ticks_cez);
323
324 /* Write */
325 if (sync_write) {
326 t.adv_wr_off = t.adv_rd_off;
327 t.we_on = 0;
328 t.we_off = t.cs_rd_off;
329 t.cs_wr_off = t.cs_rd_off;
330 t.wr_cycle = t.rd_cycle;
331 if (cpu_is_omap34xx()) {
332 t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
333 gpmc_ps_to_ticks(min_gpmc_clk_period +
334 t_rdyo * 1000));
335 t.wr_access = t.access;
336 }
337 } else {
338 t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int,
339 t_avdp, t_cer));
340 t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);
341 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
342 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
343 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
344 if (cpu_is_omap34xx()) {
345 t.wr_data_mux_bus = t.we_on;
346 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
347 }
348 }
349
350 /* Configure GPMC for synchronous read */
351 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
352 GPMC_CONFIG1_WRAPBURST_SUPP |
353 GPMC_CONFIG1_READMULTIPLE_SUPP |
354 (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
355 (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
356 (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
357 GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
358 GPMC_CONFIG1_PAGE_LEN(2) |
359 (cpu_is_omap34xx() ? 0 :
360 (GPMC_CONFIG1_WAIT_READ_MON |
361 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
362 GPMC_CONFIG1_DEVICESIZE_16 |
363 GPMC_CONFIG1_DEVICETYPE_NOR |
364 GPMC_CONFIG1_MUXADDDATA);
365
366 err = gpmc_cs_set_timings(cs, &t);
367 if (err)
368 return err;
369
370 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
371
372 *freq_ptr = freq;
373
374 return 0;
375}
376
377static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
378{
379 struct device *dev = &gpmc_onenand_device.dev;
380
381 /* Set sync timings in GPMC */
382 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
383 freq_ptr) < 0) {
384 dev_err(dev, "Unable to set synchronous mode\n");
385 return -EINVAL;
386 }
387
388 return 0;
389}
390
391void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
392{
393 gpmc_onenand_data = _onenand_data;
394 gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
395 gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
396
397 if (cpu_is_omap24xx() &&
398 (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
399 printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
400 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
401 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
402 }
403
404 if (platform_device_register(&gpmc_onenand_device) < 0) {
405 printk(KERN_ERR "Unable to register OneNAND device\n");
406 return;
407 }
408}
1/*
2 * linux/arch/arm/mach-omap2/gpmc-onenand.c
3 *
4 * Copyright (C) 2006 - 2009 Nokia Corporation
5 * Contacts: Juha Yrjola
6 * Tony Lindgren
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/mtd/onenand_regs.h>
16#include <linux/io.h>
17
18#include <asm/mach/flash.h>
19
20#include <plat/onenand.h>
21#include <plat/board.h>
22#include <plat/gpmc.h>
23
24static struct omap_onenand_platform_data *gpmc_onenand_data;
25
26static struct platform_device gpmc_onenand_device = {
27 .name = "omap2-onenand",
28 .id = -1,
29};
30
31static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
32{
33 struct gpmc_timings t;
34 u32 reg;
35 int err;
36
37 const int t_cer = 15;
38 const int t_avdp = 12;
39 const int t_aavdh = 7;
40 const int t_ce = 76;
41 const int t_aa = 76;
42 const int t_oe = 20;
43 const int t_cez = 20; /* max of t_cez, t_oez */
44 const int t_ds = 30;
45 const int t_wpl = 40;
46 const int t_wph = 30;
47
48 /* Ensure sync read and sync write are disabled */
49 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
50 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
51 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
52
53 memset(&t, 0, sizeof(t));
54 t.sync_clk = 0;
55 t.cs_on = 0;
56 t.adv_on = 0;
57
58 /* Read */
59 t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
60 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
61 t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
62 t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
63 t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
64 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
65 t.cs_rd_off = t.oe_off;
66 t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
67
68 /* Write */
69 t.adv_wr_off = t.adv_rd_off;
70 t.we_on = t.oe_on;
71 if (cpu_is_omap34xx()) {
72 t.wr_data_mux_bus = t.we_on;
73 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
74 }
75 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
76 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
77 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
78
79 /* Configure GPMC for asynchronous read */
80 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
81 GPMC_CONFIG1_DEVICESIZE_16 |
82 GPMC_CONFIG1_MUXADDDATA);
83
84 err = gpmc_cs_set_timings(cs, &t);
85 if (err)
86 return err;
87
88 /* Ensure sync read and sync write are disabled */
89 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
90 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
91 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
92
93 return 0;
94}
95
96static void set_onenand_cfg(void __iomem *onenand_base, int latency,
97 int sync_read, int sync_write, int hf, int vhf)
98{
99 u32 reg;
100
101 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
102 reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
103 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
104 ONENAND_SYS_CFG1_BL_16;
105 if (sync_read)
106 reg |= ONENAND_SYS_CFG1_SYNC_READ;
107 else
108 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
109 if (sync_write)
110 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
111 else
112 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
113 if (hf)
114 reg |= ONENAND_SYS_CFG1_HF;
115 else
116 reg &= ~ONENAND_SYS_CFG1_HF;
117 if (vhf)
118 reg |= ONENAND_SYS_CFG1_VHF;
119 else
120 reg &= ~ONENAND_SYS_CFG1_VHF;
121 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
122}
123
124static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
125 void __iomem *onenand_base, bool *clk_dep)
126{
127 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
128 int freq = 0;
129
130 if (cfg->get_freq) {
131 struct onenand_freq_info fi;
132
133 fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
134 fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
135 fi.ver_id = ver;
136 freq = cfg->get_freq(&fi, clk_dep);
137 if (freq)
138 return freq;
139 }
140
141 switch ((ver >> 4) & 0xf) {
142 case 0:
143 freq = 40;
144 break;
145 case 1:
146 freq = 54;
147 break;
148 case 2:
149 freq = 66;
150 break;
151 case 3:
152 freq = 83;
153 break;
154 case 4:
155 freq = 104;
156 break;
157 default:
158 freq = 54;
159 break;
160 }
161
162 return freq;
163}
164
165static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
166 void __iomem *onenand_base,
167 int *freq_ptr)
168{
169 struct gpmc_timings t;
170 const int t_cer = 15;
171 const int t_avdp = 12;
172 const int t_cez = 20; /* max of t_cez, t_oez */
173 const int t_ds = 30;
174 const int t_wpl = 40;
175 const int t_wph = 30;
176 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
177 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
178 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
179 int err, ticks_cez;
180 int cs = cfg->cs, freq = *freq_ptr;
181 u32 reg;
182 bool clk_dep = false;
183
184 if (cfg->flags & ONENAND_SYNC_READ) {
185 sync_read = 1;
186 } else if (cfg->flags & ONENAND_SYNC_READWRITE) {
187 sync_read = 1;
188 sync_write = 1;
189 } else
190 return omap2_onenand_set_async_mode(cs, onenand_base);
191
192 if (!freq) {
193 /* Very first call freq is not known */
194 err = omap2_onenand_set_async_mode(cs, onenand_base);
195 if (err)
196 return err;
197 freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
198 first_time = 1;
199 }
200
201 switch (freq) {
202 case 104:
203 min_gpmc_clk_period = 9600; /* 104 MHz */
204 t_ces = 3;
205 t_avds = 4;
206 t_avdh = 2;
207 t_ach = 3;
208 t_aavdh = 6;
209 t_rdyo = 6;
210 break;
211 case 83:
212 min_gpmc_clk_period = 12000; /* 83 MHz */
213 t_ces = 5;
214 t_avds = 4;
215 t_avdh = 2;
216 t_ach = 6;
217 t_aavdh = 6;
218 t_rdyo = 9;
219 break;
220 case 66:
221 min_gpmc_clk_period = 15000; /* 66 MHz */
222 t_ces = 6;
223 t_avds = 5;
224 t_avdh = 2;
225 t_ach = 6;
226 t_aavdh = 6;
227 t_rdyo = 11;
228 break;
229 default:
230 min_gpmc_clk_period = 18500; /* 54 MHz */
231 t_ces = 7;
232 t_avds = 7;
233 t_avdh = 7;
234 t_ach = 9;
235 t_aavdh = 7;
236 t_rdyo = 15;
237 sync_write = 0;
238 break;
239 }
240
241 tick_ns = gpmc_ticks_to_ns(1);
242 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
243 gpmc_clk_ns = gpmc_ticks_to_ns(div);
244 if (gpmc_clk_ns < 15) /* >66Mhz */
245 hf = 1;
246 if (gpmc_clk_ns < 12) /* >83Mhz */
247 vhf = 1;
248 if (vhf)
249 latency = 8;
250 else if (hf)
251 latency = 6;
252 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
253 latency = 3;
254 else
255 latency = 4;
256
257 if (clk_dep) {
258 if (gpmc_clk_ns < 12) { /* >83Mhz */
259 t_ces = 3;
260 t_avds = 4;
261 } else if (gpmc_clk_ns < 15) { /* >66Mhz */
262 t_ces = 5;
263 t_avds = 4;
264 } else if (gpmc_clk_ns < 25) { /* >40Mhz */
265 t_ces = 6;
266 t_avds = 5;
267 } else {
268 t_ces = 7;
269 t_avds = 7;
270 }
271 }
272
273 if (first_time)
274 set_onenand_cfg(onenand_base, latency,
275 sync_read, sync_write, hf, vhf);
276
277 if (div == 1) {
278 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
279 reg |= (1 << 7);
280 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
281 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
282 reg |= (1 << 7);
283 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
284 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
285 reg |= (1 << 7);
286 reg |= (1 << 23);
287 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
288 } else {
289 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
290 reg &= ~(1 << 7);
291 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
292 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
293 reg &= ~(1 << 7);
294 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
295 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
296 reg &= ~(1 << 7);
297 reg &= ~(1 << 23);
298 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
299 }
300
301 /* Set synchronous read timings */
302 memset(&t, 0, sizeof(t));
303 t.sync_clk = min_gpmc_clk_period;
304 t.cs_on = 0;
305 t.adv_on = 0;
306 fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
307 fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
308 t.page_burst_access = gpmc_clk_ns;
309
310 /* Read */
311 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
312 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
313 /* Force at least 1 clk between AVD High to OE Low */
314 if (t.oe_on <= t.adv_rd_off)
315 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
316 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
317 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
318 t.cs_rd_off = t.oe_off;
319 ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;
320 t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
321 ticks_cez);
322
323 /* Write */
324 if (sync_write) {
325 t.adv_wr_off = t.adv_rd_off;
326 t.we_on = 0;
327 t.we_off = t.cs_rd_off;
328 t.cs_wr_off = t.cs_rd_off;
329 t.wr_cycle = t.rd_cycle;
330 if (cpu_is_omap34xx()) {
331 t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
332 gpmc_ps_to_ticks(min_gpmc_clk_period +
333 t_rdyo * 1000));
334 t.wr_access = t.access;
335 }
336 } else {
337 t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int,
338 t_avdp, t_cer));
339 t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);
340 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
341 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
342 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
343 if (cpu_is_omap34xx()) {
344 t.wr_data_mux_bus = t.we_on;
345 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
346 }
347 }
348
349 /* Configure GPMC for synchronous read */
350 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
351 GPMC_CONFIG1_WRAPBURST_SUPP |
352 GPMC_CONFIG1_READMULTIPLE_SUPP |
353 (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
354 (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
355 (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
356 GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
357 GPMC_CONFIG1_PAGE_LEN(2) |
358 (cpu_is_omap34xx() ? 0 :
359 (GPMC_CONFIG1_WAIT_READ_MON |
360 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
361 GPMC_CONFIG1_DEVICESIZE_16 |
362 GPMC_CONFIG1_DEVICETYPE_NOR |
363 GPMC_CONFIG1_MUXADDDATA);
364
365 err = gpmc_cs_set_timings(cs, &t);
366 if (err)
367 return err;
368
369 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
370
371 *freq_ptr = freq;
372
373 return 0;
374}
375
376static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
377{
378 struct device *dev = &gpmc_onenand_device.dev;
379
380 /* Set sync timings in GPMC */
381 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
382 freq_ptr) < 0) {
383 dev_err(dev, "Unable to set synchronous mode\n");
384 return -EINVAL;
385 }
386
387 return 0;
388}
389
390void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
391{
392 gpmc_onenand_data = _onenand_data;
393 gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
394 gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
395
396 if (cpu_is_omap24xx() &&
397 (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
398 printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
399 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
400 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
401 }
402
403 if (platform_device_register(&gpmc_onenand_device) < 0) {
404 printk(KERN_ERR "Unable to register OneNAND device\n");
405 return;
406 }
407}