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1/*
2 * STMicroelectronics STM32 SPI Controller driver (master mode only)
3 *
4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
6 *
7 * License terms: GPL V2.0.
8 *
9 * spi_stm32 driver is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * spi_stm32 driver is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
16 * details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * spi_stm32 driver. If not, see <http://www.gnu.org/licenses/>.
20 */
21#include <linux/debugfs.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/dmaengine.h>
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/iopoll.h>
28#include <linux/module.h>
29#include <linux/of_platform.h>
30#include <linux/pm_runtime.h>
31#include <linux/reset.h>
32#include <linux/spi/spi.h>
33
34#define DRIVER_NAME "spi_stm32"
35
36/* STM32 SPI registers */
37#define STM32_SPI_CR1 0x00
38#define STM32_SPI_CR2 0x04
39#define STM32_SPI_CFG1 0x08
40#define STM32_SPI_CFG2 0x0C
41#define STM32_SPI_IER 0x10
42#define STM32_SPI_SR 0x14
43#define STM32_SPI_IFCR 0x18
44#define STM32_SPI_TXDR 0x20
45#define STM32_SPI_RXDR 0x30
46#define STM32_SPI_I2SCFGR 0x50
47
48/* STM32_SPI_CR1 bit fields */
49#define SPI_CR1_SPE BIT(0)
50#define SPI_CR1_MASRX BIT(8)
51#define SPI_CR1_CSTART BIT(9)
52#define SPI_CR1_CSUSP BIT(10)
53#define SPI_CR1_HDDIR BIT(11)
54#define SPI_CR1_SSI BIT(12)
55
56/* STM32_SPI_CR2 bit fields */
57#define SPI_CR2_TSIZE_SHIFT 0
58#define SPI_CR2_TSIZE GENMASK(15, 0)
59
60/* STM32_SPI_CFG1 bit fields */
61#define SPI_CFG1_DSIZE_SHIFT 0
62#define SPI_CFG1_DSIZE GENMASK(4, 0)
63#define SPI_CFG1_FTHLV_SHIFT 5
64#define SPI_CFG1_FTHLV GENMASK(8, 5)
65#define SPI_CFG1_RXDMAEN BIT(14)
66#define SPI_CFG1_TXDMAEN BIT(15)
67#define SPI_CFG1_MBR_SHIFT 28
68#define SPI_CFG1_MBR GENMASK(30, 28)
69#define SPI_CFG1_MBR_MIN 0
70#define SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
71
72/* STM32_SPI_CFG2 bit fields */
73#define SPI_CFG2_MIDI_SHIFT 4
74#define SPI_CFG2_MIDI GENMASK(7, 4)
75#define SPI_CFG2_COMM_SHIFT 17
76#define SPI_CFG2_COMM GENMASK(18, 17)
77#define SPI_CFG2_SP_SHIFT 19
78#define SPI_CFG2_SP GENMASK(21, 19)
79#define SPI_CFG2_MASTER BIT(22)
80#define SPI_CFG2_LSBFRST BIT(23)
81#define SPI_CFG2_CPHA BIT(24)
82#define SPI_CFG2_CPOL BIT(25)
83#define SPI_CFG2_SSM BIT(26)
84#define SPI_CFG2_AFCNTR BIT(31)
85
86/* STM32_SPI_IER bit fields */
87#define SPI_IER_RXPIE BIT(0)
88#define SPI_IER_TXPIE BIT(1)
89#define SPI_IER_DXPIE BIT(2)
90#define SPI_IER_EOTIE BIT(3)
91#define SPI_IER_TXTFIE BIT(4)
92#define SPI_IER_OVRIE BIT(6)
93#define SPI_IER_MODFIE BIT(9)
94#define SPI_IER_ALL GENMASK(10, 0)
95
96/* STM32_SPI_SR bit fields */
97#define SPI_SR_RXP BIT(0)
98#define SPI_SR_TXP BIT(1)
99#define SPI_SR_EOT BIT(3)
100#define SPI_SR_OVR BIT(6)
101#define SPI_SR_MODF BIT(9)
102#define SPI_SR_SUSP BIT(11)
103#define SPI_SR_RXPLVL_SHIFT 13
104#define SPI_SR_RXPLVL GENMASK(14, 13)
105#define SPI_SR_RXWNE BIT(15)
106
107/* STM32_SPI_IFCR bit fields */
108#define SPI_IFCR_ALL GENMASK(11, 3)
109
110/* STM32_SPI_I2SCFGR bit fields */
111#define SPI_I2SCFGR_I2SMOD BIT(0)
112
113/* SPI Master Baud Rate min/max divisor */
114#define SPI_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
115#define SPI_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
116
117/* SPI Communication mode */
118#define SPI_FULL_DUPLEX 0
119#define SPI_SIMPLEX_TX 1
120#define SPI_SIMPLEX_RX 2
121#define SPI_HALF_DUPLEX 3
122
123#define SPI_1HZ_NS 1000000000
124
125/**
126 * struct stm32_spi - private data of the SPI controller
127 * @dev: driver model representation of the controller
128 * @master: controller master interface
129 * @base: virtual memory area
130 * @clk: hw kernel clock feeding the SPI clock generator
131 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
132 * @rst: SPI controller reset line
133 * @lock: prevent I/O concurrent access
134 * @irq: SPI controller interrupt line
135 * @fifo_size: size of the embedded fifo in bytes
136 * @cur_midi: master inter-data idleness in ns
137 * @cur_speed: speed configured in Hz
138 * @cur_bpw: number of bits in a single SPI data frame
139 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
140 * @cur_comm: SPI communication mode
141 * @cur_xferlen: current transfer length in bytes
142 * @cur_usedma: boolean to know if dma is used in current transfer
143 * @tx_buf: data to be written, or NULL
144 * @rx_buf: data to be read, or NULL
145 * @tx_len: number of data to be written in bytes
146 * @rx_len: number of data to be read in bytes
147 * @dma_tx: dma channel for TX transfer
148 * @dma_rx: dma channel for RX transfer
149 * @phys_addr: SPI registers physical base address
150 */
151struct stm32_spi {
152 struct device *dev;
153 struct spi_master *master;
154 void __iomem *base;
155 struct clk *clk;
156 u32 clk_rate;
157 struct reset_control *rst;
158 spinlock_t lock; /* prevent I/O concurrent access */
159 int irq;
160 unsigned int fifo_size;
161
162 unsigned int cur_midi;
163 unsigned int cur_speed;
164 unsigned int cur_bpw;
165 unsigned int cur_fthlv;
166 unsigned int cur_comm;
167 unsigned int cur_xferlen;
168 bool cur_usedma;
169
170 const void *tx_buf;
171 void *rx_buf;
172 int tx_len;
173 int rx_len;
174 struct dma_chan *dma_tx;
175 struct dma_chan *dma_rx;
176 dma_addr_t phys_addr;
177};
178
179static inline void stm32_spi_set_bits(struct stm32_spi *spi,
180 u32 offset, u32 bits)
181{
182 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
183 spi->base + offset);
184}
185
186static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
187 u32 offset, u32 bits)
188{
189 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
190 spi->base + offset);
191}
192
193/**
194 * stm32_spi_get_fifo_size - Return fifo size
195 * @spi: pointer to the spi controller data structure
196 */
197static int stm32_spi_get_fifo_size(struct stm32_spi *spi)
198{
199 unsigned long flags;
200 u32 count = 0;
201
202 spin_lock_irqsave(&spi->lock, flags);
203
204 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
205
206 while (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)
207 writeb_relaxed(++count, spi->base + STM32_SPI_TXDR);
208
209 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
210
211 spin_unlock_irqrestore(&spi->lock, flags);
212
213 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
214
215 return count;
216}
217
218/**
219 * stm32_spi_get_bpw_mask - Return bits per word mask
220 * @spi: pointer to the spi controller data structure
221 */
222static int stm32_spi_get_bpw_mask(struct stm32_spi *spi)
223{
224 unsigned long flags;
225 u32 cfg1, max_bpw;
226
227 spin_lock_irqsave(&spi->lock, flags);
228
229 /*
230 * The most significant bit at DSIZE bit field is reserved when the
231 * maximum data size of periperal instances is limited to 16-bit
232 */
233 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_DSIZE);
234
235 cfg1 = readl_relaxed(spi->base + STM32_SPI_CFG1);
236 max_bpw = (cfg1 & SPI_CFG1_DSIZE) >> SPI_CFG1_DSIZE_SHIFT;
237 max_bpw += 1;
238
239 spin_unlock_irqrestore(&spi->lock, flags);
240
241 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
242
243 return SPI_BPW_RANGE_MASK(4, max_bpw);
244}
245
246/**
247 * stm32_spi_prepare_mbr - Determine SPI_CFG1.MBR value
248 * @spi: pointer to the spi controller data structure
249 * @speed_hz: requested speed
250 *
251 * Return SPI_CFG1.MBR value in case of success or -EINVAL
252 */
253static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz)
254{
255 u32 div, mbrdiv;
256
257 div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
258
259 /*
260 * SPI framework set xfer->speed_hz to master->max_speed_hz if
261 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
262 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
263 * no need to check it there.
264 * However, we need to ensure the following calculations.
265 */
266 if (div < SPI_MBR_DIV_MIN ||
267 div > SPI_MBR_DIV_MAX)
268 return -EINVAL;
269
270 /* Determine the first power of 2 greater than or equal to div */
271 if (div & (div - 1))
272 mbrdiv = fls(div);
273 else
274 mbrdiv = fls(div) - 1;
275
276 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
277
278 return mbrdiv - 1;
279}
280
281/**
282 * stm32_spi_prepare_fthlv - Determine FIFO threshold level
283 * @spi: pointer to the spi controller data structure
284 */
285static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi)
286{
287 u32 fthlv, half_fifo;
288
289 /* data packet should not exceed 1/2 of fifo space */
290 half_fifo = (spi->fifo_size / 2);
291
292 if (spi->cur_bpw <= 8)
293 fthlv = half_fifo;
294 else if (spi->cur_bpw <= 16)
295 fthlv = half_fifo / 2;
296 else
297 fthlv = half_fifo / 4;
298
299 /* align packet size with data registers access */
300 if (spi->cur_bpw > 8)
301 fthlv -= (fthlv % 2); /* multiple of 2 */
302 else
303 fthlv -= (fthlv % 4); /* multiple of 4 */
304
305 return fthlv;
306}
307
308/**
309 * stm32_spi_write_txfifo - Write bytes in Transmit Data Register
310 * @spi: pointer to the spi controller data structure
311 *
312 * Read from tx_buf depends on remaining bytes to avoid to read beyond
313 * tx_buf end.
314 */
315static void stm32_spi_write_txfifo(struct stm32_spi *spi)
316{
317 while ((spi->tx_len > 0) &&
318 (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)) {
319 u32 offs = spi->cur_xferlen - spi->tx_len;
320
321 if (spi->tx_len >= sizeof(u32)) {
322 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
323
324 writel_relaxed(*tx_buf32, spi->base + STM32_SPI_TXDR);
325 spi->tx_len -= sizeof(u32);
326 } else if (spi->tx_len >= sizeof(u16)) {
327 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
328
329 writew_relaxed(*tx_buf16, spi->base + STM32_SPI_TXDR);
330 spi->tx_len -= sizeof(u16);
331 } else {
332 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
333
334 writeb_relaxed(*tx_buf8, spi->base + STM32_SPI_TXDR);
335 spi->tx_len -= sizeof(u8);
336 }
337 }
338
339 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
340}
341
342/**
343 * stm32_spi_read_rxfifo - Read bytes in Receive Data Register
344 * @spi: pointer to the spi controller data structure
345 *
346 * Write in rx_buf depends on remaining bytes to avoid to write beyond
347 * rx_buf end.
348 */
349static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
350{
351 u32 sr = readl_relaxed(spi->base + STM32_SPI_SR);
352 u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
353
354 while ((spi->rx_len > 0) &&
355 ((sr & SPI_SR_RXP) ||
356 (flush && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
357 u32 offs = spi->cur_xferlen - spi->rx_len;
358
359 if ((spi->rx_len >= sizeof(u32)) ||
360 (flush && (sr & SPI_SR_RXWNE))) {
361 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
362
363 *rx_buf32 = readl_relaxed(spi->base + STM32_SPI_RXDR);
364 spi->rx_len -= sizeof(u32);
365 } else if ((spi->rx_len >= sizeof(u16)) ||
366 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
367 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
368
369 *rx_buf16 = readw_relaxed(spi->base + STM32_SPI_RXDR);
370 spi->rx_len -= sizeof(u16);
371 } else {
372 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
373
374 *rx_buf8 = readb_relaxed(spi->base + STM32_SPI_RXDR);
375 spi->rx_len -= sizeof(u8);
376 }
377
378 sr = readl_relaxed(spi->base + STM32_SPI_SR);
379 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
380 }
381
382 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
383 flush ? "(flush)" : "", spi->rx_len);
384}
385
386/**
387 * stm32_spi_enable - Enable SPI controller
388 * @spi: pointer to the spi controller data structure
389 *
390 * SPI data transfer is enabled but spi_ker_ck is idle.
391 * SPI_CFG1 and SPI_CFG2 are now write protected.
392 */
393static void stm32_spi_enable(struct stm32_spi *spi)
394{
395 dev_dbg(spi->dev, "enable controller\n");
396
397 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
398}
399
400/**
401 * stm32_spi_disable - Disable SPI controller
402 * @spi: pointer to the spi controller data structure
403 *
404 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
405 * loss, use stm32_spi_read_rxfifo(flush) to read the remaining bytes in
406 * RX-Fifo.
407 */
408static void stm32_spi_disable(struct stm32_spi *spi)
409{
410 unsigned long flags;
411 u32 cr1, sr;
412
413 dev_dbg(spi->dev, "disable controller\n");
414
415 spin_lock_irqsave(&spi->lock, flags);
416
417 cr1 = readl_relaxed(spi->base + STM32_SPI_CR1);
418
419 if (!(cr1 & SPI_CR1_SPE)) {
420 spin_unlock_irqrestore(&spi->lock, flags);
421 return;
422 }
423
424 /* Wait on EOT or suspend the flow */
425 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32_SPI_SR,
426 sr, !(sr & SPI_SR_EOT),
427 10, 100000) < 0) {
428 if (cr1 & SPI_CR1_CSTART) {
429 writel_relaxed(cr1 | SPI_CR1_CSUSP,
430 spi->base + STM32_SPI_CR1);
431 if (readl_relaxed_poll_timeout_atomic(
432 spi->base + STM32_SPI_SR,
433 sr, !(sr & SPI_SR_SUSP),
434 10, 100000) < 0)
435 dev_warn(spi->dev,
436 "Suspend request timeout\n");
437 }
438 }
439
440 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
441 stm32_spi_read_rxfifo(spi, true);
442
443 if (spi->cur_usedma && spi->tx_buf)
444 dmaengine_terminate_all(spi->dma_tx);
445 if (spi->cur_usedma && spi->rx_buf)
446 dmaengine_terminate_all(spi->dma_rx);
447
448 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
449
450 stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN |
451 SPI_CFG1_RXDMAEN);
452
453 /* Disable interrupts and clear status flags */
454 writel_relaxed(0, spi->base + STM32_SPI_IER);
455 writel_relaxed(SPI_IFCR_ALL, spi->base + STM32_SPI_IFCR);
456
457 spin_unlock_irqrestore(&spi->lock, flags);
458}
459
460/**
461 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
462 *
463 * If the current transfer size is greater than fifo size, use DMA.
464 */
465static bool stm32_spi_can_dma(struct spi_master *master,
466 struct spi_device *spi_dev,
467 struct spi_transfer *transfer)
468{
469 struct stm32_spi *spi = spi_master_get_devdata(master);
470
471 dev_dbg(spi->dev, "%s: %s\n", __func__,
472 (transfer->len > spi->fifo_size) ? "true" : "false");
473
474 return (transfer->len > spi->fifo_size);
475}
476
477/**
478 * stm32_spi_irq - Interrupt handler for SPI controller events
479 * @irq: interrupt line
480 * @dev_id: SPI controller master interface
481 */
482static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
483{
484 struct spi_master *master = dev_id;
485 struct stm32_spi *spi = spi_master_get_devdata(master);
486 u32 sr, ier, mask;
487 unsigned long flags;
488 bool end = false;
489
490 spin_lock_irqsave(&spi->lock, flags);
491
492 sr = readl_relaxed(spi->base + STM32_SPI_SR);
493 ier = readl_relaxed(spi->base + STM32_SPI_IER);
494
495 mask = ier;
496 /* EOTIE is triggered on EOT, SUSP and TXC events. */
497 mask |= SPI_SR_SUSP;
498 /*
499 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
500 * Full-Duplex, need to poll RXP event to know if there are remaining
501 * data, before disabling SPI.
502 */
503 if (spi->rx_buf && !spi->cur_usedma)
504 mask |= SPI_SR_RXP;
505
506 if (!(sr & mask)) {
507 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
508 sr, ier);
509 spin_unlock_irqrestore(&spi->lock, flags);
510 return IRQ_NONE;
511 }
512
513 if (sr & SPI_SR_SUSP) {
514 dev_warn(spi->dev, "Communication suspended\n");
515 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
516 stm32_spi_read_rxfifo(spi, false);
517 /*
518 * If communication is suspended while using DMA, it means
519 * that something went wrong, so stop the current transfer
520 */
521 if (spi->cur_usedma)
522 end = true;
523 }
524
525 if (sr & SPI_SR_MODF) {
526 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
527 end = true;
528 }
529
530 if (sr & SPI_SR_OVR) {
531 dev_warn(spi->dev, "Overrun: received value discarded\n");
532 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
533 stm32_spi_read_rxfifo(spi, false);
534 /*
535 * If overrun is detected while using DMA, it means that
536 * something went wrong, so stop the current transfer
537 */
538 if (spi->cur_usedma)
539 end = true;
540 }
541
542 if (sr & SPI_SR_EOT) {
543 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
544 stm32_spi_read_rxfifo(spi, true);
545 end = true;
546 }
547
548 if (sr & SPI_SR_TXP)
549 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
550 stm32_spi_write_txfifo(spi);
551
552 if (sr & SPI_SR_RXP)
553 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
554 stm32_spi_read_rxfifo(spi, false);
555
556 writel_relaxed(mask, spi->base + STM32_SPI_IFCR);
557
558 spin_unlock_irqrestore(&spi->lock, flags);
559
560 if (end) {
561 spi_finalize_current_transfer(master);
562 stm32_spi_disable(spi);
563 }
564
565 return IRQ_HANDLED;
566}
567
568/**
569 * stm32_spi_setup - setup device chip select
570 */
571static int stm32_spi_setup(struct spi_device *spi_dev)
572{
573 int ret = 0;
574
575 if (!gpio_is_valid(spi_dev->cs_gpio)) {
576 dev_err(&spi_dev->dev, "%d is not a valid gpio\n",
577 spi_dev->cs_gpio);
578 return -EINVAL;
579 }
580
581 dev_dbg(&spi_dev->dev, "%s: set gpio%d output %s\n", __func__,
582 spi_dev->cs_gpio,
583 (spi_dev->mode & SPI_CS_HIGH) ? "low" : "high");
584
585 ret = gpio_direction_output(spi_dev->cs_gpio,
586 !(spi_dev->mode & SPI_CS_HIGH));
587
588 return ret;
589}
590
591/**
592 * stm32_spi_prepare_msg - set up the controller to transfer a single message
593 */
594static int stm32_spi_prepare_msg(struct spi_master *master,
595 struct spi_message *msg)
596{
597 struct stm32_spi *spi = spi_master_get_devdata(master);
598 struct spi_device *spi_dev = msg->spi;
599 struct device_node *np = spi_dev->dev.of_node;
600 unsigned long flags;
601 u32 cfg2_clrb = 0, cfg2_setb = 0;
602
603 /* SPI slave device may need time between data frames */
604 spi->cur_midi = 0;
605 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
606 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
607
608 if (spi_dev->mode & SPI_CPOL)
609 cfg2_setb |= SPI_CFG2_CPOL;
610 else
611 cfg2_clrb |= SPI_CFG2_CPOL;
612
613 if (spi_dev->mode & SPI_CPHA)
614 cfg2_setb |= SPI_CFG2_CPHA;
615 else
616 cfg2_clrb |= SPI_CFG2_CPHA;
617
618 if (spi_dev->mode & SPI_LSB_FIRST)
619 cfg2_setb |= SPI_CFG2_LSBFRST;
620 else
621 cfg2_clrb |= SPI_CFG2_LSBFRST;
622
623 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
624 spi_dev->mode & SPI_CPOL,
625 spi_dev->mode & SPI_CPHA,
626 spi_dev->mode & SPI_LSB_FIRST,
627 spi_dev->mode & SPI_CS_HIGH);
628
629 spin_lock_irqsave(&spi->lock, flags);
630
631 if (cfg2_clrb || cfg2_setb)
632 writel_relaxed(
633 (readl_relaxed(spi->base + STM32_SPI_CFG2) &
634 ~cfg2_clrb) | cfg2_setb,
635 spi->base + STM32_SPI_CFG2);
636
637 spin_unlock_irqrestore(&spi->lock, flags);
638
639 return 0;
640}
641
642/**
643 * stm32_spi_dma_cb - dma callback
644 *
645 * DMA callback is called when the transfer is complete or when an error
646 * occurs. If the transfer is complete, EOT flag is raised.
647 */
648static void stm32_spi_dma_cb(void *data)
649{
650 struct stm32_spi *spi = data;
651 unsigned long flags;
652 u32 sr;
653
654 spin_lock_irqsave(&spi->lock, flags);
655
656 sr = readl_relaxed(spi->base + STM32_SPI_SR);
657
658 spin_unlock_irqrestore(&spi->lock, flags);
659
660 if (!(sr & SPI_SR_EOT))
661 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
662
663 /* Now wait for EOT, or SUSP or OVR in case of error */
664}
665
666/**
667 * stm32_spi_dma_config - configure dma slave channel depending on current
668 * transfer bits_per_word.
669 */
670static void stm32_spi_dma_config(struct stm32_spi *spi,
671 struct dma_slave_config *dma_conf,
672 enum dma_transfer_direction dir)
673{
674 enum dma_slave_buswidth buswidth;
675 u32 maxburst;
676
677 if (spi->cur_bpw <= 8)
678 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
679 else if (spi->cur_bpw <= 16)
680 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
681 else
682 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
683
684 /* Valid for DMA Half or Full Fifo threshold */
685 if (spi->cur_fthlv == 2)
686 maxburst = 1;
687 else
688 maxburst = spi->cur_fthlv;
689
690 memset(dma_conf, 0, sizeof(struct dma_slave_config));
691 dma_conf->direction = dir;
692 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
693 dma_conf->src_addr = spi->phys_addr + STM32_SPI_RXDR;
694 dma_conf->src_addr_width = buswidth;
695 dma_conf->src_maxburst = maxburst;
696
697 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
698 buswidth, maxburst);
699 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
700 dma_conf->dst_addr = spi->phys_addr + STM32_SPI_TXDR;
701 dma_conf->dst_addr_width = buswidth;
702 dma_conf->dst_maxburst = maxburst;
703
704 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
705 buswidth, maxburst);
706 }
707}
708
709/**
710 * stm32_spi_transfer_one_irq - transfer a single spi_transfer using
711 * interrupts
712 *
713 * It must returns 0 if the transfer is finished or 1 if the transfer is still
714 * in progress.
715 */
716static int stm32_spi_transfer_one_irq(struct stm32_spi *spi)
717{
718 unsigned long flags;
719 u32 ier = 0;
720
721 /* Enable the interrupts relative to the current communication mode */
722 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
723 ier |= SPI_IER_DXPIE;
724 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
725 ier |= SPI_IER_TXPIE;
726 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
727 ier |= SPI_IER_RXPIE;
728
729 /* Enable the interrupts relative to the end of transfer */
730 ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE;
731
732 spin_lock_irqsave(&spi->lock, flags);
733
734 stm32_spi_enable(spi);
735
736 /* Be sure to have data in fifo before starting data transfer */
737 if (spi->tx_buf)
738 stm32_spi_write_txfifo(spi);
739
740 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
741
742 writel_relaxed(ier, spi->base + STM32_SPI_IER);
743
744 spin_unlock_irqrestore(&spi->lock, flags);
745
746 return 1;
747}
748
749/**
750 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
751 *
752 * It must returns 0 if the transfer is finished or 1 if the transfer is still
753 * in progress.
754 */
755static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
756 struct spi_transfer *xfer)
757{
758 struct dma_slave_config tx_dma_conf, rx_dma_conf;
759 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
760 unsigned long flags;
761 u32 ier = 0;
762
763 spin_lock_irqsave(&spi->lock, flags);
764
765 rx_dma_desc = NULL;
766 if (spi->rx_buf) {
767 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
768 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
769
770 /* Enable Rx DMA request */
771 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
772
773 rx_dma_desc = dmaengine_prep_slave_sg(
774 spi->dma_rx, xfer->rx_sg.sgl,
775 xfer->rx_sg.nents,
776 rx_dma_conf.direction,
777 DMA_PREP_INTERRUPT);
778 }
779
780 tx_dma_desc = NULL;
781 if (spi->tx_buf) {
782 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
783 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
784
785 tx_dma_desc = dmaengine_prep_slave_sg(
786 spi->dma_tx, xfer->tx_sg.sgl,
787 xfer->tx_sg.nents,
788 tx_dma_conf.direction,
789 DMA_PREP_INTERRUPT);
790 }
791
792 if ((spi->tx_buf && !tx_dma_desc) ||
793 (spi->rx_buf && !rx_dma_desc))
794 goto dma_desc_error;
795
796 if (rx_dma_desc) {
797 rx_dma_desc->callback = stm32_spi_dma_cb;
798 rx_dma_desc->callback_param = spi;
799
800 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
801 dev_err(spi->dev, "Rx DMA submit failed\n");
802 goto dma_desc_error;
803 }
804 /* Enable Rx DMA channel */
805 dma_async_issue_pending(spi->dma_rx);
806 }
807
808 if (tx_dma_desc) {
809 if (spi->cur_comm == SPI_SIMPLEX_TX) {
810 tx_dma_desc->callback = stm32_spi_dma_cb;
811 tx_dma_desc->callback_param = spi;
812 }
813
814 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
815 dev_err(spi->dev, "Tx DMA submit failed\n");
816 goto dma_submit_error;
817 }
818 /* Enable Tx DMA channel */
819 dma_async_issue_pending(spi->dma_tx);
820
821 /* Enable Tx DMA request */
822 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN);
823 }
824
825 /* Enable the interrupts relative to the end of transfer */
826 ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE;
827 writel_relaxed(ier, spi->base + STM32_SPI_IER);
828
829 stm32_spi_enable(spi);
830
831 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
832
833 spin_unlock_irqrestore(&spi->lock, flags);
834
835 return 1;
836
837dma_submit_error:
838 if (spi->rx_buf)
839 dmaengine_terminate_all(spi->dma_rx);
840
841dma_desc_error:
842 stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
843
844 spin_unlock_irqrestore(&spi->lock, flags);
845
846 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
847
848 return stm32_spi_transfer_one_irq(spi);
849}
850
851/**
852 * stm32_spi_transfer_one_setup - common setup to transfer a single
853 * spi_transfer either using DMA or
854 * interrupts.
855 */
856static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
857 struct spi_device *spi_dev,
858 struct spi_transfer *transfer)
859{
860 unsigned long flags;
861 u32 cfg1_clrb = 0, cfg1_setb = 0, cfg2_clrb = 0, cfg2_setb = 0;
862 u32 mode, nb_words;
863 int ret = 0;
864
865 spin_lock_irqsave(&spi->lock, flags);
866
867 if (spi->cur_bpw != transfer->bits_per_word) {
868 u32 bpw, fthlv;
869
870 spi->cur_bpw = transfer->bits_per_word;
871 bpw = spi->cur_bpw - 1;
872
873 cfg1_clrb |= SPI_CFG1_DSIZE;
874 cfg1_setb |= (bpw << SPI_CFG1_DSIZE_SHIFT) & SPI_CFG1_DSIZE;
875
876 spi->cur_fthlv = stm32_spi_prepare_fthlv(spi);
877 fthlv = spi->cur_fthlv - 1;
878
879 cfg1_clrb |= SPI_CFG1_FTHLV;
880 cfg1_setb |= (fthlv << SPI_CFG1_FTHLV_SHIFT) & SPI_CFG1_FTHLV;
881 }
882
883 if (spi->cur_speed != transfer->speed_hz) {
884 int mbr;
885
886 /* Update spi->cur_speed with real clock speed */
887 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz);
888 if (mbr < 0) {
889 ret = mbr;
890 goto out;
891 }
892
893 transfer->speed_hz = spi->cur_speed;
894
895 cfg1_clrb |= SPI_CFG1_MBR;
896 cfg1_setb |= ((u32)mbr << SPI_CFG1_MBR_SHIFT) & SPI_CFG1_MBR;
897 }
898
899 if (cfg1_clrb || cfg1_setb)
900 writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG1) &
901 ~cfg1_clrb) | cfg1_setb,
902 spi->base + STM32_SPI_CFG1);
903
904 mode = SPI_FULL_DUPLEX;
905 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
906 /*
907 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
908 * is forbidden und unvalidated by SPI subsystem so depending
909 * on the valid buffer, we can determine the direction of the
910 * transfer.
911 */
912 mode = SPI_HALF_DUPLEX;
913 if (!transfer->tx_buf)
914 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
915 else if (!transfer->rx_buf)
916 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
917 } else {
918 if (!transfer->tx_buf)
919 mode = SPI_SIMPLEX_RX;
920 else if (!transfer->rx_buf)
921 mode = SPI_SIMPLEX_TX;
922 }
923 if (spi->cur_comm != mode) {
924 spi->cur_comm = mode;
925
926 cfg2_clrb |= SPI_CFG2_COMM;
927 cfg2_setb |= (mode << SPI_CFG2_COMM_SHIFT) & SPI_CFG2_COMM;
928 }
929
930 cfg2_clrb |= SPI_CFG2_MIDI;
931 if ((transfer->len > 1) && (spi->cur_midi > 0)) {
932 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
933 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
934 (u32)SPI_CFG2_MIDI >> SPI_CFG2_MIDI_SHIFT);
935
936 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
937 sck_period_ns, midi, midi * sck_period_ns);
938
939 cfg2_setb |= (midi << SPI_CFG2_MIDI_SHIFT) & SPI_CFG2_MIDI;
940 }
941
942 if (cfg2_clrb || cfg2_setb)
943 writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG2) &
944 ~cfg2_clrb) | cfg2_setb,
945 spi->base + STM32_SPI_CFG2);
946
947 if (spi->cur_bpw <= 8)
948 nb_words = transfer->len;
949 else if (spi->cur_bpw <= 16)
950 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
951 else
952 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
953 nb_words <<= SPI_CR2_TSIZE_SHIFT;
954
955 if (nb_words <= SPI_CR2_TSIZE) {
956 writel_relaxed(nb_words, spi->base + STM32_SPI_CR2);
957 } else {
958 ret = -EMSGSIZE;
959 goto out;
960 }
961
962 spi->cur_xferlen = transfer->len;
963
964 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
965 spi->cur_comm);
966 dev_dbg(spi->dev,
967 "data frame of %d-bit, data packet of %d data frames\n",
968 spi->cur_bpw, spi->cur_fthlv);
969 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
970 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
971 spi->cur_xferlen, nb_words);
972 dev_dbg(spi->dev, "dma %s\n",
973 (spi->cur_usedma) ? "enabled" : "disabled");
974
975out:
976 spin_unlock_irqrestore(&spi->lock, flags);
977
978 return ret;
979}
980
981/**
982 * stm32_spi_transfer_one - transfer a single spi_transfer
983 *
984 * It must return 0 if the transfer is finished or 1 if the transfer is still
985 * in progress.
986 */
987static int stm32_spi_transfer_one(struct spi_master *master,
988 struct spi_device *spi_dev,
989 struct spi_transfer *transfer)
990{
991 struct stm32_spi *spi = spi_master_get_devdata(master);
992 int ret;
993
994 spi->tx_buf = transfer->tx_buf;
995 spi->rx_buf = transfer->rx_buf;
996 spi->tx_len = spi->tx_buf ? transfer->len : 0;
997 spi->rx_len = spi->rx_buf ? transfer->len : 0;
998
999 spi->cur_usedma = (master->can_dma &&
1000 stm32_spi_can_dma(master, spi_dev, transfer));
1001
1002 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1003 if (ret) {
1004 dev_err(spi->dev, "SPI transfer setup failed\n");
1005 return ret;
1006 }
1007
1008 if (spi->cur_usedma)
1009 return stm32_spi_transfer_one_dma(spi, transfer);
1010 else
1011 return stm32_spi_transfer_one_irq(spi);
1012}
1013
1014/**
1015 * stm32_spi_unprepare_msg - relax the hardware
1016 *
1017 * Normally, if TSIZE has been configured, we should relax the hardware at the
1018 * reception of the EOT interrupt. But in case of error, EOT will not be
1019 * raised. So the subsystem unprepare_message call allows us to properly
1020 * complete the transfer from an hardware point of view.
1021 */
1022static int stm32_spi_unprepare_msg(struct spi_master *master,
1023 struct spi_message *msg)
1024{
1025 struct stm32_spi *spi = spi_master_get_devdata(master);
1026
1027 stm32_spi_disable(spi);
1028
1029 return 0;
1030}
1031
1032/**
1033 * stm32_spi_config - Configure SPI controller as SPI master
1034 */
1035static int stm32_spi_config(struct stm32_spi *spi)
1036{
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&spi->lock, flags);
1040
1041 /* Ensure I2SMOD bit is kept cleared */
1042 stm32_spi_clr_bits(spi, STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
1043
1044 /*
1045 * - SS input value high
1046 * - transmitter half duplex direction
1047 * - automatic communication suspend when RX-Fifo is full
1048 */
1049 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SSI |
1050 SPI_CR1_HDDIR |
1051 SPI_CR1_MASRX);
1052
1053 /*
1054 * - Set the master mode (default Motorola mode)
1055 * - Consider 1 master/n slaves configuration and
1056 * SS input value is determined by the SSI bit
1057 * - keep control of all associated GPIOs
1058 */
1059 stm32_spi_set_bits(spi, STM32_SPI_CFG2, SPI_CFG2_MASTER |
1060 SPI_CFG2_SSM |
1061 SPI_CFG2_AFCNTR);
1062
1063 spin_unlock_irqrestore(&spi->lock, flags);
1064
1065 return 0;
1066}
1067
1068static const struct of_device_id stm32_spi_of_match[] = {
1069 { .compatible = "st,stm32h7-spi", },
1070 {},
1071};
1072MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1073
1074static int stm32_spi_probe(struct platform_device *pdev)
1075{
1076 struct spi_master *master;
1077 struct stm32_spi *spi;
1078 struct resource *res;
1079 int i, ret;
1080
1081 master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1082 if (!master) {
1083 dev_err(&pdev->dev, "spi master allocation failed\n");
1084 return -ENOMEM;
1085 }
1086 platform_set_drvdata(pdev, master);
1087
1088 spi = spi_master_get_devdata(master);
1089 spi->dev = &pdev->dev;
1090 spi->master = master;
1091 spin_lock_init(&spi->lock);
1092
1093 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1094 spi->base = devm_ioremap_resource(&pdev->dev, res);
1095 if (IS_ERR(spi->base)) {
1096 ret = PTR_ERR(spi->base);
1097 goto err_master_put;
1098 }
1099 spi->phys_addr = (dma_addr_t)res->start;
1100
1101 spi->irq = platform_get_irq(pdev, 0);
1102 if (spi->irq <= 0) {
1103 dev_err(&pdev->dev, "no irq: %d\n", spi->irq);
1104 ret = -ENOENT;
1105 goto err_master_put;
1106 }
1107 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL,
1108 stm32_spi_irq, IRQF_ONESHOT,
1109 pdev->name, master);
1110 if (ret) {
1111 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1112 ret);
1113 goto err_master_put;
1114 }
1115
1116 spi->clk = devm_clk_get(&pdev->dev, 0);
1117 if (IS_ERR(spi->clk)) {
1118 ret = PTR_ERR(spi->clk);
1119 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1120 goto err_master_put;
1121 }
1122
1123 ret = clk_prepare_enable(spi->clk);
1124 if (ret) {
1125 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1126 goto err_master_put;
1127 }
1128 spi->clk_rate = clk_get_rate(spi->clk);
1129 if (!spi->clk_rate) {
1130 dev_err(&pdev->dev, "clk rate = 0\n");
1131 ret = -EINVAL;
1132 goto err_master_put;
1133 }
1134
1135 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1136 if (!IS_ERR(spi->rst)) {
1137 reset_control_assert(spi->rst);
1138 udelay(2);
1139 reset_control_deassert(spi->rst);
1140 }
1141
1142 spi->fifo_size = stm32_spi_get_fifo_size(spi);
1143
1144 ret = stm32_spi_config(spi);
1145 if (ret) {
1146 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1147 ret);
1148 goto err_clk_disable;
1149 }
1150
1151 master->dev.of_node = pdev->dev.of_node;
1152 master->auto_runtime_pm = true;
1153 master->bus_num = pdev->id;
1154 master->mode_bits = SPI_MODE_3 | SPI_CS_HIGH | SPI_LSB_FIRST |
1155 SPI_3WIRE | SPI_LOOP;
1156 master->bits_per_word_mask = stm32_spi_get_bpw_mask(spi);
1157 master->max_speed_hz = spi->clk_rate / SPI_MBR_DIV_MIN;
1158 master->min_speed_hz = spi->clk_rate / SPI_MBR_DIV_MAX;
1159 master->setup = stm32_spi_setup;
1160 master->prepare_message = stm32_spi_prepare_msg;
1161 master->transfer_one = stm32_spi_transfer_one;
1162 master->unprepare_message = stm32_spi_unprepare_msg;
1163
1164 spi->dma_tx = dma_request_slave_channel(spi->dev, "tx");
1165 if (!spi->dma_tx)
1166 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1167 else
1168 master->dma_tx = spi->dma_tx;
1169
1170 spi->dma_rx = dma_request_slave_channel(spi->dev, "rx");
1171 if (!spi->dma_rx)
1172 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1173 else
1174 master->dma_rx = spi->dma_rx;
1175
1176 if (spi->dma_tx || spi->dma_rx)
1177 master->can_dma = stm32_spi_can_dma;
1178
1179 pm_runtime_set_active(&pdev->dev);
1180 pm_runtime_enable(&pdev->dev);
1181
1182 ret = devm_spi_register_master(&pdev->dev, master);
1183 if (ret) {
1184 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1185 ret);
1186 goto err_dma_release;
1187 }
1188
1189 if (!master->cs_gpios) {
1190 dev_err(&pdev->dev, "no CS gpios available\n");
1191 ret = -EINVAL;
1192 goto err_dma_release;
1193 }
1194
1195 for (i = 0; i < master->num_chipselect; i++) {
1196 if (!gpio_is_valid(master->cs_gpios[i])) {
1197 dev_err(&pdev->dev, "%i is not a valid gpio\n",
1198 master->cs_gpios[i]);
1199 ret = -EINVAL;
1200 goto err_dma_release;
1201 }
1202
1203 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
1204 DRIVER_NAME);
1205 if (ret) {
1206 dev_err(&pdev->dev, "can't get CS gpio %i\n",
1207 master->cs_gpios[i]);
1208 goto err_dma_release;
1209 }
1210 }
1211
1212 dev_info(&pdev->dev, "driver initialized\n");
1213
1214 return 0;
1215
1216err_dma_release:
1217 if (spi->dma_tx)
1218 dma_release_channel(spi->dma_tx);
1219 if (spi->dma_rx)
1220 dma_release_channel(spi->dma_rx);
1221
1222 pm_runtime_disable(&pdev->dev);
1223err_clk_disable:
1224 clk_disable_unprepare(spi->clk);
1225err_master_put:
1226 spi_master_put(master);
1227
1228 return ret;
1229}
1230
1231static int stm32_spi_remove(struct platform_device *pdev)
1232{
1233 struct spi_master *master = platform_get_drvdata(pdev);
1234 struct stm32_spi *spi = spi_master_get_devdata(master);
1235
1236 stm32_spi_disable(spi);
1237
1238 if (master->dma_tx)
1239 dma_release_channel(master->dma_tx);
1240 if (master->dma_rx)
1241 dma_release_channel(master->dma_rx);
1242
1243 clk_disable_unprepare(spi->clk);
1244
1245 pm_runtime_disable(&pdev->dev);
1246
1247 return 0;
1248}
1249
1250#ifdef CONFIG_PM
1251static int stm32_spi_runtime_suspend(struct device *dev)
1252{
1253 struct spi_master *master = dev_get_drvdata(dev);
1254 struct stm32_spi *spi = spi_master_get_devdata(master);
1255
1256 clk_disable_unprepare(spi->clk);
1257
1258 return 0;
1259}
1260
1261static int stm32_spi_runtime_resume(struct device *dev)
1262{
1263 struct spi_master *master = dev_get_drvdata(dev);
1264 struct stm32_spi *spi = spi_master_get_devdata(master);
1265
1266 return clk_prepare_enable(spi->clk);
1267}
1268#endif
1269
1270#ifdef CONFIG_PM_SLEEP
1271static int stm32_spi_suspend(struct device *dev)
1272{
1273 struct spi_master *master = dev_get_drvdata(dev);
1274 int ret;
1275
1276 ret = spi_master_suspend(master);
1277 if (ret)
1278 return ret;
1279
1280 return pm_runtime_force_suspend(dev);
1281}
1282
1283static int stm32_spi_resume(struct device *dev)
1284{
1285 struct spi_master *master = dev_get_drvdata(dev);
1286 struct stm32_spi *spi = spi_master_get_devdata(master);
1287 int ret;
1288
1289 ret = pm_runtime_force_resume(dev);
1290 if (ret)
1291 return ret;
1292
1293 ret = spi_master_resume(master);
1294 if (ret)
1295 clk_disable_unprepare(spi->clk);
1296
1297 return ret;
1298}
1299#endif
1300
1301static const struct dev_pm_ops stm32_spi_pm_ops = {
1302 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
1303 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
1304 stm32_spi_runtime_resume, NULL)
1305};
1306
1307static struct platform_driver stm32_spi_driver = {
1308 .probe = stm32_spi_probe,
1309 .remove = stm32_spi_remove,
1310 .driver = {
1311 .name = DRIVER_NAME,
1312 .pm = &stm32_spi_pm_ops,
1313 .of_match_table = stm32_spi_of_match,
1314 },
1315};
1316
1317module_platform_driver(stm32_spi_driver);
1318
1319MODULE_ALIAS("platform:" DRIVER_NAME);
1320MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
1321MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
1322MODULE_LICENSE("GPL v2");