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1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/device.h>
23#include <linux/pm_runtime.h>
24#include <linux/pm.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/irqdomain.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31#include <mach/irqs.h>
32#include <asm/gpio.h>
33#include <asm/mach/irq.h>
34
35#define OFF_MODE 1
36
37static LIST_HEAD(omap_gpio_list);
38
39struct gpio_regs {
40 u32 irqenable1;
41 u32 irqenable2;
42 u32 wake_en;
43 u32 ctrl;
44 u32 oe;
45 u32 leveldetect0;
46 u32 leveldetect1;
47 u32 risingdetect;
48 u32 fallingdetect;
49 u32 dataout;
50 u32 debounce;
51 u32 debounce_en;
52};
53
54struct gpio_bank {
55 struct list_head node;
56 void __iomem *base;
57 u16 irq;
58 int irq_base;
59 struct irq_domain *domain;
60 u32 non_wakeup_gpios;
61 u32 enabled_non_wakeup_gpios;
62 struct gpio_regs context;
63 u32 saved_datain;
64 u32 level_mask;
65 u32 toggle_mask;
66 spinlock_t lock;
67 struct gpio_chip chip;
68 struct clk *dbck;
69 u32 mod_usage;
70 u32 dbck_enable_mask;
71 bool dbck_enabled;
72 struct device *dev;
73 bool is_mpuio;
74 bool dbck_flag;
75 bool loses_context;
76 int stride;
77 u32 width;
78 int context_loss_count;
79 int power_mode;
80 bool workaround_enabled;
81
82 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
83 int (*get_context_loss_count)(struct device *dev);
84
85 struct omap_gpio_reg_offs *regs;
86};
87
88#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
89#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
90#define GPIO_MOD_CTRL_BIT BIT(0)
91
92static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
93{
94 return gpio_irq - bank->irq_base + bank->chip.base;
95}
96
97static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
98{
99 void __iomem *reg = bank->base;
100 u32 l;
101
102 reg += bank->regs->direction;
103 l = __raw_readl(reg);
104 if (is_input)
105 l |= 1 << gpio;
106 else
107 l &= ~(1 << gpio);
108 __raw_writel(l, reg);
109 bank->context.oe = l;
110}
111
112
113/* set data out value using dedicate set/clear register */
114static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
115{
116 void __iomem *reg = bank->base;
117 u32 l = GPIO_BIT(bank, gpio);
118
119 if (enable) {
120 reg += bank->regs->set_dataout;
121 bank->context.dataout |= l;
122 } else {
123 reg += bank->regs->clr_dataout;
124 bank->context.dataout &= ~l;
125 }
126
127 __raw_writel(l, reg);
128}
129
130/* set data out value using mask register */
131static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
132{
133 void __iomem *reg = bank->base + bank->regs->dataout;
134 u32 gpio_bit = GPIO_BIT(bank, gpio);
135 u32 l;
136
137 l = __raw_readl(reg);
138 if (enable)
139 l |= gpio_bit;
140 else
141 l &= ~gpio_bit;
142 __raw_writel(l, reg);
143 bank->context.dataout = l;
144}
145
146static int _get_gpio_datain(struct gpio_bank *bank, int offset)
147{
148 void __iomem *reg = bank->base + bank->regs->datain;
149
150 return (__raw_readl(reg) & (1 << offset)) != 0;
151}
152
153static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
154{
155 void __iomem *reg = bank->base + bank->regs->dataout;
156
157 return (__raw_readl(reg) & (1 << offset)) != 0;
158}
159
160static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
161{
162 int l = __raw_readl(base + reg);
163
164 if (set)
165 l |= mask;
166 else
167 l &= ~mask;
168
169 __raw_writel(l, base + reg);
170}
171
172static inline void _gpio_dbck_enable(struct gpio_bank *bank)
173{
174 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
175 clk_enable(bank->dbck);
176 bank->dbck_enabled = true;
177
178 __raw_writel(bank->dbck_enable_mask,
179 bank->base + bank->regs->debounce_en);
180 }
181}
182
183static inline void _gpio_dbck_disable(struct gpio_bank *bank)
184{
185 if (bank->dbck_enable_mask && bank->dbck_enabled) {
186 /*
187 * Disable debounce before cutting it's clock. If debounce is
188 * enabled but the clock is not, GPIO module seems to be unable
189 * to detect events and generate interrupts at least on OMAP3.
190 */
191 __raw_writel(0, bank->base + bank->regs->debounce_en);
192
193 clk_disable(bank->dbck);
194 bank->dbck_enabled = false;
195 }
196}
197
198/**
199 * _set_gpio_debounce - low level gpio debounce time
200 * @bank: the gpio bank we're acting upon
201 * @gpio: the gpio number on this @gpio
202 * @debounce: debounce time to use
203 *
204 * OMAP's debounce time is in 31us steps so we need
205 * to convert and round up to the closest unit.
206 */
207static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
208 unsigned debounce)
209{
210 void __iomem *reg;
211 u32 val;
212 u32 l;
213
214 if (!bank->dbck_flag)
215 return;
216
217 if (debounce < 32)
218 debounce = 0x01;
219 else if (debounce > 7936)
220 debounce = 0xff;
221 else
222 debounce = (debounce / 0x1f) - 1;
223
224 l = GPIO_BIT(bank, gpio);
225
226 clk_enable(bank->dbck);
227 reg = bank->base + bank->regs->debounce;
228 __raw_writel(debounce, reg);
229
230 reg = bank->base + bank->regs->debounce_en;
231 val = __raw_readl(reg);
232
233 if (debounce)
234 val |= l;
235 else
236 val &= ~l;
237 bank->dbck_enable_mask = val;
238
239 __raw_writel(val, reg);
240 clk_disable(bank->dbck);
241 /*
242 * Enable debounce clock per module.
243 * This call is mandatory because in omap_gpio_request() when
244 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
245 * runtime callbck fails to turn on dbck because dbck_enable_mask
246 * used within _gpio_dbck_enable() is still not initialized at
247 * that point. Therefore we have to enable dbck here.
248 */
249 _gpio_dbck_enable(bank);
250 if (bank->dbck_enable_mask) {
251 bank->context.debounce = debounce;
252 bank->context.debounce_en = val;
253 }
254}
255
256static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
257 unsigned trigger)
258{
259 void __iomem *base = bank->base;
260 u32 gpio_bit = 1 << gpio;
261
262 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
263 trigger & IRQ_TYPE_LEVEL_LOW);
264 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
265 trigger & IRQ_TYPE_LEVEL_HIGH);
266 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
267 trigger & IRQ_TYPE_EDGE_RISING);
268 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
269 trigger & IRQ_TYPE_EDGE_FALLING);
270
271 bank->context.leveldetect0 =
272 __raw_readl(bank->base + bank->regs->leveldetect0);
273 bank->context.leveldetect1 =
274 __raw_readl(bank->base + bank->regs->leveldetect1);
275 bank->context.risingdetect =
276 __raw_readl(bank->base + bank->regs->risingdetect);
277 bank->context.fallingdetect =
278 __raw_readl(bank->base + bank->regs->fallingdetect);
279
280 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
281 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
282 bank->context.wake_en =
283 __raw_readl(bank->base + bank->regs->wkup_en);
284 }
285
286 /* This part needs to be executed always for OMAP{34xx, 44xx} */
287 if (!bank->regs->irqctrl) {
288 /* On omap24xx proceed only when valid GPIO bit is set */
289 if (bank->non_wakeup_gpios) {
290 if (!(bank->non_wakeup_gpios & gpio_bit))
291 goto exit;
292 }
293
294 /*
295 * Log the edge gpio and manually trigger the IRQ
296 * after resume if the input level changes
297 * to avoid irq lost during PER RET/OFF mode
298 * Applies for omap2 non-wakeup gpio and all omap3 gpios
299 */
300 if (trigger & IRQ_TYPE_EDGE_BOTH)
301 bank->enabled_non_wakeup_gpios |= gpio_bit;
302 else
303 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
304 }
305
306exit:
307 bank->level_mask =
308 __raw_readl(bank->base + bank->regs->leveldetect0) |
309 __raw_readl(bank->base + bank->regs->leveldetect1);
310}
311
312#ifdef CONFIG_ARCH_OMAP1
313/*
314 * This only applies to chips that can't do both rising and falling edge
315 * detection at once. For all other chips, this function is a noop.
316 */
317static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
318{
319 void __iomem *reg = bank->base;
320 u32 l = 0;
321
322 if (!bank->regs->irqctrl)
323 return;
324
325 reg += bank->regs->irqctrl;
326
327 l = __raw_readl(reg);
328 if ((l >> gpio) & 1)
329 l &= ~(1 << gpio);
330 else
331 l |= 1 << gpio;
332
333 __raw_writel(l, reg);
334}
335#else
336static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
337#endif
338
339static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
340 unsigned trigger)
341{
342 void __iomem *reg = bank->base;
343 void __iomem *base = bank->base;
344 u32 l = 0;
345
346 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
347 set_gpio_trigger(bank, gpio, trigger);
348 } else if (bank->regs->irqctrl) {
349 reg += bank->regs->irqctrl;
350
351 l = __raw_readl(reg);
352 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
353 bank->toggle_mask |= 1 << gpio;
354 if (trigger & IRQ_TYPE_EDGE_RISING)
355 l |= 1 << gpio;
356 else if (trigger & IRQ_TYPE_EDGE_FALLING)
357 l &= ~(1 << gpio);
358 else
359 return -EINVAL;
360
361 __raw_writel(l, reg);
362 } else if (bank->regs->edgectrl1) {
363 if (gpio & 0x08)
364 reg += bank->regs->edgectrl2;
365 else
366 reg += bank->regs->edgectrl1;
367
368 gpio &= 0x07;
369 l = __raw_readl(reg);
370 l &= ~(3 << (gpio << 1));
371 if (trigger & IRQ_TYPE_EDGE_RISING)
372 l |= 2 << (gpio << 1);
373 if (trigger & IRQ_TYPE_EDGE_FALLING)
374 l |= 1 << (gpio << 1);
375
376 /* Enable wake-up during idle for dynamic tick */
377 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
378 bank->context.wake_en =
379 __raw_readl(bank->base + bank->regs->wkup_en);
380 __raw_writel(l, reg);
381 }
382 return 0;
383}
384
385static int gpio_irq_type(struct irq_data *d, unsigned type)
386{
387 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
388 unsigned gpio;
389 int retval;
390 unsigned long flags;
391
392 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
393 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
394 else
395 gpio = irq_to_gpio(bank, d->irq);
396
397 if (type & ~IRQ_TYPE_SENSE_MASK)
398 return -EINVAL;
399
400 if (!bank->regs->leveldetect0 &&
401 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
402 return -EINVAL;
403
404 spin_lock_irqsave(&bank->lock, flags);
405 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
406 spin_unlock_irqrestore(&bank->lock, flags);
407
408 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
409 __irq_set_handler_locked(d->irq, handle_level_irq);
410 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
411 __irq_set_handler_locked(d->irq, handle_edge_irq);
412
413 return retval;
414}
415
416static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
417{
418 void __iomem *reg = bank->base;
419
420 reg += bank->regs->irqstatus;
421 __raw_writel(gpio_mask, reg);
422
423 /* Workaround for clearing DSP GPIO interrupts to allow retention */
424 if (bank->regs->irqstatus2) {
425 reg = bank->base + bank->regs->irqstatus2;
426 __raw_writel(gpio_mask, reg);
427 }
428
429 /* Flush posted write for the irq status to avoid spurious interrupts */
430 __raw_readl(reg);
431}
432
433static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
434{
435 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
436}
437
438static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
439{
440 void __iomem *reg = bank->base;
441 u32 l;
442 u32 mask = (1 << bank->width) - 1;
443
444 reg += bank->regs->irqenable;
445 l = __raw_readl(reg);
446 if (bank->regs->irqenable_inv)
447 l = ~l;
448 l &= mask;
449 return l;
450}
451
452static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
453{
454 void __iomem *reg = bank->base;
455 u32 l;
456
457 if (bank->regs->set_irqenable) {
458 reg += bank->regs->set_irqenable;
459 l = gpio_mask;
460 bank->context.irqenable1 |= gpio_mask;
461 } else {
462 reg += bank->regs->irqenable;
463 l = __raw_readl(reg);
464 if (bank->regs->irqenable_inv)
465 l &= ~gpio_mask;
466 else
467 l |= gpio_mask;
468 bank->context.irqenable1 = l;
469 }
470
471 __raw_writel(l, reg);
472}
473
474static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
475{
476 void __iomem *reg = bank->base;
477 u32 l;
478
479 if (bank->regs->clr_irqenable) {
480 reg += bank->regs->clr_irqenable;
481 l = gpio_mask;
482 bank->context.irqenable1 &= ~gpio_mask;
483 } else {
484 reg += bank->regs->irqenable;
485 l = __raw_readl(reg);
486 if (bank->regs->irqenable_inv)
487 l |= gpio_mask;
488 else
489 l &= ~gpio_mask;
490 bank->context.irqenable1 = l;
491 }
492
493 __raw_writel(l, reg);
494}
495
496static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
497{
498 if (enable)
499 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
500 else
501 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
502}
503
504/*
505 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
506 * 1510 does not seem to have a wake-up register. If JTAG is connected
507 * to the target, system will wake up always on GPIO events. While
508 * system is running all registered GPIO interrupts need to have wake-up
509 * enabled. When system is suspended, only selected GPIO interrupts need
510 * to have wake-up enabled.
511 */
512static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
513{
514 u32 gpio_bit = GPIO_BIT(bank, gpio);
515 unsigned long flags;
516
517 if (bank->non_wakeup_gpios & gpio_bit) {
518 dev_err(bank->dev,
519 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
520 return -EINVAL;
521 }
522
523 spin_lock_irqsave(&bank->lock, flags);
524 if (enable)
525 bank->context.wake_en |= gpio_bit;
526 else
527 bank->context.wake_en &= ~gpio_bit;
528
529 __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
530 spin_unlock_irqrestore(&bank->lock, flags);
531
532 return 0;
533}
534
535static void _reset_gpio(struct gpio_bank *bank, int gpio)
536{
537 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
538 _set_gpio_irqenable(bank, gpio, 0);
539 _clear_gpio_irqstatus(bank, gpio);
540 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
541}
542
543/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
544static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
545{
546 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
547 unsigned int gpio = irq_to_gpio(bank, d->irq);
548
549 return _set_gpio_wakeup(bank, gpio, enable);
550}
551
552static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
553{
554 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
555 unsigned long flags;
556
557 /*
558 * If this is the first gpio_request for the bank,
559 * enable the bank module.
560 */
561 if (!bank->mod_usage)
562 pm_runtime_get_sync(bank->dev);
563
564 spin_lock_irqsave(&bank->lock, flags);
565 /* Set trigger to none. You need to enable the desired trigger with
566 * request_irq() or set_irq_type().
567 */
568 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
569
570 if (bank->regs->pinctrl) {
571 void __iomem *reg = bank->base + bank->regs->pinctrl;
572
573 /* Claim the pin for MPU */
574 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
575 }
576
577 if (bank->regs->ctrl && !bank->mod_usage) {
578 void __iomem *reg = bank->base + bank->regs->ctrl;
579 u32 ctrl;
580
581 ctrl = __raw_readl(reg);
582 /* Module is enabled, clocks are not gated */
583 ctrl &= ~GPIO_MOD_CTRL_BIT;
584 __raw_writel(ctrl, reg);
585 bank->context.ctrl = ctrl;
586 }
587
588 bank->mod_usage |= 1 << offset;
589
590 spin_unlock_irqrestore(&bank->lock, flags);
591
592 return 0;
593}
594
595static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
596{
597 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
598 void __iomem *base = bank->base;
599 unsigned long flags;
600
601 spin_lock_irqsave(&bank->lock, flags);
602
603 if (bank->regs->wkup_en) {
604 /* Disable wake-up during idle for dynamic tick */
605 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
606 bank->context.wake_en =
607 __raw_readl(bank->base + bank->regs->wkup_en);
608 }
609
610 bank->mod_usage &= ~(1 << offset);
611
612 if (bank->regs->ctrl && !bank->mod_usage) {
613 void __iomem *reg = bank->base + bank->regs->ctrl;
614 u32 ctrl;
615
616 ctrl = __raw_readl(reg);
617 /* Module is disabled, clocks are gated */
618 ctrl |= GPIO_MOD_CTRL_BIT;
619 __raw_writel(ctrl, reg);
620 bank->context.ctrl = ctrl;
621 }
622
623 _reset_gpio(bank, bank->chip.base + offset);
624 spin_unlock_irqrestore(&bank->lock, flags);
625
626 /*
627 * If this is the last gpio to be freed in the bank,
628 * disable the bank module.
629 */
630 if (!bank->mod_usage)
631 pm_runtime_put(bank->dev);
632}
633
634/*
635 * We need to unmask the GPIO bank interrupt as soon as possible to
636 * avoid missing GPIO interrupts for other lines in the bank.
637 * Then we need to mask-read-clear-unmask the triggered GPIO lines
638 * in the bank to avoid missing nested interrupts for a GPIO line.
639 * If we wait to unmask individual GPIO lines in the bank after the
640 * line's interrupt handler has been run, we may miss some nested
641 * interrupts.
642 */
643static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
644{
645 void __iomem *isr_reg = NULL;
646 u32 isr;
647 unsigned int gpio_irq, gpio_index;
648 struct gpio_bank *bank;
649 int unmasked = 0;
650 struct irq_chip *chip = irq_desc_get_chip(desc);
651
652 chained_irq_enter(chip, desc);
653
654 bank = irq_get_handler_data(irq);
655 isr_reg = bank->base + bank->regs->irqstatus;
656 pm_runtime_get_sync(bank->dev);
657
658 if (WARN_ON(!isr_reg))
659 goto exit;
660
661 while(1) {
662 u32 isr_saved, level_mask = 0;
663 u32 enabled;
664
665 enabled = _get_gpio_irqbank_mask(bank);
666 isr_saved = isr = __raw_readl(isr_reg) & enabled;
667
668 if (bank->level_mask)
669 level_mask = bank->level_mask & enabled;
670
671 /* clear edge sensitive interrupts before handler(s) are
672 called so that we don't miss any interrupt occurred while
673 executing them */
674 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
675 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
676 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
677
678 /* if there is only edge sensitive GPIO pin interrupts
679 configured, we could unmask GPIO bank interrupt immediately */
680 if (!level_mask && !unmasked) {
681 unmasked = 1;
682 chained_irq_exit(chip, desc);
683 }
684
685 if (!isr)
686 break;
687
688 gpio_irq = bank->irq_base;
689 for (; isr != 0; isr >>= 1, gpio_irq++) {
690 int gpio = irq_to_gpio(bank, gpio_irq);
691
692 if (!(isr & 1))
693 continue;
694
695 gpio_index = GPIO_INDEX(bank, gpio);
696
697 /*
698 * Some chips can't respond to both rising and falling
699 * at the same time. If this irq was requested with
700 * both flags, we need to flip the ICR data for the IRQ
701 * to respond to the IRQ for the opposite direction.
702 * This will be indicated in the bank toggle_mask.
703 */
704 if (bank->toggle_mask & (1 << gpio_index))
705 _toggle_gpio_edge_triggering(bank, gpio_index);
706
707 generic_handle_irq(gpio_irq);
708 }
709 }
710 /* if bank has any level sensitive GPIO pin interrupt
711 configured, we must unmask the bank interrupt only after
712 handler(s) are executed in order to avoid spurious bank
713 interrupt */
714exit:
715 if (!unmasked)
716 chained_irq_exit(chip, desc);
717 pm_runtime_put(bank->dev);
718}
719
720static void gpio_irq_shutdown(struct irq_data *d)
721{
722 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
723 unsigned int gpio = irq_to_gpio(bank, d->irq);
724 unsigned long flags;
725
726 spin_lock_irqsave(&bank->lock, flags);
727 _reset_gpio(bank, gpio);
728 spin_unlock_irqrestore(&bank->lock, flags);
729}
730
731static void gpio_ack_irq(struct irq_data *d)
732{
733 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
734 unsigned int gpio = irq_to_gpio(bank, d->irq);
735
736 _clear_gpio_irqstatus(bank, gpio);
737}
738
739static void gpio_mask_irq(struct irq_data *d)
740{
741 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
742 unsigned int gpio = irq_to_gpio(bank, d->irq);
743 unsigned long flags;
744
745 spin_lock_irqsave(&bank->lock, flags);
746 _set_gpio_irqenable(bank, gpio, 0);
747 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
748 spin_unlock_irqrestore(&bank->lock, flags);
749}
750
751static void gpio_unmask_irq(struct irq_data *d)
752{
753 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
754 unsigned int gpio = irq_to_gpio(bank, d->irq);
755 unsigned int irq_mask = GPIO_BIT(bank, gpio);
756 u32 trigger = irqd_get_trigger_type(d);
757 unsigned long flags;
758
759 spin_lock_irqsave(&bank->lock, flags);
760 if (trigger)
761 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
762
763 /* For level-triggered GPIOs, the clearing must be done after
764 * the HW source is cleared, thus after the handler has run */
765 if (bank->level_mask & irq_mask) {
766 _set_gpio_irqenable(bank, gpio, 0);
767 _clear_gpio_irqstatus(bank, gpio);
768 }
769
770 _set_gpio_irqenable(bank, gpio, 1);
771 spin_unlock_irqrestore(&bank->lock, flags);
772}
773
774static struct irq_chip gpio_irq_chip = {
775 .name = "GPIO",
776 .irq_shutdown = gpio_irq_shutdown,
777 .irq_ack = gpio_ack_irq,
778 .irq_mask = gpio_mask_irq,
779 .irq_unmask = gpio_unmask_irq,
780 .irq_set_type = gpio_irq_type,
781 .irq_set_wake = gpio_wake_enable,
782};
783
784/*---------------------------------------------------------------------*/
785
786static int omap_mpuio_suspend_noirq(struct device *dev)
787{
788 struct platform_device *pdev = to_platform_device(dev);
789 struct gpio_bank *bank = platform_get_drvdata(pdev);
790 void __iomem *mask_reg = bank->base +
791 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
792 unsigned long flags;
793
794 spin_lock_irqsave(&bank->lock, flags);
795 __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
796 spin_unlock_irqrestore(&bank->lock, flags);
797
798 return 0;
799}
800
801static int omap_mpuio_resume_noirq(struct device *dev)
802{
803 struct platform_device *pdev = to_platform_device(dev);
804 struct gpio_bank *bank = platform_get_drvdata(pdev);
805 void __iomem *mask_reg = bank->base +
806 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
807 unsigned long flags;
808
809 spin_lock_irqsave(&bank->lock, flags);
810 __raw_writel(bank->context.wake_en, mask_reg);
811 spin_unlock_irqrestore(&bank->lock, flags);
812
813 return 0;
814}
815
816static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
817 .suspend_noirq = omap_mpuio_suspend_noirq,
818 .resume_noirq = omap_mpuio_resume_noirq,
819};
820
821/* use platform_driver for this. */
822static struct platform_driver omap_mpuio_driver = {
823 .driver = {
824 .name = "mpuio",
825 .pm = &omap_mpuio_dev_pm_ops,
826 },
827};
828
829static struct platform_device omap_mpuio_device = {
830 .name = "mpuio",
831 .id = -1,
832 .dev = {
833 .driver = &omap_mpuio_driver.driver,
834 }
835 /* could list the /proc/iomem resources */
836};
837
838static inline void mpuio_init(struct gpio_bank *bank)
839{
840 platform_set_drvdata(&omap_mpuio_device, bank);
841
842 if (platform_driver_register(&omap_mpuio_driver) == 0)
843 (void) platform_device_register(&omap_mpuio_device);
844}
845
846/*---------------------------------------------------------------------*/
847
848static int gpio_input(struct gpio_chip *chip, unsigned offset)
849{
850 struct gpio_bank *bank;
851 unsigned long flags;
852
853 bank = container_of(chip, struct gpio_bank, chip);
854 spin_lock_irqsave(&bank->lock, flags);
855 _set_gpio_direction(bank, offset, 1);
856 spin_unlock_irqrestore(&bank->lock, flags);
857 return 0;
858}
859
860static int gpio_is_input(struct gpio_bank *bank, int mask)
861{
862 void __iomem *reg = bank->base + bank->regs->direction;
863
864 return __raw_readl(reg) & mask;
865}
866
867static int gpio_get(struct gpio_chip *chip, unsigned offset)
868{
869 struct gpio_bank *bank;
870 u32 mask;
871
872 bank = container_of(chip, struct gpio_bank, chip);
873 mask = (1 << offset);
874
875 if (gpio_is_input(bank, mask))
876 return _get_gpio_datain(bank, offset);
877 else
878 return _get_gpio_dataout(bank, offset);
879}
880
881static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
882{
883 struct gpio_bank *bank;
884 unsigned long flags;
885
886 bank = container_of(chip, struct gpio_bank, chip);
887 spin_lock_irqsave(&bank->lock, flags);
888 bank->set_dataout(bank, offset, value);
889 _set_gpio_direction(bank, offset, 0);
890 spin_unlock_irqrestore(&bank->lock, flags);
891 return 0;
892}
893
894static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
895 unsigned debounce)
896{
897 struct gpio_bank *bank;
898 unsigned long flags;
899
900 bank = container_of(chip, struct gpio_bank, chip);
901
902 if (!bank->dbck) {
903 bank->dbck = clk_get(bank->dev, "dbclk");
904 if (IS_ERR(bank->dbck))
905 dev_err(bank->dev, "Could not get gpio dbck\n");
906 }
907
908 spin_lock_irqsave(&bank->lock, flags);
909 _set_gpio_debounce(bank, offset, debounce);
910 spin_unlock_irqrestore(&bank->lock, flags);
911
912 return 0;
913}
914
915static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
916{
917 struct gpio_bank *bank;
918 unsigned long flags;
919
920 bank = container_of(chip, struct gpio_bank, chip);
921 spin_lock_irqsave(&bank->lock, flags);
922 bank->set_dataout(bank, offset, value);
923 spin_unlock_irqrestore(&bank->lock, flags);
924}
925
926static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
927{
928 struct gpio_bank *bank;
929
930 bank = container_of(chip, struct gpio_bank, chip);
931 return bank->irq_base + offset;
932}
933
934/*---------------------------------------------------------------------*/
935
936static void __init omap_gpio_show_rev(struct gpio_bank *bank)
937{
938 static bool called;
939 u32 rev;
940
941 if (called || bank->regs->revision == USHRT_MAX)
942 return;
943
944 rev = __raw_readw(bank->base + bank->regs->revision);
945 pr_info("OMAP GPIO hardware version %d.%d\n",
946 (rev >> 4) & 0x0f, rev & 0x0f);
947
948 called = true;
949}
950
951/* This lock class tells lockdep that GPIO irqs are in a different
952 * category than their parents, so it won't report false recursion.
953 */
954static struct lock_class_key gpio_lock_class;
955
956static void omap_gpio_mod_init(struct gpio_bank *bank)
957{
958 void __iomem *base = bank->base;
959 u32 l = 0xffffffff;
960
961 if (bank->width == 16)
962 l = 0xffff;
963
964 if (bank->is_mpuio) {
965 __raw_writel(l, bank->base + bank->regs->irqenable);
966 return;
967 }
968
969 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
970 _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
971 if (bank->regs->debounce_en)
972 __raw_writel(0, base + bank->regs->debounce_en);
973
974 /* Save OE default value (0xffffffff) in the context */
975 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
976 /* Initialize interface clk ungated, module enabled */
977 if (bank->regs->ctrl)
978 __raw_writel(0, base + bank->regs->ctrl);
979}
980
981static __devinit void
982omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
983 unsigned int num)
984{
985 struct irq_chip_generic *gc;
986 struct irq_chip_type *ct;
987
988 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
989 handle_simple_irq);
990 if (!gc) {
991 dev_err(bank->dev, "Memory alloc failed for gc\n");
992 return;
993 }
994
995 ct = gc->chip_types;
996
997 /* NOTE: No ack required, reading IRQ status clears it. */
998 ct->chip.irq_mask = irq_gc_mask_set_bit;
999 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1000 ct->chip.irq_set_type = gpio_irq_type;
1001
1002 if (bank->regs->wkup_en)
1003 ct->chip.irq_set_wake = gpio_wake_enable,
1004
1005 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1006 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1007 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1008}
1009
1010static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1011{
1012 int j;
1013 static int gpio;
1014
1015 /*
1016 * REVISIT eventually switch from OMAP-specific gpio structs
1017 * over to the generic ones
1018 */
1019 bank->chip.request = omap_gpio_request;
1020 bank->chip.free = omap_gpio_free;
1021 bank->chip.direction_input = gpio_input;
1022 bank->chip.get = gpio_get;
1023 bank->chip.direction_output = gpio_output;
1024 bank->chip.set_debounce = gpio_debounce;
1025 bank->chip.set = gpio_set;
1026 bank->chip.to_irq = gpio_2irq;
1027 if (bank->is_mpuio) {
1028 bank->chip.label = "mpuio";
1029 if (bank->regs->wkup_en)
1030 bank->chip.dev = &omap_mpuio_device.dev;
1031 bank->chip.base = OMAP_MPUIO(0);
1032 } else {
1033 bank->chip.label = "gpio";
1034 bank->chip.base = gpio;
1035 gpio += bank->width;
1036 }
1037 bank->chip.ngpio = bank->width;
1038
1039 gpiochip_add(&bank->chip);
1040
1041 for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1042 irq_set_lockdep_class(j, &gpio_lock_class);
1043 irq_set_chip_data(j, bank);
1044 if (bank->is_mpuio) {
1045 omap_mpuio_alloc_gc(bank, j, bank->width);
1046 } else {
1047 irq_set_chip(j, &gpio_irq_chip);
1048 irq_set_handler(j, handle_simple_irq);
1049 set_irq_flags(j, IRQF_VALID);
1050 }
1051 }
1052 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1053 irq_set_handler_data(bank->irq, bank);
1054}
1055
1056static const struct of_device_id omap_gpio_match[];
1057
1058static int __devinit omap_gpio_probe(struct platform_device *pdev)
1059{
1060 struct device *dev = &pdev->dev;
1061 struct device_node *node = dev->of_node;
1062 const struct of_device_id *match;
1063 struct omap_gpio_platform_data *pdata;
1064 struct resource *res;
1065 struct gpio_bank *bank;
1066 int ret = 0;
1067
1068 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1069
1070 pdata = match ? match->data : dev->platform_data;
1071 if (!pdata)
1072 return -EINVAL;
1073
1074 bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL);
1075 if (!bank) {
1076 dev_err(dev, "Memory alloc failed\n");
1077 return -ENOMEM;
1078 }
1079
1080 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1081 if (unlikely(!res)) {
1082 dev_err(dev, "Invalid IRQ resource\n");
1083 return -ENODEV;
1084 }
1085
1086 bank->irq = res->start;
1087 bank->dev = dev;
1088 bank->dbck_flag = pdata->dbck_flag;
1089 bank->stride = pdata->bank_stride;
1090 bank->width = pdata->bank_width;
1091 bank->is_mpuio = pdata->is_mpuio;
1092 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1093 bank->loses_context = pdata->loses_context;
1094 bank->regs = pdata->regs;
1095#ifdef CONFIG_OF_GPIO
1096 bank->chip.of_node = of_node_get(node);
1097#endif
1098
1099 bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1100 if (bank->irq_base < 0) {
1101 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1102 return -ENODEV;
1103 }
1104
1105 bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
1106 0, &irq_domain_simple_ops, NULL);
1107
1108 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1109 bank->set_dataout = _set_gpio_dataout_reg;
1110 else
1111 bank->set_dataout = _set_gpio_dataout_mask;
1112
1113 spin_lock_init(&bank->lock);
1114
1115 /* Static mapping, never released */
1116 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1117 if (unlikely(!res)) {
1118 dev_err(dev, "Invalid mem resource\n");
1119 return -ENODEV;
1120 }
1121
1122 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1123 pdev->name)) {
1124 dev_err(dev, "Region already claimed\n");
1125 return -EBUSY;
1126 }
1127
1128 bank->base = devm_ioremap(dev, res->start, resource_size(res));
1129 if (!bank->base) {
1130 dev_err(dev, "Could not ioremap\n");
1131 return -ENOMEM;
1132 }
1133
1134 platform_set_drvdata(pdev, bank);
1135
1136 pm_runtime_enable(bank->dev);
1137 pm_runtime_irq_safe(bank->dev);
1138 pm_runtime_get_sync(bank->dev);
1139
1140 if (bank->is_mpuio)
1141 mpuio_init(bank);
1142
1143 omap_gpio_mod_init(bank);
1144 omap_gpio_chip_init(bank);
1145 omap_gpio_show_rev(bank);
1146
1147 if (bank->loses_context)
1148 bank->get_context_loss_count = pdata->get_context_loss_count;
1149
1150 pm_runtime_put(bank->dev);
1151
1152 list_add_tail(&bank->node, &omap_gpio_list);
1153
1154 return ret;
1155}
1156
1157#ifdef CONFIG_ARCH_OMAP2PLUS
1158
1159#if defined(CONFIG_PM_RUNTIME)
1160static void omap_gpio_restore_context(struct gpio_bank *bank);
1161
1162static int omap_gpio_runtime_suspend(struct device *dev)
1163{
1164 struct platform_device *pdev = to_platform_device(dev);
1165 struct gpio_bank *bank = platform_get_drvdata(pdev);
1166 u32 l1 = 0, l2 = 0;
1167 unsigned long flags;
1168 u32 wake_low, wake_hi;
1169
1170 spin_lock_irqsave(&bank->lock, flags);
1171
1172 /*
1173 * Only edges can generate a wakeup event to the PRCM.
1174 *
1175 * Therefore, ensure any wake-up capable GPIOs have
1176 * edge-detection enabled before going idle to ensure a wakeup
1177 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1178 * NDA TRM 25.5.3.1)
1179 *
1180 * The normal values will be restored upon ->runtime_resume()
1181 * by writing back the values saved in bank->context.
1182 */
1183 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1184 if (wake_low)
1185 __raw_writel(wake_low | bank->context.fallingdetect,
1186 bank->base + bank->regs->fallingdetect);
1187 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1188 if (wake_hi)
1189 __raw_writel(wake_hi | bank->context.risingdetect,
1190 bank->base + bank->regs->risingdetect);
1191
1192 if (!bank->enabled_non_wakeup_gpios)
1193 goto update_gpio_context_count;
1194
1195 if (bank->power_mode != OFF_MODE) {
1196 bank->power_mode = 0;
1197 goto update_gpio_context_count;
1198 }
1199 /*
1200 * If going to OFF, remove triggering for all
1201 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1202 * generated. See OMAP2420 Errata item 1.101.
1203 */
1204 bank->saved_datain = __raw_readl(bank->base +
1205 bank->regs->datain);
1206 l1 = bank->context.fallingdetect;
1207 l2 = bank->context.risingdetect;
1208
1209 l1 &= ~bank->enabled_non_wakeup_gpios;
1210 l2 &= ~bank->enabled_non_wakeup_gpios;
1211
1212 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1213 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1214
1215 bank->workaround_enabled = true;
1216
1217update_gpio_context_count:
1218 if (bank->get_context_loss_count)
1219 bank->context_loss_count =
1220 bank->get_context_loss_count(bank->dev);
1221
1222 _gpio_dbck_disable(bank);
1223 spin_unlock_irqrestore(&bank->lock, flags);
1224
1225 return 0;
1226}
1227
1228static int omap_gpio_runtime_resume(struct device *dev)
1229{
1230 struct platform_device *pdev = to_platform_device(dev);
1231 struct gpio_bank *bank = platform_get_drvdata(pdev);
1232 int context_lost_cnt_after;
1233 u32 l = 0, gen, gen0, gen1;
1234 unsigned long flags;
1235
1236 spin_lock_irqsave(&bank->lock, flags);
1237 _gpio_dbck_enable(bank);
1238
1239 /*
1240 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1241 * GPIOs were set to edge trigger also in order to be able to
1242 * generate a PRCM wakeup. Here we restore the
1243 * pre-runtime_suspend() values for edge triggering.
1244 */
1245 __raw_writel(bank->context.fallingdetect,
1246 bank->base + bank->regs->fallingdetect);
1247 __raw_writel(bank->context.risingdetect,
1248 bank->base + bank->regs->risingdetect);
1249
1250 if (bank->get_context_loss_count) {
1251 context_lost_cnt_after =
1252 bank->get_context_loss_count(bank->dev);
1253 if (context_lost_cnt_after != bank->context_loss_count) {
1254 omap_gpio_restore_context(bank);
1255 } else {
1256 spin_unlock_irqrestore(&bank->lock, flags);
1257 return 0;
1258 }
1259 }
1260
1261 if (!bank->workaround_enabled) {
1262 spin_unlock_irqrestore(&bank->lock, flags);
1263 return 0;
1264 }
1265
1266 __raw_writel(bank->context.fallingdetect,
1267 bank->base + bank->regs->fallingdetect);
1268 __raw_writel(bank->context.risingdetect,
1269 bank->base + bank->regs->risingdetect);
1270 l = __raw_readl(bank->base + bank->regs->datain);
1271
1272 /*
1273 * Check if any of the non-wakeup interrupt GPIOs have changed
1274 * state. If so, generate an IRQ by software. This is
1275 * horribly racy, but it's the best we can do to work around
1276 * this silicon bug.
1277 */
1278 l ^= bank->saved_datain;
1279 l &= bank->enabled_non_wakeup_gpios;
1280
1281 /*
1282 * No need to generate IRQs for the rising edge for gpio IRQs
1283 * configured with falling edge only; and vice versa.
1284 */
1285 gen0 = l & bank->context.fallingdetect;
1286 gen0 &= bank->saved_datain;
1287
1288 gen1 = l & bank->context.risingdetect;
1289 gen1 &= ~(bank->saved_datain);
1290
1291 /* FIXME: Consider GPIO IRQs with level detections properly! */
1292 gen = l & (~(bank->context.fallingdetect) &
1293 ~(bank->context.risingdetect));
1294 /* Consider all GPIO IRQs needed to be updated */
1295 gen |= gen0 | gen1;
1296
1297 if (gen) {
1298 u32 old0, old1;
1299
1300 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1301 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1302
1303 if (!bank->regs->irqstatus_raw0) {
1304 __raw_writel(old0 | gen, bank->base +
1305 bank->regs->leveldetect0);
1306 __raw_writel(old1 | gen, bank->base +
1307 bank->regs->leveldetect1);
1308 }
1309
1310 if (bank->regs->irqstatus_raw0) {
1311 __raw_writel(old0 | l, bank->base +
1312 bank->regs->leveldetect0);
1313 __raw_writel(old1 | l, bank->base +
1314 bank->regs->leveldetect1);
1315 }
1316 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1317 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1318 }
1319
1320 bank->workaround_enabled = false;
1321 spin_unlock_irqrestore(&bank->lock, flags);
1322
1323 return 0;
1324}
1325#endif /* CONFIG_PM_RUNTIME */
1326
1327void omap2_gpio_prepare_for_idle(int pwr_mode)
1328{
1329 struct gpio_bank *bank;
1330
1331 list_for_each_entry(bank, &omap_gpio_list, node) {
1332 if (!bank->mod_usage || !bank->loses_context)
1333 continue;
1334
1335 bank->power_mode = pwr_mode;
1336
1337 pm_runtime_put_sync_suspend(bank->dev);
1338 }
1339}
1340
1341void omap2_gpio_resume_after_idle(void)
1342{
1343 struct gpio_bank *bank;
1344
1345 list_for_each_entry(bank, &omap_gpio_list, node) {
1346 if (!bank->mod_usage || !bank->loses_context)
1347 continue;
1348
1349 pm_runtime_get_sync(bank->dev);
1350 }
1351}
1352
1353#if defined(CONFIG_PM_RUNTIME)
1354static void omap_gpio_restore_context(struct gpio_bank *bank)
1355{
1356 __raw_writel(bank->context.wake_en,
1357 bank->base + bank->regs->wkup_en);
1358 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1359 __raw_writel(bank->context.leveldetect0,
1360 bank->base + bank->regs->leveldetect0);
1361 __raw_writel(bank->context.leveldetect1,
1362 bank->base + bank->regs->leveldetect1);
1363 __raw_writel(bank->context.risingdetect,
1364 bank->base + bank->regs->risingdetect);
1365 __raw_writel(bank->context.fallingdetect,
1366 bank->base + bank->regs->fallingdetect);
1367 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1368 __raw_writel(bank->context.dataout,
1369 bank->base + bank->regs->set_dataout);
1370 else
1371 __raw_writel(bank->context.dataout,
1372 bank->base + bank->regs->dataout);
1373 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1374
1375 if (bank->dbck_enable_mask) {
1376 __raw_writel(bank->context.debounce, bank->base +
1377 bank->regs->debounce);
1378 __raw_writel(bank->context.debounce_en,
1379 bank->base + bank->regs->debounce_en);
1380 }
1381
1382 __raw_writel(bank->context.irqenable1,
1383 bank->base + bank->regs->irqenable);
1384 __raw_writel(bank->context.irqenable2,
1385 bank->base + bank->regs->irqenable2);
1386}
1387#endif /* CONFIG_PM_RUNTIME */
1388#else
1389#define omap_gpio_runtime_suspend NULL
1390#define omap_gpio_runtime_resume NULL
1391#endif
1392
1393static const struct dev_pm_ops gpio_pm_ops = {
1394 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1395 NULL)
1396};
1397
1398#if defined(CONFIG_OF)
1399static struct omap_gpio_reg_offs omap2_gpio_regs = {
1400 .revision = OMAP24XX_GPIO_REVISION,
1401 .direction = OMAP24XX_GPIO_OE,
1402 .datain = OMAP24XX_GPIO_DATAIN,
1403 .dataout = OMAP24XX_GPIO_DATAOUT,
1404 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1405 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1406 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1407 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1408 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1409 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1410 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1411 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1412 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1413 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1414 .ctrl = OMAP24XX_GPIO_CTRL,
1415 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1416 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1417 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1418 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1419 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1420};
1421
1422static struct omap_gpio_reg_offs omap4_gpio_regs = {
1423 .revision = OMAP4_GPIO_REVISION,
1424 .direction = OMAP4_GPIO_OE,
1425 .datain = OMAP4_GPIO_DATAIN,
1426 .dataout = OMAP4_GPIO_DATAOUT,
1427 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1428 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1429 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1430 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1431 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1432 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1433 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1434 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1435 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1436 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1437 .ctrl = OMAP4_GPIO_CTRL,
1438 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1439 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1440 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1441 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1442 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1443};
1444
1445static struct omap_gpio_platform_data omap2_pdata = {
1446 .regs = &omap2_gpio_regs,
1447 .bank_width = 32,
1448 .dbck_flag = false,
1449};
1450
1451static struct omap_gpio_platform_data omap3_pdata = {
1452 .regs = &omap2_gpio_regs,
1453 .bank_width = 32,
1454 .dbck_flag = true,
1455};
1456
1457static struct omap_gpio_platform_data omap4_pdata = {
1458 .regs = &omap4_gpio_regs,
1459 .bank_width = 32,
1460 .dbck_flag = true,
1461};
1462
1463static const struct of_device_id omap_gpio_match[] = {
1464 {
1465 .compatible = "ti,omap4-gpio",
1466 .data = &omap4_pdata,
1467 },
1468 {
1469 .compatible = "ti,omap3-gpio",
1470 .data = &omap3_pdata,
1471 },
1472 {
1473 .compatible = "ti,omap2-gpio",
1474 .data = &omap2_pdata,
1475 },
1476 { },
1477};
1478MODULE_DEVICE_TABLE(of, omap_gpio_match);
1479#endif
1480
1481static struct platform_driver omap_gpio_driver = {
1482 .probe = omap_gpio_probe,
1483 .driver = {
1484 .name = "omap_gpio",
1485 .pm = &gpio_pm_ops,
1486 .of_match_table = of_match_ptr(omap_gpio_match),
1487 },
1488};
1489
1490/*
1491 * gpio driver register needs to be done before
1492 * machine_init functions access gpio APIs.
1493 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1494 */
1495static int __init omap_gpio_drv_reg(void)
1496{
1497 return platform_driver_register(&omap_gpio_driver);
1498}
1499postcore_initcall(omap_gpio_drv_reg);
1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/device.h>
23#include <linux/pm_runtime.h>
24#include <linux/pm.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/gpio.h>
28#include <linux/bitops.h>
29#include <linux/platform_data/gpio-omap.h>
30
31#define OFF_MODE 1
32#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
33
34static LIST_HEAD(omap_gpio_list);
35
36struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
47 u32 debounce;
48 u32 debounce_en;
49};
50
51struct gpio_bank {
52 struct list_head node;
53 void __iomem *base;
54 int irq;
55 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
58 u32 saved_datain;
59 u32 level_mask;
60 u32 toggle_mask;
61 raw_spinlock_t lock;
62 raw_spinlock_t wa_lock;
63 struct gpio_chip chip;
64 struct clk *dbck;
65 u32 mod_usage;
66 u32 irq_usage;
67 u32 dbck_enable_mask;
68 bool dbck_enabled;
69 bool is_mpuio;
70 bool dbck_flag;
71 bool loses_context;
72 bool context_valid;
73 int stride;
74 u32 width;
75 int context_loss_count;
76 int power_mode;
77 bool workaround_enabled;
78
79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 int (*get_context_loss_count)(struct device *dev);
81
82 struct omap_gpio_reg_offs *regs;
83};
84
85#define GPIO_MOD_CTRL_BIT BIT(0)
86
87#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88#define LINE_USED(line, offset) (line & (BIT(offset)))
89
90static void omap_gpio_unmask_irq(struct irq_data *d);
91
92static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
93{
94 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
95 return gpiochip_get_data(chip);
96}
97
98static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
99 int is_input)
100{
101 void __iomem *reg = bank->base;
102 u32 l;
103
104 reg += bank->regs->direction;
105 l = readl_relaxed(reg);
106 if (is_input)
107 l |= BIT(gpio);
108 else
109 l &= ~(BIT(gpio));
110 writel_relaxed(l, reg);
111 bank->context.oe = l;
112}
113
114
115/* set data out value using dedicate set/clear register */
116static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
117 int enable)
118{
119 void __iomem *reg = bank->base;
120 u32 l = BIT(offset);
121
122 if (enable) {
123 reg += bank->regs->set_dataout;
124 bank->context.dataout |= l;
125 } else {
126 reg += bank->regs->clr_dataout;
127 bank->context.dataout &= ~l;
128 }
129
130 writel_relaxed(l, reg);
131}
132
133/* set data out value using mask register */
134static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
135 int enable)
136{
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = BIT(offset);
139 u32 l;
140
141 l = readl_relaxed(reg);
142 if (enable)
143 l |= gpio_bit;
144 else
145 l &= ~gpio_bit;
146 writel_relaxed(l, reg);
147 bank->context.dataout = l;
148}
149
150static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
151{
152 void __iomem *reg = bank->base + bank->regs->datain;
153
154 return (readl_relaxed(reg) & (BIT(offset))) != 0;
155}
156
157static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
158{
159 void __iomem *reg = bank->base + bank->regs->dataout;
160
161 return (readl_relaxed(reg) & (BIT(offset))) != 0;
162}
163
164static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165{
166 int l = readl_relaxed(base + reg);
167
168 if (set)
169 l |= mask;
170 else
171 l &= ~mask;
172
173 writel_relaxed(l, base + reg);
174}
175
176static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
177{
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
181
182 writel_relaxed(bank->dbck_enable_mask,
183 bank->base + bank->regs->debounce_en);
184 }
185}
186
187static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
188{
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
190 /*
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
194 */
195 writel_relaxed(0, bank->base + bank->regs->debounce_en);
196
197 clk_disable(bank->dbck);
198 bank->dbck_enabled = false;
199 }
200}
201
202/**
203 * omap2_set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @offset: the gpio number on this @bank
206 * @debounce: debounce time to use
207 *
208 * OMAP's debounce time is in 31us steps
209 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210 * so we need to convert and round up to the closest unit.
211 *
212 * Return: 0 on success, negative error otherwise.
213 */
214static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
215 unsigned debounce)
216{
217 void __iomem *reg;
218 u32 val;
219 u32 l;
220 bool enable = !!debounce;
221
222 if (!bank->dbck_flag)
223 return -ENOTSUPP;
224
225 if (enable) {
226 debounce = DIV_ROUND_UP(debounce, 31) - 1;
227 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
228 return -EINVAL;
229 }
230
231 l = BIT(offset);
232
233 clk_enable(bank->dbck);
234 reg = bank->base + bank->regs->debounce;
235 writel_relaxed(debounce, reg);
236
237 reg = bank->base + bank->regs->debounce_en;
238 val = readl_relaxed(reg);
239
240 if (enable)
241 val |= l;
242 else
243 val &= ~l;
244 bank->dbck_enable_mask = val;
245
246 writel_relaxed(val, reg);
247 clk_disable(bank->dbck);
248 /*
249 * Enable debounce clock per module.
250 * This call is mandatory because in omap_gpio_request() when
251 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
252 * runtime callbck fails to turn on dbck because dbck_enable_mask
253 * used within _gpio_dbck_enable() is still not initialized at
254 * that point. Therefore we have to enable dbck here.
255 */
256 omap_gpio_dbck_enable(bank);
257 if (bank->dbck_enable_mask) {
258 bank->context.debounce = debounce;
259 bank->context.debounce_en = val;
260 }
261
262 return 0;
263}
264
265/**
266 * omap_clear_gpio_debounce - clear debounce settings for a gpio
267 * @bank: the gpio bank we're acting upon
268 * @offset: the gpio number on this @bank
269 *
270 * If a gpio is using debounce, then clear the debounce enable bit and if
271 * this is the only gpio in this bank using debounce, then clear the debounce
272 * time too. The debounce clock will also be disabled when calling this function
273 * if this is the only gpio in the bank using debounce.
274 */
275static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
276{
277 u32 gpio_bit = BIT(offset);
278
279 if (!bank->dbck_flag)
280 return;
281
282 if (!(bank->dbck_enable_mask & gpio_bit))
283 return;
284
285 bank->dbck_enable_mask &= ~gpio_bit;
286 bank->context.debounce_en &= ~gpio_bit;
287 writel_relaxed(bank->context.debounce_en,
288 bank->base + bank->regs->debounce_en);
289
290 if (!bank->dbck_enable_mask) {
291 bank->context.debounce = 0;
292 writel_relaxed(bank->context.debounce, bank->base +
293 bank->regs->debounce);
294 clk_disable(bank->dbck);
295 bank->dbck_enabled = false;
296 }
297}
298
299static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
300 unsigned trigger)
301{
302 void __iomem *base = bank->base;
303 u32 gpio_bit = BIT(gpio);
304
305 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
306 trigger & IRQ_TYPE_LEVEL_LOW);
307 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
308 trigger & IRQ_TYPE_LEVEL_HIGH);
309 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
310 trigger & IRQ_TYPE_EDGE_RISING);
311 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
312 trigger & IRQ_TYPE_EDGE_FALLING);
313
314 bank->context.leveldetect0 =
315 readl_relaxed(bank->base + bank->regs->leveldetect0);
316 bank->context.leveldetect1 =
317 readl_relaxed(bank->base + bank->regs->leveldetect1);
318 bank->context.risingdetect =
319 readl_relaxed(bank->base + bank->regs->risingdetect);
320 bank->context.fallingdetect =
321 readl_relaxed(bank->base + bank->regs->fallingdetect);
322
323 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
324 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
325 bank->context.wake_en =
326 readl_relaxed(bank->base + bank->regs->wkup_en);
327 }
328
329 /* This part needs to be executed always for OMAP{34xx, 44xx} */
330 if (!bank->regs->irqctrl) {
331 /* On omap24xx proceed only when valid GPIO bit is set */
332 if (bank->non_wakeup_gpios) {
333 if (!(bank->non_wakeup_gpios & gpio_bit))
334 goto exit;
335 }
336
337 /*
338 * Log the edge gpio and manually trigger the IRQ
339 * after resume if the input level changes
340 * to avoid irq lost during PER RET/OFF mode
341 * Applies for omap2 non-wakeup gpio and all omap3 gpios
342 */
343 if (trigger & IRQ_TYPE_EDGE_BOTH)
344 bank->enabled_non_wakeup_gpios |= gpio_bit;
345 else
346 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
347 }
348
349exit:
350 bank->level_mask =
351 readl_relaxed(bank->base + bank->regs->leveldetect0) |
352 readl_relaxed(bank->base + bank->regs->leveldetect1);
353}
354
355#ifdef CONFIG_ARCH_OMAP1
356/*
357 * This only applies to chips that can't do both rising and falling edge
358 * detection at once. For all other chips, this function is a noop.
359 */
360static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
361{
362 void __iomem *reg = bank->base;
363 u32 l = 0;
364
365 if (!bank->regs->irqctrl)
366 return;
367
368 reg += bank->regs->irqctrl;
369
370 l = readl_relaxed(reg);
371 if ((l >> gpio) & 1)
372 l &= ~(BIT(gpio));
373 else
374 l |= BIT(gpio);
375
376 writel_relaxed(l, reg);
377}
378#else
379static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
380#endif
381
382static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
383 unsigned trigger)
384{
385 void __iomem *reg = bank->base;
386 void __iomem *base = bank->base;
387 u32 l = 0;
388
389 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
390 omap_set_gpio_trigger(bank, gpio, trigger);
391 } else if (bank->regs->irqctrl) {
392 reg += bank->regs->irqctrl;
393
394 l = readl_relaxed(reg);
395 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
396 bank->toggle_mask |= BIT(gpio);
397 if (trigger & IRQ_TYPE_EDGE_RISING)
398 l |= BIT(gpio);
399 else if (trigger & IRQ_TYPE_EDGE_FALLING)
400 l &= ~(BIT(gpio));
401 else
402 return -EINVAL;
403
404 writel_relaxed(l, reg);
405 } else if (bank->regs->edgectrl1) {
406 if (gpio & 0x08)
407 reg += bank->regs->edgectrl2;
408 else
409 reg += bank->regs->edgectrl1;
410
411 gpio &= 0x07;
412 l = readl_relaxed(reg);
413 l &= ~(3 << (gpio << 1));
414 if (trigger & IRQ_TYPE_EDGE_RISING)
415 l |= 2 << (gpio << 1);
416 if (trigger & IRQ_TYPE_EDGE_FALLING)
417 l |= BIT(gpio << 1);
418
419 /* Enable wake-up during idle for dynamic tick */
420 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
421 bank->context.wake_en =
422 readl_relaxed(bank->base + bank->regs->wkup_en);
423 writel_relaxed(l, reg);
424 }
425 return 0;
426}
427
428static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
429{
430 if (bank->regs->pinctrl) {
431 void __iomem *reg = bank->base + bank->regs->pinctrl;
432
433 /* Claim the pin for MPU */
434 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
435 }
436
437 if (bank->regs->ctrl && !BANK_USED(bank)) {
438 void __iomem *reg = bank->base + bank->regs->ctrl;
439 u32 ctrl;
440
441 ctrl = readl_relaxed(reg);
442 /* Module is enabled, clocks are not gated */
443 ctrl &= ~GPIO_MOD_CTRL_BIT;
444 writel_relaxed(ctrl, reg);
445 bank->context.ctrl = ctrl;
446 }
447}
448
449static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
450{
451 void __iomem *base = bank->base;
452
453 if (bank->regs->wkup_en &&
454 !LINE_USED(bank->mod_usage, offset) &&
455 !LINE_USED(bank->irq_usage, offset)) {
456 /* Disable wake-up during idle for dynamic tick */
457 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
458 bank->context.wake_en =
459 readl_relaxed(bank->base + bank->regs->wkup_en);
460 }
461
462 if (bank->regs->ctrl && !BANK_USED(bank)) {
463 void __iomem *reg = bank->base + bank->regs->ctrl;
464 u32 ctrl;
465
466 ctrl = readl_relaxed(reg);
467 /* Module is disabled, clocks are gated */
468 ctrl |= GPIO_MOD_CTRL_BIT;
469 writel_relaxed(ctrl, reg);
470 bank->context.ctrl = ctrl;
471 }
472}
473
474static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
475{
476 void __iomem *reg = bank->base + bank->regs->direction;
477
478 return readl_relaxed(reg) & BIT(offset);
479}
480
481static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
482{
483 if (!LINE_USED(bank->mod_usage, offset)) {
484 omap_enable_gpio_module(bank, offset);
485 omap_set_gpio_direction(bank, offset, 1);
486 }
487 bank->irq_usage |= BIT(offset);
488}
489
490static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
491{
492 struct gpio_bank *bank = omap_irq_data_get_bank(d);
493 int retval;
494 unsigned long flags;
495 unsigned offset = d->hwirq;
496
497 if (type & ~IRQ_TYPE_SENSE_MASK)
498 return -EINVAL;
499
500 if (!bank->regs->leveldetect0 &&
501 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
502 return -EINVAL;
503
504 raw_spin_lock_irqsave(&bank->lock, flags);
505 retval = omap_set_gpio_triggering(bank, offset, type);
506 if (retval) {
507 raw_spin_unlock_irqrestore(&bank->lock, flags);
508 goto error;
509 }
510 omap_gpio_init_irq(bank, offset);
511 if (!omap_gpio_is_input(bank, offset)) {
512 raw_spin_unlock_irqrestore(&bank->lock, flags);
513 retval = -EINVAL;
514 goto error;
515 }
516 raw_spin_unlock_irqrestore(&bank->lock, flags);
517
518 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
519 irq_set_handler_locked(d, handle_level_irq);
520 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
521 /*
522 * Edge IRQs are already cleared/acked in irq_handler and
523 * not need to be masked, as result handle_edge_irq()
524 * logic is excessed here and may cause lose of interrupts.
525 * So just use handle_simple_irq.
526 */
527 irq_set_handler_locked(d, handle_simple_irq);
528
529 return 0;
530
531error:
532 return retval;
533}
534
535static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
536{
537 void __iomem *reg = bank->base;
538
539 reg += bank->regs->irqstatus;
540 writel_relaxed(gpio_mask, reg);
541
542 /* Workaround for clearing DSP GPIO interrupts to allow retention */
543 if (bank->regs->irqstatus2) {
544 reg = bank->base + bank->regs->irqstatus2;
545 writel_relaxed(gpio_mask, reg);
546 }
547
548 /* Flush posted write for the irq status to avoid spurious interrupts */
549 readl_relaxed(reg);
550}
551
552static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
553 unsigned offset)
554{
555 omap_clear_gpio_irqbank(bank, BIT(offset));
556}
557
558static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
559{
560 void __iomem *reg = bank->base;
561 u32 l;
562 u32 mask = (BIT(bank->width)) - 1;
563
564 reg += bank->regs->irqenable;
565 l = readl_relaxed(reg);
566 if (bank->regs->irqenable_inv)
567 l = ~l;
568 l &= mask;
569 return l;
570}
571
572static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
573{
574 void __iomem *reg = bank->base;
575 u32 l;
576
577 if (bank->regs->set_irqenable) {
578 reg += bank->regs->set_irqenable;
579 l = gpio_mask;
580 bank->context.irqenable1 |= gpio_mask;
581 } else {
582 reg += bank->regs->irqenable;
583 l = readl_relaxed(reg);
584 if (bank->regs->irqenable_inv)
585 l &= ~gpio_mask;
586 else
587 l |= gpio_mask;
588 bank->context.irqenable1 = l;
589 }
590
591 writel_relaxed(l, reg);
592}
593
594static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
595{
596 void __iomem *reg = bank->base;
597 u32 l;
598
599 if (bank->regs->clr_irqenable) {
600 reg += bank->regs->clr_irqenable;
601 l = gpio_mask;
602 bank->context.irqenable1 &= ~gpio_mask;
603 } else {
604 reg += bank->regs->irqenable;
605 l = readl_relaxed(reg);
606 if (bank->regs->irqenable_inv)
607 l |= gpio_mask;
608 else
609 l &= ~gpio_mask;
610 bank->context.irqenable1 = l;
611 }
612
613 writel_relaxed(l, reg);
614}
615
616static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
617 unsigned offset, int enable)
618{
619 if (enable)
620 omap_enable_gpio_irqbank(bank, BIT(offset));
621 else
622 omap_disable_gpio_irqbank(bank, BIT(offset));
623}
624
625/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
626static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
627{
628 struct gpio_bank *bank = omap_irq_data_get_bank(d);
629
630 return irq_set_irq_wake(bank->irq, enable);
631}
632
633static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
634{
635 struct gpio_bank *bank = gpiochip_get_data(chip);
636 unsigned long flags;
637
638 /*
639 * If this is the first gpio_request for the bank,
640 * enable the bank module.
641 */
642 if (!BANK_USED(bank))
643 pm_runtime_get_sync(chip->parent);
644
645 raw_spin_lock_irqsave(&bank->lock, flags);
646 omap_enable_gpio_module(bank, offset);
647 bank->mod_usage |= BIT(offset);
648 raw_spin_unlock_irqrestore(&bank->lock, flags);
649
650 return 0;
651}
652
653static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
654{
655 struct gpio_bank *bank = gpiochip_get_data(chip);
656 unsigned long flags;
657
658 raw_spin_lock_irqsave(&bank->lock, flags);
659 bank->mod_usage &= ~(BIT(offset));
660 if (!LINE_USED(bank->irq_usage, offset)) {
661 omap_set_gpio_direction(bank, offset, 1);
662 omap_clear_gpio_debounce(bank, offset);
663 }
664 omap_disable_gpio_module(bank, offset);
665 raw_spin_unlock_irqrestore(&bank->lock, flags);
666
667 /*
668 * If this is the last gpio to be freed in the bank,
669 * disable the bank module.
670 */
671 if (!BANK_USED(bank))
672 pm_runtime_put(chip->parent);
673}
674
675/*
676 * We need to unmask the GPIO bank interrupt as soon as possible to
677 * avoid missing GPIO interrupts for other lines in the bank.
678 * Then we need to mask-read-clear-unmask the triggered GPIO lines
679 * in the bank to avoid missing nested interrupts for a GPIO line.
680 * If we wait to unmask individual GPIO lines in the bank after the
681 * line's interrupt handler has been run, we may miss some nested
682 * interrupts.
683 */
684static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
685{
686 void __iomem *isr_reg = NULL;
687 u32 enabled, isr, level_mask;
688 unsigned int bit;
689 struct gpio_bank *bank = gpiobank;
690 unsigned long wa_lock_flags;
691 unsigned long lock_flags;
692
693 isr_reg = bank->base + bank->regs->irqstatus;
694 if (WARN_ON(!isr_reg))
695 goto exit;
696
697 pm_runtime_get_sync(bank->chip.parent);
698
699 while (1) {
700 raw_spin_lock_irqsave(&bank->lock, lock_flags);
701
702 enabled = omap_get_gpio_irqbank_mask(bank);
703 isr = readl_relaxed(isr_reg) & enabled;
704
705 if (bank->level_mask)
706 level_mask = bank->level_mask & enabled;
707 else
708 level_mask = 0;
709
710 /* clear edge sensitive interrupts before handler(s) are
711 called so that we don't miss any interrupt occurred while
712 executing them */
713 if (isr & ~level_mask)
714 omap_clear_gpio_irqbank(bank, isr & ~level_mask);
715
716 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
717
718 if (!isr)
719 break;
720
721 while (isr) {
722 bit = __ffs(isr);
723 isr &= ~(BIT(bit));
724
725 raw_spin_lock_irqsave(&bank->lock, lock_flags);
726 /*
727 * Some chips can't respond to both rising and falling
728 * at the same time. If this irq was requested with
729 * both flags, we need to flip the ICR data for the IRQ
730 * to respond to the IRQ for the opposite direction.
731 * This will be indicated in the bank toggle_mask.
732 */
733 if (bank->toggle_mask & (BIT(bit)))
734 omap_toggle_gpio_edge_triggering(bank, bit);
735
736 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
737
738 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
739
740 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
741 bit));
742
743 raw_spin_unlock_irqrestore(&bank->wa_lock,
744 wa_lock_flags);
745 }
746 }
747exit:
748 pm_runtime_put(bank->chip.parent);
749 return IRQ_HANDLED;
750}
751
752static unsigned int omap_gpio_irq_startup(struct irq_data *d)
753{
754 struct gpio_bank *bank = omap_irq_data_get_bank(d);
755 unsigned long flags;
756 unsigned offset = d->hwirq;
757
758 raw_spin_lock_irqsave(&bank->lock, flags);
759
760 if (!LINE_USED(bank->mod_usage, offset))
761 omap_set_gpio_direction(bank, offset, 1);
762 else if (!omap_gpio_is_input(bank, offset))
763 goto err;
764 omap_enable_gpio_module(bank, offset);
765 bank->irq_usage |= BIT(offset);
766
767 raw_spin_unlock_irqrestore(&bank->lock, flags);
768 omap_gpio_unmask_irq(d);
769
770 return 0;
771err:
772 raw_spin_unlock_irqrestore(&bank->lock, flags);
773 return -EINVAL;
774}
775
776static void omap_gpio_irq_shutdown(struct irq_data *d)
777{
778 struct gpio_bank *bank = omap_irq_data_get_bank(d);
779 unsigned long flags;
780 unsigned offset = d->hwirq;
781
782 raw_spin_lock_irqsave(&bank->lock, flags);
783 bank->irq_usage &= ~(BIT(offset));
784 omap_set_gpio_irqenable(bank, offset, 0);
785 omap_clear_gpio_irqstatus(bank, offset);
786 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
787 if (!LINE_USED(bank->mod_usage, offset))
788 omap_clear_gpio_debounce(bank, offset);
789 omap_disable_gpio_module(bank, offset);
790 raw_spin_unlock_irqrestore(&bank->lock, flags);
791}
792
793static void omap_gpio_irq_bus_lock(struct irq_data *data)
794{
795 struct gpio_bank *bank = omap_irq_data_get_bank(data);
796
797 if (!BANK_USED(bank))
798 pm_runtime_get_sync(bank->chip.parent);
799}
800
801static void gpio_irq_bus_sync_unlock(struct irq_data *data)
802{
803 struct gpio_bank *bank = omap_irq_data_get_bank(data);
804
805 /*
806 * If this is the last IRQ to be freed in the bank,
807 * disable the bank module.
808 */
809 if (!BANK_USED(bank))
810 pm_runtime_put(bank->chip.parent);
811}
812
813static void omap_gpio_ack_irq(struct irq_data *d)
814{
815 struct gpio_bank *bank = omap_irq_data_get_bank(d);
816 unsigned offset = d->hwirq;
817
818 omap_clear_gpio_irqstatus(bank, offset);
819}
820
821static void omap_gpio_mask_irq(struct irq_data *d)
822{
823 struct gpio_bank *bank = omap_irq_data_get_bank(d);
824 unsigned offset = d->hwirq;
825 unsigned long flags;
826
827 raw_spin_lock_irqsave(&bank->lock, flags);
828 omap_set_gpio_irqenable(bank, offset, 0);
829 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
830 raw_spin_unlock_irqrestore(&bank->lock, flags);
831}
832
833static void omap_gpio_unmask_irq(struct irq_data *d)
834{
835 struct gpio_bank *bank = omap_irq_data_get_bank(d);
836 unsigned offset = d->hwirq;
837 u32 trigger = irqd_get_trigger_type(d);
838 unsigned long flags;
839
840 raw_spin_lock_irqsave(&bank->lock, flags);
841 if (trigger)
842 omap_set_gpio_triggering(bank, offset, trigger);
843
844 /* For level-triggered GPIOs, the clearing must be done after
845 * the HW source is cleared, thus after the handler has run */
846 if (bank->level_mask & BIT(offset)) {
847 omap_set_gpio_irqenable(bank, offset, 0);
848 omap_clear_gpio_irqstatus(bank, offset);
849 }
850
851 omap_set_gpio_irqenable(bank, offset, 1);
852 raw_spin_unlock_irqrestore(&bank->lock, flags);
853}
854
855/*---------------------------------------------------------------------*/
856
857static int omap_mpuio_suspend_noirq(struct device *dev)
858{
859 struct platform_device *pdev = to_platform_device(dev);
860 struct gpio_bank *bank = platform_get_drvdata(pdev);
861 void __iomem *mask_reg = bank->base +
862 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
863 unsigned long flags;
864
865 raw_spin_lock_irqsave(&bank->lock, flags);
866 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
867 raw_spin_unlock_irqrestore(&bank->lock, flags);
868
869 return 0;
870}
871
872static int omap_mpuio_resume_noirq(struct device *dev)
873{
874 struct platform_device *pdev = to_platform_device(dev);
875 struct gpio_bank *bank = platform_get_drvdata(pdev);
876 void __iomem *mask_reg = bank->base +
877 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
878 unsigned long flags;
879
880 raw_spin_lock_irqsave(&bank->lock, flags);
881 writel_relaxed(bank->context.wake_en, mask_reg);
882 raw_spin_unlock_irqrestore(&bank->lock, flags);
883
884 return 0;
885}
886
887static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
888 .suspend_noirq = omap_mpuio_suspend_noirq,
889 .resume_noirq = omap_mpuio_resume_noirq,
890};
891
892/* use platform_driver for this. */
893static struct platform_driver omap_mpuio_driver = {
894 .driver = {
895 .name = "mpuio",
896 .pm = &omap_mpuio_dev_pm_ops,
897 },
898};
899
900static struct platform_device omap_mpuio_device = {
901 .name = "mpuio",
902 .id = -1,
903 .dev = {
904 .driver = &omap_mpuio_driver.driver,
905 }
906 /* could list the /proc/iomem resources */
907};
908
909static inline void omap_mpuio_init(struct gpio_bank *bank)
910{
911 platform_set_drvdata(&omap_mpuio_device, bank);
912
913 if (platform_driver_register(&omap_mpuio_driver) == 0)
914 (void) platform_device_register(&omap_mpuio_device);
915}
916
917/*---------------------------------------------------------------------*/
918
919static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
920{
921 struct gpio_bank *bank;
922 unsigned long flags;
923 void __iomem *reg;
924 int dir;
925
926 bank = gpiochip_get_data(chip);
927 reg = bank->base + bank->regs->direction;
928 raw_spin_lock_irqsave(&bank->lock, flags);
929 dir = !!(readl_relaxed(reg) & BIT(offset));
930 raw_spin_unlock_irqrestore(&bank->lock, flags);
931 return dir;
932}
933
934static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
935{
936 struct gpio_bank *bank;
937 unsigned long flags;
938
939 bank = gpiochip_get_data(chip);
940 raw_spin_lock_irqsave(&bank->lock, flags);
941 omap_set_gpio_direction(bank, offset, 1);
942 raw_spin_unlock_irqrestore(&bank->lock, flags);
943 return 0;
944}
945
946static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
947{
948 struct gpio_bank *bank;
949
950 bank = gpiochip_get_data(chip);
951
952 if (omap_gpio_is_input(bank, offset))
953 return omap_get_gpio_datain(bank, offset);
954 else
955 return omap_get_gpio_dataout(bank, offset);
956}
957
958static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
959{
960 struct gpio_bank *bank;
961 unsigned long flags;
962
963 bank = gpiochip_get_data(chip);
964 raw_spin_lock_irqsave(&bank->lock, flags);
965 bank->set_dataout(bank, offset, value);
966 omap_set_gpio_direction(bank, offset, 0);
967 raw_spin_unlock_irqrestore(&bank->lock, flags);
968 return 0;
969}
970
971static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
972 unsigned debounce)
973{
974 struct gpio_bank *bank;
975 unsigned long flags;
976 int ret;
977
978 bank = gpiochip_get_data(chip);
979
980 raw_spin_lock_irqsave(&bank->lock, flags);
981 ret = omap2_set_gpio_debounce(bank, offset, debounce);
982 raw_spin_unlock_irqrestore(&bank->lock, flags);
983
984 if (ret)
985 dev_info(chip->parent,
986 "Could not set line %u debounce to %u microseconds (%d)",
987 offset, debounce, ret);
988
989 return ret;
990}
991
992static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
993 unsigned long config)
994{
995 u32 debounce;
996
997 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
998 return -ENOTSUPP;
999
1000 debounce = pinconf_to_config_argument(config);
1001 return omap_gpio_debounce(chip, offset, debounce);
1002}
1003
1004static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1005{
1006 struct gpio_bank *bank;
1007 unsigned long flags;
1008
1009 bank = gpiochip_get_data(chip);
1010 raw_spin_lock_irqsave(&bank->lock, flags);
1011 bank->set_dataout(bank, offset, value);
1012 raw_spin_unlock_irqrestore(&bank->lock, flags);
1013}
1014
1015/*---------------------------------------------------------------------*/
1016
1017static void omap_gpio_show_rev(struct gpio_bank *bank)
1018{
1019 static bool called;
1020 u32 rev;
1021
1022 if (called || bank->regs->revision == USHRT_MAX)
1023 return;
1024
1025 rev = readw_relaxed(bank->base + bank->regs->revision);
1026 pr_info("OMAP GPIO hardware version %d.%d\n",
1027 (rev >> 4) & 0x0f, rev & 0x0f);
1028
1029 called = true;
1030}
1031
1032static void omap_gpio_mod_init(struct gpio_bank *bank)
1033{
1034 void __iomem *base = bank->base;
1035 u32 l = 0xffffffff;
1036
1037 if (bank->width == 16)
1038 l = 0xffff;
1039
1040 if (bank->is_mpuio) {
1041 writel_relaxed(l, bank->base + bank->regs->irqenable);
1042 return;
1043 }
1044
1045 omap_gpio_rmw(base, bank->regs->irqenable, l,
1046 bank->regs->irqenable_inv);
1047 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1048 !bank->regs->irqenable_inv);
1049 if (bank->regs->debounce_en)
1050 writel_relaxed(0, base + bank->regs->debounce_en);
1051
1052 /* Save OE default value (0xffffffff) in the context */
1053 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1054 /* Initialize interface clk ungated, module enabled */
1055 if (bank->regs->ctrl)
1056 writel_relaxed(0, base + bank->regs->ctrl);
1057}
1058
1059static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1060{
1061 struct gpio_irq_chip *irq;
1062 static int gpio;
1063 const char *label;
1064 int irq_base = 0;
1065 int ret;
1066
1067 /*
1068 * REVISIT eventually switch from OMAP-specific gpio structs
1069 * over to the generic ones
1070 */
1071 bank->chip.request = omap_gpio_request;
1072 bank->chip.free = omap_gpio_free;
1073 bank->chip.get_direction = omap_gpio_get_direction;
1074 bank->chip.direction_input = omap_gpio_input;
1075 bank->chip.get = omap_gpio_get;
1076 bank->chip.direction_output = omap_gpio_output;
1077 bank->chip.set_config = omap_gpio_set_config;
1078 bank->chip.set = omap_gpio_set;
1079 if (bank->is_mpuio) {
1080 bank->chip.label = "mpuio";
1081 if (bank->regs->wkup_en)
1082 bank->chip.parent = &omap_mpuio_device.dev;
1083 bank->chip.base = OMAP_MPUIO(0);
1084 } else {
1085 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1086 gpio, gpio + bank->width - 1);
1087 if (!label)
1088 return -ENOMEM;
1089 bank->chip.label = label;
1090 bank->chip.base = gpio;
1091 }
1092 bank->chip.ngpio = bank->width;
1093
1094#ifdef CONFIG_ARCH_OMAP1
1095 /*
1096 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1097 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1098 */
1099 irq_base = devm_irq_alloc_descs(bank->chip.parent,
1100 -1, 0, bank->width, 0);
1101 if (irq_base < 0) {
1102 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1103 return -ENODEV;
1104 }
1105#endif
1106
1107 /* MPUIO is a bit different, reading IRQ status clears it */
1108 if (bank->is_mpuio) {
1109 irqc->irq_ack = dummy_irq_chip.irq_ack;
1110 if (!bank->regs->wkup_en)
1111 irqc->irq_set_wake = NULL;
1112 }
1113
1114 irq = &bank->chip.irq;
1115 irq->chip = irqc;
1116 irq->handler = handle_bad_irq;
1117 irq->default_type = IRQ_TYPE_NONE;
1118 irq->num_parents = 1;
1119 irq->parents = &bank->irq;
1120 irq->first = irq_base;
1121
1122 ret = gpiochip_add_data(&bank->chip, bank);
1123 if (ret) {
1124 dev_err(bank->chip.parent,
1125 "Could not register gpio chip %d\n", ret);
1126 return ret;
1127 }
1128
1129 ret = devm_request_irq(bank->chip.parent, bank->irq,
1130 omap_gpio_irq_handler,
1131 0, dev_name(bank->chip.parent), bank);
1132 if (ret)
1133 gpiochip_remove(&bank->chip);
1134
1135 if (!bank->is_mpuio)
1136 gpio += bank->width;
1137
1138 return ret;
1139}
1140
1141static const struct of_device_id omap_gpio_match[];
1142
1143static int omap_gpio_probe(struct platform_device *pdev)
1144{
1145 struct device *dev = &pdev->dev;
1146 struct device_node *node = dev->of_node;
1147 const struct of_device_id *match;
1148 const struct omap_gpio_platform_data *pdata;
1149 struct resource *res;
1150 struct gpio_bank *bank;
1151 struct irq_chip *irqc;
1152 int ret;
1153
1154 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1155
1156 pdata = match ? match->data : dev_get_platdata(dev);
1157 if (!pdata)
1158 return -EINVAL;
1159
1160 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1161 if (!bank)
1162 return -ENOMEM;
1163
1164 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1165 if (!irqc)
1166 return -ENOMEM;
1167
1168 irqc->irq_startup = omap_gpio_irq_startup,
1169 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1170 irqc->irq_ack = omap_gpio_ack_irq,
1171 irqc->irq_mask = omap_gpio_mask_irq,
1172 irqc->irq_unmask = omap_gpio_unmask_irq,
1173 irqc->irq_set_type = omap_gpio_irq_type,
1174 irqc->irq_set_wake = omap_gpio_wake_enable,
1175 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1176 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1177 irqc->name = dev_name(&pdev->dev);
1178 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1179
1180 bank->irq = platform_get_irq(pdev, 0);
1181 if (bank->irq <= 0) {
1182 if (!bank->irq)
1183 bank->irq = -ENXIO;
1184 if (bank->irq != -EPROBE_DEFER)
1185 dev_err(dev,
1186 "can't get irq resource ret=%d\n", bank->irq);
1187 return bank->irq;
1188 }
1189
1190 bank->chip.parent = dev;
1191 bank->chip.owner = THIS_MODULE;
1192 bank->dbck_flag = pdata->dbck_flag;
1193 bank->stride = pdata->bank_stride;
1194 bank->width = pdata->bank_width;
1195 bank->is_mpuio = pdata->is_mpuio;
1196 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1197 bank->regs = pdata->regs;
1198#ifdef CONFIG_OF_GPIO
1199 bank->chip.of_node = of_node_get(node);
1200#endif
1201 if (node) {
1202 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1203 bank->loses_context = true;
1204 } else {
1205 bank->loses_context = pdata->loses_context;
1206
1207 if (bank->loses_context)
1208 bank->get_context_loss_count =
1209 pdata->get_context_loss_count;
1210 }
1211
1212 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1213 bank->set_dataout = omap_set_gpio_dataout_reg;
1214 else
1215 bank->set_dataout = omap_set_gpio_dataout_mask;
1216
1217 raw_spin_lock_init(&bank->lock);
1218 raw_spin_lock_init(&bank->wa_lock);
1219
1220 /* Static mapping, never released */
1221 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1222 bank->base = devm_ioremap_resource(dev, res);
1223 if (IS_ERR(bank->base)) {
1224 return PTR_ERR(bank->base);
1225 }
1226
1227 if (bank->dbck_flag) {
1228 bank->dbck = devm_clk_get(dev, "dbclk");
1229 if (IS_ERR(bank->dbck)) {
1230 dev_err(dev,
1231 "Could not get gpio dbck. Disable debounce\n");
1232 bank->dbck_flag = false;
1233 } else {
1234 clk_prepare(bank->dbck);
1235 }
1236 }
1237
1238 platform_set_drvdata(pdev, bank);
1239
1240 pm_runtime_enable(dev);
1241 pm_runtime_irq_safe(dev);
1242 pm_runtime_get_sync(dev);
1243
1244 if (bank->is_mpuio)
1245 omap_mpuio_init(bank);
1246
1247 omap_gpio_mod_init(bank);
1248
1249 ret = omap_gpio_chip_init(bank, irqc);
1250 if (ret) {
1251 pm_runtime_put_sync(dev);
1252 pm_runtime_disable(dev);
1253 if (bank->dbck_flag)
1254 clk_unprepare(bank->dbck);
1255 return ret;
1256 }
1257
1258 omap_gpio_show_rev(bank);
1259
1260 pm_runtime_put(dev);
1261
1262 list_add_tail(&bank->node, &omap_gpio_list);
1263
1264 return 0;
1265}
1266
1267static int omap_gpio_remove(struct platform_device *pdev)
1268{
1269 struct gpio_bank *bank = platform_get_drvdata(pdev);
1270
1271 list_del(&bank->node);
1272 gpiochip_remove(&bank->chip);
1273 pm_runtime_disable(&pdev->dev);
1274 if (bank->dbck_flag)
1275 clk_unprepare(bank->dbck);
1276
1277 return 0;
1278}
1279
1280#ifdef CONFIG_ARCH_OMAP2PLUS
1281
1282#if defined(CONFIG_PM)
1283static void omap_gpio_restore_context(struct gpio_bank *bank);
1284
1285static int omap_gpio_runtime_suspend(struct device *dev)
1286{
1287 struct platform_device *pdev = to_platform_device(dev);
1288 struct gpio_bank *bank = platform_get_drvdata(pdev);
1289 u32 l1 = 0, l2 = 0;
1290 unsigned long flags;
1291 u32 wake_low, wake_hi;
1292
1293 raw_spin_lock_irqsave(&bank->lock, flags);
1294
1295 /*
1296 * Only edges can generate a wakeup event to the PRCM.
1297 *
1298 * Therefore, ensure any wake-up capable GPIOs have
1299 * edge-detection enabled before going idle to ensure a wakeup
1300 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1301 * NDA TRM 25.5.3.1)
1302 *
1303 * The normal values will be restored upon ->runtime_resume()
1304 * by writing back the values saved in bank->context.
1305 */
1306 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1307 if (wake_low)
1308 writel_relaxed(wake_low | bank->context.fallingdetect,
1309 bank->base + bank->regs->fallingdetect);
1310 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1311 if (wake_hi)
1312 writel_relaxed(wake_hi | bank->context.risingdetect,
1313 bank->base + bank->regs->risingdetect);
1314
1315 if (!bank->enabled_non_wakeup_gpios)
1316 goto update_gpio_context_count;
1317
1318 if (bank->power_mode != OFF_MODE) {
1319 bank->power_mode = 0;
1320 goto update_gpio_context_count;
1321 }
1322 /*
1323 * If going to OFF, remove triggering for all
1324 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1325 * generated. See OMAP2420 Errata item 1.101.
1326 */
1327 bank->saved_datain = readl_relaxed(bank->base +
1328 bank->regs->datain);
1329 l1 = bank->context.fallingdetect;
1330 l2 = bank->context.risingdetect;
1331
1332 l1 &= ~bank->enabled_non_wakeup_gpios;
1333 l2 &= ~bank->enabled_non_wakeup_gpios;
1334
1335 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1336 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1337
1338 bank->workaround_enabled = true;
1339
1340update_gpio_context_count:
1341 if (bank->get_context_loss_count)
1342 bank->context_loss_count =
1343 bank->get_context_loss_count(dev);
1344
1345 omap_gpio_dbck_disable(bank);
1346 raw_spin_unlock_irqrestore(&bank->lock, flags);
1347
1348 return 0;
1349}
1350
1351static void omap_gpio_init_context(struct gpio_bank *p);
1352
1353static int omap_gpio_runtime_resume(struct device *dev)
1354{
1355 struct platform_device *pdev = to_platform_device(dev);
1356 struct gpio_bank *bank = platform_get_drvdata(pdev);
1357 u32 l = 0, gen, gen0, gen1;
1358 unsigned long flags;
1359 int c;
1360
1361 raw_spin_lock_irqsave(&bank->lock, flags);
1362
1363 /*
1364 * On the first resume during the probe, the context has not
1365 * been initialised and so initialise it now. Also initialise
1366 * the context loss count.
1367 */
1368 if (bank->loses_context && !bank->context_valid) {
1369 omap_gpio_init_context(bank);
1370
1371 if (bank->get_context_loss_count)
1372 bank->context_loss_count =
1373 bank->get_context_loss_count(dev);
1374 }
1375
1376 omap_gpio_dbck_enable(bank);
1377
1378 /*
1379 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1380 * GPIOs were set to edge trigger also in order to be able to
1381 * generate a PRCM wakeup. Here we restore the
1382 * pre-runtime_suspend() values for edge triggering.
1383 */
1384 writel_relaxed(bank->context.fallingdetect,
1385 bank->base + bank->regs->fallingdetect);
1386 writel_relaxed(bank->context.risingdetect,
1387 bank->base + bank->regs->risingdetect);
1388
1389 if (bank->loses_context) {
1390 if (!bank->get_context_loss_count) {
1391 omap_gpio_restore_context(bank);
1392 } else {
1393 c = bank->get_context_loss_count(dev);
1394 if (c != bank->context_loss_count) {
1395 omap_gpio_restore_context(bank);
1396 } else {
1397 raw_spin_unlock_irqrestore(&bank->lock, flags);
1398 return 0;
1399 }
1400 }
1401 }
1402
1403 if (!bank->workaround_enabled) {
1404 raw_spin_unlock_irqrestore(&bank->lock, flags);
1405 return 0;
1406 }
1407
1408 l = readl_relaxed(bank->base + bank->regs->datain);
1409
1410 /*
1411 * Check if any of the non-wakeup interrupt GPIOs have changed
1412 * state. If so, generate an IRQ by software. This is
1413 * horribly racy, but it's the best we can do to work around
1414 * this silicon bug.
1415 */
1416 l ^= bank->saved_datain;
1417 l &= bank->enabled_non_wakeup_gpios;
1418
1419 /*
1420 * No need to generate IRQs for the rising edge for gpio IRQs
1421 * configured with falling edge only; and vice versa.
1422 */
1423 gen0 = l & bank->context.fallingdetect;
1424 gen0 &= bank->saved_datain;
1425
1426 gen1 = l & bank->context.risingdetect;
1427 gen1 &= ~(bank->saved_datain);
1428
1429 /* FIXME: Consider GPIO IRQs with level detections properly! */
1430 gen = l & (~(bank->context.fallingdetect) &
1431 ~(bank->context.risingdetect));
1432 /* Consider all GPIO IRQs needed to be updated */
1433 gen |= gen0 | gen1;
1434
1435 if (gen) {
1436 u32 old0, old1;
1437
1438 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1439 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1440
1441 if (!bank->regs->irqstatus_raw0) {
1442 writel_relaxed(old0 | gen, bank->base +
1443 bank->regs->leveldetect0);
1444 writel_relaxed(old1 | gen, bank->base +
1445 bank->regs->leveldetect1);
1446 }
1447
1448 if (bank->regs->irqstatus_raw0) {
1449 writel_relaxed(old0 | l, bank->base +
1450 bank->regs->leveldetect0);
1451 writel_relaxed(old1 | l, bank->base +
1452 bank->regs->leveldetect1);
1453 }
1454 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1455 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1456 }
1457
1458 bank->workaround_enabled = false;
1459 raw_spin_unlock_irqrestore(&bank->lock, flags);
1460
1461 return 0;
1462}
1463#endif /* CONFIG_PM */
1464
1465#if IS_BUILTIN(CONFIG_GPIO_OMAP)
1466void omap2_gpio_prepare_for_idle(int pwr_mode)
1467{
1468 struct gpio_bank *bank;
1469
1470 list_for_each_entry(bank, &omap_gpio_list, node) {
1471 if (!BANK_USED(bank) || !bank->loses_context)
1472 continue;
1473
1474 bank->power_mode = pwr_mode;
1475
1476 pm_runtime_put_sync_suspend(bank->chip.parent);
1477 }
1478}
1479
1480void omap2_gpio_resume_after_idle(void)
1481{
1482 struct gpio_bank *bank;
1483
1484 list_for_each_entry(bank, &omap_gpio_list, node) {
1485 if (!BANK_USED(bank) || !bank->loses_context)
1486 continue;
1487
1488 pm_runtime_get_sync(bank->chip.parent);
1489 }
1490}
1491#endif
1492
1493#if defined(CONFIG_PM)
1494static void omap_gpio_init_context(struct gpio_bank *p)
1495{
1496 struct omap_gpio_reg_offs *regs = p->regs;
1497 void __iomem *base = p->base;
1498
1499 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1500 p->context.oe = readl_relaxed(base + regs->direction);
1501 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1502 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1503 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1504 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1505 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1506 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1507 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1508
1509 if (regs->set_dataout && p->regs->clr_dataout)
1510 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1511 else
1512 p->context.dataout = readl_relaxed(base + regs->dataout);
1513
1514 p->context_valid = true;
1515}
1516
1517static void omap_gpio_restore_context(struct gpio_bank *bank)
1518{
1519 writel_relaxed(bank->context.wake_en,
1520 bank->base + bank->regs->wkup_en);
1521 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1522 writel_relaxed(bank->context.leveldetect0,
1523 bank->base + bank->regs->leveldetect0);
1524 writel_relaxed(bank->context.leveldetect1,
1525 bank->base + bank->regs->leveldetect1);
1526 writel_relaxed(bank->context.risingdetect,
1527 bank->base + bank->regs->risingdetect);
1528 writel_relaxed(bank->context.fallingdetect,
1529 bank->base + bank->regs->fallingdetect);
1530 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1531 writel_relaxed(bank->context.dataout,
1532 bank->base + bank->regs->set_dataout);
1533 else
1534 writel_relaxed(bank->context.dataout,
1535 bank->base + bank->regs->dataout);
1536 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1537
1538 if (bank->dbck_enable_mask) {
1539 writel_relaxed(bank->context.debounce, bank->base +
1540 bank->regs->debounce);
1541 writel_relaxed(bank->context.debounce_en,
1542 bank->base + bank->regs->debounce_en);
1543 }
1544
1545 writel_relaxed(bank->context.irqenable1,
1546 bank->base + bank->regs->irqenable);
1547 writel_relaxed(bank->context.irqenable2,
1548 bank->base + bank->regs->irqenable2);
1549}
1550#endif /* CONFIG_PM */
1551#else
1552#define omap_gpio_runtime_suspend NULL
1553#define omap_gpio_runtime_resume NULL
1554static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1555#endif
1556
1557static const struct dev_pm_ops gpio_pm_ops = {
1558 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1559 NULL)
1560};
1561
1562#if defined(CONFIG_OF)
1563static struct omap_gpio_reg_offs omap2_gpio_regs = {
1564 .revision = OMAP24XX_GPIO_REVISION,
1565 .direction = OMAP24XX_GPIO_OE,
1566 .datain = OMAP24XX_GPIO_DATAIN,
1567 .dataout = OMAP24XX_GPIO_DATAOUT,
1568 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1569 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1570 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1571 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1572 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1573 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1574 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1575 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1576 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1577 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1578 .ctrl = OMAP24XX_GPIO_CTRL,
1579 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1580 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1581 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1582 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1583 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1584};
1585
1586static struct omap_gpio_reg_offs omap4_gpio_regs = {
1587 .revision = OMAP4_GPIO_REVISION,
1588 .direction = OMAP4_GPIO_OE,
1589 .datain = OMAP4_GPIO_DATAIN,
1590 .dataout = OMAP4_GPIO_DATAOUT,
1591 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1592 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1593 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1594 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1595 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1596 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1597 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1598 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1599 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1600 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1601 .ctrl = OMAP4_GPIO_CTRL,
1602 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1603 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1604 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1605 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1606 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1607};
1608
1609static const struct omap_gpio_platform_data omap2_pdata = {
1610 .regs = &omap2_gpio_regs,
1611 .bank_width = 32,
1612 .dbck_flag = false,
1613};
1614
1615static const struct omap_gpio_platform_data omap3_pdata = {
1616 .regs = &omap2_gpio_regs,
1617 .bank_width = 32,
1618 .dbck_flag = true,
1619};
1620
1621static const struct omap_gpio_platform_data omap4_pdata = {
1622 .regs = &omap4_gpio_regs,
1623 .bank_width = 32,
1624 .dbck_flag = true,
1625};
1626
1627static const struct of_device_id omap_gpio_match[] = {
1628 {
1629 .compatible = "ti,omap4-gpio",
1630 .data = &omap4_pdata,
1631 },
1632 {
1633 .compatible = "ti,omap3-gpio",
1634 .data = &omap3_pdata,
1635 },
1636 {
1637 .compatible = "ti,omap2-gpio",
1638 .data = &omap2_pdata,
1639 },
1640 { },
1641};
1642MODULE_DEVICE_TABLE(of, omap_gpio_match);
1643#endif
1644
1645static struct platform_driver omap_gpio_driver = {
1646 .probe = omap_gpio_probe,
1647 .remove = omap_gpio_remove,
1648 .driver = {
1649 .name = "omap_gpio",
1650 .pm = &gpio_pm_ops,
1651 .of_match_table = of_match_ptr(omap_gpio_match),
1652 },
1653};
1654
1655/*
1656 * gpio driver register needs to be done before
1657 * machine_init functions access gpio APIs.
1658 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1659 */
1660static int __init omap_gpio_drv_reg(void)
1661{
1662 return platform_driver_register(&omap_gpio_driver);
1663}
1664postcore_initcall(omap_gpio_drv_reg);
1665
1666static void __exit omap_gpio_exit(void)
1667{
1668 platform_driver_unregister(&omap_gpio_driver);
1669}
1670module_exit(omap_gpio_exit);
1671
1672MODULE_DESCRIPTION("omap gpio driver");
1673MODULE_ALIAS("platform:gpio-omap");
1674MODULE_LICENSE("GPL v2");