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1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/device.h>
23#include <linux/pm_runtime.h>
24#include <linux/pm.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/irqdomain.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31#include <mach/irqs.h>
32#include <asm/gpio.h>
33#include <asm/mach/irq.h>
34
35#define OFF_MODE 1
36
37static LIST_HEAD(omap_gpio_list);
38
39struct gpio_regs {
40 u32 irqenable1;
41 u32 irqenable2;
42 u32 wake_en;
43 u32 ctrl;
44 u32 oe;
45 u32 leveldetect0;
46 u32 leveldetect1;
47 u32 risingdetect;
48 u32 fallingdetect;
49 u32 dataout;
50 u32 debounce;
51 u32 debounce_en;
52};
53
54struct gpio_bank {
55 struct list_head node;
56 void __iomem *base;
57 u16 irq;
58 int irq_base;
59 struct irq_domain *domain;
60 u32 non_wakeup_gpios;
61 u32 enabled_non_wakeup_gpios;
62 struct gpio_regs context;
63 u32 saved_datain;
64 u32 level_mask;
65 u32 toggle_mask;
66 spinlock_t lock;
67 struct gpio_chip chip;
68 struct clk *dbck;
69 u32 mod_usage;
70 u32 dbck_enable_mask;
71 bool dbck_enabled;
72 struct device *dev;
73 bool is_mpuio;
74 bool dbck_flag;
75 bool loses_context;
76 int stride;
77 u32 width;
78 int context_loss_count;
79 int power_mode;
80 bool workaround_enabled;
81
82 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
83 int (*get_context_loss_count)(struct device *dev);
84
85 struct omap_gpio_reg_offs *regs;
86};
87
88#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
89#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
90#define GPIO_MOD_CTRL_BIT BIT(0)
91
92static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
93{
94 return gpio_irq - bank->irq_base + bank->chip.base;
95}
96
97static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
98{
99 void __iomem *reg = bank->base;
100 u32 l;
101
102 reg += bank->regs->direction;
103 l = __raw_readl(reg);
104 if (is_input)
105 l |= 1 << gpio;
106 else
107 l &= ~(1 << gpio);
108 __raw_writel(l, reg);
109 bank->context.oe = l;
110}
111
112
113/* set data out value using dedicate set/clear register */
114static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
115{
116 void __iomem *reg = bank->base;
117 u32 l = GPIO_BIT(bank, gpio);
118
119 if (enable) {
120 reg += bank->regs->set_dataout;
121 bank->context.dataout |= l;
122 } else {
123 reg += bank->regs->clr_dataout;
124 bank->context.dataout &= ~l;
125 }
126
127 __raw_writel(l, reg);
128}
129
130/* set data out value using mask register */
131static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
132{
133 void __iomem *reg = bank->base + bank->regs->dataout;
134 u32 gpio_bit = GPIO_BIT(bank, gpio);
135 u32 l;
136
137 l = __raw_readl(reg);
138 if (enable)
139 l |= gpio_bit;
140 else
141 l &= ~gpio_bit;
142 __raw_writel(l, reg);
143 bank->context.dataout = l;
144}
145
146static int _get_gpio_datain(struct gpio_bank *bank, int offset)
147{
148 void __iomem *reg = bank->base + bank->regs->datain;
149
150 return (__raw_readl(reg) & (1 << offset)) != 0;
151}
152
153static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
154{
155 void __iomem *reg = bank->base + bank->regs->dataout;
156
157 return (__raw_readl(reg) & (1 << offset)) != 0;
158}
159
160static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
161{
162 int l = __raw_readl(base + reg);
163
164 if (set)
165 l |= mask;
166 else
167 l &= ~mask;
168
169 __raw_writel(l, base + reg);
170}
171
172static inline void _gpio_dbck_enable(struct gpio_bank *bank)
173{
174 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
175 clk_enable(bank->dbck);
176 bank->dbck_enabled = true;
177
178 __raw_writel(bank->dbck_enable_mask,
179 bank->base + bank->regs->debounce_en);
180 }
181}
182
183static inline void _gpio_dbck_disable(struct gpio_bank *bank)
184{
185 if (bank->dbck_enable_mask && bank->dbck_enabled) {
186 /*
187 * Disable debounce before cutting it's clock. If debounce is
188 * enabled but the clock is not, GPIO module seems to be unable
189 * to detect events and generate interrupts at least on OMAP3.
190 */
191 __raw_writel(0, bank->base + bank->regs->debounce_en);
192
193 clk_disable(bank->dbck);
194 bank->dbck_enabled = false;
195 }
196}
197
198/**
199 * _set_gpio_debounce - low level gpio debounce time
200 * @bank: the gpio bank we're acting upon
201 * @gpio: the gpio number on this @gpio
202 * @debounce: debounce time to use
203 *
204 * OMAP's debounce time is in 31us steps so we need
205 * to convert and round up to the closest unit.
206 */
207static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
208 unsigned debounce)
209{
210 void __iomem *reg;
211 u32 val;
212 u32 l;
213
214 if (!bank->dbck_flag)
215 return;
216
217 if (debounce < 32)
218 debounce = 0x01;
219 else if (debounce > 7936)
220 debounce = 0xff;
221 else
222 debounce = (debounce / 0x1f) - 1;
223
224 l = GPIO_BIT(bank, gpio);
225
226 clk_enable(bank->dbck);
227 reg = bank->base + bank->regs->debounce;
228 __raw_writel(debounce, reg);
229
230 reg = bank->base + bank->regs->debounce_en;
231 val = __raw_readl(reg);
232
233 if (debounce)
234 val |= l;
235 else
236 val &= ~l;
237 bank->dbck_enable_mask = val;
238
239 __raw_writel(val, reg);
240 clk_disable(bank->dbck);
241 /*
242 * Enable debounce clock per module.
243 * This call is mandatory because in omap_gpio_request() when
244 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
245 * runtime callbck fails to turn on dbck because dbck_enable_mask
246 * used within _gpio_dbck_enable() is still not initialized at
247 * that point. Therefore we have to enable dbck here.
248 */
249 _gpio_dbck_enable(bank);
250 if (bank->dbck_enable_mask) {
251 bank->context.debounce = debounce;
252 bank->context.debounce_en = val;
253 }
254}
255
256static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
257 unsigned trigger)
258{
259 void __iomem *base = bank->base;
260 u32 gpio_bit = 1 << gpio;
261
262 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
263 trigger & IRQ_TYPE_LEVEL_LOW);
264 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
265 trigger & IRQ_TYPE_LEVEL_HIGH);
266 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
267 trigger & IRQ_TYPE_EDGE_RISING);
268 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
269 trigger & IRQ_TYPE_EDGE_FALLING);
270
271 bank->context.leveldetect0 =
272 __raw_readl(bank->base + bank->regs->leveldetect0);
273 bank->context.leveldetect1 =
274 __raw_readl(bank->base + bank->regs->leveldetect1);
275 bank->context.risingdetect =
276 __raw_readl(bank->base + bank->regs->risingdetect);
277 bank->context.fallingdetect =
278 __raw_readl(bank->base + bank->regs->fallingdetect);
279
280 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
281 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
282 bank->context.wake_en =
283 __raw_readl(bank->base + bank->regs->wkup_en);
284 }
285
286 /* This part needs to be executed always for OMAP{34xx, 44xx} */
287 if (!bank->regs->irqctrl) {
288 /* On omap24xx proceed only when valid GPIO bit is set */
289 if (bank->non_wakeup_gpios) {
290 if (!(bank->non_wakeup_gpios & gpio_bit))
291 goto exit;
292 }
293
294 /*
295 * Log the edge gpio and manually trigger the IRQ
296 * after resume if the input level changes
297 * to avoid irq lost during PER RET/OFF mode
298 * Applies for omap2 non-wakeup gpio and all omap3 gpios
299 */
300 if (trigger & IRQ_TYPE_EDGE_BOTH)
301 bank->enabled_non_wakeup_gpios |= gpio_bit;
302 else
303 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
304 }
305
306exit:
307 bank->level_mask =
308 __raw_readl(bank->base + bank->regs->leveldetect0) |
309 __raw_readl(bank->base + bank->regs->leveldetect1);
310}
311
312#ifdef CONFIG_ARCH_OMAP1
313/*
314 * This only applies to chips that can't do both rising and falling edge
315 * detection at once. For all other chips, this function is a noop.
316 */
317static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
318{
319 void __iomem *reg = bank->base;
320 u32 l = 0;
321
322 if (!bank->regs->irqctrl)
323 return;
324
325 reg += bank->regs->irqctrl;
326
327 l = __raw_readl(reg);
328 if ((l >> gpio) & 1)
329 l &= ~(1 << gpio);
330 else
331 l |= 1 << gpio;
332
333 __raw_writel(l, reg);
334}
335#else
336static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
337#endif
338
339static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
340 unsigned trigger)
341{
342 void __iomem *reg = bank->base;
343 void __iomem *base = bank->base;
344 u32 l = 0;
345
346 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
347 set_gpio_trigger(bank, gpio, trigger);
348 } else if (bank->regs->irqctrl) {
349 reg += bank->regs->irqctrl;
350
351 l = __raw_readl(reg);
352 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
353 bank->toggle_mask |= 1 << gpio;
354 if (trigger & IRQ_TYPE_EDGE_RISING)
355 l |= 1 << gpio;
356 else if (trigger & IRQ_TYPE_EDGE_FALLING)
357 l &= ~(1 << gpio);
358 else
359 return -EINVAL;
360
361 __raw_writel(l, reg);
362 } else if (bank->regs->edgectrl1) {
363 if (gpio & 0x08)
364 reg += bank->regs->edgectrl2;
365 else
366 reg += bank->regs->edgectrl1;
367
368 gpio &= 0x07;
369 l = __raw_readl(reg);
370 l &= ~(3 << (gpio << 1));
371 if (trigger & IRQ_TYPE_EDGE_RISING)
372 l |= 2 << (gpio << 1);
373 if (trigger & IRQ_TYPE_EDGE_FALLING)
374 l |= 1 << (gpio << 1);
375
376 /* Enable wake-up during idle for dynamic tick */
377 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
378 bank->context.wake_en =
379 __raw_readl(bank->base + bank->regs->wkup_en);
380 __raw_writel(l, reg);
381 }
382 return 0;
383}
384
385static int gpio_irq_type(struct irq_data *d, unsigned type)
386{
387 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
388 unsigned gpio;
389 int retval;
390 unsigned long flags;
391
392 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
393 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
394 else
395 gpio = irq_to_gpio(bank, d->irq);
396
397 if (type & ~IRQ_TYPE_SENSE_MASK)
398 return -EINVAL;
399
400 if (!bank->regs->leveldetect0 &&
401 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
402 return -EINVAL;
403
404 spin_lock_irqsave(&bank->lock, flags);
405 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
406 spin_unlock_irqrestore(&bank->lock, flags);
407
408 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
409 __irq_set_handler_locked(d->irq, handle_level_irq);
410 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
411 __irq_set_handler_locked(d->irq, handle_edge_irq);
412
413 return retval;
414}
415
416static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
417{
418 void __iomem *reg = bank->base;
419
420 reg += bank->regs->irqstatus;
421 __raw_writel(gpio_mask, reg);
422
423 /* Workaround for clearing DSP GPIO interrupts to allow retention */
424 if (bank->regs->irqstatus2) {
425 reg = bank->base + bank->regs->irqstatus2;
426 __raw_writel(gpio_mask, reg);
427 }
428
429 /* Flush posted write for the irq status to avoid spurious interrupts */
430 __raw_readl(reg);
431}
432
433static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
434{
435 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
436}
437
438static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
439{
440 void __iomem *reg = bank->base;
441 u32 l;
442 u32 mask = (1 << bank->width) - 1;
443
444 reg += bank->regs->irqenable;
445 l = __raw_readl(reg);
446 if (bank->regs->irqenable_inv)
447 l = ~l;
448 l &= mask;
449 return l;
450}
451
452static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
453{
454 void __iomem *reg = bank->base;
455 u32 l;
456
457 if (bank->regs->set_irqenable) {
458 reg += bank->regs->set_irqenable;
459 l = gpio_mask;
460 bank->context.irqenable1 |= gpio_mask;
461 } else {
462 reg += bank->regs->irqenable;
463 l = __raw_readl(reg);
464 if (bank->regs->irqenable_inv)
465 l &= ~gpio_mask;
466 else
467 l |= gpio_mask;
468 bank->context.irqenable1 = l;
469 }
470
471 __raw_writel(l, reg);
472}
473
474static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
475{
476 void __iomem *reg = bank->base;
477 u32 l;
478
479 if (bank->regs->clr_irqenable) {
480 reg += bank->regs->clr_irqenable;
481 l = gpio_mask;
482 bank->context.irqenable1 &= ~gpio_mask;
483 } else {
484 reg += bank->regs->irqenable;
485 l = __raw_readl(reg);
486 if (bank->regs->irqenable_inv)
487 l |= gpio_mask;
488 else
489 l &= ~gpio_mask;
490 bank->context.irqenable1 = l;
491 }
492
493 __raw_writel(l, reg);
494}
495
496static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
497{
498 if (enable)
499 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
500 else
501 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
502}
503
504/*
505 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
506 * 1510 does not seem to have a wake-up register. If JTAG is connected
507 * to the target, system will wake up always on GPIO events. While
508 * system is running all registered GPIO interrupts need to have wake-up
509 * enabled. When system is suspended, only selected GPIO interrupts need
510 * to have wake-up enabled.
511 */
512static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
513{
514 u32 gpio_bit = GPIO_BIT(bank, gpio);
515 unsigned long flags;
516
517 if (bank->non_wakeup_gpios & gpio_bit) {
518 dev_err(bank->dev,
519 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
520 return -EINVAL;
521 }
522
523 spin_lock_irqsave(&bank->lock, flags);
524 if (enable)
525 bank->context.wake_en |= gpio_bit;
526 else
527 bank->context.wake_en &= ~gpio_bit;
528
529 __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
530 spin_unlock_irqrestore(&bank->lock, flags);
531
532 return 0;
533}
534
535static void _reset_gpio(struct gpio_bank *bank, int gpio)
536{
537 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
538 _set_gpio_irqenable(bank, gpio, 0);
539 _clear_gpio_irqstatus(bank, gpio);
540 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
541}
542
543/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
544static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
545{
546 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
547 unsigned int gpio = irq_to_gpio(bank, d->irq);
548
549 return _set_gpio_wakeup(bank, gpio, enable);
550}
551
552static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
553{
554 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
555 unsigned long flags;
556
557 /*
558 * If this is the first gpio_request for the bank,
559 * enable the bank module.
560 */
561 if (!bank->mod_usage)
562 pm_runtime_get_sync(bank->dev);
563
564 spin_lock_irqsave(&bank->lock, flags);
565 /* Set trigger to none. You need to enable the desired trigger with
566 * request_irq() or set_irq_type().
567 */
568 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
569
570 if (bank->regs->pinctrl) {
571 void __iomem *reg = bank->base + bank->regs->pinctrl;
572
573 /* Claim the pin for MPU */
574 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
575 }
576
577 if (bank->regs->ctrl && !bank->mod_usage) {
578 void __iomem *reg = bank->base + bank->regs->ctrl;
579 u32 ctrl;
580
581 ctrl = __raw_readl(reg);
582 /* Module is enabled, clocks are not gated */
583 ctrl &= ~GPIO_MOD_CTRL_BIT;
584 __raw_writel(ctrl, reg);
585 bank->context.ctrl = ctrl;
586 }
587
588 bank->mod_usage |= 1 << offset;
589
590 spin_unlock_irqrestore(&bank->lock, flags);
591
592 return 0;
593}
594
595static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
596{
597 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
598 void __iomem *base = bank->base;
599 unsigned long flags;
600
601 spin_lock_irqsave(&bank->lock, flags);
602
603 if (bank->regs->wkup_en) {
604 /* Disable wake-up during idle for dynamic tick */
605 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
606 bank->context.wake_en =
607 __raw_readl(bank->base + bank->regs->wkup_en);
608 }
609
610 bank->mod_usage &= ~(1 << offset);
611
612 if (bank->regs->ctrl && !bank->mod_usage) {
613 void __iomem *reg = bank->base + bank->regs->ctrl;
614 u32 ctrl;
615
616 ctrl = __raw_readl(reg);
617 /* Module is disabled, clocks are gated */
618 ctrl |= GPIO_MOD_CTRL_BIT;
619 __raw_writel(ctrl, reg);
620 bank->context.ctrl = ctrl;
621 }
622
623 _reset_gpio(bank, bank->chip.base + offset);
624 spin_unlock_irqrestore(&bank->lock, flags);
625
626 /*
627 * If this is the last gpio to be freed in the bank,
628 * disable the bank module.
629 */
630 if (!bank->mod_usage)
631 pm_runtime_put(bank->dev);
632}
633
634/*
635 * We need to unmask the GPIO bank interrupt as soon as possible to
636 * avoid missing GPIO interrupts for other lines in the bank.
637 * Then we need to mask-read-clear-unmask the triggered GPIO lines
638 * in the bank to avoid missing nested interrupts for a GPIO line.
639 * If we wait to unmask individual GPIO lines in the bank after the
640 * line's interrupt handler has been run, we may miss some nested
641 * interrupts.
642 */
643static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
644{
645 void __iomem *isr_reg = NULL;
646 u32 isr;
647 unsigned int gpio_irq, gpio_index;
648 struct gpio_bank *bank;
649 int unmasked = 0;
650 struct irq_chip *chip = irq_desc_get_chip(desc);
651
652 chained_irq_enter(chip, desc);
653
654 bank = irq_get_handler_data(irq);
655 isr_reg = bank->base + bank->regs->irqstatus;
656 pm_runtime_get_sync(bank->dev);
657
658 if (WARN_ON(!isr_reg))
659 goto exit;
660
661 while(1) {
662 u32 isr_saved, level_mask = 0;
663 u32 enabled;
664
665 enabled = _get_gpio_irqbank_mask(bank);
666 isr_saved = isr = __raw_readl(isr_reg) & enabled;
667
668 if (bank->level_mask)
669 level_mask = bank->level_mask & enabled;
670
671 /* clear edge sensitive interrupts before handler(s) are
672 called so that we don't miss any interrupt occurred while
673 executing them */
674 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
675 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
676 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
677
678 /* if there is only edge sensitive GPIO pin interrupts
679 configured, we could unmask GPIO bank interrupt immediately */
680 if (!level_mask && !unmasked) {
681 unmasked = 1;
682 chained_irq_exit(chip, desc);
683 }
684
685 if (!isr)
686 break;
687
688 gpio_irq = bank->irq_base;
689 for (; isr != 0; isr >>= 1, gpio_irq++) {
690 int gpio = irq_to_gpio(bank, gpio_irq);
691
692 if (!(isr & 1))
693 continue;
694
695 gpio_index = GPIO_INDEX(bank, gpio);
696
697 /*
698 * Some chips can't respond to both rising and falling
699 * at the same time. If this irq was requested with
700 * both flags, we need to flip the ICR data for the IRQ
701 * to respond to the IRQ for the opposite direction.
702 * This will be indicated in the bank toggle_mask.
703 */
704 if (bank->toggle_mask & (1 << gpio_index))
705 _toggle_gpio_edge_triggering(bank, gpio_index);
706
707 generic_handle_irq(gpio_irq);
708 }
709 }
710 /* if bank has any level sensitive GPIO pin interrupt
711 configured, we must unmask the bank interrupt only after
712 handler(s) are executed in order to avoid spurious bank
713 interrupt */
714exit:
715 if (!unmasked)
716 chained_irq_exit(chip, desc);
717 pm_runtime_put(bank->dev);
718}
719
720static void gpio_irq_shutdown(struct irq_data *d)
721{
722 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
723 unsigned int gpio = irq_to_gpio(bank, d->irq);
724 unsigned long flags;
725
726 spin_lock_irqsave(&bank->lock, flags);
727 _reset_gpio(bank, gpio);
728 spin_unlock_irqrestore(&bank->lock, flags);
729}
730
731static void gpio_ack_irq(struct irq_data *d)
732{
733 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
734 unsigned int gpio = irq_to_gpio(bank, d->irq);
735
736 _clear_gpio_irqstatus(bank, gpio);
737}
738
739static void gpio_mask_irq(struct irq_data *d)
740{
741 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
742 unsigned int gpio = irq_to_gpio(bank, d->irq);
743 unsigned long flags;
744
745 spin_lock_irqsave(&bank->lock, flags);
746 _set_gpio_irqenable(bank, gpio, 0);
747 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
748 spin_unlock_irqrestore(&bank->lock, flags);
749}
750
751static void gpio_unmask_irq(struct irq_data *d)
752{
753 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
754 unsigned int gpio = irq_to_gpio(bank, d->irq);
755 unsigned int irq_mask = GPIO_BIT(bank, gpio);
756 u32 trigger = irqd_get_trigger_type(d);
757 unsigned long flags;
758
759 spin_lock_irqsave(&bank->lock, flags);
760 if (trigger)
761 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
762
763 /* For level-triggered GPIOs, the clearing must be done after
764 * the HW source is cleared, thus after the handler has run */
765 if (bank->level_mask & irq_mask) {
766 _set_gpio_irqenable(bank, gpio, 0);
767 _clear_gpio_irqstatus(bank, gpio);
768 }
769
770 _set_gpio_irqenable(bank, gpio, 1);
771 spin_unlock_irqrestore(&bank->lock, flags);
772}
773
774static struct irq_chip gpio_irq_chip = {
775 .name = "GPIO",
776 .irq_shutdown = gpio_irq_shutdown,
777 .irq_ack = gpio_ack_irq,
778 .irq_mask = gpio_mask_irq,
779 .irq_unmask = gpio_unmask_irq,
780 .irq_set_type = gpio_irq_type,
781 .irq_set_wake = gpio_wake_enable,
782};
783
784/*---------------------------------------------------------------------*/
785
786static int omap_mpuio_suspend_noirq(struct device *dev)
787{
788 struct platform_device *pdev = to_platform_device(dev);
789 struct gpio_bank *bank = platform_get_drvdata(pdev);
790 void __iomem *mask_reg = bank->base +
791 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
792 unsigned long flags;
793
794 spin_lock_irqsave(&bank->lock, flags);
795 __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
796 spin_unlock_irqrestore(&bank->lock, flags);
797
798 return 0;
799}
800
801static int omap_mpuio_resume_noirq(struct device *dev)
802{
803 struct platform_device *pdev = to_platform_device(dev);
804 struct gpio_bank *bank = platform_get_drvdata(pdev);
805 void __iomem *mask_reg = bank->base +
806 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
807 unsigned long flags;
808
809 spin_lock_irqsave(&bank->lock, flags);
810 __raw_writel(bank->context.wake_en, mask_reg);
811 spin_unlock_irqrestore(&bank->lock, flags);
812
813 return 0;
814}
815
816static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
817 .suspend_noirq = omap_mpuio_suspend_noirq,
818 .resume_noirq = omap_mpuio_resume_noirq,
819};
820
821/* use platform_driver for this. */
822static struct platform_driver omap_mpuio_driver = {
823 .driver = {
824 .name = "mpuio",
825 .pm = &omap_mpuio_dev_pm_ops,
826 },
827};
828
829static struct platform_device omap_mpuio_device = {
830 .name = "mpuio",
831 .id = -1,
832 .dev = {
833 .driver = &omap_mpuio_driver.driver,
834 }
835 /* could list the /proc/iomem resources */
836};
837
838static inline void mpuio_init(struct gpio_bank *bank)
839{
840 platform_set_drvdata(&omap_mpuio_device, bank);
841
842 if (platform_driver_register(&omap_mpuio_driver) == 0)
843 (void) platform_device_register(&omap_mpuio_device);
844}
845
846/*---------------------------------------------------------------------*/
847
848static int gpio_input(struct gpio_chip *chip, unsigned offset)
849{
850 struct gpio_bank *bank;
851 unsigned long flags;
852
853 bank = container_of(chip, struct gpio_bank, chip);
854 spin_lock_irqsave(&bank->lock, flags);
855 _set_gpio_direction(bank, offset, 1);
856 spin_unlock_irqrestore(&bank->lock, flags);
857 return 0;
858}
859
860static int gpio_is_input(struct gpio_bank *bank, int mask)
861{
862 void __iomem *reg = bank->base + bank->regs->direction;
863
864 return __raw_readl(reg) & mask;
865}
866
867static int gpio_get(struct gpio_chip *chip, unsigned offset)
868{
869 struct gpio_bank *bank;
870 u32 mask;
871
872 bank = container_of(chip, struct gpio_bank, chip);
873 mask = (1 << offset);
874
875 if (gpio_is_input(bank, mask))
876 return _get_gpio_datain(bank, offset);
877 else
878 return _get_gpio_dataout(bank, offset);
879}
880
881static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
882{
883 struct gpio_bank *bank;
884 unsigned long flags;
885
886 bank = container_of(chip, struct gpio_bank, chip);
887 spin_lock_irqsave(&bank->lock, flags);
888 bank->set_dataout(bank, offset, value);
889 _set_gpio_direction(bank, offset, 0);
890 spin_unlock_irqrestore(&bank->lock, flags);
891 return 0;
892}
893
894static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
895 unsigned debounce)
896{
897 struct gpio_bank *bank;
898 unsigned long flags;
899
900 bank = container_of(chip, struct gpio_bank, chip);
901
902 if (!bank->dbck) {
903 bank->dbck = clk_get(bank->dev, "dbclk");
904 if (IS_ERR(bank->dbck))
905 dev_err(bank->dev, "Could not get gpio dbck\n");
906 }
907
908 spin_lock_irqsave(&bank->lock, flags);
909 _set_gpio_debounce(bank, offset, debounce);
910 spin_unlock_irqrestore(&bank->lock, flags);
911
912 return 0;
913}
914
915static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
916{
917 struct gpio_bank *bank;
918 unsigned long flags;
919
920 bank = container_of(chip, struct gpio_bank, chip);
921 spin_lock_irqsave(&bank->lock, flags);
922 bank->set_dataout(bank, offset, value);
923 spin_unlock_irqrestore(&bank->lock, flags);
924}
925
926static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
927{
928 struct gpio_bank *bank;
929
930 bank = container_of(chip, struct gpio_bank, chip);
931 return bank->irq_base + offset;
932}
933
934/*---------------------------------------------------------------------*/
935
936static void __init omap_gpio_show_rev(struct gpio_bank *bank)
937{
938 static bool called;
939 u32 rev;
940
941 if (called || bank->regs->revision == USHRT_MAX)
942 return;
943
944 rev = __raw_readw(bank->base + bank->regs->revision);
945 pr_info("OMAP GPIO hardware version %d.%d\n",
946 (rev >> 4) & 0x0f, rev & 0x0f);
947
948 called = true;
949}
950
951/* This lock class tells lockdep that GPIO irqs are in a different
952 * category than their parents, so it won't report false recursion.
953 */
954static struct lock_class_key gpio_lock_class;
955
956static void omap_gpio_mod_init(struct gpio_bank *bank)
957{
958 void __iomem *base = bank->base;
959 u32 l = 0xffffffff;
960
961 if (bank->width == 16)
962 l = 0xffff;
963
964 if (bank->is_mpuio) {
965 __raw_writel(l, bank->base + bank->regs->irqenable);
966 return;
967 }
968
969 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
970 _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
971 if (bank->regs->debounce_en)
972 __raw_writel(0, base + bank->regs->debounce_en);
973
974 /* Save OE default value (0xffffffff) in the context */
975 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
976 /* Initialize interface clk ungated, module enabled */
977 if (bank->regs->ctrl)
978 __raw_writel(0, base + bank->regs->ctrl);
979}
980
981static __devinit void
982omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
983 unsigned int num)
984{
985 struct irq_chip_generic *gc;
986 struct irq_chip_type *ct;
987
988 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
989 handle_simple_irq);
990 if (!gc) {
991 dev_err(bank->dev, "Memory alloc failed for gc\n");
992 return;
993 }
994
995 ct = gc->chip_types;
996
997 /* NOTE: No ack required, reading IRQ status clears it. */
998 ct->chip.irq_mask = irq_gc_mask_set_bit;
999 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1000 ct->chip.irq_set_type = gpio_irq_type;
1001
1002 if (bank->regs->wkup_en)
1003 ct->chip.irq_set_wake = gpio_wake_enable,
1004
1005 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1006 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1007 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1008}
1009
1010static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1011{
1012 int j;
1013 static int gpio;
1014
1015 /*
1016 * REVISIT eventually switch from OMAP-specific gpio structs
1017 * over to the generic ones
1018 */
1019 bank->chip.request = omap_gpio_request;
1020 bank->chip.free = omap_gpio_free;
1021 bank->chip.direction_input = gpio_input;
1022 bank->chip.get = gpio_get;
1023 bank->chip.direction_output = gpio_output;
1024 bank->chip.set_debounce = gpio_debounce;
1025 bank->chip.set = gpio_set;
1026 bank->chip.to_irq = gpio_2irq;
1027 if (bank->is_mpuio) {
1028 bank->chip.label = "mpuio";
1029 if (bank->regs->wkup_en)
1030 bank->chip.dev = &omap_mpuio_device.dev;
1031 bank->chip.base = OMAP_MPUIO(0);
1032 } else {
1033 bank->chip.label = "gpio";
1034 bank->chip.base = gpio;
1035 gpio += bank->width;
1036 }
1037 bank->chip.ngpio = bank->width;
1038
1039 gpiochip_add(&bank->chip);
1040
1041 for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1042 irq_set_lockdep_class(j, &gpio_lock_class);
1043 irq_set_chip_data(j, bank);
1044 if (bank->is_mpuio) {
1045 omap_mpuio_alloc_gc(bank, j, bank->width);
1046 } else {
1047 irq_set_chip(j, &gpio_irq_chip);
1048 irq_set_handler(j, handle_simple_irq);
1049 set_irq_flags(j, IRQF_VALID);
1050 }
1051 }
1052 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1053 irq_set_handler_data(bank->irq, bank);
1054}
1055
1056static const struct of_device_id omap_gpio_match[];
1057
1058static int __devinit omap_gpio_probe(struct platform_device *pdev)
1059{
1060 struct device *dev = &pdev->dev;
1061 struct device_node *node = dev->of_node;
1062 const struct of_device_id *match;
1063 struct omap_gpio_platform_data *pdata;
1064 struct resource *res;
1065 struct gpio_bank *bank;
1066 int ret = 0;
1067
1068 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1069
1070 pdata = match ? match->data : dev->platform_data;
1071 if (!pdata)
1072 return -EINVAL;
1073
1074 bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL);
1075 if (!bank) {
1076 dev_err(dev, "Memory alloc failed\n");
1077 return -ENOMEM;
1078 }
1079
1080 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1081 if (unlikely(!res)) {
1082 dev_err(dev, "Invalid IRQ resource\n");
1083 return -ENODEV;
1084 }
1085
1086 bank->irq = res->start;
1087 bank->dev = dev;
1088 bank->dbck_flag = pdata->dbck_flag;
1089 bank->stride = pdata->bank_stride;
1090 bank->width = pdata->bank_width;
1091 bank->is_mpuio = pdata->is_mpuio;
1092 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1093 bank->loses_context = pdata->loses_context;
1094 bank->regs = pdata->regs;
1095#ifdef CONFIG_OF_GPIO
1096 bank->chip.of_node = of_node_get(node);
1097#endif
1098
1099 bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1100 if (bank->irq_base < 0) {
1101 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1102 return -ENODEV;
1103 }
1104
1105 bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
1106 0, &irq_domain_simple_ops, NULL);
1107
1108 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1109 bank->set_dataout = _set_gpio_dataout_reg;
1110 else
1111 bank->set_dataout = _set_gpio_dataout_mask;
1112
1113 spin_lock_init(&bank->lock);
1114
1115 /* Static mapping, never released */
1116 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1117 if (unlikely(!res)) {
1118 dev_err(dev, "Invalid mem resource\n");
1119 return -ENODEV;
1120 }
1121
1122 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1123 pdev->name)) {
1124 dev_err(dev, "Region already claimed\n");
1125 return -EBUSY;
1126 }
1127
1128 bank->base = devm_ioremap(dev, res->start, resource_size(res));
1129 if (!bank->base) {
1130 dev_err(dev, "Could not ioremap\n");
1131 return -ENOMEM;
1132 }
1133
1134 platform_set_drvdata(pdev, bank);
1135
1136 pm_runtime_enable(bank->dev);
1137 pm_runtime_irq_safe(bank->dev);
1138 pm_runtime_get_sync(bank->dev);
1139
1140 if (bank->is_mpuio)
1141 mpuio_init(bank);
1142
1143 omap_gpio_mod_init(bank);
1144 omap_gpio_chip_init(bank);
1145 omap_gpio_show_rev(bank);
1146
1147 if (bank->loses_context)
1148 bank->get_context_loss_count = pdata->get_context_loss_count;
1149
1150 pm_runtime_put(bank->dev);
1151
1152 list_add_tail(&bank->node, &omap_gpio_list);
1153
1154 return ret;
1155}
1156
1157#ifdef CONFIG_ARCH_OMAP2PLUS
1158
1159#if defined(CONFIG_PM_RUNTIME)
1160static void omap_gpio_restore_context(struct gpio_bank *bank);
1161
1162static int omap_gpio_runtime_suspend(struct device *dev)
1163{
1164 struct platform_device *pdev = to_platform_device(dev);
1165 struct gpio_bank *bank = platform_get_drvdata(pdev);
1166 u32 l1 = 0, l2 = 0;
1167 unsigned long flags;
1168 u32 wake_low, wake_hi;
1169
1170 spin_lock_irqsave(&bank->lock, flags);
1171
1172 /*
1173 * Only edges can generate a wakeup event to the PRCM.
1174 *
1175 * Therefore, ensure any wake-up capable GPIOs have
1176 * edge-detection enabled before going idle to ensure a wakeup
1177 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1178 * NDA TRM 25.5.3.1)
1179 *
1180 * The normal values will be restored upon ->runtime_resume()
1181 * by writing back the values saved in bank->context.
1182 */
1183 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1184 if (wake_low)
1185 __raw_writel(wake_low | bank->context.fallingdetect,
1186 bank->base + bank->regs->fallingdetect);
1187 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1188 if (wake_hi)
1189 __raw_writel(wake_hi | bank->context.risingdetect,
1190 bank->base + bank->regs->risingdetect);
1191
1192 if (!bank->enabled_non_wakeup_gpios)
1193 goto update_gpio_context_count;
1194
1195 if (bank->power_mode != OFF_MODE) {
1196 bank->power_mode = 0;
1197 goto update_gpio_context_count;
1198 }
1199 /*
1200 * If going to OFF, remove triggering for all
1201 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1202 * generated. See OMAP2420 Errata item 1.101.
1203 */
1204 bank->saved_datain = __raw_readl(bank->base +
1205 bank->regs->datain);
1206 l1 = bank->context.fallingdetect;
1207 l2 = bank->context.risingdetect;
1208
1209 l1 &= ~bank->enabled_non_wakeup_gpios;
1210 l2 &= ~bank->enabled_non_wakeup_gpios;
1211
1212 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1213 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1214
1215 bank->workaround_enabled = true;
1216
1217update_gpio_context_count:
1218 if (bank->get_context_loss_count)
1219 bank->context_loss_count =
1220 bank->get_context_loss_count(bank->dev);
1221
1222 _gpio_dbck_disable(bank);
1223 spin_unlock_irqrestore(&bank->lock, flags);
1224
1225 return 0;
1226}
1227
1228static int omap_gpio_runtime_resume(struct device *dev)
1229{
1230 struct platform_device *pdev = to_platform_device(dev);
1231 struct gpio_bank *bank = platform_get_drvdata(pdev);
1232 int context_lost_cnt_after;
1233 u32 l = 0, gen, gen0, gen1;
1234 unsigned long flags;
1235
1236 spin_lock_irqsave(&bank->lock, flags);
1237 _gpio_dbck_enable(bank);
1238
1239 /*
1240 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1241 * GPIOs were set to edge trigger also in order to be able to
1242 * generate a PRCM wakeup. Here we restore the
1243 * pre-runtime_suspend() values for edge triggering.
1244 */
1245 __raw_writel(bank->context.fallingdetect,
1246 bank->base + bank->regs->fallingdetect);
1247 __raw_writel(bank->context.risingdetect,
1248 bank->base + bank->regs->risingdetect);
1249
1250 if (bank->get_context_loss_count) {
1251 context_lost_cnt_after =
1252 bank->get_context_loss_count(bank->dev);
1253 if (context_lost_cnt_after != bank->context_loss_count) {
1254 omap_gpio_restore_context(bank);
1255 } else {
1256 spin_unlock_irqrestore(&bank->lock, flags);
1257 return 0;
1258 }
1259 }
1260
1261 if (!bank->workaround_enabled) {
1262 spin_unlock_irqrestore(&bank->lock, flags);
1263 return 0;
1264 }
1265
1266 __raw_writel(bank->context.fallingdetect,
1267 bank->base + bank->regs->fallingdetect);
1268 __raw_writel(bank->context.risingdetect,
1269 bank->base + bank->regs->risingdetect);
1270 l = __raw_readl(bank->base + bank->regs->datain);
1271
1272 /*
1273 * Check if any of the non-wakeup interrupt GPIOs have changed
1274 * state. If so, generate an IRQ by software. This is
1275 * horribly racy, but it's the best we can do to work around
1276 * this silicon bug.
1277 */
1278 l ^= bank->saved_datain;
1279 l &= bank->enabled_non_wakeup_gpios;
1280
1281 /*
1282 * No need to generate IRQs for the rising edge for gpio IRQs
1283 * configured with falling edge only; and vice versa.
1284 */
1285 gen0 = l & bank->context.fallingdetect;
1286 gen0 &= bank->saved_datain;
1287
1288 gen1 = l & bank->context.risingdetect;
1289 gen1 &= ~(bank->saved_datain);
1290
1291 /* FIXME: Consider GPIO IRQs with level detections properly! */
1292 gen = l & (~(bank->context.fallingdetect) &
1293 ~(bank->context.risingdetect));
1294 /* Consider all GPIO IRQs needed to be updated */
1295 gen |= gen0 | gen1;
1296
1297 if (gen) {
1298 u32 old0, old1;
1299
1300 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1301 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1302
1303 if (!bank->regs->irqstatus_raw0) {
1304 __raw_writel(old0 | gen, bank->base +
1305 bank->regs->leveldetect0);
1306 __raw_writel(old1 | gen, bank->base +
1307 bank->regs->leveldetect1);
1308 }
1309
1310 if (bank->regs->irqstatus_raw0) {
1311 __raw_writel(old0 | l, bank->base +
1312 bank->regs->leveldetect0);
1313 __raw_writel(old1 | l, bank->base +
1314 bank->regs->leveldetect1);
1315 }
1316 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1317 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1318 }
1319
1320 bank->workaround_enabled = false;
1321 spin_unlock_irqrestore(&bank->lock, flags);
1322
1323 return 0;
1324}
1325#endif /* CONFIG_PM_RUNTIME */
1326
1327void omap2_gpio_prepare_for_idle(int pwr_mode)
1328{
1329 struct gpio_bank *bank;
1330
1331 list_for_each_entry(bank, &omap_gpio_list, node) {
1332 if (!bank->mod_usage || !bank->loses_context)
1333 continue;
1334
1335 bank->power_mode = pwr_mode;
1336
1337 pm_runtime_put_sync_suspend(bank->dev);
1338 }
1339}
1340
1341void omap2_gpio_resume_after_idle(void)
1342{
1343 struct gpio_bank *bank;
1344
1345 list_for_each_entry(bank, &omap_gpio_list, node) {
1346 if (!bank->mod_usage || !bank->loses_context)
1347 continue;
1348
1349 pm_runtime_get_sync(bank->dev);
1350 }
1351}
1352
1353#if defined(CONFIG_PM_RUNTIME)
1354static void omap_gpio_restore_context(struct gpio_bank *bank)
1355{
1356 __raw_writel(bank->context.wake_en,
1357 bank->base + bank->regs->wkup_en);
1358 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1359 __raw_writel(bank->context.leveldetect0,
1360 bank->base + bank->regs->leveldetect0);
1361 __raw_writel(bank->context.leveldetect1,
1362 bank->base + bank->regs->leveldetect1);
1363 __raw_writel(bank->context.risingdetect,
1364 bank->base + bank->regs->risingdetect);
1365 __raw_writel(bank->context.fallingdetect,
1366 bank->base + bank->regs->fallingdetect);
1367 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1368 __raw_writel(bank->context.dataout,
1369 bank->base + bank->regs->set_dataout);
1370 else
1371 __raw_writel(bank->context.dataout,
1372 bank->base + bank->regs->dataout);
1373 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1374
1375 if (bank->dbck_enable_mask) {
1376 __raw_writel(bank->context.debounce, bank->base +
1377 bank->regs->debounce);
1378 __raw_writel(bank->context.debounce_en,
1379 bank->base + bank->regs->debounce_en);
1380 }
1381
1382 __raw_writel(bank->context.irqenable1,
1383 bank->base + bank->regs->irqenable);
1384 __raw_writel(bank->context.irqenable2,
1385 bank->base + bank->regs->irqenable2);
1386}
1387#endif /* CONFIG_PM_RUNTIME */
1388#else
1389#define omap_gpio_runtime_suspend NULL
1390#define omap_gpio_runtime_resume NULL
1391#endif
1392
1393static const struct dev_pm_ops gpio_pm_ops = {
1394 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1395 NULL)
1396};
1397
1398#if defined(CONFIG_OF)
1399static struct omap_gpio_reg_offs omap2_gpio_regs = {
1400 .revision = OMAP24XX_GPIO_REVISION,
1401 .direction = OMAP24XX_GPIO_OE,
1402 .datain = OMAP24XX_GPIO_DATAIN,
1403 .dataout = OMAP24XX_GPIO_DATAOUT,
1404 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1405 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1406 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1407 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1408 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1409 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1410 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1411 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1412 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1413 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1414 .ctrl = OMAP24XX_GPIO_CTRL,
1415 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1416 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1417 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1418 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1419 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1420};
1421
1422static struct omap_gpio_reg_offs omap4_gpio_regs = {
1423 .revision = OMAP4_GPIO_REVISION,
1424 .direction = OMAP4_GPIO_OE,
1425 .datain = OMAP4_GPIO_DATAIN,
1426 .dataout = OMAP4_GPIO_DATAOUT,
1427 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1428 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1429 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1430 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1431 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1432 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1433 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1434 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1435 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1436 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1437 .ctrl = OMAP4_GPIO_CTRL,
1438 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1439 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1440 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1441 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1442 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1443};
1444
1445static struct omap_gpio_platform_data omap2_pdata = {
1446 .regs = &omap2_gpio_regs,
1447 .bank_width = 32,
1448 .dbck_flag = false,
1449};
1450
1451static struct omap_gpio_platform_data omap3_pdata = {
1452 .regs = &omap2_gpio_regs,
1453 .bank_width = 32,
1454 .dbck_flag = true,
1455};
1456
1457static struct omap_gpio_platform_data omap4_pdata = {
1458 .regs = &omap4_gpio_regs,
1459 .bank_width = 32,
1460 .dbck_flag = true,
1461};
1462
1463static const struct of_device_id omap_gpio_match[] = {
1464 {
1465 .compatible = "ti,omap4-gpio",
1466 .data = &omap4_pdata,
1467 },
1468 {
1469 .compatible = "ti,omap3-gpio",
1470 .data = &omap3_pdata,
1471 },
1472 {
1473 .compatible = "ti,omap2-gpio",
1474 .data = &omap2_pdata,
1475 },
1476 { },
1477};
1478MODULE_DEVICE_TABLE(of, omap_gpio_match);
1479#endif
1480
1481static struct platform_driver omap_gpio_driver = {
1482 .probe = omap_gpio_probe,
1483 .driver = {
1484 .name = "omap_gpio",
1485 .pm = &gpio_pm_ops,
1486 .of_match_table = of_match_ptr(omap_gpio_match),
1487 },
1488};
1489
1490/*
1491 * gpio driver register needs to be done before
1492 * machine_init functions access gpio APIs.
1493 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1494 */
1495static int __init omap_gpio_drv_reg(void)
1496{
1497 return platform_driver_register(&omap_gpio_driver);
1498}
1499postcore_initcall(omap_gpio_drv_reg);
1/*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/syscore_ops.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/device.h>
23#include <linux/pm_runtime.h>
24#include <linux/pm.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/gpio.h>
28#include <linux/bitops.h>
29#include <linux/platform_data/gpio-omap.h>
30
31#define OFF_MODE 1
32#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
33
34static LIST_HEAD(omap_gpio_list);
35
36struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
47 u32 debounce;
48 u32 debounce_en;
49};
50
51struct gpio_bank {
52 struct list_head node;
53 void __iomem *base;
54 int irq;
55 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
58 u32 saved_datain;
59 u32 level_mask;
60 u32 toggle_mask;
61 raw_spinlock_t lock;
62 raw_spinlock_t wa_lock;
63 struct gpio_chip chip;
64 struct clk *dbck;
65 u32 mod_usage;
66 u32 irq_usage;
67 u32 dbck_enable_mask;
68 bool dbck_enabled;
69 bool is_mpuio;
70 bool dbck_flag;
71 bool loses_context;
72 bool context_valid;
73 int stride;
74 u32 width;
75 int context_loss_count;
76 int power_mode;
77 bool workaround_enabled;
78
79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 int (*get_context_loss_count)(struct device *dev);
81
82 struct omap_gpio_reg_offs *regs;
83};
84
85#define GPIO_MOD_CTRL_BIT BIT(0)
86
87#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88#define LINE_USED(line, offset) (line & (BIT(offset)))
89
90static void omap_gpio_unmask_irq(struct irq_data *d);
91
92static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
93{
94 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
95 return gpiochip_get_data(chip);
96}
97
98static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
99 int is_input)
100{
101 void __iomem *reg = bank->base;
102 u32 l;
103
104 reg += bank->regs->direction;
105 l = readl_relaxed(reg);
106 if (is_input)
107 l |= BIT(gpio);
108 else
109 l &= ~(BIT(gpio));
110 writel_relaxed(l, reg);
111 bank->context.oe = l;
112}
113
114
115/* set data out value using dedicate set/clear register */
116static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
117 int enable)
118{
119 void __iomem *reg = bank->base;
120 u32 l = BIT(offset);
121
122 if (enable) {
123 reg += bank->regs->set_dataout;
124 bank->context.dataout |= l;
125 } else {
126 reg += bank->regs->clr_dataout;
127 bank->context.dataout &= ~l;
128 }
129
130 writel_relaxed(l, reg);
131}
132
133/* set data out value using mask register */
134static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
135 int enable)
136{
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = BIT(offset);
139 u32 l;
140
141 l = readl_relaxed(reg);
142 if (enable)
143 l |= gpio_bit;
144 else
145 l &= ~gpio_bit;
146 writel_relaxed(l, reg);
147 bank->context.dataout = l;
148}
149
150static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
151{
152 void __iomem *reg = bank->base + bank->regs->datain;
153
154 return (readl_relaxed(reg) & (BIT(offset))) != 0;
155}
156
157static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
158{
159 void __iomem *reg = bank->base + bank->regs->dataout;
160
161 return (readl_relaxed(reg) & (BIT(offset))) != 0;
162}
163
164static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165{
166 int l = readl_relaxed(base + reg);
167
168 if (set)
169 l |= mask;
170 else
171 l &= ~mask;
172
173 writel_relaxed(l, base + reg);
174}
175
176static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
177{
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
181
182 writel_relaxed(bank->dbck_enable_mask,
183 bank->base + bank->regs->debounce_en);
184 }
185}
186
187static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
188{
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
190 /*
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
194 */
195 writel_relaxed(0, bank->base + bank->regs->debounce_en);
196
197 clk_disable(bank->dbck);
198 bank->dbck_enabled = false;
199 }
200}
201
202/**
203 * omap2_set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @offset: the gpio number on this @bank
206 * @debounce: debounce time to use
207 *
208 * OMAP's debounce time is in 31us steps
209 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210 * so we need to convert and round up to the closest unit.
211 */
212static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
213 unsigned debounce)
214{
215 void __iomem *reg;
216 u32 val;
217 u32 l;
218 bool enable = !!debounce;
219
220 if (!bank->dbck_flag)
221 return;
222
223 if (enable) {
224 debounce = DIV_ROUND_UP(debounce, 31) - 1;
225 debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
226 }
227
228 l = BIT(offset);
229
230 clk_enable(bank->dbck);
231 reg = bank->base + bank->regs->debounce;
232 writel_relaxed(debounce, reg);
233
234 reg = bank->base + bank->regs->debounce_en;
235 val = readl_relaxed(reg);
236
237 if (enable)
238 val |= l;
239 else
240 val &= ~l;
241 bank->dbck_enable_mask = val;
242
243 writel_relaxed(val, reg);
244 clk_disable(bank->dbck);
245 /*
246 * Enable debounce clock per module.
247 * This call is mandatory because in omap_gpio_request() when
248 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
249 * runtime callbck fails to turn on dbck because dbck_enable_mask
250 * used within _gpio_dbck_enable() is still not initialized at
251 * that point. Therefore we have to enable dbck here.
252 */
253 omap_gpio_dbck_enable(bank);
254 if (bank->dbck_enable_mask) {
255 bank->context.debounce = debounce;
256 bank->context.debounce_en = val;
257 }
258}
259
260/**
261 * omap_clear_gpio_debounce - clear debounce settings for a gpio
262 * @bank: the gpio bank we're acting upon
263 * @offset: the gpio number on this @bank
264 *
265 * If a gpio is using debounce, then clear the debounce enable bit and if
266 * this is the only gpio in this bank using debounce, then clear the debounce
267 * time too. The debounce clock will also be disabled when calling this function
268 * if this is the only gpio in the bank using debounce.
269 */
270static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
271{
272 u32 gpio_bit = BIT(offset);
273
274 if (!bank->dbck_flag)
275 return;
276
277 if (!(bank->dbck_enable_mask & gpio_bit))
278 return;
279
280 bank->dbck_enable_mask &= ~gpio_bit;
281 bank->context.debounce_en &= ~gpio_bit;
282 writel_relaxed(bank->context.debounce_en,
283 bank->base + bank->regs->debounce_en);
284
285 if (!bank->dbck_enable_mask) {
286 bank->context.debounce = 0;
287 writel_relaxed(bank->context.debounce, bank->base +
288 bank->regs->debounce);
289 clk_disable(bank->dbck);
290 bank->dbck_enabled = false;
291 }
292}
293
294static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
295 unsigned trigger)
296{
297 void __iomem *base = bank->base;
298 u32 gpio_bit = BIT(gpio);
299
300 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
301 trigger & IRQ_TYPE_LEVEL_LOW);
302 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
303 trigger & IRQ_TYPE_LEVEL_HIGH);
304 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
305 trigger & IRQ_TYPE_EDGE_RISING);
306 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
307 trigger & IRQ_TYPE_EDGE_FALLING);
308
309 bank->context.leveldetect0 =
310 readl_relaxed(bank->base + bank->regs->leveldetect0);
311 bank->context.leveldetect1 =
312 readl_relaxed(bank->base + bank->regs->leveldetect1);
313 bank->context.risingdetect =
314 readl_relaxed(bank->base + bank->regs->risingdetect);
315 bank->context.fallingdetect =
316 readl_relaxed(bank->base + bank->regs->fallingdetect);
317
318 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
319 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
320 bank->context.wake_en =
321 readl_relaxed(bank->base + bank->regs->wkup_en);
322 }
323
324 /* This part needs to be executed always for OMAP{34xx, 44xx} */
325 if (!bank->regs->irqctrl) {
326 /* On omap24xx proceed only when valid GPIO bit is set */
327 if (bank->non_wakeup_gpios) {
328 if (!(bank->non_wakeup_gpios & gpio_bit))
329 goto exit;
330 }
331
332 /*
333 * Log the edge gpio and manually trigger the IRQ
334 * after resume if the input level changes
335 * to avoid irq lost during PER RET/OFF mode
336 * Applies for omap2 non-wakeup gpio and all omap3 gpios
337 */
338 if (trigger & IRQ_TYPE_EDGE_BOTH)
339 bank->enabled_non_wakeup_gpios |= gpio_bit;
340 else
341 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
342 }
343
344exit:
345 bank->level_mask =
346 readl_relaxed(bank->base + bank->regs->leveldetect0) |
347 readl_relaxed(bank->base + bank->regs->leveldetect1);
348}
349
350#ifdef CONFIG_ARCH_OMAP1
351/*
352 * This only applies to chips that can't do both rising and falling edge
353 * detection at once. For all other chips, this function is a noop.
354 */
355static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
356{
357 void __iomem *reg = bank->base;
358 u32 l = 0;
359
360 if (!bank->regs->irqctrl)
361 return;
362
363 reg += bank->regs->irqctrl;
364
365 l = readl_relaxed(reg);
366 if ((l >> gpio) & 1)
367 l &= ~(BIT(gpio));
368 else
369 l |= BIT(gpio);
370
371 writel_relaxed(l, reg);
372}
373#else
374static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
375#endif
376
377static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
378 unsigned trigger)
379{
380 void __iomem *reg = bank->base;
381 void __iomem *base = bank->base;
382 u32 l = 0;
383
384 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
385 omap_set_gpio_trigger(bank, gpio, trigger);
386 } else if (bank->regs->irqctrl) {
387 reg += bank->regs->irqctrl;
388
389 l = readl_relaxed(reg);
390 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
391 bank->toggle_mask |= BIT(gpio);
392 if (trigger & IRQ_TYPE_EDGE_RISING)
393 l |= BIT(gpio);
394 else if (trigger & IRQ_TYPE_EDGE_FALLING)
395 l &= ~(BIT(gpio));
396 else
397 return -EINVAL;
398
399 writel_relaxed(l, reg);
400 } else if (bank->regs->edgectrl1) {
401 if (gpio & 0x08)
402 reg += bank->regs->edgectrl2;
403 else
404 reg += bank->regs->edgectrl1;
405
406 gpio &= 0x07;
407 l = readl_relaxed(reg);
408 l &= ~(3 << (gpio << 1));
409 if (trigger & IRQ_TYPE_EDGE_RISING)
410 l |= 2 << (gpio << 1);
411 if (trigger & IRQ_TYPE_EDGE_FALLING)
412 l |= BIT(gpio << 1);
413
414 /* Enable wake-up during idle for dynamic tick */
415 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
416 bank->context.wake_en =
417 readl_relaxed(bank->base + bank->regs->wkup_en);
418 writel_relaxed(l, reg);
419 }
420 return 0;
421}
422
423static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
424{
425 if (bank->regs->pinctrl) {
426 void __iomem *reg = bank->base + bank->regs->pinctrl;
427
428 /* Claim the pin for MPU */
429 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
430 }
431
432 if (bank->regs->ctrl && !BANK_USED(bank)) {
433 void __iomem *reg = bank->base + bank->regs->ctrl;
434 u32 ctrl;
435
436 ctrl = readl_relaxed(reg);
437 /* Module is enabled, clocks are not gated */
438 ctrl &= ~GPIO_MOD_CTRL_BIT;
439 writel_relaxed(ctrl, reg);
440 bank->context.ctrl = ctrl;
441 }
442}
443
444static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
445{
446 void __iomem *base = bank->base;
447
448 if (bank->regs->wkup_en &&
449 !LINE_USED(bank->mod_usage, offset) &&
450 !LINE_USED(bank->irq_usage, offset)) {
451 /* Disable wake-up during idle for dynamic tick */
452 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
453 bank->context.wake_en =
454 readl_relaxed(bank->base + bank->regs->wkup_en);
455 }
456
457 if (bank->regs->ctrl && !BANK_USED(bank)) {
458 void __iomem *reg = bank->base + bank->regs->ctrl;
459 u32 ctrl;
460
461 ctrl = readl_relaxed(reg);
462 /* Module is disabled, clocks are gated */
463 ctrl |= GPIO_MOD_CTRL_BIT;
464 writel_relaxed(ctrl, reg);
465 bank->context.ctrl = ctrl;
466 }
467}
468
469static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
470{
471 void __iomem *reg = bank->base + bank->regs->direction;
472
473 return readl_relaxed(reg) & BIT(offset);
474}
475
476static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
477{
478 if (!LINE_USED(bank->mod_usage, offset)) {
479 omap_enable_gpio_module(bank, offset);
480 omap_set_gpio_direction(bank, offset, 1);
481 }
482 bank->irq_usage |= BIT(offset);
483}
484
485static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
486{
487 struct gpio_bank *bank = omap_irq_data_get_bank(d);
488 int retval;
489 unsigned long flags;
490 unsigned offset = d->hwirq;
491
492 if (type & ~IRQ_TYPE_SENSE_MASK)
493 return -EINVAL;
494
495 if (!bank->regs->leveldetect0 &&
496 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
497 return -EINVAL;
498
499 raw_spin_lock_irqsave(&bank->lock, flags);
500 retval = omap_set_gpio_triggering(bank, offset, type);
501 if (retval) {
502 raw_spin_unlock_irqrestore(&bank->lock, flags);
503 goto error;
504 }
505 omap_gpio_init_irq(bank, offset);
506 if (!omap_gpio_is_input(bank, offset)) {
507 raw_spin_unlock_irqrestore(&bank->lock, flags);
508 retval = -EINVAL;
509 goto error;
510 }
511 raw_spin_unlock_irqrestore(&bank->lock, flags);
512
513 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
514 irq_set_handler_locked(d, handle_level_irq);
515 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
516 irq_set_handler_locked(d, handle_edge_irq);
517
518 return 0;
519
520error:
521 return retval;
522}
523
524static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
525{
526 void __iomem *reg = bank->base;
527
528 reg += bank->regs->irqstatus;
529 writel_relaxed(gpio_mask, reg);
530
531 /* Workaround for clearing DSP GPIO interrupts to allow retention */
532 if (bank->regs->irqstatus2) {
533 reg = bank->base + bank->regs->irqstatus2;
534 writel_relaxed(gpio_mask, reg);
535 }
536
537 /* Flush posted write for the irq status to avoid spurious interrupts */
538 readl_relaxed(reg);
539}
540
541static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
542 unsigned offset)
543{
544 omap_clear_gpio_irqbank(bank, BIT(offset));
545}
546
547static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
548{
549 void __iomem *reg = bank->base;
550 u32 l;
551 u32 mask = (BIT(bank->width)) - 1;
552
553 reg += bank->regs->irqenable;
554 l = readl_relaxed(reg);
555 if (bank->regs->irqenable_inv)
556 l = ~l;
557 l &= mask;
558 return l;
559}
560
561static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
562{
563 void __iomem *reg = bank->base;
564 u32 l;
565
566 if (bank->regs->set_irqenable) {
567 reg += bank->regs->set_irqenable;
568 l = gpio_mask;
569 bank->context.irqenable1 |= gpio_mask;
570 } else {
571 reg += bank->regs->irqenable;
572 l = readl_relaxed(reg);
573 if (bank->regs->irqenable_inv)
574 l &= ~gpio_mask;
575 else
576 l |= gpio_mask;
577 bank->context.irqenable1 = l;
578 }
579
580 writel_relaxed(l, reg);
581}
582
583static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
584{
585 void __iomem *reg = bank->base;
586 u32 l;
587
588 if (bank->regs->clr_irqenable) {
589 reg += bank->regs->clr_irqenable;
590 l = gpio_mask;
591 bank->context.irqenable1 &= ~gpio_mask;
592 } else {
593 reg += bank->regs->irqenable;
594 l = readl_relaxed(reg);
595 if (bank->regs->irqenable_inv)
596 l |= gpio_mask;
597 else
598 l &= ~gpio_mask;
599 bank->context.irqenable1 = l;
600 }
601
602 writel_relaxed(l, reg);
603}
604
605static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
606 unsigned offset, int enable)
607{
608 if (enable)
609 omap_enable_gpio_irqbank(bank, BIT(offset));
610 else
611 omap_disable_gpio_irqbank(bank, BIT(offset));
612}
613
614/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
615static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
616{
617 struct gpio_bank *bank = omap_irq_data_get_bank(d);
618
619 return irq_set_irq_wake(bank->irq, enable);
620}
621
622static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
623{
624 struct gpio_bank *bank = gpiochip_get_data(chip);
625 unsigned long flags;
626
627 /*
628 * If this is the first gpio_request for the bank,
629 * enable the bank module.
630 */
631 if (!BANK_USED(bank))
632 pm_runtime_get_sync(chip->parent);
633
634 raw_spin_lock_irqsave(&bank->lock, flags);
635 omap_enable_gpio_module(bank, offset);
636 bank->mod_usage |= BIT(offset);
637 raw_spin_unlock_irqrestore(&bank->lock, flags);
638
639 return 0;
640}
641
642static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
643{
644 struct gpio_bank *bank = gpiochip_get_data(chip);
645 unsigned long flags;
646
647 raw_spin_lock_irqsave(&bank->lock, flags);
648 bank->mod_usage &= ~(BIT(offset));
649 if (!LINE_USED(bank->irq_usage, offset)) {
650 omap_set_gpio_direction(bank, offset, 1);
651 omap_clear_gpio_debounce(bank, offset);
652 }
653 omap_disable_gpio_module(bank, offset);
654 raw_spin_unlock_irqrestore(&bank->lock, flags);
655
656 /*
657 * If this is the last gpio to be freed in the bank,
658 * disable the bank module.
659 */
660 if (!BANK_USED(bank))
661 pm_runtime_put(chip->parent);
662}
663
664/*
665 * We need to unmask the GPIO bank interrupt as soon as possible to
666 * avoid missing GPIO interrupts for other lines in the bank.
667 * Then we need to mask-read-clear-unmask the triggered GPIO lines
668 * in the bank to avoid missing nested interrupts for a GPIO line.
669 * If we wait to unmask individual GPIO lines in the bank after the
670 * line's interrupt handler has been run, we may miss some nested
671 * interrupts.
672 */
673static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
674{
675 void __iomem *isr_reg = NULL;
676 u32 isr;
677 unsigned int bit;
678 struct gpio_bank *bank = gpiobank;
679 unsigned long wa_lock_flags;
680 unsigned long lock_flags;
681
682 isr_reg = bank->base + bank->regs->irqstatus;
683 if (WARN_ON(!isr_reg))
684 goto exit;
685
686 pm_runtime_get_sync(bank->chip.parent);
687
688 while (1) {
689 u32 isr_saved, level_mask = 0;
690 u32 enabled;
691
692 raw_spin_lock_irqsave(&bank->lock, lock_flags);
693
694 enabled = omap_get_gpio_irqbank_mask(bank);
695 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
696
697 if (bank->level_mask)
698 level_mask = bank->level_mask & enabled;
699
700 /* clear edge sensitive interrupts before handler(s) are
701 called so that we don't miss any interrupt occurred while
702 executing them */
703 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
704 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
705 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
706
707 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
708
709 if (!isr)
710 break;
711
712 while (isr) {
713 bit = __ffs(isr);
714 isr &= ~(BIT(bit));
715
716 raw_spin_lock_irqsave(&bank->lock, lock_flags);
717 /*
718 * Some chips can't respond to both rising and falling
719 * at the same time. If this irq was requested with
720 * both flags, we need to flip the ICR data for the IRQ
721 * to respond to the IRQ for the opposite direction.
722 * This will be indicated in the bank toggle_mask.
723 */
724 if (bank->toggle_mask & (BIT(bit)))
725 omap_toggle_gpio_edge_triggering(bank, bit);
726
727 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
728
729 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
730
731 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
732 bit));
733
734 raw_spin_unlock_irqrestore(&bank->wa_lock,
735 wa_lock_flags);
736 }
737 }
738exit:
739 pm_runtime_put(bank->chip.parent);
740 return IRQ_HANDLED;
741}
742
743static unsigned int omap_gpio_irq_startup(struct irq_data *d)
744{
745 struct gpio_bank *bank = omap_irq_data_get_bank(d);
746 unsigned long flags;
747 unsigned offset = d->hwirq;
748
749 raw_spin_lock_irqsave(&bank->lock, flags);
750
751 if (!LINE_USED(bank->mod_usage, offset))
752 omap_set_gpio_direction(bank, offset, 1);
753 else if (!omap_gpio_is_input(bank, offset))
754 goto err;
755 omap_enable_gpio_module(bank, offset);
756 bank->irq_usage |= BIT(offset);
757
758 raw_spin_unlock_irqrestore(&bank->lock, flags);
759 omap_gpio_unmask_irq(d);
760
761 return 0;
762err:
763 raw_spin_unlock_irqrestore(&bank->lock, flags);
764 return -EINVAL;
765}
766
767static void omap_gpio_irq_shutdown(struct irq_data *d)
768{
769 struct gpio_bank *bank = omap_irq_data_get_bank(d);
770 unsigned long flags;
771 unsigned offset = d->hwirq;
772
773 raw_spin_lock_irqsave(&bank->lock, flags);
774 bank->irq_usage &= ~(BIT(offset));
775 omap_set_gpio_irqenable(bank, offset, 0);
776 omap_clear_gpio_irqstatus(bank, offset);
777 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
778 if (!LINE_USED(bank->mod_usage, offset))
779 omap_clear_gpio_debounce(bank, offset);
780 omap_disable_gpio_module(bank, offset);
781 raw_spin_unlock_irqrestore(&bank->lock, flags);
782}
783
784static void omap_gpio_irq_bus_lock(struct irq_data *data)
785{
786 struct gpio_bank *bank = omap_irq_data_get_bank(data);
787
788 if (!BANK_USED(bank))
789 pm_runtime_get_sync(bank->chip.parent);
790}
791
792static void gpio_irq_bus_sync_unlock(struct irq_data *data)
793{
794 struct gpio_bank *bank = omap_irq_data_get_bank(data);
795
796 /*
797 * If this is the last IRQ to be freed in the bank,
798 * disable the bank module.
799 */
800 if (!BANK_USED(bank))
801 pm_runtime_put(bank->chip.parent);
802}
803
804static void omap_gpio_ack_irq(struct irq_data *d)
805{
806 struct gpio_bank *bank = omap_irq_data_get_bank(d);
807 unsigned offset = d->hwirq;
808
809 omap_clear_gpio_irqstatus(bank, offset);
810}
811
812static void omap_gpio_mask_irq(struct irq_data *d)
813{
814 struct gpio_bank *bank = omap_irq_data_get_bank(d);
815 unsigned offset = d->hwirq;
816 unsigned long flags;
817
818 raw_spin_lock_irqsave(&bank->lock, flags);
819 omap_set_gpio_irqenable(bank, offset, 0);
820 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
821 raw_spin_unlock_irqrestore(&bank->lock, flags);
822}
823
824static void omap_gpio_unmask_irq(struct irq_data *d)
825{
826 struct gpio_bank *bank = omap_irq_data_get_bank(d);
827 unsigned offset = d->hwirq;
828 u32 trigger = irqd_get_trigger_type(d);
829 unsigned long flags;
830
831 raw_spin_lock_irqsave(&bank->lock, flags);
832 if (trigger)
833 omap_set_gpio_triggering(bank, offset, trigger);
834
835 /* For level-triggered GPIOs, the clearing must be done after
836 * the HW source is cleared, thus after the handler has run */
837 if (bank->level_mask & BIT(offset)) {
838 omap_set_gpio_irqenable(bank, offset, 0);
839 omap_clear_gpio_irqstatus(bank, offset);
840 }
841
842 omap_set_gpio_irqenable(bank, offset, 1);
843 raw_spin_unlock_irqrestore(&bank->lock, flags);
844}
845
846/*---------------------------------------------------------------------*/
847
848static int omap_mpuio_suspend_noirq(struct device *dev)
849{
850 struct platform_device *pdev = to_platform_device(dev);
851 struct gpio_bank *bank = platform_get_drvdata(pdev);
852 void __iomem *mask_reg = bank->base +
853 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
854 unsigned long flags;
855
856 raw_spin_lock_irqsave(&bank->lock, flags);
857 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
858 raw_spin_unlock_irqrestore(&bank->lock, flags);
859
860 return 0;
861}
862
863static int omap_mpuio_resume_noirq(struct device *dev)
864{
865 struct platform_device *pdev = to_platform_device(dev);
866 struct gpio_bank *bank = platform_get_drvdata(pdev);
867 void __iomem *mask_reg = bank->base +
868 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
869 unsigned long flags;
870
871 raw_spin_lock_irqsave(&bank->lock, flags);
872 writel_relaxed(bank->context.wake_en, mask_reg);
873 raw_spin_unlock_irqrestore(&bank->lock, flags);
874
875 return 0;
876}
877
878static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
879 .suspend_noirq = omap_mpuio_suspend_noirq,
880 .resume_noirq = omap_mpuio_resume_noirq,
881};
882
883/* use platform_driver for this. */
884static struct platform_driver omap_mpuio_driver = {
885 .driver = {
886 .name = "mpuio",
887 .pm = &omap_mpuio_dev_pm_ops,
888 },
889};
890
891static struct platform_device omap_mpuio_device = {
892 .name = "mpuio",
893 .id = -1,
894 .dev = {
895 .driver = &omap_mpuio_driver.driver,
896 }
897 /* could list the /proc/iomem resources */
898};
899
900static inline void omap_mpuio_init(struct gpio_bank *bank)
901{
902 platform_set_drvdata(&omap_mpuio_device, bank);
903
904 if (platform_driver_register(&omap_mpuio_driver) == 0)
905 (void) platform_device_register(&omap_mpuio_device);
906}
907
908/*---------------------------------------------------------------------*/
909
910static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
911{
912 struct gpio_bank *bank;
913 unsigned long flags;
914 void __iomem *reg;
915 int dir;
916
917 bank = gpiochip_get_data(chip);
918 reg = bank->base + bank->regs->direction;
919 raw_spin_lock_irqsave(&bank->lock, flags);
920 dir = !!(readl_relaxed(reg) & BIT(offset));
921 raw_spin_unlock_irqrestore(&bank->lock, flags);
922 return dir;
923}
924
925static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
926{
927 struct gpio_bank *bank;
928 unsigned long flags;
929
930 bank = gpiochip_get_data(chip);
931 raw_spin_lock_irqsave(&bank->lock, flags);
932 omap_set_gpio_direction(bank, offset, 1);
933 raw_spin_unlock_irqrestore(&bank->lock, flags);
934 return 0;
935}
936
937static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
938{
939 struct gpio_bank *bank;
940
941 bank = gpiochip_get_data(chip);
942
943 if (omap_gpio_is_input(bank, offset))
944 return omap_get_gpio_datain(bank, offset);
945 else
946 return omap_get_gpio_dataout(bank, offset);
947}
948
949static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
950{
951 struct gpio_bank *bank;
952 unsigned long flags;
953
954 bank = gpiochip_get_data(chip);
955 raw_spin_lock_irqsave(&bank->lock, flags);
956 bank->set_dataout(bank, offset, value);
957 omap_set_gpio_direction(bank, offset, 0);
958 raw_spin_unlock_irqrestore(&bank->lock, flags);
959 return 0;
960}
961
962static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
963 unsigned debounce)
964{
965 struct gpio_bank *bank;
966 unsigned long flags;
967
968 bank = gpiochip_get_data(chip);
969
970 raw_spin_lock_irqsave(&bank->lock, flags);
971 omap2_set_gpio_debounce(bank, offset, debounce);
972 raw_spin_unlock_irqrestore(&bank->lock, flags);
973
974 return 0;
975}
976
977static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
978{
979 struct gpio_bank *bank;
980 unsigned long flags;
981
982 bank = gpiochip_get_data(chip);
983 raw_spin_lock_irqsave(&bank->lock, flags);
984 bank->set_dataout(bank, offset, value);
985 raw_spin_unlock_irqrestore(&bank->lock, flags);
986}
987
988/*---------------------------------------------------------------------*/
989
990static void __init omap_gpio_show_rev(struct gpio_bank *bank)
991{
992 static bool called;
993 u32 rev;
994
995 if (called || bank->regs->revision == USHRT_MAX)
996 return;
997
998 rev = readw_relaxed(bank->base + bank->regs->revision);
999 pr_info("OMAP GPIO hardware version %d.%d\n",
1000 (rev >> 4) & 0x0f, rev & 0x0f);
1001
1002 called = true;
1003}
1004
1005static void omap_gpio_mod_init(struct gpio_bank *bank)
1006{
1007 void __iomem *base = bank->base;
1008 u32 l = 0xffffffff;
1009
1010 if (bank->width == 16)
1011 l = 0xffff;
1012
1013 if (bank->is_mpuio) {
1014 writel_relaxed(l, bank->base + bank->regs->irqenable);
1015 return;
1016 }
1017
1018 omap_gpio_rmw(base, bank->regs->irqenable, l,
1019 bank->regs->irqenable_inv);
1020 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1021 !bank->regs->irqenable_inv);
1022 if (bank->regs->debounce_en)
1023 writel_relaxed(0, base + bank->regs->debounce_en);
1024
1025 /* Save OE default value (0xffffffff) in the context */
1026 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1027 /* Initialize interface clk ungated, module enabled */
1028 if (bank->regs->ctrl)
1029 writel_relaxed(0, base + bank->regs->ctrl);
1030}
1031
1032static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1033{
1034 static int gpio;
1035 int irq_base = 0;
1036 int ret;
1037
1038 /*
1039 * REVISIT eventually switch from OMAP-specific gpio structs
1040 * over to the generic ones
1041 */
1042 bank->chip.request = omap_gpio_request;
1043 bank->chip.free = omap_gpio_free;
1044 bank->chip.get_direction = omap_gpio_get_direction;
1045 bank->chip.direction_input = omap_gpio_input;
1046 bank->chip.get = omap_gpio_get;
1047 bank->chip.direction_output = omap_gpio_output;
1048 bank->chip.set_debounce = omap_gpio_debounce;
1049 bank->chip.set = omap_gpio_set;
1050 if (bank->is_mpuio) {
1051 bank->chip.label = "mpuio";
1052 if (bank->regs->wkup_en)
1053 bank->chip.parent = &omap_mpuio_device.dev;
1054 bank->chip.base = OMAP_MPUIO(0);
1055 } else {
1056 bank->chip.label = "gpio";
1057 bank->chip.base = gpio;
1058 }
1059 bank->chip.ngpio = bank->width;
1060
1061 ret = gpiochip_add_data(&bank->chip, bank);
1062 if (ret) {
1063 dev_err(bank->chip.parent,
1064 "Could not register gpio chip %d\n", ret);
1065 return ret;
1066 }
1067
1068 if (!bank->is_mpuio)
1069 gpio += bank->width;
1070
1071#ifdef CONFIG_ARCH_OMAP1
1072 /*
1073 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1074 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1075 */
1076 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1077 if (irq_base < 0) {
1078 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1079 return -ENODEV;
1080 }
1081#endif
1082
1083 /* MPUIO is a bit different, reading IRQ status clears it */
1084 if (bank->is_mpuio) {
1085 irqc->irq_ack = dummy_irq_chip.irq_ack;
1086 if (!bank->regs->wkup_en)
1087 irqc->irq_set_wake = NULL;
1088 }
1089
1090 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1091 irq_base, handle_bad_irq,
1092 IRQ_TYPE_NONE);
1093
1094 if (ret) {
1095 dev_err(bank->chip.parent,
1096 "Couldn't add irqchip to gpiochip %d\n", ret);
1097 gpiochip_remove(&bank->chip);
1098 return -ENODEV;
1099 }
1100
1101 gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1102
1103 ret = devm_request_irq(bank->chip.parent, bank->irq,
1104 omap_gpio_irq_handler,
1105 0, dev_name(bank->chip.parent), bank);
1106 if (ret)
1107 gpiochip_remove(&bank->chip);
1108
1109 return ret;
1110}
1111
1112static const struct of_device_id omap_gpio_match[];
1113
1114static int omap_gpio_probe(struct platform_device *pdev)
1115{
1116 struct device *dev = &pdev->dev;
1117 struct device_node *node = dev->of_node;
1118 const struct of_device_id *match;
1119 const struct omap_gpio_platform_data *pdata;
1120 struct resource *res;
1121 struct gpio_bank *bank;
1122 struct irq_chip *irqc;
1123 int ret;
1124
1125 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1126
1127 pdata = match ? match->data : dev_get_platdata(dev);
1128 if (!pdata)
1129 return -EINVAL;
1130
1131 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1132 if (!bank) {
1133 dev_err(dev, "Memory alloc failed\n");
1134 return -ENOMEM;
1135 }
1136
1137 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1138 if (!irqc)
1139 return -ENOMEM;
1140
1141 irqc->irq_startup = omap_gpio_irq_startup,
1142 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1143 irqc->irq_ack = omap_gpio_ack_irq,
1144 irqc->irq_mask = omap_gpio_mask_irq,
1145 irqc->irq_unmask = omap_gpio_unmask_irq,
1146 irqc->irq_set_type = omap_gpio_irq_type,
1147 irqc->irq_set_wake = omap_gpio_wake_enable,
1148 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1149 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1150 irqc->name = dev_name(&pdev->dev);
1151 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1152
1153 bank->irq = platform_get_irq(pdev, 0);
1154 if (bank->irq <= 0) {
1155 if (!bank->irq)
1156 bank->irq = -ENXIO;
1157 if (bank->irq != -EPROBE_DEFER)
1158 dev_err(dev,
1159 "can't get irq resource ret=%d\n", bank->irq);
1160 return bank->irq;
1161 }
1162
1163 bank->chip.parent = dev;
1164 bank->chip.owner = THIS_MODULE;
1165 bank->dbck_flag = pdata->dbck_flag;
1166 bank->stride = pdata->bank_stride;
1167 bank->width = pdata->bank_width;
1168 bank->is_mpuio = pdata->is_mpuio;
1169 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1170 bank->regs = pdata->regs;
1171#ifdef CONFIG_OF_GPIO
1172 bank->chip.of_node = of_node_get(node);
1173#endif
1174 if (node) {
1175 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1176 bank->loses_context = true;
1177 } else {
1178 bank->loses_context = pdata->loses_context;
1179
1180 if (bank->loses_context)
1181 bank->get_context_loss_count =
1182 pdata->get_context_loss_count;
1183 }
1184
1185 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1186 bank->set_dataout = omap_set_gpio_dataout_reg;
1187 else
1188 bank->set_dataout = omap_set_gpio_dataout_mask;
1189
1190 raw_spin_lock_init(&bank->lock);
1191 raw_spin_lock_init(&bank->wa_lock);
1192
1193 /* Static mapping, never released */
1194 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1195 bank->base = devm_ioremap_resource(dev, res);
1196 if (IS_ERR(bank->base)) {
1197 return PTR_ERR(bank->base);
1198 }
1199
1200 if (bank->dbck_flag) {
1201 bank->dbck = devm_clk_get(dev, "dbclk");
1202 if (IS_ERR(bank->dbck)) {
1203 dev_err(dev,
1204 "Could not get gpio dbck. Disable debounce\n");
1205 bank->dbck_flag = false;
1206 } else {
1207 clk_prepare(bank->dbck);
1208 }
1209 }
1210
1211 platform_set_drvdata(pdev, bank);
1212
1213 pm_runtime_enable(dev);
1214 pm_runtime_irq_safe(dev);
1215 pm_runtime_get_sync(dev);
1216
1217 if (bank->is_mpuio)
1218 omap_mpuio_init(bank);
1219
1220 omap_gpio_mod_init(bank);
1221
1222 ret = omap_gpio_chip_init(bank, irqc);
1223 if (ret) {
1224 pm_runtime_put_sync(dev);
1225 pm_runtime_disable(dev);
1226 return ret;
1227 }
1228
1229 omap_gpio_show_rev(bank);
1230
1231 pm_runtime_put(dev);
1232
1233 list_add_tail(&bank->node, &omap_gpio_list);
1234
1235 return 0;
1236}
1237
1238static int omap_gpio_remove(struct platform_device *pdev)
1239{
1240 struct gpio_bank *bank = platform_get_drvdata(pdev);
1241
1242 list_del(&bank->node);
1243 gpiochip_remove(&bank->chip);
1244 pm_runtime_disable(&pdev->dev);
1245 if (bank->dbck_flag)
1246 clk_unprepare(bank->dbck);
1247
1248 return 0;
1249}
1250
1251#ifdef CONFIG_ARCH_OMAP2PLUS
1252
1253#if defined(CONFIG_PM)
1254static void omap_gpio_restore_context(struct gpio_bank *bank);
1255
1256static int omap_gpio_runtime_suspend(struct device *dev)
1257{
1258 struct platform_device *pdev = to_platform_device(dev);
1259 struct gpio_bank *bank = platform_get_drvdata(pdev);
1260 u32 l1 = 0, l2 = 0;
1261 unsigned long flags;
1262 u32 wake_low, wake_hi;
1263
1264 raw_spin_lock_irqsave(&bank->lock, flags);
1265
1266 /*
1267 * Only edges can generate a wakeup event to the PRCM.
1268 *
1269 * Therefore, ensure any wake-up capable GPIOs have
1270 * edge-detection enabled before going idle to ensure a wakeup
1271 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1272 * NDA TRM 25.5.3.1)
1273 *
1274 * The normal values will be restored upon ->runtime_resume()
1275 * by writing back the values saved in bank->context.
1276 */
1277 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1278 if (wake_low)
1279 writel_relaxed(wake_low | bank->context.fallingdetect,
1280 bank->base + bank->regs->fallingdetect);
1281 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1282 if (wake_hi)
1283 writel_relaxed(wake_hi | bank->context.risingdetect,
1284 bank->base + bank->regs->risingdetect);
1285
1286 if (!bank->enabled_non_wakeup_gpios)
1287 goto update_gpio_context_count;
1288
1289 if (bank->power_mode != OFF_MODE) {
1290 bank->power_mode = 0;
1291 goto update_gpio_context_count;
1292 }
1293 /*
1294 * If going to OFF, remove triggering for all
1295 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1296 * generated. See OMAP2420 Errata item 1.101.
1297 */
1298 bank->saved_datain = readl_relaxed(bank->base +
1299 bank->regs->datain);
1300 l1 = bank->context.fallingdetect;
1301 l2 = bank->context.risingdetect;
1302
1303 l1 &= ~bank->enabled_non_wakeup_gpios;
1304 l2 &= ~bank->enabled_non_wakeup_gpios;
1305
1306 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1307 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1308
1309 bank->workaround_enabled = true;
1310
1311update_gpio_context_count:
1312 if (bank->get_context_loss_count)
1313 bank->context_loss_count =
1314 bank->get_context_loss_count(dev);
1315
1316 omap_gpio_dbck_disable(bank);
1317 raw_spin_unlock_irqrestore(&bank->lock, flags);
1318
1319 return 0;
1320}
1321
1322static void omap_gpio_init_context(struct gpio_bank *p);
1323
1324static int omap_gpio_runtime_resume(struct device *dev)
1325{
1326 struct platform_device *pdev = to_platform_device(dev);
1327 struct gpio_bank *bank = platform_get_drvdata(pdev);
1328 u32 l = 0, gen, gen0, gen1;
1329 unsigned long flags;
1330 int c;
1331
1332 raw_spin_lock_irqsave(&bank->lock, flags);
1333
1334 /*
1335 * On the first resume during the probe, the context has not
1336 * been initialised and so initialise it now. Also initialise
1337 * the context loss count.
1338 */
1339 if (bank->loses_context && !bank->context_valid) {
1340 omap_gpio_init_context(bank);
1341
1342 if (bank->get_context_loss_count)
1343 bank->context_loss_count =
1344 bank->get_context_loss_count(dev);
1345 }
1346
1347 omap_gpio_dbck_enable(bank);
1348
1349 /*
1350 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1351 * GPIOs were set to edge trigger also in order to be able to
1352 * generate a PRCM wakeup. Here we restore the
1353 * pre-runtime_suspend() values for edge triggering.
1354 */
1355 writel_relaxed(bank->context.fallingdetect,
1356 bank->base + bank->regs->fallingdetect);
1357 writel_relaxed(bank->context.risingdetect,
1358 bank->base + bank->regs->risingdetect);
1359
1360 if (bank->loses_context) {
1361 if (!bank->get_context_loss_count) {
1362 omap_gpio_restore_context(bank);
1363 } else {
1364 c = bank->get_context_loss_count(dev);
1365 if (c != bank->context_loss_count) {
1366 omap_gpio_restore_context(bank);
1367 } else {
1368 raw_spin_unlock_irqrestore(&bank->lock, flags);
1369 return 0;
1370 }
1371 }
1372 }
1373
1374 if (!bank->workaround_enabled) {
1375 raw_spin_unlock_irqrestore(&bank->lock, flags);
1376 return 0;
1377 }
1378
1379 l = readl_relaxed(bank->base + bank->regs->datain);
1380
1381 /*
1382 * Check if any of the non-wakeup interrupt GPIOs have changed
1383 * state. If so, generate an IRQ by software. This is
1384 * horribly racy, but it's the best we can do to work around
1385 * this silicon bug.
1386 */
1387 l ^= bank->saved_datain;
1388 l &= bank->enabled_non_wakeup_gpios;
1389
1390 /*
1391 * No need to generate IRQs for the rising edge for gpio IRQs
1392 * configured with falling edge only; and vice versa.
1393 */
1394 gen0 = l & bank->context.fallingdetect;
1395 gen0 &= bank->saved_datain;
1396
1397 gen1 = l & bank->context.risingdetect;
1398 gen1 &= ~(bank->saved_datain);
1399
1400 /* FIXME: Consider GPIO IRQs with level detections properly! */
1401 gen = l & (~(bank->context.fallingdetect) &
1402 ~(bank->context.risingdetect));
1403 /* Consider all GPIO IRQs needed to be updated */
1404 gen |= gen0 | gen1;
1405
1406 if (gen) {
1407 u32 old0, old1;
1408
1409 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1410 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1411
1412 if (!bank->regs->irqstatus_raw0) {
1413 writel_relaxed(old0 | gen, bank->base +
1414 bank->regs->leveldetect0);
1415 writel_relaxed(old1 | gen, bank->base +
1416 bank->regs->leveldetect1);
1417 }
1418
1419 if (bank->regs->irqstatus_raw0) {
1420 writel_relaxed(old0 | l, bank->base +
1421 bank->regs->leveldetect0);
1422 writel_relaxed(old1 | l, bank->base +
1423 bank->regs->leveldetect1);
1424 }
1425 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1426 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1427 }
1428
1429 bank->workaround_enabled = false;
1430 raw_spin_unlock_irqrestore(&bank->lock, flags);
1431
1432 return 0;
1433}
1434#endif /* CONFIG_PM */
1435
1436#if IS_BUILTIN(CONFIG_GPIO_OMAP)
1437void omap2_gpio_prepare_for_idle(int pwr_mode)
1438{
1439 struct gpio_bank *bank;
1440
1441 list_for_each_entry(bank, &omap_gpio_list, node) {
1442 if (!BANK_USED(bank) || !bank->loses_context)
1443 continue;
1444
1445 bank->power_mode = pwr_mode;
1446
1447 pm_runtime_put_sync_suspend(bank->chip.parent);
1448 }
1449}
1450
1451void omap2_gpio_resume_after_idle(void)
1452{
1453 struct gpio_bank *bank;
1454
1455 list_for_each_entry(bank, &omap_gpio_list, node) {
1456 if (!BANK_USED(bank) || !bank->loses_context)
1457 continue;
1458
1459 pm_runtime_get_sync(bank->chip.parent);
1460 }
1461}
1462#endif
1463
1464#if defined(CONFIG_PM)
1465static void omap_gpio_init_context(struct gpio_bank *p)
1466{
1467 struct omap_gpio_reg_offs *regs = p->regs;
1468 void __iomem *base = p->base;
1469
1470 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1471 p->context.oe = readl_relaxed(base + regs->direction);
1472 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1473 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1474 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1475 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1476 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1477 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1478 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1479
1480 if (regs->set_dataout && p->regs->clr_dataout)
1481 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1482 else
1483 p->context.dataout = readl_relaxed(base + regs->dataout);
1484
1485 p->context_valid = true;
1486}
1487
1488static void omap_gpio_restore_context(struct gpio_bank *bank)
1489{
1490 writel_relaxed(bank->context.wake_en,
1491 bank->base + bank->regs->wkup_en);
1492 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1493 writel_relaxed(bank->context.leveldetect0,
1494 bank->base + bank->regs->leveldetect0);
1495 writel_relaxed(bank->context.leveldetect1,
1496 bank->base + bank->regs->leveldetect1);
1497 writel_relaxed(bank->context.risingdetect,
1498 bank->base + bank->regs->risingdetect);
1499 writel_relaxed(bank->context.fallingdetect,
1500 bank->base + bank->regs->fallingdetect);
1501 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1502 writel_relaxed(bank->context.dataout,
1503 bank->base + bank->regs->set_dataout);
1504 else
1505 writel_relaxed(bank->context.dataout,
1506 bank->base + bank->regs->dataout);
1507 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1508
1509 if (bank->dbck_enable_mask) {
1510 writel_relaxed(bank->context.debounce, bank->base +
1511 bank->regs->debounce);
1512 writel_relaxed(bank->context.debounce_en,
1513 bank->base + bank->regs->debounce_en);
1514 }
1515
1516 writel_relaxed(bank->context.irqenable1,
1517 bank->base + bank->regs->irqenable);
1518 writel_relaxed(bank->context.irqenable2,
1519 bank->base + bank->regs->irqenable2);
1520}
1521#endif /* CONFIG_PM */
1522#else
1523#define omap_gpio_runtime_suspend NULL
1524#define omap_gpio_runtime_resume NULL
1525static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1526#endif
1527
1528static const struct dev_pm_ops gpio_pm_ops = {
1529 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1530 NULL)
1531};
1532
1533#if defined(CONFIG_OF)
1534static struct omap_gpio_reg_offs omap2_gpio_regs = {
1535 .revision = OMAP24XX_GPIO_REVISION,
1536 .direction = OMAP24XX_GPIO_OE,
1537 .datain = OMAP24XX_GPIO_DATAIN,
1538 .dataout = OMAP24XX_GPIO_DATAOUT,
1539 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1540 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1541 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1542 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1543 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1544 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1545 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1546 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1547 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1548 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1549 .ctrl = OMAP24XX_GPIO_CTRL,
1550 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1551 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1552 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1553 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1554 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1555};
1556
1557static struct omap_gpio_reg_offs omap4_gpio_regs = {
1558 .revision = OMAP4_GPIO_REVISION,
1559 .direction = OMAP4_GPIO_OE,
1560 .datain = OMAP4_GPIO_DATAIN,
1561 .dataout = OMAP4_GPIO_DATAOUT,
1562 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1563 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1564 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1565 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1566 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1567 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1568 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1569 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1570 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1571 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1572 .ctrl = OMAP4_GPIO_CTRL,
1573 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1574 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1575 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1576 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1577 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1578};
1579
1580static const struct omap_gpio_platform_data omap2_pdata = {
1581 .regs = &omap2_gpio_regs,
1582 .bank_width = 32,
1583 .dbck_flag = false,
1584};
1585
1586static const struct omap_gpio_platform_data omap3_pdata = {
1587 .regs = &omap2_gpio_regs,
1588 .bank_width = 32,
1589 .dbck_flag = true,
1590};
1591
1592static const struct omap_gpio_platform_data omap4_pdata = {
1593 .regs = &omap4_gpio_regs,
1594 .bank_width = 32,
1595 .dbck_flag = true,
1596};
1597
1598static const struct of_device_id omap_gpio_match[] = {
1599 {
1600 .compatible = "ti,omap4-gpio",
1601 .data = &omap4_pdata,
1602 },
1603 {
1604 .compatible = "ti,omap3-gpio",
1605 .data = &omap3_pdata,
1606 },
1607 {
1608 .compatible = "ti,omap2-gpio",
1609 .data = &omap2_pdata,
1610 },
1611 { },
1612};
1613MODULE_DEVICE_TABLE(of, omap_gpio_match);
1614#endif
1615
1616static struct platform_driver omap_gpio_driver = {
1617 .probe = omap_gpio_probe,
1618 .remove = omap_gpio_remove,
1619 .driver = {
1620 .name = "omap_gpio",
1621 .pm = &gpio_pm_ops,
1622 .of_match_table = of_match_ptr(omap_gpio_match),
1623 },
1624};
1625
1626/*
1627 * gpio driver register needs to be done before
1628 * machine_init functions access gpio APIs.
1629 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1630 */
1631static int __init omap_gpio_drv_reg(void)
1632{
1633 return platform_driver_register(&omap_gpio_driver);
1634}
1635postcore_initcall(omap_gpio_drv_reg);
1636
1637static void __exit omap_gpio_exit(void)
1638{
1639 platform_driver_unregister(&omap_gpio_driver);
1640}
1641module_exit(omap_gpio_exit);
1642
1643MODULE_DESCRIPTION("omap gpio driver");
1644MODULE_ALIAS("platform:gpio-omap");
1645MODULE_LICENSE("GPL v2");