1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
   7 * Copyright (C) 1995, 1996 Paul M. Antoine
   8 * Copyright (C) 1998 Ulf Carlsson
   9 * Copyright (C) 1999 Silicon Graphics, Inc.
  10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
  12 * Copyright (C) 2002, 2003, 2004, 2005, 2007  Maciej W. Rozycki
 
 
  13 */
 
  14#include <linux/bug.h>
  15#include <linux/compiler.h>
 
 
 
  16#include <linux/init.h>
  17#include <linux/kernel.h>
  18#include <linux/module.h>
 
  19#include <linux/mm.h>
  20#include <linux/sched.h>
 
  21#include <linux/smp.h>
  22#include <linux/spinlock.h>
  23#include <linux/kallsyms.h>
  24#include <linux/bootmem.h>
  25#include <linux/interrupt.h>
  26#include <linux/ptrace.h>
  27#include <linux/kgdb.h>
  28#include <linux/kdebug.h>
  29#include <linux/kprobes.h>
  30#include <linux/notifier.h>
  31#include <linux/kdb.h>
  32#include <linux/irq.h>
  33#include <linux/perf_event.h>
  34
 
  35#include <asm/bootinfo.h>
  36#include <asm/branch.h>
  37#include <asm/break.h>
  38#include <asm/cop2.h>
  39#include <asm/cpu.h>
 
  40#include <asm/dsp.h>
  41#include <asm/fpu.h>
  42#include <asm/fpu_emulator.h>
 
 
 
  43#include <asm/mipsregs.h>
  44#include <asm/mipsmtregs.h>
  45#include <asm/module.h>
 
  46#include <asm/pgtable.h>
  47#include <asm/ptrace.h>
  48#include <asm/sections.h>
 
  49#include <asm/tlbdebug.h>
  50#include <asm/traps.h>
  51#include <asm/uaccess.h>
  52#include <asm/watch.h>
  53#include <asm/mmu_context.h>
  54#include <asm/types.h>
  55#include <asm/stacktrace.h>
  56#include <asm/uasm.h>
  57
  58extern void check_wait(void);
  59extern asmlinkage void r4k_wait(void);
  60extern asmlinkage void rollback_handle_int(void);
  61extern asmlinkage void handle_int(void);
  62extern asmlinkage void handle_tlbm(void);
  63extern asmlinkage void handle_tlbl(void);
  64extern asmlinkage void handle_tlbs(void);
  65extern asmlinkage void handle_adel(void);
  66extern asmlinkage void handle_ades(void);
  67extern asmlinkage void handle_ibe(void);
  68extern asmlinkage void handle_dbe(void);
  69extern asmlinkage void handle_sys(void);
  70extern asmlinkage void handle_bp(void);
  71extern asmlinkage void handle_ri(void);
  72extern asmlinkage void handle_ri_rdhwr_vivt(void);
  73extern asmlinkage void handle_ri_rdhwr(void);
  74extern asmlinkage void handle_cpu(void);
  75extern asmlinkage void handle_ov(void);
  76extern asmlinkage void handle_tr(void);
 
  77extern asmlinkage void handle_fpe(void);
 
 
  78extern asmlinkage void handle_mdmx(void);
  79extern asmlinkage void handle_watch(void);
  80extern asmlinkage void handle_mt(void);
  81extern asmlinkage void handle_dsp(void);
  82extern asmlinkage void handle_mcheck(void);
  83extern asmlinkage void handle_reserved(void);
  84
  85extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
  86				    struct mips_fpu_struct *ctx, int has_fpu,
  87				    void *__user *fault_addr);
  88
  89void (*board_be_init)(void);
  90int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
  91void (*board_nmi_handler_setup)(void);
  92void (*board_ejtag_handler_setup)(void);
  93void (*board_bind_eic_interrupt)(int irq, int regset);
  94void (*board_ebase_setup)(void);
  95void __cpuinitdata(*board_cache_error_setup)(void);
  96
  97static void show_raw_backtrace(unsigned long reg29)
  98{
  99	unsigned long *sp = (unsigned long *)(reg29 & ~3);
 100	unsigned long addr;
 101
 102	printk("Call Trace:");
 103#ifdef CONFIG_KALLSYMS
 104	printk("\n");
 105#endif
 106	while (!kstack_end(sp)) {
 107		unsigned long __user *p =
 108			(unsigned long __user *)(unsigned long)sp++;
 109		if (__get_user(addr, p)) {
 110			printk(" (Bad stack address)");
 111			break;
 112		}
 113		if (__kernel_text_address(addr))
 114			print_ip_sym(addr);
 115	}
 116	printk("\n");
 117}
 118
 119#ifdef CONFIG_KALLSYMS
 120int raw_show_trace;
 121static int __init set_raw_show_trace(char *str)
 122{
 123	raw_show_trace = 1;
 124	return 1;
 125}
 126__setup("raw_show_trace", set_raw_show_trace);
 127#endif
 128
 129static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
 130{
 131	unsigned long sp = regs->regs[29];
 132	unsigned long ra = regs->regs[31];
 133	unsigned long pc = regs->cp0_epc;
 134
 135	if (!task)
 136		task = current;
 137
 138	if (raw_show_trace || !__kernel_text_address(pc)) {
 139		show_raw_backtrace(sp);
 140		return;
 141	}
 142	printk("Call Trace:\n");
 143	do {
 144		print_ip_sym(pc);
 145		pc = unwind_stack(task, &sp, pc, &ra);
 146	} while (pc);
 147	printk("\n");
 148}
 149
 150/*
 151 * This routine abuses get_user()/put_user() to reference pointers
 152 * with at least a bit of error checking ...
 153 */
 154static void show_stacktrace(struct task_struct *task,
 155	const struct pt_regs *regs)
 156{
 157	const int field = 2 * sizeof(unsigned long);
 158	long stackdata;
 159	int i;
 160	unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
 161
 162	printk("Stack :");
 163	i = 0;
 164	while ((unsigned long) sp & (PAGE_SIZE - 1)) {
 165		if (i && ((i % (64 / field)) == 0))
 166			printk("\n       ");
 
 
 167		if (i > 39) {
 168			printk(" ...");
 169			break;
 170		}
 171
 172		if (__get_user(stackdata, sp++)) {
 173			printk(" (Bad stack address)");
 174			break;
 175		}
 176
 177		printk(" %0*lx", field, stackdata);
 178		i++;
 179	}
 180	printk("\n");
 181	show_backtrace(task, regs);
 182}
 183
 184void show_stack(struct task_struct *task, unsigned long *sp)
 185{
 186	struct pt_regs regs;
 
 
 
 187	if (sp) {
 188		regs.regs[29] = (unsigned long)sp;
 189		regs.regs[31] = 0;
 190		regs.cp0_epc = 0;
 191	} else {
 192		if (task && task != current) {
 193			regs.regs[29] = task->thread.reg29;
 194			regs.regs[31] = 0;
 195			regs.cp0_epc = task->thread.reg31;
 196#ifdef CONFIG_KGDB_KDB
 197		} else if (atomic_read(&kgdb_active) != -1 &&
 198			   kdb_current_regs) {
 199			memcpy(&regs, kdb_current_regs, sizeof(regs));
 200#endif /* CONFIG_KGDB_KDB */
 201		} else {
 202			prepare_frametrace(&regs);
 203		}
 204	}
 
 
 
 
 
 205	show_stacktrace(task, &regs);
 
 206}
 207
 208/*
 209 * The architecture-independent dump_stack generator
 210 */
 211void dump_stack(void)
 212{
 213	struct pt_regs regs;
 214
 215	prepare_frametrace(&regs);
 216	show_backtrace(current, &regs);
 217}
 218
 219EXPORT_SYMBOL(dump_stack);
 220
 221static void show_code(unsigned int __user *pc)
 222{
 223	long i;
 224	unsigned short __user *pc16 = NULL;
 225
 226	printk("\nCode:");
 227
 228	if ((unsigned long)pc & 1)
 229		pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
 230	for(i = -3 ; i < 6 ; i++) {
 231		unsigned int insn;
 232		if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
 233			printk(" (Bad address in epc)\n");
 234			break;
 235		}
 236		printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
 237	}
 
 238}
 239
 240static void __show_regs(const struct pt_regs *regs)
 241{
 242	const int field = 2 * sizeof(unsigned long);
 243	unsigned int cause = regs->cp0_cause;
 
 244	int i;
 245
 246	printk("Cpu %d\n", smp_processor_id());
 247
 248	/*
 249	 * Saved main processor registers
 250	 */
 251	for (i = 0; i < 32; ) {
 252		if ((i % 4) == 0)
 253			printk("$%2d   :", i);
 254		if (i == 0)
 255			printk(" %0*lx", field, 0UL);
 256		else if (i == 26 || i == 27)
 257			printk(" %*s", field, "");
 258		else
 259			printk(" %0*lx", field, regs->regs[i]);
 260
 261		i++;
 262		if ((i % 4) == 0)
 263			printk("\n");
 264	}
 265
 266#ifdef CONFIG_CPU_HAS_SMARTMIPS
 267	printk("Acx    : %0*lx\n", field, regs->acx);
 268#endif
 269	printk("Hi    : %0*lx\n", field, regs->hi);
 270	printk("Lo    : %0*lx\n", field, regs->lo);
 271
 272	/*
 273	 * Saved cp0 registers
 274	 */
 275	printk("epc   : %0*lx %pS\n", field, regs->cp0_epc,
 276	       (void *) regs->cp0_epc);
 277	printk("    %s\n", print_tainted());
 278	printk("ra    : %0*lx %pS\n", field, regs->regs[31],
 279	       (void *) regs->regs[31]);
 280
 281	printk("Status: %08x    ", (uint32_t) regs->cp0_status);
 282
 283	if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
 284		if (regs->cp0_status & ST0_KUO)
 285			printk("KUo ");
 286		if (regs->cp0_status & ST0_IEO)
 287			printk("IEo ");
 288		if (regs->cp0_status & ST0_KUP)
 289			printk("KUp ");
 290		if (regs->cp0_status & ST0_IEP)
 291			printk("IEp ");
 292		if (regs->cp0_status & ST0_KUC)
 293			printk("KUc ");
 294		if (regs->cp0_status & ST0_IEC)
 295			printk("IEc ");
 296	} else {
 297		if (regs->cp0_status & ST0_KX)
 298			printk("KX ");
 299		if (regs->cp0_status & ST0_SX)
 300			printk("SX ");
 301		if (regs->cp0_status & ST0_UX)
 302			printk("UX ");
 303		switch (regs->cp0_status & ST0_KSU) {
 304		case KSU_USER:
 305			printk("USER ");
 306			break;
 307		case KSU_SUPERVISOR:
 308			printk("SUPERVISOR ");
 309			break;
 310		case KSU_KERNEL:
 311			printk("KERNEL ");
 312			break;
 313		default:
 314			printk("BAD_MODE ");
 315			break;
 316		}
 317		if (regs->cp0_status & ST0_ERL)
 318			printk("ERL ");
 319		if (regs->cp0_status & ST0_EXL)
 320			printk("EXL ");
 321		if (regs->cp0_status & ST0_IE)
 322			printk("IE ");
 323	}
 324	printk("\n");
 325
 326	printk("Cause : %08x\n", cause);
 
 327
 328	cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 329	if (1 <= cause && cause <= 5)
 330		printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
 331
 332	printk("PrId  : %08x (%s)\n", read_c0_prid(),
 333	       cpu_name_string());
 334}
 335
 336/*
 337 * FIXME: really the generic show_regs should take a const pointer argument.
 338 */
 339void show_regs(struct pt_regs *regs)
 340{
 341	__show_regs((struct pt_regs *)regs);
 342}
 343
 344void show_registers(struct pt_regs *regs)
 345{
 346	const int field = 2 * sizeof(unsigned long);
 
 347
 348	__show_regs(regs);
 349	print_modules();
 350	printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
 351	       current->comm, current->pid, current_thread_info(), current,
 352	      field, current_thread_info()->tp_value);
 353	if (cpu_has_userlocal) {
 354		unsigned long tls;
 355
 356		tls = read_c0_userlocal();
 357		if (tls != current_thread_info()->tp_value)
 358			printk("*HwTLS: %0*lx\n", field, tls);
 359	}
 360
 
 
 
 361	show_stacktrace(current, regs);
 362	show_code((unsigned int __user *) regs->cp0_epc);
 363	printk("\n");
 364}
 365
 366static int regs_to_trapnr(struct pt_regs *regs)
 367{
 368	return (regs->cp0_cause >> 2) & 0x1f;
 369}
 370
 371static DEFINE_RAW_SPINLOCK(die_lock);
 372
 373void __noreturn die(const char *str, struct pt_regs *regs)
 374{
 375	static int die_counter;
 376	int sig = SIGSEGV;
 377#ifdef CONFIG_MIPS_MT_SMTC
 378	unsigned long dvpret;
 379#endif /* CONFIG_MIPS_MT_SMTC */
 380
 381	oops_enter();
 382
 383	if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
 
 384		sig = 0;
 385
 386	console_verbose();
 387	raw_spin_lock_irq(&die_lock);
 388#ifdef CONFIG_MIPS_MT_SMTC
 389	dvpret = dvpe();
 390#endif /* CONFIG_MIPS_MT_SMTC */
 391	bust_spinlocks(1);
 392#ifdef CONFIG_MIPS_MT_SMTC
 393	mips_mt_regdump(dvpret);
 394#endif /* CONFIG_MIPS_MT_SMTC */
 395
 396	printk("%s[#%d]:\n", str, ++die_counter);
 397	show_registers(regs);
 398	add_taint(TAINT_DIE);
 399	raw_spin_unlock_irq(&die_lock);
 400
 401	oops_exit();
 402
 403	if (in_interrupt())
 404		panic("Fatal exception in interrupt");
 405
 406	if (panic_on_oops) {
 407		printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
 408		ssleep(5);
 409		panic("Fatal exception");
 410	}
 
 
 411
 412	do_exit(sig);
 413}
 414
 415extern struct exception_table_entry __start___dbe_table[];
 416extern struct exception_table_entry __stop___dbe_table[];
 417
 418__asm__(
 419"	.section	__dbe_table, \"a\"\n"
 420"	.previous			\n");
 421
 422/* Given an address, look for it in the exception tables. */
 423static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
 424{
 425	const struct exception_table_entry *e;
 426
 427	e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
 
 428	if (!e)
 429		e = search_module_dbetables(addr);
 430	return e;
 431}
 432
 433asmlinkage void do_be(struct pt_regs *regs)
 434{
 435	const int field = 2 * sizeof(unsigned long);
 436	const struct exception_table_entry *fixup = NULL;
 437	int data = regs->cp0_cause & 4;
 438	int action = MIPS_BE_FATAL;
 
 439
 440	/* XXX For now.  Fixme, this searches the wrong table ...  */
 
 441	if (data && !user_mode(regs))
 442		fixup = search_dbe_tables(exception_epc(regs));
 443
 444	if (fixup)
 445		action = MIPS_BE_FIXUP;
 446
 447	if (board_be_handler)
 448		action = board_be_handler(regs, fixup != NULL);
 
 
 449
 450	switch (action) {
 451	case MIPS_BE_DISCARD:
 452		return;
 453	case MIPS_BE_FIXUP:
 454		if (fixup) {
 455			regs->cp0_epc = fixup->nextinsn;
 456			return;
 457		}
 458		break;
 459	default:
 460		break;
 461	}
 462
 463	/*
 464	 * Assume it would be too dangerous to continue ...
 465	 */
 466	printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
 467	       data ? "Data" : "Instruction",
 468	       field, regs->cp0_epc, field, regs->regs[31]);
 469	if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
 470	    == NOTIFY_STOP)
 471		return;
 472
 473	die_if_kernel("Oops", regs);
 474	force_sig(SIGBUS, current);
 
 
 
 475}
 476
 477/*
 478 * ll/sc, rdhwr, sync emulation
 479 */
 480
 481#define OPCODE 0xfc000000
 482#define BASE   0x03e00000
 483#define RT     0x001f0000
 484#define OFFSET 0x0000ffff
 485#define LL     0xc0000000
 486#define SC     0xe0000000
 487#define SPEC0  0x00000000
 488#define SPEC3  0x7c000000
 489#define RD     0x0000f800
 490#define FUNC   0x0000003f
 491#define SYNC   0x0000000f
 492#define RDHWR  0x0000003b
 493
 
 
 
 
 
 
 494/*
 495 * The ll_bit is cleared by r*_switch.S
 496 */
 497
 498unsigned int ll_bit;
 499struct task_struct *ll_task;
 500
 501static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
 502{
 503	unsigned long value, __user *vaddr;
 504	long offset;
 505
 506	/*
 507	 * analyse the ll instruction that just caused a ri exception
 508	 * and put the referenced address to addr.
 509	 */
 510
 511	/* sign extend offset */
 512	offset = opcode & OFFSET;
 513	offset <<= 16;
 514	offset >>= 16;
 515
 516	vaddr = (unsigned long __user *)
 517	        ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 518
 519	if ((unsigned long)vaddr & 3)
 520		return SIGBUS;
 521	if (get_user(value, vaddr))
 522		return SIGSEGV;
 523
 524	preempt_disable();
 525
 526	if (ll_task == NULL || ll_task == current) {
 527		ll_bit = 1;
 528	} else {
 529		ll_bit = 0;
 530	}
 531	ll_task = current;
 532
 533	preempt_enable();
 534
 535	regs->regs[(opcode & RT) >> 16] = value;
 536
 537	return 0;
 538}
 539
 540static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
 541{
 542	unsigned long __user *vaddr;
 543	unsigned long reg;
 544	long offset;
 545
 546	/*
 547	 * analyse the sc instruction that just caused a ri exception
 548	 * and put the referenced address to addr.
 549	 */
 550
 551	/* sign extend offset */
 552	offset = opcode & OFFSET;
 553	offset <<= 16;
 554	offset >>= 16;
 555
 556	vaddr = (unsigned long __user *)
 557	        ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 558	reg = (opcode & RT) >> 16;
 559
 560	if ((unsigned long)vaddr & 3)
 561		return SIGBUS;
 562
 563	preempt_disable();
 564
 565	if (ll_bit == 0 || ll_task != current) {
 566		regs->regs[reg] = 0;
 567		preempt_enable();
 568		return 0;
 569	}
 570
 571	preempt_enable();
 572
 573	if (put_user(regs->regs[reg], vaddr))
 574		return SIGSEGV;
 575
 576	regs->regs[reg] = 1;
 577
 578	return 0;
 579}
 580
 581/*
 582 * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
 583 * opcodes are supposed to result in coprocessor unusable exceptions if
 584 * executed on ll/sc-less processors.  That's the theory.  In practice a
 585 * few processors such as NEC's VR4100 throw reserved instruction exceptions
 586 * instead, so we're doing the emulation thing in both exception handlers.
 587 */
 588static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
 589{
 590	if ((opcode & OPCODE) == LL) {
 591		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
 592				1, regs, 0);
 593		return simulate_ll(regs, opcode);
 594	}
 595	if ((opcode & OPCODE) == SC) {
 596		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
 597				1, regs, 0);
 598		return simulate_sc(regs, opcode);
 599	}
 600
 601	return -1;			/* Must be something else ... */
 602}
 603
 604/*
 605 * Simulate trapping 'rdhwr' instructions to provide user accessible
 606 * registers not implemented in hardware.
 607 */
 608static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
 609{
 610	struct thread_info *ti = task_thread_info(current);
 611
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 612	if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 613		int rd = (opcode & RD) >> 11;
 614		int rt = (opcode & RT) >> 16;
 615		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
 616				1, regs, 0);
 617		switch (rd) {
 618		case 0:		/* CPU number */
 619			regs->regs[rt] = smp_processor_id();
 620			return 0;
 621		case 1:		/* SYNCI length */
 622			regs->regs[rt] = min(current_cpu_data.dcache.linesz,
 623					     current_cpu_data.icache.linesz);
 624			return 0;
 625		case 2:		/* Read count register */
 626			regs->regs[rt] = read_c0_count();
 627			return 0;
 628		case 3:		/* Count register resolution */
 629			switch (current_cpu_data.cputype) {
 630			case CPU_20KC:
 631			case CPU_25KF:
 632				regs->regs[rt] = 1;
 633				break;
 634			default:
 635				regs->regs[rt] = 2;
 636			}
 637			return 0;
 638		case 29:
 639			regs->regs[rt] = ti->tp_value;
 640			return 0;
 641		default:
 642			return -1;
 643		}
 644	}
 645
 646	/* Not ours.  */
 647	return -1;
 648}
 649
 650static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
 651{
 652	if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
 653		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
 654				1, regs, 0);
 655		return 0;
 656	}
 657
 658	return -1;			/* Must be something else ... */
 659}
 660
 661asmlinkage void do_ov(struct pt_regs *regs)
 662{
 
 663	siginfo_t info;
 664
 
 
 
 
 
 
 665	die_if_kernel("Integer overflow", regs);
 666
 667	info.si_code = FPE_INTOVF;
 668	info.si_signo = SIGFPE;
 669	info.si_errno = 0;
 670	info.si_addr = (void __user *) regs->cp0_epc;
 671	force_sig_info(SIGFPE, &info, current);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 672}
 673
 674static int process_fpemu_return(int sig, void __user *fault_addr)
 675{
 676	if (sig == SIGSEGV || sig == SIGBUS) {
 677		struct siginfo si = {0};
 
 
 
 
 
 
 
 
 
 
 
 678		si.si_addr = fault_addr;
 679		si.si_signo = sig;
 680		if (sig == SIGSEGV) {
 681			if (find_vma(current->mm, (unsigned long)fault_addr))
 682				si.si_code = SEGV_ACCERR;
 683			else
 684				si.si_code = SEGV_MAPERR;
 685		} else {
 686			si.si_code = BUS_ADRERR;
 687		}
 688		force_sig_info(sig, &si, current);
 689		return 1;
 690	} else if (sig) {
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 691		force_sig(sig, current);
 692		return 1;
 693	} else {
 694		return 0;
 695	}
 696}
 697
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 698/*
 699 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
 700 */
 701asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 702{
 703	siginfo_t info = {0};
 
 
 
 
 
 
 
 
 
 
 
 704
 705	if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
 706	    == NOTIFY_STOP)
 707		return;
 708	die_if_kernel("FP exception in kernel code", regs);
 709
 710	if (fcr31 & FPU_CSR_UNI_X) {
 711		int sig;
 712		void __user *fault_addr = NULL;
 713
 714		/*
 715		 * Unimplemented operation exception.  If we've got the full
 716		 * software emulator on-board, let's use it...
 717		 *
 718		 * Force FPU to dump state into task/thread context.  We're
 719		 * moving a lot of data here for what is probably a single
 720		 * instruction, but the alternative is to pre-decode the FP
 721		 * register operands before invoking the emulator, which seems
 722		 * a bit extreme for what should be an infrequent event.
 723		 */
 724		/* Ensure 'resume' not overwrite saved fp context again. */
 725		lose_fpu(1);
 726
 727		/* Run the emulator */
 728		sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
 729					       &fault_addr);
 730
 731		/*
 732		 * We can't allow the emulated instruction to leave any of
 733		 * the cause bit set in $fcr31.
 734		 */
 735		current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
 
 736
 737		/* Restore the hardware register state */
 738		own_fpu(1);	/* Using the FPU again.  */
 
 
 
 
 739
 740		/* If something went wrong, signal */
 741		process_fpemu_return(sig, fault_addr);
 742
 743		return;
 744	} else if (fcr31 & FPU_CSR_INV_X)
 745		info.si_code = FPE_FLTINV;
 746	else if (fcr31 & FPU_CSR_DIV_X)
 747		info.si_code = FPE_FLTDIV;
 748	else if (fcr31 & FPU_CSR_OVF_X)
 749		info.si_code = FPE_FLTOVF;
 750	else if (fcr31 & FPU_CSR_UDF_X)
 751		info.si_code = FPE_FLTUND;
 752	else if (fcr31 & FPU_CSR_INE_X)
 753		info.si_code = FPE_FLTRES;
 754	else
 755		info.si_code = __SI_FAULT;
 756	info.si_signo = SIGFPE;
 757	info.si_errno = 0;
 758	info.si_addr = (void __user *) regs->cp0_epc;
 759	force_sig_info(SIGFPE, &info, current);
 760}
 761
 762static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
 763	const char *str)
 764{
 765	siginfo_t info;
 766	char b[40];
 767
 
 768#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
 769	if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
 
 770		return;
 771#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
 772
 773	if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
 
 774		return;
 775
 776	/*
 777	 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
 778	 * insns, even for trap and break codes that indicate arithmetic
 779	 * failures.  Weird ...
 780	 * But should we continue the brokenness???  --macro
 781	 */
 782	switch (code) {
 783	case BRK_OVERFLOW:
 784	case BRK_DIVZERO:
 785		scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
 786		die_if_kernel(b, regs);
 787		if (code == BRK_DIVZERO)
 788			info.si_code = FPE_INTDIV;
 789		else
 790			info.si_code = FPE_INTOVF;
 791		info.si_signo = SIGFPE;
 792		info.si_errno = 0;
 793		info.si_addr = (void __user *) regs->cp0_epc;
 794		force_sig_info(SIGFPE, &info, current);
 795		break;
 796	case BRK_BUG:
 797		die_if_kernel("Kernel bug detected", regs);
 798		force_sig(SIGTRAP, current);
 799		break;
 800	case BRK_MEMU:
 801		/*
 802		 * Address errors may be deliberately induced by the FPU
 803		 * emulator to retake control of the CPU after executing the
 804		 * instruction in the delay slot of an emulated branch.
 805		 *
 806		 * Terminate if exception was recognized as a delay slot return
 807		 * otherwise handle as normal.
 808		 */
 809		if (do_dsemulret(regs))
 810			return;
 811
 812		die_if_kernel("Math emu break/trap", regs);
 813		force_sig(SIGTRAP, current);
 814		break;
 815	default:
 816		scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
 817		die_if_kernel(b, regs);
 818		force_sig(SIGTRAP, current);
 
 
 
 
 
 
 819	}
 820}
 821
 822asmlinkage void do_bp(struct pt_regs *regs)
 823{
 
 824	unsigned int opcode, bcode;
 
 
 825
 826	if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
 827		goto out_sigsegv;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 828
 829	/*
 830	 * There is the ancient bug in the MIPS assemblers that the break
 831	 * code starts left to bit 16 instead to bit 6 in the opcode.
 832	 * Gas is bug-compatible, but not always, grrr...
 833	 * We handle both cases with a simple heuristics.  --macro
 834	 */
 835	bcode = ((opcode >> 6) & ((1 << 20) - 1));
 836	if (bcode >= (1 << 10))
 837		bcode >>= 10;
 838
 839	/*
 840	 * notify the kprobe handlers, if instruction is likely to
 841	 * pertain to them.
 842	 */
 843	switch (bcode) {
 
 
 
 
 
 
 
 
 
 
 
 
 844	case BRK_KPROBE_BP:
 845		if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
 846			return;
 
 847		else
 848			break;
 849	case BRK_KPROBE_SSTEPBP:
 850		if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
 851			return;
 
 852		else
 853			break;
 854	default:
 855		break;
 856	}
 857
 858	do_trap_or_bp(regs, bcode, "Break");
 
 
 
 
 859	return;
 860
 861out_sigsegv:
 862	force_sig(SIGSEGV, current);
 
 863}
 864
 865asmlinkage void do_tr(struct pt_regs *regs)
 866{
 867	unsigned int opcode, tcode = 0;
 868
 869	if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
 870		goto out_sigsegv;
 871
 872	/* Immediate versions don't provide a code.  */
 873	if (!(opcode & OPCODE))
 874		tcode = ((opcode >> 6) & ((1 << 10) - 1));
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 875
 876	do_trap_or_bp(regs, tcode, "Trap");
 
 
 
 
 877	return;
 878
 879out_sigsegv:
 880	force_sig(SIGSEGV, current);
 
 881}
 882
 883asmlinkage void do_ri(struct pt_regs *regs)
 884{
 885	unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
 886	unsigned long old_epc = regs->cp0_epc;
 
 
 887	unsigned int opcode = 0;
 888	int status = -1;
 889
 890	if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
 891	    == NOTIFY_STOP)
 892		return;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 893
 894	die_if_kernel("Reserved instruction in kernel code", regs);
 895
 896	if (unlikely(compute_return_epc(regs) < 0))
 897		return;
 
 
 
 
 898
 899	if (unlikely(get_user(opcode, epc) < 0))
 900		status = SIGSEGV;
 901
 902	if (!cpu_has_llsc && status < 0)
 903		status = simulate_llsc(regs, opcode);
 904
 905	if (status < 0)
 906		status = simulate_rdhwr(regs, opcode);
 907
 908	if (status < 0)
 909		status = simulate_sync(regs, opcode);
 
 
 
 
 
 
 
 
 
 
 
 
 
 910
 911	if (status < 0)
 912		status = SIGILL;
 913
 914	if (unlikely(status > 0)) {
 915		regs->cp0_epc = old_epc;		/* Undo skip-over.  */
 
 916		force_sig(status, current);
 917	}
 
 
 
 918}
 919
 920/*
 921 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
 922 * emulated more than some threshold number of instructions, force migration to
 923 * a "CPU" that has FP support.
 924 */
 925static void mt_ase_fp_affinity(void)
 926{
 927#ifdef CONFIG_MIPS_MT_FPAFF
 928	if (mt_fpemul_threshold > 0 &&
 929	     ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
 930		/*
 931		 * If there's no FPU present, or if the application has already
 932		 * restricted the allowed set to exclude any CPUs with FPUs,
 933		 * we'll skip the procedure.
 934		 */
 935		if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
 936			cpumask_t tmask;
 937
 938			current->thread.user_cpus_allowed
 939				= current->cpus_allowed;
 940			cpus_and(tmask, current->cpus_allowed,
 941				mt_fpu_cpumask);
 942			set_cpus_allowed_ptr(current, &tmask);
 943			set_thread_flag(TIF_FPUBOUND);
 944		}
 945	}
 946#endif /* CONFIG_MIPS_MT_FPAFF */
 947}
 948
 949/*
 950 * No lock; only written during early bootup by CPU 0.
 951 */
 952static RAW_NOTIFIER_HEAD(cu2_chain);
 953
 954int __ref register_cu2_notifier(struct notifier_block *nb)
 955{
 956	return raw_notifier_chain_register(&cu2_chain, nb);
 957}
 958
 959int cu2_notifier_call_chain(unsigned long val, void *v)
 960{
 961	return raw_notifier_call_chain(&cu2_chain, val, v);
 962}
 963
 964static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
 965        void *data)
 966{
 967	struct pt_regs *regs = data;
 968
 969	switch (action) {
 970	default:
 971		die_if_kernel("Unhandled kernel unaligned access or invalid "
 972			      "instruction", regs);
 973		/* Fall through  */
 974
 975	case CU2_EXCEPTION:
 976		force_sig(SIGILL, current);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 977	}
 978
 979	return NOTIFY_OK;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 980}
 981
 982asmlinkage void do_cpu(struct pt_regs *regs)
 983{
 
 984	unsigned int __user *epc;
 985	unsigned long old_epc;
 
 986	unsigned int opcode;
 
 987	unsigned int cpid;
 988	int status;
 989	unsigned long __maybe_unused flags;
 990
 991	die_if_kernel("do_cpu invoked from kernel context!", regs);
 992
 
 993	cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
 994
 
 
 
 995	switch (cpid) {
 996	case 0:
 997		epc = (unsigned int __user *)exception_epc(regs);
 998		old_epc = regs->cp0_epc;
 
 999		opcode = 0;
1000		status = -1;
1001
1002		if (unlikely(compute_return_epc(regs) < 0))
1003			return;
1004
1005		if (unlikely(get_user(opcode, epc) < 0))
1006			status = SIGSEGV;
 
1007
1008		if (!cpu_has_llsc && status < 0)
1009			status = simulate_llsc(regs, opcode);
1010
1011		if (status < 0)
1012			status = simulate_rdhwr(regs, opcode);
1013
1014		if (status < 0)
1015			status = SIGILL;
1016
1017		if (unlikely(status > 0)) {
1018			regs->cp0_epc = old_epc;	/* Undo skip-over.  */
 
1019			force_sig(status, current);
1020		}
1021
1022		return;
1023
1024	case 1:
1025		if (used_math())	/* Using the FPU again.  */
1026			own_fpu(1);
1027		else {			/* First time FPU user.  */
1028			init_fpu();
1029			set_used_math();
 
 
 
 
 
 
 
 
 
 
1030		}
 
1031
1032		if (!raw_cpu_has_fpu) {
1033			int sig;
1034			void __user *fault_addr = NULL;
1035			sig = fpu_emulator_cop1Handler(regs,
1036						       &current->thread.fpu,
1037						       0, &fault_addr);
1038			if (!process_fpemu_return(sig, fault_addr))
1039				mt_ase_fp_affinity();
1040		}
1041
1042		return;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1043
1044	case 2:
1045		raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1046		return;
1047
1048	case 3:
1049		break;
1050	}
1051
1052	force_sig(SIGILL, current);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1053}
1054
1055asmlinkage void do_mdmx(struct pt_regs *regs)
1056{
 
 
 
1057	force_sig(SIGILL, current);
 
1058}
1059
1060/*
1061 * Called with interrupts disabled.
1062 */
1063asmlinkage void do_watch(struct pt_regs *regs)
1064{
1065	u32 cause;
 
 
 
 
 
1066
 
1067	/*
1068	 * Clear WP (bit 22) bit of cause register so we don't loop
1069	 * forever.
1070	 */
1071	cause = read_c0_cause();
1072	cause &= ~(1 << 22);
1073	write_c0_cause(cause);
1074
1075	/*
1076	 * If the current thread has the watch registers loaded, save
1077	 * their values and send SIGTRAP.  Otherwise another thread
1078	 * left the registers set, clear them and continue.
1079	 */
1080	if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1081		mips_read_watch_registers();
1082		local_irq_enable();
1083		force_sig(SIGTRAP, current);
1084	} else {
1085		mips_clear_watch_registers();
1086		local_irq_enable();
1087	}
 
1088}
1089
1090asmlinkage void do_mcheck(struct pt_regs *regs)
1091{
1092	const int field = 2 * sizeof(unsigned long);
1093	int multi_match = regs->cp0_status & ST0_TS;
 
 
1094
 
1095	show_regs(regs);
1096
1097	if (multi_match) {
1098		printk("Index   : %0x\n", read_c0_index());
1099		printk("Pagemask: %0x\n", read_c0_pagemask());
1100		printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1101		printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1102		printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1103		printk("\n");
1104		dump_tlb_all();
1105	}
1106
 
 
 
1107	show_code((unsigned int __user *) regs->cp0_epc);
1108
 
 
1109	/*
1110	 * Some chips may have other causes of machine check (e.g. SB1
1111	 * graduation timer)
1112	 */
1113	panic("Caught Machine Check exception - %scaused by multiple "
1114	      "matching entries in the TLB.",
1115	      (multi_match) ? "" : "not ");
1116}
1117
1118asmlinkage void do_mt(struct pt_regs *regs)
1119{
1120	int subcode;
1121
1122	subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1123			>> VPECONTROL_EXCPT_SHIFT;
1124	switch (subcode) {
1125	case 0:
1126		printk(KERN_DEBUG "Thread Underflow\n");
1127		break;
1128	case 1:
1129		printk(KERN_DEBUG "Thread Overflow\n");
1130		break;
1131	case 2:
1132		printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1133		break;
1134	case 3:
1135		printk(KERN_DEBUG "Gating Storage Exception\n");
1136		break;
1137	case 4:
1138		printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1139		break;
1140	case 5:
1141		printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1142		break;
1143	default:
1144		printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1145			subcode);
1146		break;
1147	}
1148	die_if_kernel("MIPS MT Thread exception in kernel", regs);
1149
1150	force_sig(SIGILL, current);
1151}
1152
1153
1154asmlinkage void do_dsp(struct pt_regs *regs)
1155{
1156	if (cpu_has_dsp)
1157		panic("Unexpected DSP exception");
1158
1159	force_sig(SIGILL, current);
1160}
1161
1162asmlinkage void do_reserved(struct pt_regs *regs)
1163{
1164	/*
1165	 * Game over - no way to handle this if it ever occurs.  Most probably
1166	 * caused by a new unknown cpu type or after another deadly
1167	 * hard/software error.
1168	 */
1169	show_regs(regs);
1170	panic("Caught reserved exception %ld - should not happen.",
1171	      (regs->cp0_cause & 0x7f) >> 2);
1172}
1173
1174static int __initdata l1parity = 1;
1175static int __init nol1parity(char *s)
1176{
1177	l1parity = 0;
1178	return 1;
1179}
1180__setup("nol1par", nol1parity);
1181static int __initdata l2parity = 1;
1182static int __init nol2parity(char *s)
1183{
1184	l2parity = 0;
1185	return 1;
1186}
1187__setup("nol2par", nol2parity);
1188
1189/*
1190 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1191 * it different ways.
1192 */
1193static inline void parity_protection_init(void)
1194{
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1195	switch (current_cpu_type()) {
1196	case CPU_24K:
1197	case CPU_34K:
1198	case CPU_74K:
1199	case CPU_1004K:
 
 
 
 
 
 
1200		{
1201#define ERRCTL_PE	0x80000000
1202#define ERRCTL_L2P	0x00800000
1203			unsigned long errctl;
1204			unsigned int l1parity_present, l2parity_present;
1205
1206			errctl = read_c0_ecc();
1207			errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1208
1209			/* probe L1 parity support */
1210			write_c0_ecc(errctl | ERRCTL_PE);
1211			back_to_back_c0_hazard();
1212			l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1213
1214			/* probe L2 parity support */
1215			write_c0_ecc(errctl|ERRCTL_L2P);
1216			back_to_back_c0_hazard();
1217			l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1218
1219			if (l1parity_present && l2parity_present) {
1220				if (l1parity)
1221					errctl |= ERRCTL_PE;
1222				if (l1parity ^ l2parity)
1223					errctl |= ERRCTL_L2P;
1224			} else if (l1parity_present) {
1225				if (l1parity)
1226					errctl |= ERRCTL_PE;
1227			} else if (l2parity_present) {
1228				if (l2parity)
1229					errctl |= ERRCTL_L2P;
1230			} else {
1231				/* No parity available */
1232			}
1233
1234			printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1235
1236			write_c0_ecc(errctl);
1237			back_to_back_c0_hazard();
1238			errctl = read_c0_ecc();
1239			printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1240
1241			if (l1parity_present)
1242				printk(KERN_INFO "Cache parity protection %sabled\n",
1243				       (errctl & ERRCTL_PE) ? "en" : "dis");
1244
1245			if (l2parity_present) {
1246				if (l1parity_present && l1parity)
1247					errctl ^= ERRCTL_L2P;
1248				printk(KERN_INFO "L2 cache parity protection %sabled\n",
1249				       (errctl & ERRCTL_L2P) ? "en" : "dis");
1250			}
1251		}
1252		break;
1253
1254	case CPU_5KC:
1255	case CPU_5KE:
 
1256		write_c0_ecc(0x80000000);
1257		back_to_back_c0_hazard();
1258		/* Set the PE bit (bit 31) in the c0_errctl register. */
1259		printk(KERN_INFO "Cache parity protection %sabled\n",
1260		       (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1261		break;
1262	case CPU_20KC:
1263	case CPU_25KF:
1264		/* Clear the DE bit (bit 16) in the c0_status register. */
1265		printk(KERN_INFO "Enable cache parity protection for "
1266		       "MIPS 20KC/25KF CPUs.\n");
1267		clear_c0_status(ST0_DE);
1268		break;
1269	default:
1270		break;
1271	}
1272}
1273
1274asmlinkage void cache_parity_error(void)
1275{
1276	const int field = 2 * sizeof(unsigned long);
1277	unsigned int reg_val;
1278
1279	/* For the moment, report the problem and hang. */
1280	printk("Cache error exception:\n");
1281	printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1282	reg_val = read_c0_cacheerr();
1283	printk("c0_cacheerr == %08x\n", reg_val);
1284
1285	printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1286	       reg_val & (1<<30) ? "secondary" : "primary",
1287	       reg_val & (1<<31) ? "data" : "insn");
1288	printk("Error bits: %s%s%s%s%s%s%s\n",
1289	       reg_val & (1<<29) ? "ED " : "",
1290	       reg_val & (1<<28) ? "ET " : "",
1291	       reg_val & (1<<26) ? "EE " : "",
1292	       reg_val & (1<<25) ? "EB " : "",
1293	       reg_val & (1<<24) ? "EI " : "",
1294	       reg_val & (1<<23) ? "E1 " : "",
1295	       reg_val & (1<<22) ? "E0 " : "");
 
 
 
 
 
 
 
 
 
 
 
 
 
1296	printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1297
1298#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1299	if (reg_val & (1<<22))
1300		printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1301
1302	if (reg_val & (1<<23))
1303		printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1304#endif
1305
1306	panic("Can't handle the cache error!");
1307}
1308
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1309/*
1310 * SDBBP EJTAG debug exception handler.
1311 * We skip the instruction and return to the next instruction.
1312 */
1313void ejtag_exception_handler(struct pt_regs *regs)
1314{
1315	const int field = 2 * sizeof(unsigned long);
1316	unsigned long depc, old_epc;
1317	unsigned int debug;
1318
1319	printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1320	depc = read_c0_depc();
1321	debug = read_c0_debug();
1322	printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1323	if (debug & 0x80000000) {
1324		/*
1325		 * In branch delay slot.
1326		 * We cheat a little bit here and use EPC to calculate the
1327		 * debug return address (DEPC). EPC is restored after the
1328		 * calculation.
1329		 */
1330		old_epc = regs->cp0_epc;
 
1331		regs->cp0_epc = depc;
1332		__compute_return_epc(regs);
1333		depc = regs->cp0_epc;
1334		regs->cp0_epc = old_epc;
 
1335	} else
1336		depc += 4;
1337	write_c0_depc(depc);
1338
1339#if 0
1340	printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1341	write_c0_debug(debug | 0x100);
1342#endif
1343}
1344
1345/*
1346 * NMI exception handler.
1347 * No lock; only written during early bootup by CPU 0.
1348 */
1349static RAW_NOTIFIER_HEAD(nmi_chain);
1350
1351int register_nmi_notifier(struct notifier_block *nb)
1352{
1353	return raw_notifier_chain_register(&nmi_chain, nb);
1354}
1355
1356void __noreturn nmi_exception_handler(struct pt_regs *regs)
1357{
 
 
 
1358	raw_notifier_call_chain(&nmi_chain, 0, regs);
1359	bust_spinlocks(1);
1360	printk("NMI taken!!!!\n");
1361	die("NMI", regs);
 
 
 
1362}
1363
1364#define VECTORSPACING 0x100	/* for EI/VI mode */
1365
1366unsigned long ebase;
 
1367unsigned long exception_handlers[32];
1368unsigned long vi_handlers[64];
1369
1370void __init *set_except_vector(int n, void *addr)
1371{
1372	unsigned long handler = (unsigned long) addr;
1373	unsigned long old_handler = exception_handlers[n];
 
 
 
 
 
 
 
 
 
 
 
 
 
1374
1375	exception_handlers[n] = handler;
1376	if (n == 0 && cpu_has_divec) {
 
 
 
1377		unsigned long jump_mask = ~((1 << 28) - 1);
 
1378		u32 *buf = (u32 *)(ebase + 0x200);
1379		unsigned int k0 = 26;
1380		if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1381			uasm_i_j(&buf, handler & ~jump_mask);
1382			uasm_i_nop(&buf);
1383		} else {
1384			UASM_i_LA(&buf, k0, handler);
1385			uasm_i_jr(&buf, k0);
1386			uasm_i_nop(&buf);
1387		}
1388		local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1389	}
1390	return (void *)old_handler;
1391}
1392
1393static asmlinkage void do_default_vi(void)
1394{
1395	show_regs(get_irq_regs());
1396	panic("Caught unexpected vectored interrupt.");
1397}
1398
1399static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1400{
1401	unsigned long handler;
1402	unsigned long old_handler = vi_handlers[n];
1403	int srssets = current_cpu_data.srsets;
1404	u32 *w;
1405	unsigned char *b;
1406
1407	BUG_ON(!cpu_has_veic && !cpu_has_vint);
1408
1409	if (addr == NULL) {
1410		handler = (unsigned long) do_default_vi;
1411		srs = 0;
1412	} else
1413		handler = (unsigned long) addr;
1414	vi_handlers[n] = (unsigned long) addr;
1415
1416	b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1417
1418	if (srs >= srssets)
1419		panic("Shadow register set %d not supported", srs);
1420
1421	if (cpu_has_veic) {
1422		if (board_bind_eic_interrupt)
1423			board_bind_eic_interrupt(n, srs);
1424	} else if (cpu_has_vint) {
1425		/* SRSMap is only defined if shadow sets are implemented */
1426		if (srssets > 1)
1427			change_c0_srsmap(0xf << n*4, srs << n*4);
1428	}
1429
1430	if (srs == 0) {
1431		/*
1432		 * If no shadow set is selected then use the default handler
1433		 * that does normal register saving and a standard interrupt exit
1434		 */
1435
1436		extern char except_vec_vi, except_vec_vi_lui;
1437		extern char except_vec_vi_ori, except_vec_vi_end;
1438		extern char rollback_except_vec_vi;
1439		char *vec_start = (cpu_wait == r4k_wait) ?
1440			&rollback_except_vec_vi : &except_vec_vi;
1441#ifdef CONFIG_MIPS_MT_SMTC
1442		/*
1443		 * We need to provide the SMTC vectored interrupt handler
1444		 * not only with the address of the handler, but with the
1445		 * Status.IM bit to be masked before going there.
1446		 */
1447		extern char except_vec_vi_mori;
1448		const int mori_offset = &except_vec_vi_mori - vec_start;
1449#endif /* CONFIG_MIPS_MT_SMTC */
1450		const int handler_len = &except_vec_vi_end - vec_start;
1451		const int lui_offset = &except_vec_vi_lui - vec_start;
1452		const int ori_offset = &except_vec_vi_ori - vec_start;
 
 
1453
1454		if (handler_len > VECTORSPACING) {
1455			/*
1456			 * Sigh... panicing won't help as the console
1457			 * is probably not configured :(
1458			 */
1459			panic("VECTORSPACING too small");
1460		}
1461
1462		memcpy(b, vec_start, handler_len);
1463#ifdef CONFIG_MIPS_MT_SMTC
1464		BUG_ON(n > 7);	/* Vector index %d exceeds SMTC maximum. */
1465
1466		w = (u32 *)(b + mori_offset);
1467		*w = (*w & 0xffff0000) | (0x100 << n);
1468#endif /* CONFIG_MIPS_MT_SMTC */
1469		w = (u32 *)(b + lui_offset);
1470		*w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1471		w = (u32 *)(b + ori_offset);
1472		*w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1473		local_flush_icache_range((unsigned long)b,
1474					 (unsigned long)(b+handler_len));
1475	}
1476	else {
1477		/*
1478		 * In other cases jump directly to the interrupt handler
1479		 *
1480		 * It is the handlers responsibility to save registers if required
1481		 * (eg hi/lo) and return from the exception using "eret"
1482		 */
1483		w = (u32 *)b;
1484		*w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1485		*w = 0;
 
 
 
 
 
 
 
 
 
 
1486		local_flush_icache_range((unsigned long)b,
1487					 (unsigned long)(b+8));
1488	}
1489
1490	return (void *)old_handler;
1491}
1492
1493void *set_vi_handler(int n, vi_handler_t addr)
1494{
1495	return set_vi_srs_handler(n, addr, 0);
1496}
1497
1498extern void tlb_init(void);
1499extern void flush_tlb_handlers(void);
1500
1501/*
1502 * Timer interrupt
1503 */
1504int cp0_compare_irq;
1505EXPORT_SYMBOL_GPL(cp0_compare_irq);
1506int cp0_compare_irq_shift;
1507
1508/*
1509 * Performance counter IRQ or -1 if shared with timer
1510 */
1511int cp0_perfcount_irq;
1512EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1513
1514static int __cpuinitdata noulri;
 
 
 
 
 
 
1515
1516static int __init ulri_disable(char *s)
1517{
1518	pr_info("Disabling ulri\n");
1519	noulri = 1;
1520
1521	return 1;
1522}
1523__setup("noulri", ulri_disable);
1524
1525void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
 
1526{
1527	unsigned int cpu = smp_processor_id();
1528	unsigned int status_set = ST0_CU0;
1529	unsigned int hwrena = cpu_hwrena_impl_bits;
1530#ifdef CONFIG_MIPS_MT_SMTC
1531	int secondaryTC = 0;
1532	int bootTC = (cpu == 0);
1533
1534	/*
1535	 * Only do per_cpu_trap_init() for first TC of Each VPE.
1536	 * Note that this hack assumes that the SMTC init code
1537	 * assigns TCs consecutively and in ascending order.
1538	 */
1539
1540	if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1541	    ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1542		secondaryTC = 1;
1543#endif /* CONFIG_MIPS_MT_SMTC */
1544
1545	/*
1546	 * Disable coprocessors and select 32-bit or 64-bit addressing
1547	 * and the 16/32 or 32/32 FPR register model.  Reset the BEV
1548	 * flag that some firmware may have left set and the TS bit (for
1549	 * IP27).  Set XX for ISA IV code to work.
1550	 */
 
1551#ifdef CONFIG_64BIT
1552	status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1553#endif
1554	if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1555		status_set |= ST0_XX;
1556	if (cpu_has_dsp)
1557		status_set |= ST0_MX;
1558
1559	change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1560			 status_set);
 
1561
1562	if (cpu_has_mips_r2)
1563		hwrena |= 0x0000000f;
 
 
 
 
 
 
 
 
 
 
 
1564
1565	if (!noulri && cpu_has_userlocal)
1566		hwrena |= (1 << 29);
1567
1568	if (hwrena)
1569		write_c0_hwrena(hwrena);
 
1570
1571#ifdef CONFIG_MIPS_MT_SMTC
1572	if (!secondaryTC) {
1573#endif /* CONFIG_MIPS_MT_SMTC */
1574
1575	if (cpu_has_veic || cpu_has_vint) {
1576		unsigned long sr = set_c0_status(ST0_BEV);
 
 
 
 
 
 
 
 
1577		write_c0_ebase(ebase);
1578		write_c0_status(sr);
1579		/* Setting vector spacing enables EI/VI mode  */
1580		change_c0_intctl(0x3e0, VECTORSPACING);
1581	}
1582	if (cpu_has_divec) {
1583		if (cpu_has_mipsmt) {
1584			unsigned int vpflags = dvpe();
1585			set_c0_cause(CAUSEF_IV);
1586			evpe(vpflags);
1587		} else
1588			set_c0_cause(CAUSEF_IV);
1589	}
 
 
 
 
 
 
 
 
 
 
1590
1591	/*
1592	 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1593	 *
1594	 *  o read IntCtl.IPTI to determine the timer interrupt
1595	 *  o read IntCtl.IPPCI to determine the performance counter interrupt
 
1596	 */
1597	if (cpu_has_mips_r2) {
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1598		cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1599		cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1600		cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1601		if (cp0_perfcount_irq == cp0_compare_irq)
1602			cp0_perfcount_irq = -1;
 
 
1603	} else {
1604		cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1605		cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
1606		cp0_perfcount_irq = -1;
 
1607	}
1608
1609#ifdef CONFIG_MIPS_MT_SMTC
1610	}
1611#endif /* CONFIG_MIPS_MT_SMTC */
1612
1613	if (!cpu_data[cpu].asid_cache)
1614		cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1615
1616	atomic_inc(&init_mm.mm_count);
1617	current->active_mm = &init_mm;
1618	BUG_ON(current->mm);
1619	enter_lazy_tlb(&init_mm, current);
1620
1621#ifdef CONFIG_MIPS_MT_SMTC
1622	if (bootTC) {
1623#endif /* CONFIG_MIPS_MT_SMTC */
1624		/* Boot CPU's cache setup in setup_arch(). */
1625		if (!is_boot_cpu)
1626			cpu_cache_init();
1627		tlb_init();
1628#ifdef CONFIG_MIPS_MT_SMTC
1629	} else if (!secondaryTC) {
1630		/*
1631		 * First TC in non-boot VPE must do subset of tlb_init()
1632		 * for MMU countrol registers.
1633		 */
1634		write_c0_pagemask(PM_DEFAULT_MASK);
1635		write_c0_wired(0);
1636	}
1637#endif /* CONFIG_MIPS_MT_SMTC */
1638	TLBMISS_HANDLER_SETUP();
1639}
1640
1641/* Install CPU exception handler */
1642void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size)
1643{
 
 
 
1644	memcpy((void *)(ebase + offset), addr, size);
 
1645	local_flush_icache_range(ebase + offset, ebase + offset + size);
1646}
1647
1648static char panic_null_cerr[] __cpuinitdata =
1649	"Trying to set NULL cache error exception handler";
1650
1651/*
1652 * Install uncached CPU exception handler.
1653 * This is suitable only for the cache error exception which is the only
1654 * exception handler that is being run uncached.
1655 */
1656void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1657	unsigned long size)
1658{
1659	unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1660
1661	if (!addr)
1662		panic(panic_null_cerr);
1663
1664	memcpy((void *)(uncached_ebase + offset), addr, size);
1665}
1666
1667static int __initdata rdhwr_noopt;
1668static int __init set_rdhwr_noopt(char *str)
1669{
1670	rdhwr_noopt = 1;
1671	return 1;
1672}
1673
1674__setup("rdhwr_noopt", set_rdhwr_noopt);
1675
1676void __init trap_init(void)
1677{
1678	extern char except_vec3_generic, except_vec3_r4000;
1679	extern char except_vec4;
 
1680	unsigned long i;
1681	int rollback;
1682
1683	check_wait();
1684	rollback = (cpu_wait == r4k_wait);
1685
1686#if defined(CONFIG_KGDB)
1687	if (kgdb_early_setup)
1688		return;	/* Already done */
1689#endif
1690
1691	if (cpu_has_veic || cpu_has_vint) {
1692		unsigned long size = 0x200 + VECTORSPACING*64;
 
 
1693		ebase = (unsigned long)
1694			__alloc_bootmem(size, 1 << fls(size), 0);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1695	} else {
1696		ebase = CKSEG0;
1697		if (cpu_has_mips_r2)
1698			ebase += (read_c0_ebase() & 0x3ffff000);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1699	}
1700
1701	if (board_ebase_setup)
1702		board_ebase_setup();
1703	per_cpu_trap_init(true);
1704
1705	/*
1706	 * Copy the generic exception handlers to their final destination.
1707	 * This will be overriden later as suitable for a particular
1708	 * configuration.
1709	 */
1710	set_handler(0x180, &except_vec3_generic, 0x80);
1711
1712	/*
1713	 * Setup default vectors
1714	 */
1715	for (i = 0; i <= 31; i++)
1716		set_except_vector(i, handle_reserved);
1717
1718	/*
1719	 * Copy the EJTAG debug exception vector handler code to it's final
1720	 * destination.
1721	 */
1722	if (cpu_has_ejtag && board_ejtag_handler_setup)
1723		board_ejtag_handler_setup();
1724
1725	/*
1726	 * Only some CPUs have the watch exceptions.
1727	 */
1728	if (cpu_has_watch)
1729		set_except_vector(23, handle_watch);
1730
1731	/*
1732	 * Initialise interrupt handlers
1733	 */
1734	if (cpu_has_veic || cpu_has_vint) {
1735		int nvec = cpu_has_veic ? 64 : 8;
1736		for (i = 0; i < nvec; i++)
1737			set_vi_handler(i, NULL);
1738	}
1739	else if (cpu_has_divec)
1740		set_handler(0x200, &except_vec4, 0x8);
1741
1742	/*
1743	 * Some CPUs can enable/disable for cache parity detection, but does
1744	 * it different ways.
1745	 */
1746	parity_protection_init();
1747
1748	/*
1749	 * The Data Bus Errors / Instruction Bus Errors are signaled
1750	 * by external hardware.  Therefore these two exceptions
1751	 * may have board specific handlers.
1752	 */
1753	if (board_be_init)
1754		board_be_init();
1755
1756	set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1757	set_except_vector(1, handle_tlbm);
1758	set_except_vector(2, handle_tlbl);
1759	set_except_vector(3, handle_tlbs);
1760
1761	set_except_vector(4, handle_adel);
1762	set_except_vector(5, handle_ades);
1763
1764	set_except_vector(6, handle_ibe);
1765	set_except_vector(7, handle_dbe);
1766
1767	set_except_vector(8, handle_sys);
1768	set_except_vector(9, handle_bp);
1769	set_except_vector(10, rdhwr_noopt ? handle_ri :
1770			  (cpu_has_vtag_icache ?
1771			   handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1772	set_except_vector(11, handle_cpu);
1773	set_except_vector(12, handle_ov);
1774	set_except_vector(13, handle_tr);
1775
1776	if (current_cpu_type() == CPU_R6000 ||
1777	    current_cpu_type() == CPU_R6000A) {
1778		/*
1779		 * The R6000 is the only R-series CPU that features a machine
1780		 * check exception (similar to the R4000 cache error) and
1781		 * unaligned ldc1/sdc1 exception.  The handlers have not been
1782		 * written yet.  Well, anyway there is no R6000 machine on the
1783		 * current list of targets for Linux/MIPS.
1784		 * (Duh, crap, there is someone with a triple R6k machine)
1785		 */
1786		//set_except_vector(14, handle_mc);
1787		//set_except_vector(15, handle_ndc);
 
 
 
1788	}
1789
 
 
 
 
1790
1791	if (board_nmi_handler_setup)
1792		board_nmi_handler_setup();
1793
1794	if (cpu_has_fpu && !cpu_has_nofpuex)
1795		set_except_vector(15, handle_fpe);
 
 
1796
1797	set_except_vector(22, handle_mdmx);
 
 
 
 
 
 
1798
1799	if (cpu_has_mcheck)
1800		set_except_vector(24, handle_mcheck);
1801
1802	if (cpu_has_mipsmt)
1803		set_except_vector(25, handle_mt);
1804
1805	set_except_vector(26, handle_dsp);
1806
1807	if (board_cache_error_setup)
1808		board_cache_error_setup();
1809
1810	if (cpu_has_vce)
1811		/* Special exception: R4[04]00 uses also the divec space. */
1812		memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1813	else if (cpu_has_4kex)
1814		memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1815	else
1816		memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1817
1818	local_flush_icache_range(ebase, ebase + 0x400);
1819	flush_tlb_handlers();
1820
1821	sort_extable(__start___dbe_table, __stop___dbe_table);
1822
1823	cu2_notifier(default_cu2_call, 0x80000000);	/* Run last  */
1824}