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1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2000, 2001 Kanoj Sarcar
17 * Copyright (C) 2000, 2001 Ralf Baechle
18 * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
19 * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
20 */
21#include <linux/cache.h>
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/smp.h>
26#include <linux/spinlock.h>
27#include <linux/threads.h>
28#include <linux/module.h>
29#include <linux/time.h>
30#include <linux/timex.h>
31#include <linux/sched.h>
32#include <linux/cpumask.h>
33#include <linux/cpu.h>
34#include <linux/err.h>
35#include <linux/ftrace.h>
36
37#include <linux/atomic.h>
38#include <asm/cpu.h>
39#include <asm/processor.h>
40#include <asm/r4k-timer.h>
41#include <asm/mmu_context.h>
42#include <asm/time.h>
43#include <asm/setup.h>
44
45#ifdef CONFIG_MIPS_MT_SMTC
46#include <asm/mipsmtregs.h>
47#endif /* CONFIG_MIPS_MT_SMTC */
48
49volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
50
51int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
52EXPORT_SYMBOL(__cpu_number_map);
53
54int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
55EXPORT_SYMBOL(__cpu_logical_map);
56
57/* Number of TCs (or siblings in Intel speak) per CPU core */
58int smp_num_siblings = 1;
59EXPORT_SYMBOL(smp_num_siblings);
60
61/* representing the TCs (or siblings in Intel speak) of each logical CPU */
62cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
63EXPORT_SYMBOL(cpu_sibling_map);
64
65/* representing cpus for which sibling maps can be computed */
66static cpumask_t cpu_sibling_setup_map;
67
68static inline void set_cpu_sibling_map(int cpu)
69{
70 int i;
71
72 cpu_set(cpu, cpu_sibling_setup_map);
73
74 if (smp_num_siblings > 1) {
75 for_each_cpu_mask(i, cpu_sibling_setup_map) {
76 if (cpu_data[cpu].core == cpu_data[i].core) {
77 cpu_set(i, cpu_sibling_map[cpu]);
78 cpu_set(cpu, cpu_sibling_map[i]);
79 }
80 }
81 } else
82 cpu_set(cpu, cpu_sibling_map[cpu]);
83}
84
85struct plat_smp_ops *mp_ops;
86
87__cpuinit void register_smp_ops(struct plat_smp_ops *ops)
88{
89 if (mp_ops)
90 printk(KERN_WARNING "Overriding previously set SMP ops\n");
91
92 mp_ops = ops;
93}
94
95/*
96 * First C code run on the secondary CPUs after being started up by
97 * the master.
98 */
99asmlinkage __cpuinit void start_secondary(void)
100{
101 unsigned int cpu;
102
103#ifdef CONFIG_MIPS_MT_SMTC
104 /* Only do cpu_probe for first TC of CPU */
105 if ((read_c0_tcbind() & TCBIND_CURTC) == 0)
106#endif /* CONFIG_MIPS_MT_SMTC */
107 cpu_probe();
108 cpu_report();
109 per_cpu_trap_init(false);
110 mips_clockevent_init();
111 mp_ops->init_secondary();
112
113 /*
114 * XXX parity protection should be folded in here when it's converted
115 * to an option instead of something based on .cputype
116 */
117
118 calibrate_delay();
119 preempt_disable();
120 cpu = smp_processor_id();
121 cpu_data[cpu].udelay_val = loops_per_jiffy;
122
123 notify_cpu_starting(cpu);
124
125 set_cpu_online(cpu, true);
126
127 set_cpu_sibling_map(cpu);
128
129 cpu_set(cpu, cpu_callin_map);
130
131 synchronise_count_slave();
132
133 /*
134 * irq will be enabled in ->smp_finish(), enabling it too early
135 * is dangerous.
136 */
137 WARN_ON_ONCE(!irqs_disabled());
138 mp_ops->smp_finish();
139
140 cpu_idle();
141}
142
143/*
144 * Call into both interrupt handlers, as we share the IPI for them
145 */
146void __irq_entry smp_call_function_interrupt(void)
147{
148 irq_enter();
149 generic_smp_call_function_single_interrupt();
150 generic_smp_call_function_interrupt();
151 irq_exit();
152}
153
154static void stop_this_cpu(void *dummy)
155{
156 /*
157 * Remove this CPU:
158 */
159 set_cpu_online(smp_processor_id(), false);
160 for (;;) {
161 if (cpu_wait)
162 (*cpu_wait)(); /* Wait if available. */
163 }
164}
165
166void smp_send_stop(void)
167{
168 smp_call_function(stop_this_cpu, NULL, 0);
169}
170
171void __init smp_cpus_done(unsigned int max_cpus)
172{
173 mp_ops->cpus_done();
174 synchronise_count_master();
175}
176
177/* called from main before smp_init() */
178void __init smp_prepare_cpus(unsigned int max_cpus)
179{
180 init_new_context(current, &init_mm);
181 current_thread_info()->cpu = 0;
182 mp_ops->prepare_cpus(max_cpus);
183 set_cpu_sibling_map(0);
184#ifndef CONFIG_HOTPLUG_CPU
185 init_cpu_present(cpu_possible_mask);
186#endif
187}
188
189/* preload SMP state for boot cpu */
190void __devinit smp_prepare_boot_cpu(void)
191{
192 set_cpu_possible(0, true);
193 set_cpu_online(0, true);
194 cpu_set(0, cpu_callin_map);
195}
196
197int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
198{
199 mp_ops->boot_secondary(cpu, tidle);
200
201 /*
202 * Trust is futile. We should really have timeouts ...
203 */
204 while (!cpu_isset(cpu, cpu_callin_map))
205 udelay(100);
206
207 return 0;
208}
209
210/* Not really SMP stuff ... */
211int setup_profiling_timer(unsigned int multiplier)
212{
213 return 0;
214}
215
216static void flush_tlb_all_ipi(void *info)
217{
218 local_flush_tlb_all();
219}
220
221void flush_tlb_all(void)
222{
223 on_each_cpu(flush_tlb_all_ipi, NULL, 1);
224}
225
226static void flush_tlb_mm_ipi(void *mm)
227{
228 local_flush_tlb_mm((struct mm_struct *)mm);
229}
230
231/*
232 * Special Variant of smp_call_function for use by TLB functions:
233 *
234 * o No return value
235 * o collapses to normal function call on UP kernels
236 * o collapses to normal function call on systems with a single shared
237 * primary cache.
238 * o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core.
239 */
240static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
241{
242#ifndef CONFIG_MIPS_MT_SMTC
243 smp_call_function(func, info, 1);
244#endif
245}
246
247static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
248{
249 preempt_disable();
250
251 smp_on_other_tlbs(func, info);
252 func(info);
253
254 preempt_enable();
255}
256
257/*
258 * The following tlb flush calls are invoked when old translations are
259 * being torn down, or pte attributes are changing. For single threaded
260 * address spaces, a new context is obtained on the current cpu, and tlb
261 * context on other cpus are invalidated to force a new context allocation
262 * at switch_mm time, should the mm ever be used on other cpus. For
263 * multithreaded address spaces, intercpu interrupts have to be sent.
264 * Another case where intercpu interrupts are required is when the target
265 * mm might be active on another cpu (eg debuggers doing the flushes on
266 * behalf of debugees, kswapd stealing pages from another process etc).
267 * Kanoj 07/00.
268 */
269
270void flush_tlb_mm(struct mm_struct *mm)
271{
272 preempt_disable();
273
274 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
275 smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
276 } else {
277 unsigned int cpu;
278
279 for_each_online_cpu(cpu) {
280 if (cpu != smp_processor_id() && cpu_context(cpu, mm))
281 cpu_context(cpu, mm) = 0;
282 }
283 }
284 local_flush_tlb_mm(mm);
285
286 preempt_enable();
287}
288
289struct flush_tlb_data {
290 struct vm_area_struct *vma;
291 unsigned long addr1;
292 unsigned long addr2;
293};
294
295static void flush_tlb_range_ipi(void *info)
296{
297 struct flush_tlb_data *fd = info;
298
299 local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
300}
301
302void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
303{
304 struct mm_struct *mm = vma->vm_mm;
305
306 preempt_disable();
307 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
308 struct flush_tlb_data fd = {
309 .vma = vma,
310 .addr1 = start,
311 .addr2 = end,
312 };
313
314 smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
315 } else {
316 unsigned int cpu;
317
318 for_each_online_cpu(cpu) {
319 if (cpu != smp_processor_id() && cpu_context(cpu, mm))
320 cpu_context(cpu, mm) = 0;
321 }
322 }
323 local_flush_tlb_range(vma, start, end);
324 preempt_enable();
325}
326
327static void flush_tlb_kernel_range_ipi(void *info)
328{
329 struct flush_tlb_data *fd = info;
330
331 local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
332}
333
334void flush_tlb_kernel_range(unsigned long start, unsigned long end)
335{
336 struct flush_tlb_data fd = {
337 .addr1 = start,
338 .addr2 = end,
339 };
340
341 on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
342}
343
344static void flush_tlb_page_ipi(void *info)
345{
346 struct flush_tlb_data *fd = info;
347
348 local_flush_tlb_page(fd->vma, fd->addr1);
349}
350
351void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
352{
353 preempt_disable();
354 if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
355 struct flush_tlb_data fd = {
356 .vma = vma,
357 .addr1 = page,
358 };
359
360 smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
361 } else {
362 unsigned int cpu;
363
364 for_each_online_cpu(cpu) {
365 if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
366 cpu_context(cpu, vma->vm_mm) = 0;
367 }
368 }
369 local_flush_tlb_page(vma, page);
370 preempt_enable();
371}
372
373static void flush_tlb_one_ipi(void *info)
374{
375 unsigned long vaddr = (unsigned long) info;
376
377 local_flush_tlb_one(vaddr);
378}
379
380void flush_tlb_one(unsigned long vaddr)
381{
382 smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
383}
384
385EXPORT_SYMBOL(flush_tlb_page);
386EXPORT_SYMBOL(flush_tlb_one);
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2000, 2001 Kanoj Sarcar
17 * Copyright (C) 2000, 2001 Ralf Baechle
18 * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
19 * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
20 */
21#include <linux/cache.h>
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/smp.h>
26#include <linux/spinlock.h>
27#include <linux/threads.h>
28#include <linux/module.h>
29#include <linux/time.h>
30#include <linux/timex.h>
31#include <linux/sched.h>
32#include <linux/cpumask.h>
33#include <linux/cpu.h>
34#include <linux/err.h>
35#include <linux/ftrace.h>
36
37#include <linux/atomic.h>
38#include <asm/cpu.h>
39#include <asm/processor.h>
40#include <asm/idle.h>
41#include <asm/r4k-timer.h>
42#include <asm/mmu_context.h>
43#include <asm/time.h>
44#include <asm/setup.h>
45
46#ifdef CONFIG_MIPS_MT_SMTC
47#include <asm/mipsmtregs.h>
48#endif /* CONFIG_MIPS_MT_SMTC */
49
50volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
51
52int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
53EXPORT_SYMBOL(__cpu_number_map);
54
55int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
56EXPORT_SYMBOL(__cpu_logical_map);
57
58/* Number of TCs (or siblings in Intel speak) per CPU core */
59int smp_num_siblings = 1;
60EXPORT_SYMBOL(smp_num_siblings);
61
62/* representing the TCs (or siblings in Intel speak) of each logical CPU */
63cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
64EXPORT_SYMBOL(cpu_sibling_map);
65
66/* representing cpus for which sibling maps can be computed */
67static cpumask_t cpu_sibling_setup_map;
68
69static inline void set_cpu_sibling_map(int cpu)
70{
71 int i;
72
73 cpu_set(cpu, cpu_sibling_setup_map);
74
75 if (smp_num_siblings > 1) {
76 for_each_cpu_mask(i, cpu_sibling_setup_map) {
77 if (cpu_data[cpu].core == cpu_data[i].core) {
78 cpu_set(i, cpu_sibling_map[cpu]);
79 cpu_set(cpu, cpu_sibling_map[i]);
80 }
81 }
82 } else
83 cpu_set(cpu, cpu_sibling_map[cpu]);
84}
85
86struct plat_smp_ops *mp_ops;
87EXPORT_SYMBOL(mp_ops);
88
89void register_smp_ops(struct plat_smp_ops *ops)
90{
91 if (mp_ops)
92 printk(KERN_WARNING "Overriding previously set SMP ops\n");
93
94 mp_ops = ops;
95}
96
97/*
98 * First C code run on the secondary CPUs after being started up by
99 * the master.
100 */
101asmlinkage void start_secondary(void)
102{
103 unsigned int cpu;
104
105#ifdef CONFIG_MIPS_MT_SMTC
106 /* Only do cpu_probe for first TC of CPU */
107 if ((read_c0_tcbind() & TCBIND_CURTC) != 0)
108 __cpu_name[smp_processor_id()] = __cpu_name[0];
109 else
110#endif /* CONFIG_MIPS_MT_SMTC */
111 cpu_probe();
112 cpu_report();
113 per_cpu_trap_init(false);
114 mips_clockevent_init();
115 mp_ops->init_secondary();
116
117 /*
118 * XXX parity protection should be folded in here when it's converted
119 * to an option instead of something based on .cputype
120 */
121
122 calibrate_delay();
123 preempt_disable();
124 cpu = smp_processor_id();
125 cpu_data[cpu].udelay_val = loops_per_jiffy;
126
127 notify_cpu_starting(cpu);
128
129 set_cpu_online(cpu, true);
130
131 set_cpu_sibling_map(cpu);
132
133 cpu_set(cpu, cpu_callin_map);
134
135 synchronise_count_slave(cpu);
136
137 /*
138 * irq will be enabled in ->smp_finish(), enabling it too early
139 * is dangerous.
140 */
141 WARN_ON_ONCE(!irqs_disabled());
142 mp_ops->smp_finish();
143
144 cpu_startup_entry(CPUHP_ONLINE);
145}
146
147/*
148 * Call into both interrupt handlers, as we share the IPI for them
149 */
150void __irq_entry smp_call_function_interrupt(void)
151{
152 irq_enter();
153 generic_smp_call_function_interrupt();
154 irq_exit();
155}
156
157static void stop_this_cpu(void *dummy)
158{
159 /*
160 * Remove this CPU:
161 */
162 set_cpu_online(smp_processor_id(), false);
163 for (;;) {
164 if (cpu_wait)
165 (*cpu_wait)(); /* Wait if available. */
166 }
167}
168
169void smp_send_stop(void)
170{
171 smp_call_function(stop_this_cpu, NULL, 0);
172}
173
174void __init smp_cpus_done(unsigned int max_cpus)
175{
176 mp_ops->cpus_done();
177}
178
179/* called from main before smp_init() */
180void __init smp_prepare_cpus(unsigned int max_cpus)
181{
182 init_new_context(current, &init_mm);
183 current_thread_info()->cpu = 0;
184 mp_ops->prepare_cpus(max_cpus);
185 set_cpu_sibling_map(0);
186#ifndef CONFIG_HOTPLUG_CPU
187 init_cpu_present(cpu_possible_mask);
188#endif
189}
190
191/* preload SMP state for boot cpu */
192void smp_prepare_boot_cpu(void)
193{
194 set_cpu_possible(0, true);
195 set_cpu_online(0, true);
196 cpu_set(0, cpu_callin_map);
197}
198
199int __cpu_up(unsigned int cpu, struct task_struct *tidle)
200{
201 mp_ops->boot_secondary(cpu, tidle);
202
203 /*
204 * Trust is futile. We should really have timeouts ...
205 */
206 while (!cpu_isset(cpu, cpu_callin_map))
207 udelay(100);
208
209 synchronise_count_master(cpu);
210 return 0;
211}
212
213/* Not really SMP stuff ... */
214int setup_profiling_timer(unsigned int multiplier)
215{
216 return 0;
217}
218
219static void flush_tlb_all_ipi(void *info)
220{
221 local_flush_tlb_all();
222}
223
224void flush_tlb_all(void)
225{
226 on_each_cpu(flush_tlb_all_ipi, NULL, 1);
227}
228
229static void flush_tlb_mm_ipi(void *mm)
230{
231 local_flush_tlb_mm((struct mm_struct *)mm);
232}
233
234/*
235 * Special Variant of smp_call_function for use by TLB functions:
236 *
237 * o No return value
238 * o collapses to normal function call on UP kernels
239 * o collapses to normal function call on systems with a single shared
240 * primary cache.
241 * o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core.
242 */
243static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
244{
245#ifndef CONFIG_MIPS_MT_SMTC
246 smp_call_function(func, info, 1);
247#endif
248}
249
250static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
251{
252 preempt_disable();
253
254 smp_on_other_tlbs(func, info);
255 func(info);
256
257 preempt_enable();
258}
259
260/*
261 * The following tlb flush calls are invoked when old translations are
262 * being torn down, or pte attributes are changing. For single threaded
263 * address spaces, a new context is obtained on the current cpu, and tlb
264 * context on other cpus are invalidated to force a new context allocation
265 * at switch_mm time, should the mm ever be used on other cpus. For
266 * multithreaded address spaces, intercpu interrupts have to be sent.
267 * Another case where intercpu interrupts are required is when the target
268 * mm might be active on another cpu (eg debuggers doing the flushes on
269 * behalf of debugees, kswapd stealing pages from another process etc).
270 * Kanoj 07/00.
271 */
272
273void flush_tlb_mm(struct mm_struct *mm)
274{
275 preempt_disable();
276
277 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
278 smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
279 } else {
280 unsigned int cpu;
281
282 for_each_online_cpu(cpu) {
283 if (cpu != smp_processor_id() && cpu_context(cpu, mm))
284 cpu_context(cpu, mm) = 0;
285 }
286 }
287 local_flush_tlb_mm(mm);
288
289 preempt_enable();
290}
291
292struct flush_tlb_data {
293 struct vm_area_struct *vma;
294 unsigned long addr1;
295 unsigned long addr2;
296};
297
298static void flush_tlb_range_ipi(void *info)
299{
300 struct flush_tlb_data *fd = info;
301
302 local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
303}
304
305void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
306{
307 struct mm_struct *mm = vma->vm_mm;
308
309 preempt_disable();
310 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
311 struct flush_tlb_data fd = {
312 .vma = vma,
313 .addr1 = start,
314 .addr2 = end,
315 };
316
317 smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
318 } else {
319 unsigned int cpu;
320
321 for_each_online_cpu(cpu) {
322 if (cpu != smp_processor_id() && cpu_context(cpu, mm))
323 cpu_context(cpu, mm) = 0;
324 }
325 }
326 local_flush_tlb_range(vma, start, end);
327 preempt_enable();
328}
329
330static void flush_tlb_kernel_range_ipi(void *info)
331{
332 struct flush_tlb_data *fd = info;
333
334 local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
335}
336
337void flush_tlb_kernel_range(unsigned long start, unsigned long end)
338{
339 struct flush_tlb_data fd = {
340 .addr1 = start,
341 .addr2 = end,
342 };
343
344 on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
345}
346
347static void flush_tlb_page_ipi(void *info)
348{
349 struct flush_tlb_data *fd = info;
350
351 local_flush_tlb_page(fd->vma, fd->addr1);
352}
353
354void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
355{
356 preempt_disable();
357 if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
358 struct flush_tlb_data fd = {
359 .vma = vma,
360 .addr1 = page,
361 };
362
363 smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
364 } else {
365 unsigned int cpu;
366
367 for_each_online_cpu(cpu) {
368 if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
369 cpu_context(cpu, vma->vm_mm) = 0;
370 }
371 }
372 local_flush_tlb_page(vma, page);
373 preempt_enable();
374}
375
376static void flush_tlb_one_ipi(void *info)
377{
378 unsigned long vaddr = (unsigned long) info;
379
380 local_flush_tlb_one(vaddr);
381}
382
383void flush_tlb_one(unsigned long vaddr)
384{
385 smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
386}
387
388EXPORT_SYMBOL(flush_tlb_page);
389EXPORT_SYMBOL(flush_tlb_one);
390
391#if defined(CONFIG_KEXEC)
392void (*dump_ipi_function_ptr)(void *) = NULL;
393void dump_send_ipi(void (*dump_ipi_callback)(void *))
394{
395 int i;
396 int cpu = smp_processor_id();
397
398 dump_ipi_function_ptr = dump_ipi_callback;
399 smp_mb();
400 for_each_online_cpu(i)
401 if (i != cpu)
402 mp_ops->send_ipi_single(i, SMP_DUMP);
403
404}
405EXPORT_SYMBOL(dump_send_ipi);
406#endif