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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11#include <linux/init.h>
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/smp.h>
16#include <linux/interrupt.h>
17#include <linux/spinlock.h>
18#include <linux/cpu.h>
19#include <linux/cpumask.h>
20#include <linux/reboot.h>
21#include <linux/io.h>
22#include <linux/compiler.h>
23#include <linux/linkage.h>
24#include <linux/bug.h>
25#include <linux/kernel.h>
26
27#include <asm/time.h>
28#include <asm/pgtable.h>
29#include <asm/processor.h>
30#include <asm/bootinfo.h>
31#include <asm/pmon.h>
32#include <asm/cacheflush.h>
33#include <asm/tlbflush.h>
34#include <asm/mipsregs.h>
35#include <asm/bmips.h>
36#include <asm/traps.h>
37#include <asm/barrier.h>
38
39static int __maybe_unused max_cpus = 1;
40
41/* these may be configured by the platform code */
42int bmips_smp_enabled = 1;
43int bmips_cpu_offset;
44cpumask_t bmips_booted_mask;
45
46#ifdef CONFIG_SMP
47
48/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
49unsigned long bmips_smp_boot_sp;
50unsigned long bmips_smp_boot_gp;
51
52static void bmips_send_ipi_single(int cpu, unsigned int action);
53static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
54
55/* SW interrupts 0,1 are used for interprocessor signaling */
56#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
57#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
58
59#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
60#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
61#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
62#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
63
64static void __init bmips_smp_setup(void)
65{
66 int i;
67
68#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
69 /* arbitration priority */
70 clear_c0_brcm_cmt_ctrl(0x30);
71
72 /* NBK and weak order flags */
73 set_c0_brcm_config_0(0x30000);
74
75 /*
76 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
77 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
78 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
79 */
80 change_c0_brcm_cmt_intr(0xf8018000,
81 (0x02 << 27) | (0x03 << 15));
82
83 /* single core, 2 threads (2 pipelines) */
84 max_cpus = 2;
85#elif defined(CONFIG_CPU_BMIPS5000)
86 /* enable raceless SW interrupts */
87 set_c0_brcm_config(0x03 << 22);
88
89 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
90 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
91
92 /* N cores, 2 threads per core */
93 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
94
95 /* clear any pending SW interrupts */
96 for (i = 0; i < max_cpus; i++) {
97 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
98 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
99 }
100#endif
101
102 if (!bmips_smp_enabled)
103 max_cpus = 1;
104
105 /* this can be overridden by the BSP */
106 if (!board_ebase_setup)
107 board_ebase_setup = &bmips_ebase_setup;
108
109 for (i = 0; i < max_cpus; i++) {
110 __cpu_number_map[i] = 1;
111 __cpu_logical_map[i] = 1;
112 set_cpu_possible(i, 1);
113 set_cpu_present(i, 1);
114 }
115}
116
117/*
118 * IPI IRQ setup - runs on CPU0
119 */
120static void bmips_prepare_cpus(unsigned int max_cpus)
121{
122 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
123 "smp_ipi0", NULL))
124 panic("Can't request IPI0 interrupt\n");
125 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
126 "smp_ipi1", NULL))
127 panic("Can't request IPI1 interrupt\n");
128}
129
130/*
131 * Tell the hardware to boot CPUx - runs on CPU0
132 */
133static void bmips_boot_secondary(int cpu, struct task_struct *idle)
134{
135 bmips_smp_boot_sp = __KSTK_TOS(idle);
136 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
137 mb();
138
139 /*
140 * Initial boot sequence for secondary CPU:
141 * bmips_reset_nmi_vec @ a000_0000 ->
142 * bmips_smp_entry ->
143 * plat_wired_tlb_setup (cached function call; optional) ->
144 * start_secondary (cached jump)
145 *
146 * Warm restart sequence:
147 * play_dead WAIT loop ->
148 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
149 * eret to play_dead ->
150 * bmips_secondary_reentry ->
151 * start_secondary
152 */
153
154 pr_info("SMP: Booting CPU%d...\n", cpu);
155
156 if (cpumask_test_cpu(cpu, &bmips_booted_mask))
157 bmips_send_ipi_single(cpu, 0);
158 else {
159#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
160 set_c0_brcm_cmt_ctrl(0x01);
161#elif defined(CONFIG_CPU_BMIPS5000)
162 if (cpu & 0x01)
163 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
164 else {
165 /*
166 * core N thread 0 was already booted; just
167 * pulse the NMI line
168 */
169 bmips_write_zscm_reg(0x210, 0xc0000000);
170 udelay(10);
171 bmips_write_zscm_reg(0x210, 0x00);
172 }
173#endif
174 cpumask_set_cpu(cpu, &bmips_booted_mask);
175 }
176}
177
178/*
179 * Early setup - runs on secondary CPU after cache probe
180 */
181static void bmips_init_secondary(void)
182{
183 /* move NMI vector to kseg0, in case XKS01 is enabled */
184
185#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
186 void __iomem *cbr = BMIPS_GET_CBR();
187 unsigned long old_vec;
188
189 old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
190 __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
191
192 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
193#elif defined(CONFIG_CPU_BMIPS5000)
194 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
195 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
196
197 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
198#endif
199}
200
201/*
202 * Late setup - runs on secondary CPU before entering the idle loop
203 */
204static void bmips_smp_finish(void)
205{
206 pr_info("SMP: CPU%d is running\n", smp_processor_id());
207
208 /* make sure there won't be a timer interrupt for a little while */
209 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
210
211 irq_enable_hazard();
212 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
213 irq_enable_hazard();
214}
215
216/*
217 * Runs on CPU0 after all CPUs have been booted
218 */
219static void bmips_cpus_done(void)
220{
221}
222
223#if defined(CONFIG_CPU_BMIPS5000)
224
225/*
226 * BMIPS5000 raceless IPIs
227 *
228 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
229 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
230 * IPI1 is used for SMP_CALL_FUNCTION
231 */
232
233static void bmips_send_ipi_single(int cpu, unsigned int action)
234{
235 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
236}
237
238static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
239{
240 int action = irq - IPI0_IRQ;
241
242 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
243
244 if (action == 0)
245 scheduler_ipi();
246 else
247 smp_call_function_interrupt();
248
249 return IRQ_HANDLED;
250}
251
252#else
253
254/*
255 * BMIPS43xx racey IPIs
256 *
257 * We use one inbound SW IRQ for each CPU.
258 *
259 * A spinlock must be held in order to keep CPUx from accidentally clearing
260 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
261 * same spinlock is used to protect the action masks.
262 */
263
264static DEFINE_SPINLOCK(ipi_lock);
265static DEFINE_PER_CPU(int, ipi_action_mask);
266
267static void bmips_send_ipi_single(int cpu, unsigned int action)
268{
269 unsigned long flags;
270
271 spin_lock_irqsave(&ipi_lock, flags);
272 set_c0_cause(cpu ? C_SW1 : C_SW0);
273 per_cpu(ipi_action_mask, cpu) |= action;
274 irq_enable_hazard();
275 spin_unlock_irqrestore(&ipi_lock, flags);
276}
277
278static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
279{
280 unsigned long flags;
281 int action, cpu = irq - IPI0_IRQ;
282
283 spin_lock_irqsave(&ipi_lock, flags);
284 action = __get_cpu_var(ipi_action_mask);
285 per_cpu(ipi_action_mask, cpu) = 0;
286 clear_c0_cause(cpu ? C_SW1 : C_SW0);
287 spin_unlock_irqrestore(&ipi_lock, flags);
288
289 if (action & SMP_RESCHEDULE_YOURSELF)
290 scheduler_ipi();
291 if (action & SMP_CALL_FUNCTION)
292 smp_call_function_interrupt();
293
294 return IRQ_HANDLED;
295}
296
297#endif /* BMIPS type */
298
299static void bmips_send_ipi_mask(const struct cpumask *mask,
300 unsigned int action)
301{
302 unsigned int i;
303
304 for_each_cpu(i, mask)
305 bmips_send_ipi_single(i, action);
306}
307
308#ifdef CONFIG_HOTPLUG_CPU
309
310static int bmips_cpu_disable(void)
311{
312 unsigned int cpu = smp_processor_id();
313
314 if (cpu == 0)
315 return -EBUSY;
316
317 pr_info("SMP: CPU%d is offline\n", cpu);
318
319 set_cpu_online(cpu, false);
320 cpu_clear(cpu, cpu_callin_map);
321
322 local_flush_tlb_all();
323 local_flush_icache_range(0, ~0);
324
325 return 0;
326}
327
328static void bmips_cpu_die(unsigned int cpu)
329{
330}
331
332void __ref play_dead(void)
333{
334 idle_task_exit();
335
336 /* flush data cache */
337 _dma_cache_wback_inv(0, ~0);
338
339 /*
340 * Wakeup is on SW0 or SW1; disable everything else
341 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
342 * IRQ handlers; this clears ST0_IE and returns immediately.
343 */
344 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
345 change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
346 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
347 irq_disable_hazard();
348
349 /*
350 * wait for SW interrupt from bmips_boot_secondary(), then jump
351 * back to start_secondary()
352 */
353 __asm__ __volatile__(
354 " wait\n"
355 " j bmips_secondary_reentry\n"
356 : : : "memory");
357}
358
359#endif /* CONFIG_HOTPLUG_CPU */
360
361struct plat_smp_ops bmips_smp_ops = {
362 .smp_setup = bmips_smp_setup,
363 .prepare_cpus = bmips_prepare_cpus,
364 .boot_secondary = bmips_boot_secondary,
365 .smp_finish = bmips_smp_finish,
366 .init_secondary = bmips_init_secondary,
367 .cpus_done = bmips_cpus_done,
368 .send_ipi_single = bmips_send_ipi_single,
369 .send_ipi_mask = bmips_send_ipi_mask,
370#ifdef CONFIG_HOTPLUG_CPU
371 .cpu_disable = bmips_cpu_disable,
372 .cpu_die = bmips_cpu_die,
373#endif
374};
375
376#endif /* CONFIG_SMP */
377
378/***********************************************************************
379 * BMIPS vector relocation
380 * This is primarily used for SMP boot, but it is applicable to some
381 * UP BMIPS systems as well.
382 ***********************************************************************/
383
384static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end)
385{
386 memcpy((void *)dst, start, end - start);
387 dma_cache_wback((unsigned long)start, end - start);
388 local_flush_icache_range(dst, dst + (end - start));
389 instruction_hazard();
390}
391
392static inline void __cpuinit bmips_nmi_handler_setup(void)
393{
394 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
395 &bmips_reset_nmi_vec_end);
396 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
397 &bmips_smp_int_vec_end);
398}
399
400void __cpuinit bmips_ebase_setup(void)
401{
402 unsigned long new_ebase = ebase;
403 void __iomem __maybe_unused *cbr;
404
405 BUG_ON(ebase != CKSEG0);
406
407#if defined(CONFIG_CPU_BMIPS4350)
408 /*
409 * BMIPS4350 cannot relocate the normal vectors, but it
410 * can relocate the BEV=1 vectors. So CPU1 starts up at
411 * the relocated BEV=1, IV=0 general exception vector @
412 * 0xa000_0380.
413 *
414 * set_uncached_handler() is used here because:
415 * - CPU1 will run this from uncached space
416 * - None of the cacheflush functions are set up yet
417 */
418 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
419 &bmips_smp_int_vec, 0x80);
420 __sync();
421 return;
422#elif defined(CONFIG_CPU_BMIPS4380)
423 /*
424 * 0x8000_0000: reset/NMI (initially in kseg1)
425 * 0x8000_0400: normal vectors
426 */
427 new_ebase = 0x80000400;
428 cbr = BMIPS_GET_CBR();
429 __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
430 __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
431#elif defined(CONFIG_CPU_BMIPS5000)
432 /*
433 * 0x8000_0000: reset/NMI (initially in kseg1)
434 * 0x8000_1000: normal vectors
435 */
436 new_ebase = 0x80001000;
437 write_c0_brcm_bootvec(0xa0088008);
438 write_c0_ebase(new_ebase);
439 if (max_cpus > 2)
440 bmips_write_zscm_reg(0xa0, 0xa008a008);
441#else
442 return;
443#endif
444 board_nmi_handler_setup = &bmips_nmi_handler_setup;
445 ebase = new_ebase;
446}
447
448asmlinkage void __weak plat_wired_tlb_setup(void)
449{
450 /*
451 * Called when starting/restarting a secondary CPU.
452 * Kernel stacks and other important data might only be accessible
453 * once the wired entries are present.
454 */
455}
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11#include <linux/init.h>
12#include <linux/sched.h>
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/smp.h>
16#include <linux/interrupt.h>
17#include <linux/spinlock.h>
18#include <linux/cpu.h>
19#include <linux/cpumask.h>
20#include <linux/reboot.h>
21#include <linux/io.h>
22#include <linux/compiler.h>
23#include <linux/linkage.h>
24#include <linux/bug.h>
25#include <linux/kernel.h>
26
27#include <asm/time.h>
28#include <asm/pgtable.h>
29#include <asm/processor.h>
30#include <asm/bootinfo.h>
31#include <asm/pmon.h>
32#include <asm/cacheflush.h>
33#include <asm/tlbflush.h>
34#include <asm/mipsregs.h>
35#include <asm/bmips.h>
36#include <asm/traps.h>
37#include <asm/barrier.h>
38
39static int __maybe_unused max_cpus = 1;
40
41/* these may be configured by the platform code */
42int bmips_smp_enabled = 1;
43int bmips_cpu_offset;
44cpumask_t bmips_booted_mask;
45
46#ifdef CONFIG_SMP
47
48/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
49unsigned long bmips_smp_boot_sp;
50unsigned long bmips_smp_boot_gp;
51
52static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
53static void bmips5000_send_ipi_single(int cpu, unsigned int action);
54static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
55static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
56
57/* SW interrupts 0,1 are used for interprocessor signaling */
58#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
59#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
60
61#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
62#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
63#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
64#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
65
66static void __init bmips_smp_setup(void)
67{
68 int i, cpu = 1, boot_cpu = 0;
69 int cpu_hw_intr;
70
71 switch (current_cpu_type()) {
72 case CPU_BMIPS4350:
73 case CPU_BMIPS4380:
74 /* arbitration priority */
75 clear_c0_brcm_cmt_ctrl(0x30);
76
77 /* NBK and weak order flags */
78 set_c0_brcm_config_0(0x30000);
79
80 /* Find out if we are running on TP0 or TP1 */
81 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
82
83 /*
84 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
85 * thread
86 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
87 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
88 */
89 if (boot_cpu == 0)
90 cpu_hw_intr = 0x02;
91 else
92 cpu_hw_intr = 0x1d;
93
94 change_c0_brcm_cmt_intr(0xf8018000,
95 (cpu_hw_intr << 27) | (0x03 << 15));
96
97 /* single core, 2 threads (2 pipelines) */
98 max_cpus = 2;
99
100 break;
101 case CPU_BMIPS5000:
102 /* enable raceless SW interrupts */
103 set_c0_brcm_config(0x03 << 22);
104
105 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
106 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
107
108 /* N cores, 2 threads per core */
109 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
110
111 /* clear any pending SW interrupts */
112 for (i = 0; i < max_cpus; i++) {
113 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
114 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
115 }
116
117 break;
118 default:
119 max_cpus = 1;
120 }
121
122 if (!bmips_smp_enabled)
123 max_cpus = 1;
124
125 /* this can be overridden by the BSP */
126 if (!board_ebase_setup)
127 board_ebase_setup = &bmips_ebase_setup;
128
129 __cpu_number_map[boot_cpu] = 0;
130 __cpu_logical_map[0] = boot_cpu;
131
132 for (i = 0; i < max_cpus; i++) {
133 if (i != boot_cpu) {
134 __cpu_number_map[i] = cpu;
135 __cpu_logical_map[cpu] = i;
136 cpu++;
137 }
138 set_cpu_possible(i, 1);
139 set_cpu_present(i, 1);
140 }
141}
142
143/*
144 * IPI IRQ setup - runs on CPU0
145 */
146static void bmips_prepare_cpus(unsigned int max_cpus)
147{
148 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
149
150 switch (current_cpu_type()) {
151 case CPU_BMIPS4350:
152 case CPU_BMIPS4380:
153 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
154 break;
155 case CPU_BMIPS5000:
156 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
157 break;
158 default:
159 return;
160 }
161
162 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
163 "smp_ipi0", NULL))
164 panic("Can't request IPI0 interrupt");
165 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
166 "smp_ipi1", NULL))
167 panic("Can't request IPI1 interrupt");
168}
169
170/*
171 * Tell the hardware to boot CPUx - runs on CPU0
172 */
173static void bmips_boot_secondary(int cpu, struct task_struct *idle)
174{
175 bmips_smp_boot_sp = __KSTK_TOS(idle);
176 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
177 mb();
178
179 /*
180 * Initial boot sequence for secondary CPU:
181 * bmips_reset_nmi_vec @ a000_0000 ->
182 * bmips_smp_entry ->
183 * plat_wired_tlb_setup (cached function call; optional) ->
184 * start_secondary (cached jump)
185 *
186 * Warm restart sequence:
187 * play_dead WAIT loop ->
188 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
189 * eret to play_dead ->
190 * bmips_secondary_reentry ->
191 * start_secondary
192 */
193
194 pr_info("SMP: Booting CPU%d...\n", cpu);
195
196 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
197 switch (current_cpu_type()) {
198 case CPU_BMIPS4350:
199 case CPU_BMIPS4380:
200 bmips43xx_send_ipi_single(cpu, 0);
201 break;
202 case CPU_BMIPS5000:
203 bmips5000_send_ipi_single(cpu, 0);
204 break;
205 }
206 }
207 else {
208 switch (current_cpu_type()) {
209 case CPU_BMIPS4350:
210 case CPU_BMIPS4380:
211 /* Reset slave TP1 if booting from TP0 */
212 if (cpu_logical_map(cpu) == 1)
213 set_c0_brcm_cmt_ctrl(0x01);
214 break;
215 case CPU_BMIPS5000:
216 if (cpu & 0x01)
217 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
218 else {
219 /*
220 * core N thread 0 was already booted; just
221 * pulse the NMI line
222 */
223 bmips_write_zscm_reg(0x210, 0xc0000000);
224 udelay(10);
225 bmips_write_zscm_reg(0x210, 0x00);
226 }
227 break;
228 }
229 cpumask_set_cpu(cpu, &bmips_booted_mask);
230 }
231}
232
233/*
234 * Early setup - runs on secondary CPU after cache probe
235 */
236static void bmips_init_secondary(void)
237{
238 /* move NMI vector to kseg0, in case XKS01 is enabled */
239
240 void __iomem *cbr;
241 unsigned long old_vec;
242 unsigned long relo_vector;
243 int boot_cpu;
244
245 switch (current_cpu_type()) {
246 case CPU_BMIPS4350:
247 case CPU_BMIPS4380:
248 cbr = BMIPS_GET_CBR();
249
250 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
251 relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
252 BMIPS_RELO_VECTOR_CONTROL_1;
253
254 old_vec = __raw_readl(cbr + relo_vector);
255 __raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
256
257 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
258 break;
259 case CPU_BMIPS5000:
260 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
261 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
262
263 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
264 break;
265 }
266}
267
268/*
269 * Late setup - runs on secondary CPU before entering the idle loop
270 */
271static void bmips_smp_finish(void)
272{
273 pr_info("SMP: CPU%d is running\n", smp_processor_id());
274
275 /* make sure there won't be a timer interrupt for a little while */
276 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
277
278 irq_enable_hazard();
279 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
280 irq_enable_hazard();
281}
282
283/*
284 * Runs on CPU0 after all CPUs have been booted
285 */
286static void bmips_cpus_done(void)
287{
288}
289
290/*
291 * BMIPS5000 raceless IPIs
292 *
293 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
294 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
295 * IPI1 is used for SMP_CALL_FUNCTION
296 */
297
298static void bmips5000_send_ipi_single(int cpu, unsigned int action)
299{
300 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
301}
302
303static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
304{
305 int action = irq - IPI0_IRQ;
306
307 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
308
309 if (action == 0)
310 scheduler_ipi();
311 else
312 smp_call_function_interrupt();
313
314 return IRQ_HANDLED;
315}
316
317static void bmips5000_send_ipi_mask(const struct cpumask *mask,
318 unsigned int action)
319{
320 unsigned int i;
321
322 for_each_cpu(i, mask)
323 bmips5000_send_ipi_single(i, action);
324}
325
326/*
327 * BMIPS43xx racey IPIs
328 *
329 * We use one inbound SW IRQ for each CPU.
330 *
331 * A spinlock must be held in order to keep CPUx from accidentally clearing
332 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
333 * same spinlock is used to protect the action masks.
334 */
335
336static DEFINE_SPINLOCK(ipi_lock);
337static DEFINE_PER_CPU(int, ipi_action_mask);
338
339static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
340{
341 unsigned long flags;
342
343 spin_lock_irqsave(&ipi_lock, flags);
344 set_c0_cause(cpu ? C_SW1 : C_SW0);
345 per_cpu(ipi_action_mask, cpu) |= action;
346 irq_enable_hazard();
347 spin_unlock_irqrestore(&ipi_lock, flags);
348}
349
350static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
351{
352 unsigned long flags;
353 int action, cpu = irq - IPI0_IRQ;
354
355 spin_lock_irqsave(&ipi_lock, flags);
356 action = __get_cpu_var(ipi_action_mask);
357 per_cpu(ipi_action_mask, cpu) = 0;
358 clear_c0_cause(cpu ? C_SW1 : C_SW0);
359 spin_unlock_irqrestore(&ipi_lock, flags);
360
361 if (action & SMP_RESCHEDULE_YOURSELF)
362 scheduler_ipi();
363 if (action & SMP_CALL_FUNCTION)
364 smp_call_function_interrupt();
365
366 return IRQ_HANDLED;
367}
368
369static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
370 unsigned int action)
371{
372 unsigned int i;
373
374 for_each_cpu(i, mask)
375 bmips43xx_send_ipi_single(i, action);
376}
377
378#ifdef CONFIG_HOTPLUG_CPU
379
380static int bmips_cpu_disable(void)
381{
382 unsigned int cpu = smp_processor_id();
383
384 if (cpu == 0)
385 return -EBUSY;
386
387 pr_info("SMP: CPU%d is offline\n", cpu);
388
389 set_cpu_online(cpu, false);
390 cpu_clear(cpu, cpu_callin_map);
391
392 local_flush_tlb_all();
393 local_flush_icache_range(0, ~0);
394
395 return 0;
396}
397
398static void bmips_cpu_die(unsigned int cpu)
399{
400}
401
402void __ref play_dead(void)
403{
404 idle_task_exit();
405
406 /* flush data cache */
407 _dma_cache_wback_inv(0, ~0);
408
409 /*
410 * Wakeup is on SW0 or SW1; disable everything else
411 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
412 * IRQ handlers; this clears ST0_IE and returns immediately.
413 */
414 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
415 change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
416 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
417 irq_disable_hazard();
418
419 /*
420 * wait for SW interrupt from bmips_boot_secondary(), then jump
421 * back to start_secondary()
422 */
423 __asm__ __volatile__(
424 " wait\n"
425 " j bmips_secondary_reentry\n"
426 : : : "memory");
427}
428
429#endif /* CONFIG_HOTPLUG_CPU */
430
431struct plat_smp_ops bmips43xx_smp_ops = {
432 .smp_setup = bmips_smp_setup,
433 .prepare_cpus = bmips_prepare_cpus,
434 .boot_secondary = bmips_boot_secondary,
435 .smp_finish = bmips_smp_finish,
436 .init_secondary = bmips_init_secondary,
437 .cpus_done = bmips_cpus_done,
438 .send_ipi_single = bmips43xx_send_ipi_single,
439 .send_ipi_mask = bmips43xx_send_ipi_mask,
440#ifdef CONFIG_HOTPLUG_CPU
441 .cpu_disable = bmips_cpu_disable,
442 .cpu_die = bmips_cpu_die,
443#endif
444};
445
446struct plat_smp_ops bmips5000_smp_ops = {
447 .smp_setup = bmips_smp_setup,
448 .prepare_cpus = bmips_prepare_cpus,
449 .boot_secondary = bmips_boot_secondary,
450 .smp_finish = bmips_smp_finish,
451 .init_secondary = bmips_init_secondary,
452 .cpus_done = bmips_cpus_done,
453 .send_ipi_single = bmips5000_send_ipi_single,
454 .send_ipi_mask = bmips5000_send_ipi_mask,
455#ifdef CONFIG_HOTPLUG_CPU
456 .cpu_disable = bmips_cpu_disable,
457 .cpu_die = bmips_cpu_die,
458#endif
459};
460
461#endif /* CONFIG_SMP */
462
463/***********************************************************************
464 * BMIPS vector relocation
465 * This is primarily used for SMP boot, but it is applicable to some
466 * UP BMIPS systems as well.
467 ***********************************************************************/
468
469static void bmips_wr_vec(unsigned long dst, char *start, char *end)
470{
471 memcpy((void *)dst, start, end - start);
472 dma_cache_wback((unsigned long)start, end - start);
473 local_flush_icache_range(dst, dst + (end - start));
474 instruction_hazard();
475}
476
477static inline void bmips_nmi_handler_setup(void)
478{
479 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
480 &bmips_reset_nmi_vec_end);
481 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
482 &bmips_smp_int_vec_end);
483}
484
485void bmips_ebase_setup(void)
486{
487 unsigned long new_ebase = ebase;
488 void __iomem __maybe_unused *cbr;
489
490 BUG_ON(ebase != CKSEG0);
491
492 switch (current_cpu_type()) {
493 case CPU_BMIPS4350:
494 /*
495 * BMIPS4350 cannot relocate the normal vectors, but it
496 * can relocate the BEV=1 vectors. So CPU1 starts up at
497 * the relocated BEV=1, IV=0 general exception vector @
498 * 0xa000_0380.
499 *
500 * set_uncached_handler() is used here because:
501 * - CPU1 will run this from uncached space
502 * - None of the cacheflush functions are set up yet
503 */
504 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
505 &bmips_smp_int_vec, 0x80);
506 __sync();
507 return;
508 case CPU_BMIPS4380:
509 /*
510 * 0x8000_0000: reset/NMI (initially in kseg1)
511 * 0x8000_0400: normal vectors
512 */
513 new_ebase = 0x80000400;
514 cbr = BMIPS_GET_CBR();
515 __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
516 __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
517 break;
518 case CPU_BMIPS5000:
519 /*
520 * 0x8000_0000: reset/NMI (initially in kseg1)
521 * 0x8000_1000: normal vectors
522 */
523 new_ebase = 0x80001000;
524 write_c0_brcm_bootvec(0xa0088008);
525 write_c0_ebase(new_ebase);
526 if (max_cpus > 2)
527 bmips_write_zscm_reg(0xa0, 0xa008a008);
528 break;
529 default:
530 return;
531 }
532
533 board_nmi_handler_setup = &bmips_nmi_handler_setup;
534 ebase = new_ebase;
535}
536
537asmlinkage void __weak plat_wired_tlb_setup(void)
538{
539 /*
540 * Called when starting/restarting a secondary CPU.
541 * Kernel stacks and other important data might only be accessible
542 * once the wired entries are present.
543 */
544}