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1/*
2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <plat/omap_hwmod.h>
12#include <plat/serial.h>
13#include <plat/gpio.h>
14#include <plat/dma.h>
15#include <plat/dmtimer.h>
16#include <plat/mcspi.h>
17
18#include <mach/irqs.h>
19
20#include "omap_hwmod_common_data.h"
21#include "cm-regbits-24xx.h"
22#include "prm-regbits-24xx.h"
23#include "wd_timer.h"
24
25struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
26 { .irq = 48, },
27 { .irq = -1 }
28};
29
30struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
31 { .name = "dispc", .dma_req = 5 },
32 { .dma_req = -1 }
33};
34
35/*
36 * 'dispc' class
37 * display controller
38 */
39
40static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
41 .rev_offs = 0x0000,
42 .sysc_offs = 0x0010,
43 .syss_offs = 0x0014,
44 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
45 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
46 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
47 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
48 .sysc_fields = &omap_hwmod_sysc_type1,
49};
50
51struct omap_hwmod_class omap2_dispc_hwmod_class = {
52 .name = "dispc",
53 .sysc = &omap2_dispc_sysc,
54};
55
56/* OMAP2xxx Timer Common */
57static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
58 .rev_offs = 0x0000,
59 .sysc_offs = 0x0010,
60 .syss_offs = 0x0014,
61 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
62 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
63 SYSC_HAS_AUTOIDLE),
64 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
65 .sysc_fields = &omap_hwmod_sysc_type1,
66};
67
68struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
69 .name = "timer",
70 .sysc = &omap2xxx_timer_sysc,
71 .rev = OMAP_TIMER_IP_VERSION_1,
72};
73
74/*
75 * 'wd_timer' class
76 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
77 * overflow condition
78 */
79
80static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
81 .rev_offs = 0x0000,
82 .sysc_offs = 0x0010,
83 .syss_offs = 0x0014,
84 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
85 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
86 .sysc_fields = &omap_hwmod_sysc_type1,
87};
88
89struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
90 .name = "wd_timer",
91 .sysc = &omap2xxx_wd_timer_sysc,
92 .pre_shutdown = &omap2_wd_timer_disable,
93 .reset = &omap2_wd_timer_reset,
94};
95
96/*
97 * 'gpio' class
98 * general purpose io module
99 */
100static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
101 .rev_offs = 0x0000,
102 .sysc_offs = 0x0010,
103 .syss_offs = 0x0014,
104 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
105 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
106 SYSS_HAS_RESET_STATUS),
107 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
108 .sysc_fields = &omap_hwmod_sysc_type1,
109};
110
111struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
112 .name = "gpio",
113 .sysc = &omap2xxx_gpio_sysc,
114 .rev = 0,
115};
116
117/* system dma */
118static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
119 .rev_offs = 0x0000,
120 .sysc_offs = 0x002c,
121 .syss_offs = 0x0028,
122 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
123 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
124 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
125 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
126 .sysc_fields = &omap_hwmod_sysc_type1,
127};
128
129struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
130 .name = "dma",
131 .sysc = &omap2xxx_dma_sysc,
132};
133
134/*
135 * 'mailbox' class
136 * mailbox module allowing communication between the on-chip processors
137 * using a queued mailbox-interrupt mechanism.
138 */
139
140static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
141 .rev_offs = 0x000,
142 .sysc_offs = 0x010,
143 .syss_offs = 0x014,
144 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
145 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
146 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
147 .sysc_fields = &omap_hwmod_sysc_type1,
148};
149
150struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
151 .name = "mailbox",
152 .sysc = &omap2xxx_mailbox_sysc,
153};
154
155/*
156 * 'mcspi' class
157 * multichannel serial port interface (mcspi) / master/slave synchronous serial
158 * bus
159 */
160
161static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
162 .rev_offs = 0x0000,
163 .sysc_offs = 0x0010,
164 .syss_offs = 0x0014,
165 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
166 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
167 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
168 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
169 .sysc_fields = &omap_hwmod_sysc_type1,
170};
171
172struct omap_hwmod_class omap2xxx_mcspi_class = {
173 .name = "mcspi",
174 .sysc = &omap2xxx_mcspi_sysc,
175 .rev = OMAP2_MCSPI_REV,
176};
177
178/*
179 * IP blocks
180 */
181
182/* L3 */
183struct omap_hwmod omap2xxx_l3_main_hwmod = {
184 .name = "l3_main",
185 .class = &l3_hwmod_class,
186 .flags = HWMOD_NO_IDLEST,
187};
188
189/* L4 CORE */
190struct omap_hwmod omap2xxx_l4_core_hwmod = {
191 .name = "l4_core",
192 .class = &l4_hwmod_class,
193 .flags = HWMOD_NO_IDLEST,
194};
195
196/* L4 WKUP */
197struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
198 .name = "l4_wkup",
199 .class = &l4_hwmod_class,
200 .flags = HWMOD_NO_IDLEST,
201};
202
203/* MPU */
204struct omap_hwmod omap2xxx_mpu_hwmod = {
205 .name = "mpu",
206 .class = &mpu_hwmod_class,
207 .main_clk = "mpu_ck",
208};
209
210/* IVA2 */
211struct omap_hwmod omap2xxx_iva_hwmod = {
212 .name = "iva",
213 .class = &iva_hwmod_class,
214};
215
216/* always-on timers dev attribute */
217static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
218 .timer_capability = OMAP_TIMER_ALWON,
219};
220
221/* pwm timers dev attribute */
222static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
223 .timer_capability = OMAP_TIMER_HAS_PWM,
224};
225
226/* timer1 */
227
228struct omap_hwmod omap2xxx_timer1_hwmod = {
229 .name = "timer1",
230 .mpu_irqs = omap2_timer1_mpu_irqs,
231 .main_clk = "gpt1_fck",
232 .prcm = {
233 .omap2 = {
234 .prcm_reg_id = 1,
235 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
236 .module_offs = WKUP_MOD,
237 .idlest_reg_id = 1,
238 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
239 },
240 },
241 .dev_attr = &capability_alwon_dev_attr,
242 .class = &omap2xxx_timer_hwmod_class,
243};
244
245/* timer2 */
246
247struct omap_hwmod omap2xxx_timer2_hwmod = {
248 .name = "timer2",
249 .mpu_irqs = omap2_timer2_mpu_irqs,
250 .main_clk = "gpt2_fck",
251 .prcm = {
252 .omap2 = {
253 .prcm_reg_id = 1,
254 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
255 .module_offs = CORE_MOD,
256 .idlest_reg_id = 1,
257 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
258 },
259 },
260 .dev_attr = &capability_alwon_dev_attr,
261 .class = &omap2xxx_timer_hwmod_class,
262};
263
264/* timer3 */
265
266struct omap_hwmod omap2xxx_timer3_hwmod = {
267 .name = "timer3",
268 .mpu_irqs = omap2_timer3_mpu_irqs,
269 .main_clk = "gpt3_fck",
270 .prcm = {
271 .omap2 = {
272 .prcm_reg_id = 1,
273 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
274 .module_offs = CORE_MOD,
275 .idlest_reg_id = 1,
276 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
277 },
278 },
279 .dev_attr = &capability_alwon_dev_attr,
280 .class = &omap2xxx_timer_hwmod_class,
281};
282
283/* timer4 */
284
285struct omap_hwmod omap2xxx_timer4_hwmod = {
286 .name = "timer4",
287 .mpu_irqs = omap2_timer4_mpu_irqs,
288 .main_clk = "gpt4_fck",
289 .prcm = {
290 .omap2 = {
291 .prcm_reg_id = 1,
292 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
293 .module_offs = CORE_MOD,
294 .idlest_reg_id = 1,
295 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
296 },
297 },
298 .dev_attr = &capability_alwon_dev_attr,
299 .class = &omap2xxx_timer_hwmod_class,
300};
301
302/* timer5 */
303
304struct omap_hwmod omap2xxx_timer5_hwmod = {
305 .name = "timer5",
306 .mpu_irqs = omap2_timer5_mpu_irqs,
307 .main_clk = "gpt5_fck",
308 .prcm = {
309 .omap2 = {
310 .prcm_reg_id = 1,
311 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
312 .module_offs = CORE_MOD,
313 .idlest_reg_id = 1,
314 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
315 },
316 },
317 .dev_attr = &capability_alwon_dev_attr,
318 .class = &omap2xxx_timer_hwmod_class,
319};
320
321/* timer6 */
322
323struct omap_hwmod omap2xxx_timer6_hwmod = {
324 .name = "timer6",
325 .mpu_irqs = omap2_timer6_mpu_irqs,
326 .main_clk = "gpt6_fck",
327 .prcm = {
328 .omap2 = {
329 .prcm_reg_id = 1,
330 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
331 .module_offs = CORE_MOD,
332 .idlest_reg_id = 1,
333 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
334 },
335 },
336 .dev_attr = &capability_alwon_dev_attr,
337 .class = &omap2xxx_timer_hwmod_class,
338};
339
340/* timer7 */
341
342struct omap_hwmod omap2xxx_timer7_hwmod = {
343 .name = "timer7",
344 .mpu_irqs = omap2_timer7_mpu_irqs,
345 .main_clk = "gpt7_fck",
346 .prcm = {
347 .omap2 = {
348 .prcm_reg_id = 1,
349 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
350 .module_offs = CORE_MOD,
351 .idlest_reg_id = 1,
352 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
353 },
354 },
355 .dev_attr = &capability_alwon_dev_attr,
356 .class = &omap2xxx_timer_hwmod_class,
357};
358
359/* timer8 */
360
361struct omap_hwmod omap2xxx_timer8_hwmod = {
362 .name = "timer8",
363 .mpu_irqs = omap2_timer8_mpu_irqs,
364 .main_clk = "gpt8_fck",
365 .prcm = {
366 .omap2 = {
367 .prcm_reg_id = 1,
368 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
369 .module_offs = CORE_MOD,
370 .idlest_reg_id = 1,
371 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
372 },
373 },
374 .dev_attr = &capability_alwon_dev_attr,
375 .class = &omap2xxx_timer_hwmod_class,
376};
377
378/* timer9 */
379
380struct omap_hwmod omap2xxx_timer9_hwmod = {
381 .name = "timer9",
382 .mpu_irqs = omap2_timer9_mpu_irqs,
383 .main_clk = "gpt9_fck",
384 .prcm = {
385 .omap2 = {
386 .prcm_reg_id = 1,
387 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
388 .module_offs = CORE_MOD,
389 .idlest_reg_id = 1,
390 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
391 },
392 },
393 .dev_attr = &capability_pwm_dev_attr,
394 .class = &omap2xxx_timer_hwmod_class,
395};
396
397/* timer10 */
398
399struct omap_hwmod omap2xxx_timer10_hwmod = {
400 .name = "timer10",
401 .mpu_irqs = omap2_timer10_mpu_irqs,
402 .main_clk = "gpt10_fck",
403 .prcm = {
404 .omap2 = {
405 .prcm_reg_id = 1,
406 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
407 .module_offs = CORE_MOD,
408 .idlest_reg_id = 1,
409 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
410 },
411 },
412 .dev_attr = &capability_pwm_dev_attr,
413 .class = &omap2xxx_timer_hwmod_class,
414};
415
416/* timer11 */
417
418struct omap_hwmod omap2xxx_timer11_hwmod = {
419 .name = "timer11",
420 .mpu_irqs = omap2_timer11_mpu_irqs,
421 .main_clk = "gpt11_fck",
422 .prcm = {
423 .omap2 = {
424 .prcm_reg_id = 1,
425 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
426 .module_offs = CORE_MOD,
427 .idlest_reg_id = 1,
428 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
429 },
430 },
431 .dev_attr = &capability_pwm_dev_attr,
432 .class = &omap2xxx_timer_hwmod_class,
433};
434
435/* timer12 */
436
437struct omap_hwmod omap2xxx_timer12_hwmod = {
438 .name = "timer12",
439 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
440 .main_clk = "gpt12_fck",
441 .prcm = {
442 .omap2 = {
443 .prcm_reg_id = 1,
444 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
445 .module_offs = CORE_MOD,
446 .idlest_reg_id = 1,
447 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
448 },
449 },
450 .dev_attr = &capability_pwm_dev_attr,
451 .class = &omap2xxx_timer_hwmod_class,
452};
453
454/* wd_timer2 */
455struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
456 .name = "wd_timer2",
457 .class = &omap2xxx_wd_timer_hwmod_class,
458 .main_clk = "mpu_wdt_fck",
459 .prcm = {
460 .omap2 = {
461 .prcm_reg_id = 1,
462 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
463 .module_offs = WKUP_MOD,
464 .idlest_reg_id = 1,
465 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
466 },
467 },
468};
469
470/* UART1 */
471
472struct omap_hwmod omap2xxx_uart1_hwmod = {
473 .name = "uart1",
474 .mpu_irqs = omap2_uart1_mpu_irqs,
475 .sdma_reqs = omap2_uart1_sdma_reqs,
476 .main_clk = "uart1_fck",
477 .prcm = {
478 .omap2 = {
479 .module_offs = CORE_MOD,
480 .prcm_reg_id = 1,
481 .module_bit = OMAP24XX_EN_UART1_SHIFT,
482 .idlest_reg_id = 1,
483 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
484 },
485 },
486 .class = &omap2_uart_class,
487};
488
489/* UART2 */
490
491struct omap_hwmod omap2xxx_uart2_hwmod = {
492 .name = "uart2",
493 .mpu_irqs = omap2_uart2_mpu_irqs,
494 .sdma_reqs = omap2_uart2_sdma_reqs,
495 .main_clk = "uart2_fck",
496 .prcm = {
497 .omap2 = {
498 .module_offs = CORE_MOD,
499 .prcm_reg_id = 1,
500 .module_bit = OMAP24XX_EN_UART2_SHIFT,
501 .idlest_reg_id = 1,
502 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
503 },
504 },
505 .class = &omap2_uart_class,
506};
507
508/* UART3 */
509
510struct omap_hwmod omap2xxx_uart3_hwmod = {
511 .name = "uart3",
512 .mpu_irqs = omap2_uart3_mpu_irqs,
513 .sdma_reqs = omap2_uart3_sdma_reqs,
514 .main_clk = "uart3_fck",
515 .prcm = {
516 .omap2 = {
517 .module_offs = CORE_MOD,
518 .prcm_reg_id = 2,
519 .module_bit = OMAP24XX_EN_UART3_SHIFT,
520 .idlest_reg_id = 2,
521 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
522 },
523 },
524 .class = &omap2_uart_class,
525};
526
527/* dss */
528
529static struct omap_hwmod_opt_clk dss_opt_clks[] = {
530 /*
531 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
532 * driver does not use these clocks.
533 */
534 { .role = "tv_clk", .clk = "dss_54m_fck" },
535 { .role = "sys_clk", .clk = "dss2_fck" },
536};
537
538struct omap_hwmod omap2xxx_dss_core_hwmod = {
539 .name = "dss_core",
540 .class = &omap2_dss_hwmod_class,
541 .main_clk = "dss1_fck", /* instead of dss_fck */
542 .sdma_reqs = omap2xxx_dss_sdma_chs,
543 .prcm = {
544 .omap2 = {
545 .prcm_reg_id = 1,
546 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
547 .module_offs = CORE_MOD,
548 .idlest_reg_id = 1,
549 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
550 },
551 },
552 .opt_clks = dss_opt_clks,
553 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
554 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
555};
556
557struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
558 .name = "dss_dispc",
559 .class = &omap2_dispc_hwmod_class,
560 .mpu_irqs = omap2_dispc_irqs,
561 .main_clk = "dss1_fck",
562 .prcm = {
563 .omap2 = {
564 .prcm_reg_id = 1,
565 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
566 .module_offs = CORE_MOD,
567 .idlest_reg_id = 1,
568 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
569 },
570 },
571 .flags = HWMOD_NO_IDLEST,
572 .dev_attr = &omap2_3_dss_dispc_dev_attr
573};
574
575static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
576 { .role = "ick", .clk = "dss_ick" },
577};
578
579struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
580 .name = "dss_rfbi",
581 .class = &omap2_rfbi_hwmod_class,
582 .main_clk = "dss1_fck",
583 .prcm = {
584 .omap2 = {
585 .prcm_reg_id = 1,
586 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
587 .module_offs = CORE_MOD,
588 },
589 },
590 .opt_clks = dss_rfbi_opt_clks,
591 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
592 .flags = HWMOD_NO_IDLEST,
593};
594
595struct omap_hwmod omap2xxx_dss_venc_hwmod = {
596 .name = "dss_venc",
597 .class = &omap2_venc_hwmod_class,
598 .main_clk = "dss_54m_fck",
599 .prcm = {
600 .omap2 = {
601 .prcm_reg_id = 1,
602 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
603 .module_offs = CORE_MOD,
604 },
605 },
606 .flags = HWMOD_NO_IDLEST,
607};
608
609/* gpio dev_attr */
610struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
611 .bank_width = 32,
612 .dbck_flag = false,
613};
614
615/* gpio1 */
616struct omap_hwmod omap2xxx_gpio1_hwmod = {
617 .name = "gpio1",
618 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
619 .mpu_irqs = omap2_gpio1_irqs,
620 .main_clk = "gpios_fck",
621 .prcm = {
622 .omap2 = {
623 .prcm_reg_id = 1,
624 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
625 .module_offs = WKUP_MOD,
626 .idlest_reg_id = 1,
627 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
628 },
629 },
630 .class = &omap2xxx_gpio_hwmod_class,
631 .dev_attr = &omap2xxx_gpio_dev_attr,
632};
633
634/* gpio2 */
635struct omap_hwmod omap2xxx_gpio2_hwmod = {
636 .name = "gpio2",
637 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
638 .mpu_irqs = omap2_gpio2_irqs,
639 .main_clk = "gpios_fck",
640 .prcm = {
641 .omap2 = {
642 .prcm_reg_id = 1,
643 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
644 .module_offs = WKUP_MOD,
645 .idlest_reg_id = 1,
646 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
647 },
648 },
649 .class = &omap2xxx_gpio_hwmod_class,
650 .dev_attr = &omap2xxx_gpio_dev_attr,
651};
652
653/* gpio3 */
654struct omap_hwmod omap2xxx_gpio3_hwmod = {
655 .name = "gpio3",
656 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
657 .mpu_irqs = omap2_gpio3_irqs,
658 .main_clk = "gpios_fck",
659 .prcm = {
660 .omap2 = {
661 .prcm_reg_id = 1,
662 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
663 .module_offs = WKUP_MOD,
664 .idlest_reg_id = 1,
665 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
666 },
667 },
668 .class = &omap2xxx_gpio_hwmod_class,
669 .dev_attr = &omap2xxx_gpio_dev_attr,
670};
671
672/* gpio4 */
673struct omap_hwmod omap2xxx_gpio4_hwmod = {
674 .name = "gpio4",
675 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
676 .mpu_irqs = omap2_gpio4_irqs,
677 .main_clk = "gpios_fck",
678 .prcm = {
679 .omap2 = {
680 .prcm_reg_id = 1,
681 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
682 .module_offs = WKUP_MOD,
683 .idlest_reg_id = 1,
684 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
685 },
686 },
687 .class = &omap2xxx_gpio_hwmod_class,
688 .dev_attr = &omap2xxx_gpio_dev_attr,
689};
690
691/* mcspi1 */
692static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
693 .num_chipselect = 4,
694};
695
696struct omap_hwmod omap2xxx_mcspi1_hwmod = {
697 .name = "mcspi1",
698 .mpu_irqs = omap2_mcspi1_mpu_irqs,
699 .sdma_reqs = omap2_mcspi1_sdma_reqs,
700 .main_clk = "mcspi1_fck",
701 .prcm = {
702 .omap2 = {
703 .module_offs = CORE_MOD,
704 .prcm_reg_id = 1,
705 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
706 .idlest_reg_id = 1,
707 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
708 },
709 },
710 .class = &omap2xxx_mcspi_class,
711 .dev_attr = &omap_mcspi1_dev_attr,
712};
713
714/* mcspi2 */
715static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
716 .num_chipselect = 2,
717};
718
719struct omap_hwmod omap2xxx_mcspi2_hwmod = {
720 .name = "mcspi2",
721 .mpu_irqs = omap2_mcspi2_mpu_irqs,
722 .sdma_reqs = omap2_mcspi2_sdma_reqs,
723 .main_clk = "mcspi2_fck",
724 .prcm = {
725 .omap2 = {
726 .module_offs = CORE_MOD,
727 .prcm_reg_id = 1,
728 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
729 .idlest_reg_id = 1,
730 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
731 },
732 },
733 .class = &omap2xxx_mcspi_class,
734 .dev_attr = &omap_mcspi2_dev_attr,
735};
736
737
738static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
739 .name = "counter",
740};
741
742struct omap_hwmod omap2xxx_counter_32k_hwmod = {
743 .name = "counter_32k",
744 .main_clk = "func_32k_ck",
745 .prcm = {
746 .omap2 = {
747 .module_offs = WKUP_MOD,
748 .prcm_reg_id = 1,
749 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
750 .idlest_reg_id = 1,
751 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
752 },
753 },
754 .class = &omap2xxx_counter_hwmod_class,
755};
1/*
2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/platform_data/gpio-omap.h>
13#include <linux/omap-dma.h>
14#include <plat/dmtimer.h>
15#include <linux/platform_data/spi-omap2-mcspi.h>
16
17#include "omap_hwmod.h"
18#include "omap_hwmod_common_data.h"
19#include "cm-regbits-24xx.h"
20#include "prm-regbits-24xx.h"
21#include "wd_timer.h"
22
23struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
24 { .name = "dispc", .dma_req = 5 },
25 { .dma_req = -1, },
26};
27
28/*
29 * 'dispc' class
30 * display controller
31 */
32
33static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
34 .rev_offs = 0x0000,
35 .sysc_offs = 0x0010,
36 .syss_offs = 0x0014,
37 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
38 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
39 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
40 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
41 .sysc_fields = &omap_hwmod_sysc_type1,
42};
43
44struct omap_hwmod_class omap2_dispc_hwmod_class = {
45 .name = "dispc",
46 .sysc = &omap2_dispc_sysc,
47};
48
49/* OMAP2xxx Timer Common */
50static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
51 .rev_offs = 0x0000,
52 .sysc_offs = 0x0010,
53 .syss_offs = 0x0014,
54 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
55 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
56 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
57 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
58 .clockact = CLOCKACT_TEST_ICLK,
59 .sysc_fields = &omap_hwmod_sysc_type1,
60};
61
62struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
63 .name = "timer",
64 .sysc = &omap2xxx_timer_sysc,
65};
66
67/*
68 * 'wd_timer' class
69 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
70 * overflow condition
71 */
72
73static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
74 .rev_offs = 0x0000,
75 .sysc_offs = 0x0010,
76 .syss_offs = 0x0014,
77 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
78 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
79 .sysc_fields = &omap_hwmod_sysc_type1,
80};
81
82struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
83 .name = "wd_timer",
84 .sysc = &omap2xxx_wd_timer_sysc,
85 .pre_shutdown = &omap2_wd_timer_disable,
86 .reset = &omap2_wd_timer_reset,
87};
88
89/*
90 * 'gpio' class
91 * general purpose io module
92 */
93static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
94 .rev_offs = 0x0000,
95 .sysc_offs = 0x0010,
96 .syss_offs = 0x0014,
97 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
98 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
99 SYSS_HAS_RESET_STATUS),
100 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
101 .sysc_fields = &omap_hwmod_sysc_type1,
102};
103
104struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
105 .name = "gpio",
106 .sysc = &omap2xxx_gpio_sysc,
107 .rev = 0,
108};
109
110/* system dma */
111static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
112 .rev_offs = 0x0000,
113 .sysc_offs = 0x002c,
114 .syss_offs = 0x0028,
115 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
116 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
117 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
118 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
119 .sysc_fields = &omap_hwmod_sysc_type1,
120};
121
122struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
123 .name = "dma",
124 .sysc = &omap2xxx_dma_sysc,
125};
126
127/*
128 * 'mailbox' class
129 * mailbox module allowing communication between the on-chip processors
130 * using a queued mailbox-interrupt mechanism.
131 */
132
133static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
134 .rev_offs = 0x000,
135 .sysc_offs = 0x010,
136 .syss_offs = 0x014,
137 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
138 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
139 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
140 .sysc_fields = &omap_hwmod_sysc_type1,
141};
142
143struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
144 .name = "mailbox",
145 .sysc = &omap2xxx_mailbox_sysc,
146};
147
148/*
149 * 'mcspi' class
150 * multichannel serial port interface (mcspi) / master/slave synchronous serial
151 * bus
152 */
153
154static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
155 .rev_offs = 0x0000,
156 .sysc_offs = 0x0010,
157 .syss_offs = 0x0014,
158 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
159 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
160 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
161 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
162 .sysc_fields = &omap_hwmod_sysc_type1,
163};
164
165struct omap_hwmod_class omap2xxx_mcspi_class = {
166 .name = "mcspi",
167 .sysc = &omap2xxx_mcspi_sysc,
168 .rev = OMAP2_MCSPI_REV,
169};
170
171/*
172 * 'gpmc' class
173 * general purpose memory controller
174 */
175
176static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
177 .rev_offs = 0x0000,
178 .sysc_offs = 0x0010,
179 .syss_offs = 0x0014,
180 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
181 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
182 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
183 .sysc_fields = &omap_hwmod_sysc_type1,
184};
185
186static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
187 .name = "gpmc",
188 .sysc = &omap2xxx_gpmc_sysc,
189};
190
191/*
192 * IP blocks
193 */
194
195/* L3 */
196struct omap_hwmod omap2xxx_l3_main_hwmod = {
197 .name = "l3_main",
198 .class = &l3_hwmod_class,
199 .flags = HWMOD_NO_IDLEST,
200};
201
202/* L4 CORE */
203struct omap_hwmod omap2xxx_l4_core_hwmod = {
204 .name = "l4_core",
205 .class = &l4_hwmod_class,
206 .flags = HWMOD_NO_IDLEST,
207};
208
209/* L4 WKUP */
210struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
211 .name = "l4_wkup",
212 .class = &l4_hwmod_class,
213 .flags = HWMOD_NO_IDLEST,
214};
215
216/* MPU */
217struct omap_hwmod omap2xxx_mpu_hwmod = {
218 .name = "mpu",
219 .class = &mpu_hwmod_class,
220 .main_clk = "mpu_ck",
221};
222
223/* IVA2 */
224struct omap_hwmod omap2xxx_iva_hwmod = {
225 .name = "iva",
226 .class = &iva_hwmod_class,
227};
228
229/* always-on timers dev attribute */
230static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
231 .timer_capability = OMAP_TIMER_ALWON,
232};
233
234/* pwm timers dev attribute */
235static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
236 .timer_capability = OMAP_TIMER_HAS_PWM,
237};
238
239/* timers with DSP interrupt dev attribute */
240static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
241 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
242};
243
244/* timer1 */
245
246struct omap_hwmod omap2xxx_timer1_hwmod = {
247 .name = "timer1",
248 .main_clk = "gpt1_fck",
249 .prcm = {
250 .omap2 = {
251 .prcm_reg_id = 1,
252 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
253 .module_offs = WKUP_MOD,
254 .idlest_reg_id = 1,
255 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
256 },
257 },
258 .dev_attr = &capability_alwon_dev_attr,
259 .class = &omap2xxx_timer_hwmod_class,
260 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
261};
262
263/* timer2 */
264
265struct omap_hwmod omap2xxx_timer2_hwmod = {
266 .name = "timer2",
267 .main_clk = "gpt2_fck",
268 .prcm = {
269 .omap2 = {
270 .prcm_reg_id = 1,
271 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
272 .module_offs = CORE_MOD,
273 .idlest_reg_id = 1,
274 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
275 },
276 },
277 .class = &omap2xxx_timer_hwmod_class,
278 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
279};
280
281/* timer3 */
282
283struct omap_hwmod omap2xxx_timer3_hwmod = {
284 .name = "timer3",
285 .main_clk = "gpt3_fck",
286 .prcm = {
287 .omap2 = {
288 .prcm_reg_id = 1,
289 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
290 .module_offs = CORE_MOD,
291 .idlest_reg_id = 1,
292 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
293 },
294 },
295 .class = &omap2xxx_timer_hwmod_class,
296 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
297};
298
299/* timer4 */
300
301struct omap_hwmod omap2xxx_timer4_hwmod = {
302 .name = "timer4",
303 .main_clk = "gpt4_fck",
304 .prcm = {
305 .omap2 = {
306 .prcm_reg_id = 1,
307 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
308 .module_offs = CORE_MOD,
309 .idlest_reg_id = 1,
310 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
311 },
312 },
313 .class = &omap2xxx_timer_hwmod_class,
314 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
315};
316
317/* timer5 */
318
319struct omap_hwmod omap2xxx_timer5_hwmod = {
320 .name = "timer5",
321 .main_clk = "gpt5_fck",
322 .prcm = {
323 .omap2 = {
324 .prcm_reg_id = 1,
325 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
326 .module_offs = CORE_MOD,
327 .idlest_reg_id = 1,
328 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
329 },
330 },
331 .dev_attr = &capability_dsp_dev_attr,
332 .class = &omap2xxx_timer_hwmod_class,
333 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
334};
335
336/* timer6 */
337
338struct omap_hwmod omap2xxx_timer6_hwmod = {
339 .name = "timer6",
340 .main_clk = "gpt6_fck",
341 .prcm = {
342 .omap2 = {
343 .prcm_reg_id = 1,
344 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
345 .module_offs = CORE_MOD,
346 .idlest_reg_id = 1,
347 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
348 },
349 },
350 .dev_attr = &capability_dsp_dev_attr,
351 .class = &omap2xxx_timer_hwmod_class,
352 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
353};
354
355/* timer7 */
356
357struct omap_hwmod omap2xxx_timer7_hwmod = {
358 .name = "timer7",
359 .main_clk = "gpt7_fck",
360 .prcm = {
361 .omap2 = {
362 .prcm_reg_id = 1,
363 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
364 .module_offs = CORE_MOD,
365 .idlest_reg_id = 1,
366 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
367 },
368 },
369 .dev_attr = &capability_dsp_dev_attr,
370 .class = &omap2xxx_timer_hwmod_class,
371 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
372};
373
374/* timer8 */
375
376struct omap_hwmod omap2xxx_timer8_hwmod = {
377 .name = "timer8",
378 .main_clk = "gpt8_fck",
379 .prcm = {
380 .omap2 = {
381 .prcm_reg_id = 1,
382 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
383 .module_offs = CORE_MOD,
384 .idlest_reg_id = 1,
385 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
386 },
387 },
388 .dev_attr = &capability_dsp_dev_attr,
389 .class = &omap2xxx_timer_hwmod_class,
390 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
391};
392
393/* timer9 */
394
395struct omap_hwmod omap2xxx_timer9_hwmod = {
396 .name = "timer9",
397 .main_clk = "gpt9_fck",
398 .prcm = {
399 .omap2 = {
400 .prcm_reg_id = 1,
401 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
402 .module_offs = CORE_MOD,
403 .idlest_reg_id = 1,
404 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
405 },
406 },
407 .dev_attr = &capability_pwm_dev_attr,
408 .class = &omap2xxx_timer_hwmod_class,
409 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
410};
411
412/* timer10 */
413
414struct omap_hwmod omap2xxx_timer10_hwmod = {
415 .name = "timer10",
416 .main_clk = "gpt10_fck",
417 .prcm = {
418 .omap2 = {
419 .prcm_reg_id = 1,
420 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
421 .module_offs = CORE_MOD,
422 .idlest_reg_id = 1,
423 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
424 },
425 },
426 .dev_attr = &capability_pwm_dev_attr,
427 .class = &omap2xxx_timer_hwmod_class,
428 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
429};
430
431/* timer11 */
432
433struct omap_hwmod omap2xxx_timer11_hwmod = {
434 .name = "timer11",
435 .main_clk = "gpt11_fck",
436 .prcm = {
437 .omap2 = {
438 .prcm_reg_id = 1,
439 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
440 .module_offs = CORE_MOD,
441 .idlest_reg_id = 1,
442 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
443 },
444 },
445 .dev_attr = &capability_pwm_dev_attr,
446 .class = &omap2xxx_timer_hwmod_class,
447 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
448};
449
450/* timer12 */
451
452struct omap_hwmod omap2xxx_timer12_hwmod = {
453 .name = "timer12",
454 .main_clk = "gpt12_fck",
455 .prcm = {
456 .omap2 = {
457 .prcm_reg_id = 1,
458 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
459 .module_offs = CORE_MOD,
460 .idlest_reg_id = 1,
461 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
462 },
463 },
464 .dev_attr = &capability_pwm_dev_attr,
465 .class = &omap2xxx_timer_hwmod_class,
466 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
467};
468
469/* wd_timer2 */
470struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
471 .name = "wd_timer2",
472 .class = &omap2xxx_wd_timer_hwmod_class,
473 .main_clk = "mpu_wdt_fck",
474 .prcm = {
475 .omap2 = {
476 .prcm_reg_id = 1,
477 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
478 .module_offs = WKUP_MOD,
479 .idlest_reg_id = 1,
480 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
481 },
482 },
483};
484
485/* UART1 */
486
487struct omap_hwmod omap2xxx_uart1_hwmod = {
488 .name = "uart1",
489 .main_clk = "uart1_fck",
490 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
491 .prcm = {
492 .omap2 = {
493 .module_offs = CORE_MOD,
494 .prcm_reg_id = 1,
495 .module_bit = OMAP24XX_EN_UART1_SHIFT,
496 .idlest_reg_id = 1,
497 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
498 },
499 },
500 .class = &omap2_uart_class,
501};
502
503/* UART2 */
504
505struct omap_hwmod omap2xxx_uart2_hwmod = {
506 .name = "uart2",
507 .main_clk = "uart2_fck",
508 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
509 .prcm = {
510 .omap2 = {
511 .module_offs = CORE_MOD,
512 .prcm_reg_id = 1,
513 .module_bit = OMAP24XX_EN_UART2_SHIFT,
514 .idlest_reg_id = 1,
515 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
516 },
517 },
518 .class = &omap2_uart_class,
519};
520
521/* UART3 */
522
523struct omap_hwmod omap2xxx_uart3_hwmod = {
524 .name = "uart3",
525 .main_clk = "uart3_fck",
526 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
527 .prcm = {
528 .omap2 = {
529 .module_offs = CORE_MOD,
530 .prcm_reg_id = 2,
531 .module_bit = OMAP24XX_EN_UART3_SHIFT,
532 .idlest_reg_id = 2,
533 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
534 },
535 },
536 .class = &omap2_uart_class,
537};
538
539/* dss */
540
541static struct omap_hwmod_opt_clk dss_opt_clks[] = {
542 /*
543 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
544 * driver does not use these clocks.
545 */
546 { .role = "tv_clk", .clk = "dss_54m_fck" },
547 { .role = "sys_clk", .clk = "dss2_fck" },
548};
549
550struct omap_hwmod omap2xxx_dss_core_hwmod = {
551 .name = "dss_core",
552 .class = &omap2_dss_hwmod_class,
553 .main_clk = "dss1_fck", /* instead of dss_fck */
554 .sdma_reqs = omap2xxx_dss_sdma_chs,
555 .prcm = {
556 .omap2 = {
557 .prcm_reg_id = 1,
558 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
559 .module_offs = CORE_MOD,
560 .idlest_reg_id = 1,
561 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
562 },
563 },
564 .opt_clks = dss_opt_clks,
565 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
566 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
567};
568
569struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
570 .name = "dss_dispc",
571 .class = &omap2_dispc_hwmod_class,
572 .mpu_irqs = omap2_dispc_irqs,
573 .main_clk = "dss1_fck",
574 .prcm = {
575 .omap2 = {
576 .prcm_reg_id = 1,
577 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
578 .module_offs = CORE_MOD,
579 .idlest_reg_id = 1,
580 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
581 },
582 },
583 .flags = HWMOD_NO_IDLEST,
584 .dev_attr = &omap2_3_dss_dispc_dev_attr,
585};
586
587static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
588 { .role = "ick", .clk = "dss_ick" },
589};
590
591struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
592 .name = "dss_rfbi",
593 .class = &omap2_rfbi_hwmod_class,
594 .main_clk = "dss1_fck",
595 .prcm = {
596 .omap2 = {
597 .prcm_reg_id = 1,
598 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
599 .module_offs = CORE_MOD,
600 },
601 },
602 .opt_clks = dss_rfbi_opt_clks,
603 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
604 .flags = HWMOD_NO_IDLEST,
605};
606
607struct omap_hwmod omap2xxx_dss_venc_hwmod = {
608 .name = "dss_venc",
609 .class = &omap2_venc_hwmod_class,
610 .main_clk = "dss_54m_fck",
611 .prcm = {
612 .omap2 = {
613 .prcm_reg_id = 1,
614 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
615 .module_offs = CORE_MOD,
616 },
617 },
618 .flags = HWMOD_NO_IDLEST,
619};
620
621/* gpio dev_attr */
622struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
623 .bank_width = 32,
624 .dbck_flag = false,
625};
626
627/* gpio1 */
628struct omap_hwmod omap2xxx_gpio1_hwmod = {
629 .name = "gpio1",
630 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
631 .main_clk = "gpios_fck",
632 .prcm = {
633 .omap2 = {
634 .prcm_reg_id = 1,
635 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
636 .module_offs = WKUP_MOD,
637 .idlest_reg_id = 1,
638 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
639 },
640 },
641 .class = &omap2xxx_gpio_hwmod_class,
642 .dev_attr = &omap2xxx_gpio_dev_attr,
643};
644
645/* gpio2 */
646struct omap_hwmod omap2xxx_gpio2_hwmod = {
647 .name = "gpio2",
648 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
649 .main_clk = "gpios_fck",
650 .prcm = {
651 .omap2 = {
652 .prcm_reg_id = 1,
653 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
654 .module_offs = WKUP_MOD,
655 .idlest_reg_id = 1,
656 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
657 },
658 },
659 .class = &omap2xxx_gpio_hwmod_class,
660 .dev_attr = &omap2xxx_gpio_dev_attr,
661};
662
663/* gpio3 */
664struct omap_hwmod omap2xxx_gpio3_hwmod = {
665 .name = "gpio3",
666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
667 .main_clk = "gpios_fck",
668 .prcm = {
669 .omap2 = {
670 .prcm_reg_id = 1,
671 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
672 .module_offs = WKUP_MOD,
673 .idlest_reg_id = 1,
674 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
675 },
676 },
677 .class = &omap2xxx_gpio_hwmod_class,
678 .dev_attr = &omap2xxx_gpio_dev_attr,
679};
680
681/* gpio4 */
682struct omap_hwmod omap2xxx_gpio4_hwmod = {
683 .name = "gpio4",
684 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
685 .main_clk = "gpios_fck",
686 .prcm = {
687 .omap2 = {
688 .prcm_reg_id = 1,
689 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
690 .module_offs = WKUP_MOD,
691 .idlest_reg_id = 1,
692 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
693 },
694 },
695 .class = &omap2xxx_gpio_hwmod_class,
696 .dev_attr = &omap2xxx_gpio_dev_attr,
697};
698
699/* mcspi1 */
700static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
701 .num_chipselect = 4,
702};
703
704struct omap_hwmod omap2xxx_mcspi1_hwmod = {
705 .name = "mcspi1",
706 .main_clk = "mcspi1_fck",
707 .prcm = {
708 .omap2 = {
709 .module_offs = CORE_MOD,
710 .prcm_reg_id = 1,
711 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
712 .idlest_reg_id = 1,
713 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
714 },
715 },
716 .class = &omap2xxx_mcspi_class,
717 .dev_attr = &omap_mcspi1_dev_attr,
718};
719
720/* mcspi2 */
721static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
722 .num_chipselect = 2,
723};
724
725struct omap_hwmod omap2xxx_mcspi2_hwmod = {
726 .name = "mcspi2",
727 .main_clk = "mcspi2_fck",
728 .prcm = {
729 .omap2 = {
730 .module_offs = CORE_MOD,
731 .prcm_reg_id = 1,
732 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
733 .idlest_reg_id = 1,
734 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
735 },
736 },
737 .class = &omap2xxx_mcspi_class,
738 .dev_attr = &omap_mcspi2_dev_attr,
739};
740
741static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
742 .name = "counter",
743};
744
745struct omap_hwmod omap2xxx_counter_32k_hwmod = {
746 .name = "counter_32k",
747 .main_clk = "func_32k_ck",
748 .prcm = {
749 .omap2 = {
750 .module_offs = WKUP_MOD,
751 .prcm_reg_id = 1,
752 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
753 .idlest_reg_id = 1,
754 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
755 },
756 },
757 .class = &omap2xxx_counter_hwmod_class,
758};
759
760/* gpmc */
761struct omap_hwmod omap2xxx_gpmc_hwmod = {
762 .name = "gpmc",
763 .class = &omap2xxx_gpmc_hwmod_class,
764 .main_clk = "gpmc_fck",
765 /*
766 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
767 * block. It is not being added due to any known bugs with
768 * resetting the GPMC IP block, but rather because any timings
769 * set by the bootloader are not being correctly programmed by
770 * the kernel from the board file or DT data.
771 * HWMOD_INIT_NO_RESET should be removed ASAP.
772 */
773 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
774 HWMOD_NO_IDLEST),
775 .prcm = {
776 .omap2 = {
777 .prcm_reg_id = 3,
778 .module_bit = OMAP24XX_EN_GPMC_MASK,
779 .module_offs = CORE_MOD,
780 },
781 },
782};
783
784/* RNG */
785
786static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
787 .rev_offs = 0x3c,
788 .sysc_offs = 0x40,
789 .syss_offs = 0x44,
790 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
791 SYSS_HAS_RESET_STATUS),
792 .sysc_fields = &omap_hwmod_sysc_type1,
793};
794
795static struct omap_hwmod_class omap2_rng_hwmod_class = {
796 .name = "rng",
797 .sysc = &omap2_rng_sysc,
798};
799
800struct omap_hwmod omap2xxx_rng_hwmod = {
801 .name = "rng",
802 .main_clk = "l4_ck",
803 .prcm = {
804 .omap2 = {
805 .module_offs = CORE_MOD,
806 .prcm_reg_id = 4,
807 .module_bit = OMAP24XX_EN_RNG_SHIFT,
808 .idlest_reg_id = 4,
809 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
810 },
811 },
812 /*
813 * XXX The first read from the SYSSTATUS register of the RNG
814 * after the SYSCONFIG SOFTRESET bit is set triggers an
815 * imprecise external abort. It's unclear why this happens.
816 * Until this is analyzed, skip the IP block reset.
817 */
818 .flags = HWMOD_INIT_NO_RESET,
819 .class = &omap2_rng_hwmod_class,
820};
821
822/* SHAM */
823
824static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
825 .rev_offs = 0x5c,
826 .sysc_offs = 0x60,
827 .syss_offs = 0x64,
828 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
829 SYSS_HAS_RESET_STATUS),
830 .sysc_fields = &omap_hwmod_sysc_type1,
831};
832
833static struct omap_hwmod_class omap2xxx_sham_class = {
834 .name = "sham",
835 .sysc = &omap2_sham_sysc,
836};
837
838struct omap_hwmod omap2xxx_sham_hwmod = {
839 .name = "sham",
840 .main_clk = "l4_ck",
841 .prcm = {
842 .omap2 = {
843 .module_offs = CORE_MOD,
844 .prcm_reg_id = 4,
845 .module_bit = OMAP24XX_EN_SHA_SHIFT,
846 .idlest_reg_id = 4,
847 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
848 },
849 },
850 .class = &omap2xxx_sham_class,
851};
852
853/* AES */
854
855static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
856 .rev_offs = 0x44,
857 .sysc_offs = 0x48,
858 .syss_offs = 0x4c,
859 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
860 SYSS_HAS_RESET_STATUS),
861 .sysc_fields = &omap_hwmod_sysc_type1,
862};
863
864static struct omap_hwmod_class omap2xxx_aes_class = {
865 .name = "aes",
866 .sysc = &omap2_aes_sysc,
867};
868
869struct omap_hwmod omap2xxx_aes_hwmod = {
870 .name = "aes",
871 .main_clk = "l4_ck",
872 .prcm = {
873 .omap2 = {
874 .module_offs = CORE_MOD,
875 .prcm_reg_id = 4,
876 .module_bit = OMAP24XX_EN_AES_SHIFT,
877 .idlest_reg_id = 4,
878 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
879 },
880 },
881 .class = &omap2xxx_aes_class,
882};