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1/*
2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <plat/omap_hwmod.h>
12#include <plat/serial.h>
13#include <plat/gpio.h>
14#include <plat/dma.h>
15#include <plat/dmtimer.h>
16#include <plat/mcspi.h>
17
18#include <mach/irqs.h>
19
20#include "omap_hwmod_common_data.h"
21#include "cm-regbits-24xx.h"
22#include "prm-regbits-24xx.h"
23#include "wd_timer.h"
24
25struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
26 { .irq = 48, },
27 { .irq = -1 }
28};
29
30struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
31 { .name = "dispc", .dma_req = 5 },
32 { .dma_req = -1 }
33};
34
35/*
36 * 'dispc' class
37 * display controller
38 */
39
40static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
41 .rev_offs = 0x0000,
42 .sysc_offs = 0x0010,
43 .syss_offs = 0x0014,
44 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
45 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
46 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
47 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
48 .sysc_fields = &omap_hwmod_sysc_type1,
49};
50
51struct omap_hwmod_class omap2_dispc_hwmod_class = {
52 .name = "dispc",
53 .sysc = &omap2_dispc_sysc,
54};
55
56/* OMAP2xxx Timer Common */
57static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
58 .rev_offs = 0x0000,
59 .sysc_offs = 0x0010,
60 .syss_offs = 0x0014,
61 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
62 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
63 SYSC_HAS_AUTOIDLE),
64 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
65 .sysc_fields = &omap_hwmod_sysc_type1,
66};
67
68struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
69 .name = "timer",
70 .sysc = &omap2xxx_timer_sysc,
71 .rev = OMAP_TIMER_IP_VERSION_1,
72};
73
74/*
75 * 'wd_timer' class
76 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
77 * overflow condition
78 */
79
80static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
81 .rev_offs = 0x0000,
82 .sysc_offs = 0x0010,
83 .syss_offs = 0x0014,
84 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
85 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
86 .sysc_fields = &omap_hwmod_sysc_type1,
87};
88
89struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
90 .name = "wd_timer",
91 .sysc = &omap2xxx_wd_timer_sysc,
92 .pre_shutdown = &omap2_wd_timer_disable,
93 .reset = &omap2_wd_timer_reset,
94};
95
96/*
97 * 'gpio' class
98 * general purpose io module
99 */
100static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
101 .rev_offs = 0x0000,
102 .sysc_offs = 0x0010,
103 .syss_offs = 0x0014,
104 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
105 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
106 SYSS_HAS_RESET_STATUS),
107 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
108 .sysc_fields = &omap_hwmod_sysc_type1,
109};
110
111struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
112 .name = "gpio",
113 .sysc = &omap2xxx_gpio_sysc,
114 .rev = 0,
115};
116
117/* system dma */
118static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
119 .rev_offs = 0x0000,
120 .sysc_offs = 0x002c,
121 .syss_offs = 0x0028,
122 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
123 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
124 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
125 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
126 .sysc_fields = &omap_hwmod_sysc_type1,
127};
128
129struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
130 .name = "dma",
131 .sysc = &omap2xxx_dma_sysc,
132};
133
134/*
135 * 'mailbox' class
136 * mailbox module allowing communication between the on-chip processors
137 * using a queued mailbox-interrupt mechanism.
138 */
139
140static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
141 .rev_offs = 0x000,
142 .sysc_offs = 0x010,
143 .syss_offs = 0x014,
144 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
145 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
146 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
147 .sysc_fields = &omap_hwmod_sysc_type1,
148};
149
150struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
151 .name = "mailbox",
152 .sysc = &omap2xxx_mailbox_sysc,
153};
154
155/*
156 * 'mcspi' class
157 * multichannel serial port interface (mcspi) / master/slave synchronous serial
158 * bus
159 */
160
161static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
162 .rev_offs = 0x0000,
163 .sysc_offs = 0x0010,
164 .syss_offs = 0x0014,
165 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
166 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
167 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
168 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
169 .sysc_fields = &omap_hwmod_sysc_type1,
170};
171
172struct omap_hwmod_class omap2xxx_mcspi_class = {
173 .name = "mcspi",
174 .sysc = &omap2xxx_mcspi_sysc,
175 .rev = OMAP2_MCSPI_REV,
176};
177
178/*
179 * IP blocks
180 */
181
182/* L3 */
183struct omap_hwmod omap2xxx_l3_main_hwmod = {
184 .name = "l3_main",
185 .class = &l3_hwmod_class,
186 .flags = HWMOD_NO_IDLEST,
187};
188
189/* L4 CORE */
190struct omap_hwmod omap2xxx_l4_core_hwmod = {
191 .name = "l4_core",
192 .class = &l4_hwmod_class,
193 .flags = HWMOD_NO_IDLEST,
194};
195
196/* L4 WKUP */
197struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
198 .name = "l4_wkup",
199 .class = &l4_hwmod_class,
200 .flags = HWMOD_NO_IDLEST,
201};
202
203/* MPU */
204struct omap_hwmod omap2xxx_mpu_hwmod = {
205 .name = "mpu",
206 .class = &mpu_hwmod_class,
207 .main_clk = "mpu_ck",
208};
209
210/* IVA2 */
211struct omap_hwmod omap2xxx_iva_hwmod = {
212 .name = "iva",
213 .class = &iva_hwmod_class,
214};
215
216/* always-on timers dev attribute */
217static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
218 .timer_capability = OMAP_TIMER_ALWON,
219};
220
221/* pwm timers dev attribute */
222static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
223 .timer_capability = OMAP_TIMER_HAS_PWM,
224};
225
226/* timer1 */
227
228struct omap_hwmod omap2xxx_timer1_hwmod = {
229 .name = "timer1",
230 .mpu_irqs = omap2_timer1_mpu_irqs,
231 .main_clk = "gpt1_fck",
232 .prcm = {
233 .omap2 = {
234 .prcm_reg_id = 1,
235 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
236 .module_offs = WKUP_MOD,
237 .idlest_reg_id = 1,
238 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
239 },
240 },
241 .dev_attr = &capability_alwon_dev_attr,
242 .class = &omap2xxx_timer_hwmod_class,
243};
244
245/* timer2 */
246
247struct omap_hwmod omap2xxx_timer2_hwmod = {
248 .name = "timer2",
249 .mpu_irqs = omap2_timer2_mpu_irqs,
250 .main_clk = "gpt2_fck",
251 .prcm = {
252 .omap2 = {
253 .prcm_reg_id = 1,
254 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
255 .module_offs = CORE_MOD,
256 .idlest_reg_id = 1,
257 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
258 },
259 },
260 .dev_attr = &capability_alwon_dev_attr,
261 .class = &omap2xxx_timer_hwmod_class,
262};
263
264/* timer3 */
265
266struct omap_hwmod omap2xxx_timer3_hwmod = {
267 .name = "timer3",
268 .mpu_irqs = omap2_timer3_mpu_irqs,
269 .main_clk = "gpt3_fck",
270 .prcm = {
271 .omap2 = {
272 .prcm_reg_id = 1,
273 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
274 .module_offs = CORE_MOD,
275 .idlest_reg_id = 1,
276 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
277 },
278 },
279 .dev_attr = &capability_alwon_dev_attr,
280 .class = &omap2xxx_timer_hwmod_class,
281};
282
283/* timer4 */
284
285struct omap_hwmod omap2xxx_timer4_hwmod = {
286 .name = "timer4",
287 .mpu_irqs = omap2_timer4_mpu_irqs,
288 .main_clk = "gpt4_fck",
289 .prcm = {
290 .omap2 = {
291 .prcm_reg_id = 1,
292 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
293 .module_offs = CORE_MOD,
294 .idlest_reg_id = 1,
295 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
296 },
297 },
298 .dev_attr = &capability_alwon_dev_attr,
299 .class = &omap2xxx_timer_hwmod_class,
300};
301
302/* timer5 */
303
304struct omap_hwmod omap2xxx_timer5_hwmod = {
305 .name = "timer5",
306 .mpu_irqs = omap2_timer5_mpu_irqs,
307 .main_clk = "gpt5_fck",
308 .prcm = {
309 .omap2 = {
310 .prcm_reg_id = 1,
311 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
312 .module_offs = CORE_MOD,
313 .idlest_reg_id = 1,
314 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
315 },
316 },
317 .dev_attr = &capability_alwon_dev_attr,
318 .class = &omap2xxx_timer_hwmod_class,
319};
320
321/* timer6 */
322
323struct omap_hwmod omap2xxx_timer6_hwmod = {
324 .name = "timer6",
325 .mpu_irqs = omap2_timer6_mpu_irqs,
326 .main_clk = "gpt6_fck",
327 .prcm = {
328 .omap2 = {
329 .prcm_reg_id = 1,
330 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
331 .module_offs = CORE_MOD,
332 .idlest_reg_id = 1,
333 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
334 },
335 },
336 .dev_attr = &capability_alwon_dev_attr,
337 .class = &omap2xxx_timer_hwmod_class,
338};
339
340/* timer7 */
341
342struct omap_hwmod omap2xxx_timer7_hwmod = {
343 .name = "timer7",
344 .mpu_irqs = omap2_timer7_mpu_irqs,
345 .main_clk = "gpt7_fck",
346 .prcm = {
347 .omap2 = {
348 .prcm_reg_id = 1,
349 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
350 .module_offs = CORE_MOD,
351 .idlest_reg_id = 1,
352 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
353 },
354 },
355 .dev_attr = &capability_alwon_dev_attr,
356 .class = &omap2xxx_timer_hwmod_class,
357};
358
359/* timer8 */
360
361struct omap_hwmod omap2xxx_timer8_hwmod = {
362 .name = "timer8",
363 .mpu_irqs = omap2_timer8_mpu_irqs,
364 .main_clk = "gpt8_fck",
365 .prcm = {
366 .omap2 = {
367 .prcm_reg_id = 1,
368 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
369 .module_offs = CORE_MOD,
370 .idlest_reg_id = 1,
371 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
372 },
373 },
374 .dev_attr = &capability_alwon_dev_attr,
375 .class = &omap2xxx_timer_hwmod_class,
376};
377
378/* timer9 */
379
380struct omap_hwmod omap2xxx_timer9_hwmod = {
381 .name = "timer9",
382 .mpu_irqs = omap2_timer9_mpu_irqs,
383 .main_clk = "gpt9_fck",
384 .prcm = {
385 .omap2 = {
386 .prcm_reg_id = 1,
387 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
388 .module_offs = CORE_MOD,
389 .idlest_reg_id = 1,
390 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
391 },
392 },
393 .dev_attr = &capability_pwm_dev_attr,
394 .class = &omap2xxx_timer_hwmod_class,
395};
396
397/* timer10 */
398
399struct omap_hwmod omap2xxx_timer10_hwmod = {
400 .name = "timer10",
401 .mpu_irqs = omap2_timer10_mpu_irqs,
402 .main_clk = "gpt10_fck",
403 .prcm = {
404 .omap2 = {
405 .prcm_reg_id = 1,
406 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
407 .module_offs = CORE_MOD,
408 .idlest_reg_id = 1,
409 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
410 },
411 },
412 .dev_attr = &capability_pwm_dev_attr,
413 .class = &omap2xxx_timer_hwmod_class,
414};
415
416/* timer11 */
417
418struct omap_hwmod omap2xxx_timer11_hwmod = {
419 .name = "timer11",
420 .mpu_irqs = omap2_timer11_mpu_irqs,
421 .main_clk = "gpt11_fck",
422 .prcm = {
423 .omap2 = {
424 .prcm_reg_id = 1,
425 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
426 .module_offs = CORE_MOD,
427 .idlest_reg_id = 1,
428 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
429 },
430 },
431 .dev_attr = &capability_pwm_dev_attr,
432 .class = &omap2xxx_timer_hwmod_class,
433};
434
435/* timer12 */
436
437struct omap_hwmod omap2xxx_timer12_hwmod = {
438 .name = "timer12",
439 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
440 .main_clk = "gpt12_fck",
441 .prcm = {
442 .omap2 = {
443 .prcm_reg_id = 1,
444 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
445 .module_offs = CORE_MOD,
446 .idlest_reg_id = 1,
447 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
448 },
449 },
450 .dev_attr = &capability_pwm_dev_attr,
451 .class = &omap2xxx_timer_hwmod_class,
452};
453
454/* wd_timer2 */
455struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
456 .name = "wd_timer2",
457 .class = &omap2xxx_wd_timer_hwmod_class,
458 .main_clk = "mpu_wdt_fck",
459 .prcm = {
460 .omap2 = {
461 .prcm_reg_id = 1,
462 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
463 .module_offs = WKUP_MOD,
464 .idlest_reg_id = 1,
465 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
466 },
467 },
468};
469
470/* UART1 */
471
472struct omap_hwmod omap2xxx_uart1_hwmod = {
473 .name = "uart1",
474 .mpu_irqs = omap2_uart1_mpu_irqs,
475 .sdma_reqs = omap2_uart1_sdma_reqs,
476 .main_clk = "uart1_fck",
477 .prcm = {
478 .omap2 = {
479 .module_offs = CORE_MOD,
480 .prcm_reg_id = 1,
481 .module_bit = OMAP24XX_EN_UART1_SHIFT,
482 .idlest_reg_id = 1,
483 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
484 },
485 },
486 .class = &omap2_uart_class,
487};
488
489/* UART2 */
490
491struct omap_hwmod omap2xxx_uart2_hwmod = {
492 .name = "uart2",
493 .mpu_irqs = omap2_uart2_mpu_irqs,
494 .sdma_reqs = omap2_uart2_sdma_reqs,
495 .main_clk = "uart2_fck",
496 .prcm = {
497 .omap2 = {
498 .module_offs = CORE_MOD,
499 .prcm_reg_id = 1,
500 .module_bit = OMAP24XX_EN_UART2_SHIFT,
501 .idlest_reg_id = 1,
502 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
503 },
504 },
505 .class = &omap2_uart_class,
506};
507
508/* UART3 */
509
510struct omap_hwmod omap2xxx_uart3_hwmod = {
511 .name = "uart3",
512 .mpu_irqs = omap2_uart3_mpu_irqs,
513 .sdma_reqs = omap2_uart3_sdma_reqs,
514 .main_clk = "uart3_fck",
515 .prcm = {
516 .omap2 = {
517 .module_offs = CORE_MOD,
518 .prcm_reg_id = 2,
519 .module_bit = OMAP24XX_EN_UART3_SHIFT,
520 .idlest_reg_id = 2,
521 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
522 },
523 },
524 .class = &omap2_uart_class,
525};
526
527/* dss */
528
529static struct omap_hwmod_opt_clk dss_opt_clks[] = {
530 /*
531 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
532 * driver does not use these clocks.
533 */
534 { .role = "tv_clk", .clk = "dss_54m_fck" },
535 { .role = "sys_clk", .clk = "dss2_fck" },
536};
537
538struct omap_hwmod omap2xxx_dss_core_hwmod = {
539 .name = "dss_core",
540 .class = &omap2_dss_hwmod_class,
541 .main_clk = "dss1_fck", /* instead of dss_fck */
542 .sdma_reqs = omap2xxx_dss_sdma_chs,
543 .prcm = {
544 .omap2 = {
545 .prcm_reg_id = 1,
546 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
547 .module_offs = CORE_MOD,
548 .idlest_reg_id = 1,
549 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
550 },
551 },
552 .opt_clks = dss_opt_clks,
553 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
554 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
555};
556
557struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
558 .name = "dss_dispc",
559 .class = &omap2_dispc_hwmod_class,
560 .mpu_irqs = omap2_dispc_irqs,
561 .main_clk = "dss1_fck",
562 .prcm = {
563 .omap2 = {
564 .prcm_reg_id = 1,
565 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
566 .module_offs = CORE_MOD,
567 .idlest_reg_id = 1,
568 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
569 },
570 },
571 .flags = HWMOD_NO_IDLEST,
572 .dev_attr = &omap2_3_dss_dispc_dev_attr
573};
574
575static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
576 { .role = "ick", .clk = "dss_ick" },
577};
578
579struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
580 .name = "dss_rfbi",
581 .class = &omap2_rfbi_hwmod_class,
582 .main_clk = "dss1_fck",
583 .prcm = {
584 .omap2 = {
585 .prcm_reg_id = 1,
586 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
587 .module_offs = CORE_MOD,
588 },
589 },
590 .opt_clks = dss_rfbi_opt_clks,
591 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
592 .flags = HWMOD_NO_IDLEST,
593};
594
595struct omap_hwmod omap2xxx_dss_venc_hwmod = {
596 .name = "dss_venc",
597 .class = &omap2_venc_hwmod_class,
598 .main_clk = "dss_54m_fck",
599 .prcm = {
600 .omap2 = {
601 .prcm_reg_id = 1,
602 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
603 .module_offs = CORE_MOD,
604 },
605 },
606 .flags = HWMOD_NO_IDLEST,
607};
608
609/* gpio dev_attr */
610struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
611 .bank_width = 32,
612 .dbck_flag = false,
613};
614
615/* gpio1 */
616struct omap_hwmod omap2xxx_gpio1_hwmod = {
617 .name = "gpio1",
618 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
619 .mpu_irqs = omap2_gpio1_irqs,
620 .main_clk = "gpios_fck",
621 .prcm = {
622 .omap2 = {
623 .prcm_reg_id = 1,
624 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
625 .module_offs = WKUP_MOD,
626 .idlest_reg_id = 1,
627 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
628 },
629 },
630 .class = &omap2xxx_gpio_hwmod_class,
631 .dev_attr = &omap2xxx_gpio_dev_attr,
632};
633
634/* gpio2 */
635struct omap_hwmod omap2xxx_gpio2_hwmod = {
636 .name = "gpio2",
637 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
638 .mpu_irqs = omap2_gpio2_irqs,
639 .main_clk = "gpios_fck",
640 .prcm = {
641 .omap2 = {
642 .prcm_reg_id = 1,
643 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
644 .module_offs = WKUP_MOD,
645 .idlest_reg_id = 1,
646 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
647 },
648 },
649 .class = &omap2xxx_gpio_hwmod_class,
650 .dev_attr = &omap2xxx_gpio_dev_attr,
651};
652
653/* gpio3 */
654struct omap_hwmod omap2xxx_gpio3_hwmod = {
655 .name = "gpio3",
656 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
657 .mpu_irqs = omap2_gpio3_irqs,
658 .main_clk = "gpios_fck",
659 .prcm = {
660 .omap2 = {
661 .prcm_reg_id = 1,
662 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
663 .module_offs = WKUP_MOD,
664 .idlest_reg_id = 1,
665 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
666 },
667 },
668 .class = &omap2xxx_gpio_hwmod_class,
669 .dev_attr = &omap2xxx_gpio_dev_attr,
670};
671
672/* gpio4 */
673struct omap_hwmod omap2xxx_gpio4_hwmod = {
674 .name = "gpio4",
675 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
676 .mpu_irqs = omap2_gpio4_irqs,
677 .main_clk = "gpios_fck",
678 .prcm = {
679 .omap2 = {
680 .prcm_reg_id = 1,
681 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
682 .module_offs = WKUP_MOD,
683 .idlest_reg_id = 1,
684 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
685 },
686 },
687 .class = &omap2xxx_gpio_hwmod_class,
688 .dev_attr = &omap2xxx_gpio_dev_attr,
689};
690
691/* mcspi1 */
692static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
693 .num_chipselect = 4,
694};
695
696struct omap_hwmod omap2xxx_mcspi1_hwmod = {
697 .name = "mcspi1",
698 .mpu_irqs = omap2_mcspi1_mpu_irqs,
699 .sdma_reqs = omap2_mcspi1_sdma_reqs,
700 .main_clk = "mcspi1_fck",
701 .prcm = {
702 .omap2 = {
703 .module_offs = CORE_MOD,
704 .prcm_reg_id = 1,
705 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
706 .idlest_reg_id = 1,
707 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
708 },
709 },
710 .class = &omap2xxx_mcspi_class,
711 .dev_attr = &omap_mcspi1_dev_attr,
712};
713
714/* mcspi2 */
715static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
716 .num_chipselect = 2,
717};
718
719struct omap_hwmod omap2xxx_mcspi2_hwmod = {
720 .name = "mcspi2",
721 .mpu_irqs = omap2_mcspi2_mpu_irqs,
722 .sdma_reqs = omap2_mcspi2_sdma_reqs,
723 .main_clk = "mcspi2_fck",
724 .prcm = {
725 .omap2 = {
726 .module_offs = CORE_MOD,
727 .prcm_reg_id = 1,
728 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
729 .idlest_reg_id = 1,
730 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
731 },
732 },
733 .class = &omap2xxx_mcspi_class,
734 .dev_attr = &omap_mcspi2_dev_attr,
735};
736
737
738static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
739 .name = "counter",
740};
741
742struct omap_hwmod omap2xxx_counter_32k_hwmod = {
743 .name = "counter_32k",
744 .main_clk = "func_32k_ck",
745 .prcm = {
746 .omap2 = {
747 .module_offs = WKUP_MOD,
748 .prcm_reg_id = 1,
749 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
750 .idlest_reg_id = 1,
751 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
752 },
753 },
754 .class = &omap2xxx_counter_hwmod_class,
755};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 *
5 * Copyright (C) 2011 Nokia Corporation
6 * Paul Walmsley
7 */
8
9#include <linux/types.h>
10
11#include "omap_hwmod.h"
12#include "omap_hwmod_common_data.h"
13#include "cm-regbits-24xx.h"
14#include "prm-regbits-24xx.h"
15#include "wd_timer.h"
16
17/*
18 * 'dispc' class
19 * display controller
20 */
21
22static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
23 .rev_offs = 0x0000,
24 .sysc_offs = 0x0010,
25 .syss_offs = 0x0014,
26 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
27 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
29 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
30 .sysc_fields = &omap_hwmod_sysc_type1,
31};
32
33struct omap_hwmod_class omap2_dispc_hwmod_class = {
34 .name = "dispc",
35 .sysc = &omap2_dispc_sysc,
36};
37
38/* OMAP2xxx Timer Common */
39static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
40 .rev_offs = 0x0000,
41 .sysc_offs = 0x0010,
42 .syss_offs = 0x0014,
43 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
44 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
45 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
46 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
47 .sysc_fields = &omap_hwmod_sysc_type1,
48};
49
50struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
51 .name = "timer",
52 .sysc = &omap2xxx_timer_sysc,
53};
54
55/*
56 * 'wd_timer' class
57 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
58 * overflow condition
59 */
60
61static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
62 .rev_offs = 0x0000,
63 .sysc_offs = 0x0010,
64 .syss_offs = 0x0014,
65 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
66 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
67 .sysc_fields = &omap_hwmod_sysc_type1,
68};
69
70struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
71 .name = "wd_timer",
72 .sysc = &omap2xxx_wd_timer_sysc,
73 .pre_shutdown = &omap2_wd_timer_disable,
74 .reset = &omap2_wd_timer_reset,
75};
76
77/*
78 * 'gpio' class
79 * general purpose io module
80 */
81static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
82 .rev_offs = 0x0000,
83 .sysc_offs = 0x0010,
84 .syss_offs = 0x0014,
85 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
86 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
87 SYSS_HAS_RESET_STATUS),
88 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
89 .sysc_fields = &omap_hwmod_sysc_type1,
90};
91
92struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
93 .name = "gpio",
94 .sysc = &omap2xxx_gpio_sysc,
95};
96
97/*
98 * 'mailbox' class
99 * mailbox module allowing communication between the on-chip processors
100 * using a queued mailbox-interrupt mechanism.
101 */
102
103static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
104 .rev_offs = 0x000,
105 .sysc_offs = 0x010,
106 .syss_offs = 0x014,
107 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
108 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
109 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
110 .sysc_fields = &omap_hwmod_sysc_type1,
111};
112
113struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
114 .name = "mailbox",
115 .sysc = &omap2xxx_mailbox_sysc,
116};
117
118/*
119 * 'mcspi' class
120 * multichannel serial port interface (mcspi) / master/slave synchronous serial
121 * bus
122 */
123
124static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
125 .rev_offs = 0x0000,
126 .sysc_offs = 0x0010,
127 .syss_offs = 0x0014,
128 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
129 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
130 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
132 .sysc_fields = &omap_hwmod_sysc_type1,
133};
134
135struct omap_hwmod_class omap2xxx_mcspi_class = {
136 .name = "mcspi",
137 .sysc = &omap2xxx_mcspi_sysc,
138};
139
140/*
141 * 'gpmc' class
142 * general purpose memory controller
143 */
144
145static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
146 .rev_offs = 0x0000,
147 .sysc_offs = 0x0010,
148 .syss_offs = 0x0014,
149 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
150 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
152 .sysc_fields = &omap_hwmod_sysc_type1,
153};
154
155static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
156 .name = "gpmc",
157 .sysc = &omap2xxx_gpmc_sysc,
158};
159
160/*
161 * IP blocks
162 */
163
164/* L3 */
165struct omap_hwmod omap2xxx_l3_main_hwmod = {
166 .name = "l3_main",
167 .class = &l3_hwmod_class,
168 .flags = HWMOD_NO_IDLEST,
169};
170
171/* L4 CORE */
172struct omap_hwmod omap2xxx_l4_core_hwmod = {
173 .name = "l4_core",
174 .class = &l4_hwmod_class,
175 .flags = HWMOD_NO_IDLEST,
176};
177
178/* L4 WKUP */
179struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
180 .name = "l4_wkup",
181 .class = &l4_hwmod_class,
182 .flags = HWMOD_NO_IDLEST,
183};
184
185/* MPU */
186struct omap_hwmod omap2xxx_mpu_hwmod = {
187 .name = "mpu",
188 .class = &mpu_hwmod_class,
189 .main_clk = "mpu_ck",
190};
191
192/* IVA2 */
193struct omap_hwmod omap2xxx_iva_hwmod = {
194 .name = "iva",
195 .class = &iva_hwmod_class,
196};
197
198/* timer3 */
199struct omap_hwmod omap2xxx_timer3_hwmod = {
200 .name = "timer3",
201 .main_clk = "gpt3_fck",
202 .prcm = {
203 .omap2 = {
204 .module_offs = CORE_MOD,
205 .idlest_reg_id = 1,
206 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
207 },
208 },
209 .class = &omap2xxx_timer_hwmod_class,
210 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
211};
212
213/* timer4 */
214struct omap_hwmod omap2xxx_timer4_hwmod = {
215 .name = "timer4",
216 .main_clk = "gpt4_fck",
217 .prcm = {
218 .omap2 = {
219 .module_offs = CORE_MOD,
220 .idlest_reg_id = 1,
221 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
222 },
223 },
224 .class = &omap2xxx_timer_hwmod_class,
225 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
226};
227
228/* timer5 */
229struct omap_hwmod omap2xxx_timer5_hwmod = {
230 .name = "timer5",
231 .main_clk = "gpt5_fck",
232 .prcm = {
233 .omap2 = {
234 .module_offs = CORE_MOD,
235 .idlest_reg_id = 1,
236 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
237 },
238 },
239 .class = &omap2xxx_timer_hwmod_class,
240 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
241};
242
243/* timer6 */
244struct omap_hwmod omap2xxx_timer6_hwmod = {
245 .name = "timer6",
246 .main_clk = "gpt6_fck",
247 .prcm = {
248 .omap2 = {
249 .module_offs = CORE_MOD,
250 .idlest_reg_id = 1,
251 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
252 },
253 },
254 .class = &omap2xxx_timer_hwmod_class,
255 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
256};
257
258/* timer7 */
259struct omap_hwmod omap2xxx_timer7_hwmod = {
260 .name = "timer7",
261 .main_clk = "gpt7_fck",
262 .prcm = {
263 .omap2 = {
264 .module_offs = CORE_MOD,
265 .idlest_reg_id = 1,
266 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
267 },
268 },
269 .class = &omap2xxx_timer_hwmod_class,
270 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
271};
272
273/* timer8 */
274struct omap_hwmod omap2xxx_timer8_hwmod = {
275 .name = "timer8",
276 .main_clk = "gpt8_fck",
277 .prcm = {
278 .omap2 = {
279 .module_offs = CORE_MOD,
280 .idlest_reg_id = 1,
281 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
282 },
283 },
284 .class = &omap2xxx_timer_hwmod_class,
285 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
286};
287
288/* timer9 */
289struct omap_hwmod omap2xxx_timer9_hwmod = {
290 .name = "timer9",
291 .main_clk = "gpt9_fck",
292 .prcm = {
293 .omap2 = {
294 .module_offs = CORE_MOD,
295 .idlest_reg_id = 1,
296 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
297 },
298 },
299 .class = &omap2xxx_timer_hwmod_class,
300 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
301};
302
303/* timer10 */
304struct omap_hwmod omap2xxx_timer10_hwmod = {
305 .name = "timer10",
306 .main_clk = "gpt10_fck",
307 .prcm = {
308 .omap2 = {
309 .module_offs = CORE_MOD,
310 .idlest_reg_id = 1,
311 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
312 },
313 },
314 .class = &omap2xxx_timer_hwmod_class,
315 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
316};
317
318/* timer11 */
319struct omap_hwmod omap2xxx_timer11_hwmod = {
320 .name = "timer11",
321 .main_clk = "gpt11_fck",
322 .prcm = {
323 .omap2 = {
324 .module_offs = CORE_MOD,
325 .idlest_reg_id = 1,
326 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
327 },
328 },
329 .class = &omap2xxx_timer_hwmod_class,
330 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
331};
332
333/* timer12 */
334struct omap_hwmod omap2xxx_timer12_hwmod = {
335 .name = "timer12",
336 .main_clk = "gpt12_fck",
337 .prcm = {
338 .omap2 = {
339 .module_offs = CORE_MOD,
340 .idlest_reg_id = 1,
341 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
342 },
343 },
344 .class = &omap2xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
346};
347
348/* wd_timer2 */
349struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
350 .name = "wd_timer2",
351 .class = &omap2xxx_wd_timer_hwmod_class,
352 .main_clk = "mpu_wdt_fck",
353 .prcm = {
354 .omap2 = {
355 .module_offs = WKUP_MOD,
356 .idlest_reg_id = 1,
357 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
358 },
359 },
360};
361
362/* UART1 */
363
364struct omap_hwmod omap2xxx_uart1_hwmod = {
365 .name = "uart1",
366 .main_clk = "uart1_fck",
367 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
368 .prcm = {
369 .omap2 = {
370 .module_offs = CORE_MOD,
371 .idlest_reg_id = 1,
372 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
373 },
374 },
375 .class = &omap2_uart_class,
376};
377
378/* UART2 */
379
380struct omap_hwmod omap2xxx_uart2_hwmod = {
381 .name = "uart2",
382 .main_clk = "uart2_fck",
383 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
384 .prcm = {
385 .omap2 = {
386 .module_offs = CORE_MOD,
387 .idlest_reg_id = 1,
388 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
389 },
390 },
391 .class = &omap2_uart_class,
392};
393
394/* UART3 */
395
396struct omap_hwmod omap2xxx_uart3_hwmod = {
397 .name = "uart3",
398 .main_clk = "uart3_fck",
399 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
400 .prcm = {
401 .omap2 = {
402 .module_offs = CORE_MOD,
403 .idlest_reg_id = 2,
404 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
405 },
406 },
407 .class = &omap2_uart_class,
408};
409
410/* dss */
411
412static struct omap_hwmod_opt_clk dss_opt_clks[] = {
413 /*
414 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
415 * driver does not use these clocks.
416 */
417 { .role = "tv_clk", .clk = "dss_54m_fck" },
418 { .role = "sys_clk", .clk = "dss2_fck" },
419};
420
421struct omap_hwmod omap2xxx_dss_core_hwmod = {
422 .name = "dss_core",
423 .class = &omap2_dss_hwmod_class,
424 .main_clk = "dss1_fck", /* instead of dss_fck */
425 .prcm = {
426 .omap2 = {
427 .module_offs = CORE_MOD,
428 .idlest_reg_id = 1,
429 },
430 },
431 .opt_clks = dss_opt_clks,
432 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
433 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
434};
435
436struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
437 .name = "dss_dispc",
438 .class = &omap2_dispc_hwmod_class,
439 .main_clk = "dss1_fck",
440 .prcm = {
441 .omap2 = {
442 .module_offs = CORE_MOD,
443 .idlest_reg_id = 1,
444 },
445 },
446 .flags = HWMOD_NO_IDLEST,
447 .dev_attr = &omap2_3_dss_dispc_dev_attr,
448};
449
450static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
451 { .role = "ick", .clk = "dss_ick" },
452};
453
454struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
455 .name = "dss_rfbi",
456 .class = &omap2_rfbi_hwmod_class,
457 .main_clk = "dss1_fck",
458 .prcm = {
459 .omap2 = {
460 .module_offs = CORE_MOD,
461 },
462 },
463 .opt_clks = dss_rfbi_opt_clks,
464 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
465 .flags = HWMOD_NO_IDLEST,
466};
467
468struct omap_hwmod omap2xxx_dss_venc_hwmod = {
469 .name = "dss_venc",
470 .class = &omap2_venc_hwmod_class,
471 .main_clk = "dss_54m_fck",
472 .prcm = {
473 .omap2 = {
474 .module_offs = CORE_MOD,
475 },
476 },
477 .flags = HWMOD_NO_IDLEST,
478};
479
480/* gpio1 */
481struct omap_hwmod omap2xxx_gpio1_hwmod = {
482 .name = "gpio1",
483 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
484 .main_clk = "gpios_fck",
485 .prcm = {
486 .omap2 = {
487 .module_offs = WKUP_MOD,
488 .idlest_reg_id = 1,
489 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
490 },
491 },
492 .class = &omap2xxx_gpio_hwmod_class,
493};
494
495/* gpio2 */
496struct omap_hwmod omap2xxx_gpio2_hwmod = {
497 .name = "gpio2",
498 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
499 .main_clk = "gpios_fck",
500 .prcm = {
501 .omap2 = {
502 .module_offs = WKUP_MOD,
503 .idlest_reg_id = 1,
504 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
505 },
506 },
507 .class = &omap2xxx_gpio_hwmod_class,
508};
509
510/* gpio3 */
511struct omap_hwmod omap2xxx_gpio3_hwmod = {
512 .name = "gpio3",
513 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
514 .main_clk = "gpios_fck",
515 .prcm = {
516 .omap2 = {
517 .module_offs = WKUP_MOD,
518 .idlest_reg_id = 1,
519 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
520 },
521 },
522 .class = &omap2xxx_gpio_hwmod_class,
523};
524
525/* gpio4 */
526struct omap_hwmod omap2xxx_gpio4_hwmod = {
527 .name = "gpio4",
528 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
529 .main_clk = "gpios_fck",
530 .prcm = {
531 .omap2 = {
532 .module_offs = WKUP_MOD,
533 .idlest_reg_id = 1,
534 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
535 },
536 },
537 .class = &omap2xxx_gpio_hwmod_class,
538};
539
540/* mcspi1 */
541struct omap_hwmod omap2xxx_mcspi1_hwmod = {
542 .name = "mcspi1",
543 .main_clk = "mcspi1_fck",
544 .prcm = {
545 .omap2 = {
546 .module_offs = CORE_MOD,
547 .idlest_reg_id = 1,
548 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
549 },
550 },
551 .class = &omap2xxx_mcspi_class,
552};
553
554/* mcspi2 */
555struct omap_hwmod omap2xxx_mcspi2_hwmod = {
556 .name = "mcspi2",
557 .main_clk = "mcspi2_fck",
558 .prcm = {
559 .omap2 = {
560 .module_offs = CORE_MOD,
561 .idlest_reg_id = 1,
562 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
563 },
564 },
565 .class = &omap2xxx_mcspi_class,
566};
567
568/* gpmc */
569struct omap_hwmod omap2xxx_gpmc_hwmod = {
570 .name = "gpmc",
571 .class = &omap2xxx_gpmc_hwmod_class,
572 .main_clk = "gpmc_fck",
573 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
574 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
575 .prcm = {
576 .omap2 = {
577 .module_offs = CORE_MOD,
578 },
579 },
580};
581
582/* RNG */
583
584static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
585 .rev_offs = 0x3c,
586 .sysc_offs = 0x40,
587 .syss_offs = 0x44,
588 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
589 SYSS_HAS_RESET_STATUS),
590 .sysc_fields = &omap_hwmod_sysc_type1,
591};
592
593static struct omap_hwmod_class omap2_rng_hwmod_class = {
594 .name = "rng",
595 .sysc = &omap2_rng_sysc,
596};
597
598struct omap_hwmod omap2xxx_rng_hwmod = {
599 .name = "rng",
600 .main_clk = "l4_ck",
601 .prcm = {
602 .omap2 = {
603 .module_offs = CORE_MOD,
604 .idlest_reg_id = 4,
605 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
606 },
607 },
608 /*
609 * XXX The first read from the SYSSTATUS register of the RNG
610 * after the SYSCONFIG SOFTRESET bit is set triggers an
611 * imprecise external abort. It's unclear why this happens.
612 * Until this is analyzed, skip the IP block reset.
613 */
614 .flags = HWMOD_INIT_NO_RESET,
615 .class = &omap2_rng_hwmod_class,
616};
617
618/* SHAM */
619
620static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
621 .rev_offs = 0x5c,
622 .sysc_offs = 0x60,
623 .syss_offs = 0x64,
624 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
625 SYSS_HAS_RESET_STATUS),
626 .sysc_fields = &omap_hwmod_sysc_type1,
627};
628
629static struct omap_hwmod_class omap2xxx_sham_class = {
630 .name = "sham",
631 .sysc = &omap2_sham_sysc,
632};
633
634struct omap_hwmod omap2xxx_sham_hwmod = {
635 .name = "sham",
636 .main_clk = "l4_ck",
637 .prcm = {
638 .omap2 = {
639 .module_offs = CORE_MOD,
640 .idlest_reg_id = 4,
641 .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
642 },
643 },
644 .class = &omap2xxx_sham_class,
645};
646
647/* AES */
648
649static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
650 .rev_offs = 0x44,
651 .sysc_offs = 0x48,
652 .syss_offs = 0x4c,
653 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
654 SYSS_HAS_RESET_STATUS),
655 .sysc_fields = &omap_hwmod_sysc_type1,
656};
657
658static struct omap_hwmod_class omap2xxx_aes_class = {
659 .name = "aes",
660 .sysc = &omap2_aes_sysc,
661};
662
663struct omap_hwmod omap2xxx_aes_hwmod = {
664 .name = "aes",
665 .main_clk = "l4_ck",
666 .prcm = {
667 .omap2 = {
668 .module_offs = CORE_MOD,
669 .idlest_reg_id = 4,
670 .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
671 },
672 },
673 .class = &omap2xxx_aes_class,
674};