1#ifndef __ASM_ARM_SWITCH_TO_H
 2#define __ASM_ARM_SWITCH_TO_H
 3
 4#include <linux/thread_info.h>
 5
 6/*
 
 
 
 
 
 
 
 
 
 
 7 * switch_to(prev, next) should switch from task `prev' to `next'
 8 * `prev' will never be the same as `next'.  schedule() itself
 9 * contains the memory barrier to tell GCC not to cache `current'.
10 */
11extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
12
13#define switch_to(prev,next,last)					\
14do {									\
15	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
16} while (0)
17
18#endif /* __ASM_ARM_SWITCH_TO_H */

 1#ifndef __ASM_ARM_SWITCH_TO_H
 2#define __ASM_ARM_SWITCH_TO_H
 3
 4#include <linux/thread_info.h>
 5
 6/*
 7 * For v7 SMP cores running a preemptible kernel we may be pre-empted
 8 * during a TLB maintenance operation, so execute an inner-shareable dsb
 9 * to ensure that the maintenance completes in case we migrate to another
10 * CPU.
11 */
12#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
13#define finish_arch_switch(prev)	dsb(ish)
14#endif
15
16/*
17 * switch_to(prev, next) should switch from task `prev' to `next'
18 * `prev' will never be the same as `next'.  schedule() itself
19 * contains the memory barrier to tell GCC not to cache `current'.
20 */
21extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
22
23#define switch_to(prev,next,last)					\
24do {									\
25	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
26} while (0)
27
28#endif /* __ASM_ARM_SWITCH_TO_H */