1#ifndef __ASM_ARM_SWITCH_TO_H
 2#define __ASM_ARM_SWITCH_TO_H
 3
 4#include <linux/thread_info.h>
 5
 6/*
 
 
 
 
 
 
 
 
 
 
 
 
 7 * switch_to(prev, next) should switch from task `prev' to `next'
 8 * `prev' will never be the same as `next'.  schedule() itself
 9 * contains the memory barrier to tell GCC not to cache `current'.
10 */
11extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
12
13#define switch_to(prev,next,last)					\
14do {									\
 
15	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
16} while (0)
17
18#endif /* __ASM_ARM_SWITCH_TO_H */

 1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __ASM_ARM_SWITCH_TO_H
 3#define __ASM_ARM_SWITCH_TO_H
 4
 5#include <linux/thread_info.h>
 6
 7/*
 8 * For v7 SMP cores running a preemptible kernel we may be pre-empted
 9 * during a TLB maintenance operation, so execute an inner-shareable dsb
10 * to ensure that the maintenance completes in case we migrate to another
11 * CPU.
12 */
13#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
14#define __complete_pending_tlbi()	dsb(ish)
15#else
16#define __complete_pending_tlbi()
17#endif
18
19/*
20 * switch_to(prev, next) should switch from task `prev' to `next'
21 * `prev' will never be the same as `next'.  schedule() itself
22 * contains the memory barrier to tell GCC not to cache `current'.
23 */
24extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
25
26#define switch_to(prev,next,last)					\
27do {									\
28	__complete_pending_tlbi();					\
29	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
30} while (0)
31
32#endif /* __ASM_ARM_SWITCH_TO_H */