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1/*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/highmem.h>
22#include <linux/log2.h>
23#include <linux/mmc/host.h>
24#include <linux/mmc/card.h>
25#include <linux/amba/bus.h>
26#include <linux/clk.h>
27#include <linux/scatterlist.h>
28#include <linux/gpio.h>
29#include <linux/of_gpio.h>
30#include <linux/regulator/consumer.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/amba/mmci.h>
34#include <linux/pm_runtime.h>
35#include <linux/types.h>
36
37#include <asm/div64.h>
38#include <asm/io.h>
39#include <asm/sizes.h>
40
41#include "mmci.h"
42
43#define DRIVER_NAME "mmci-pl18x"
44
45static unsigned int fmax = 515633;
46
47/**
48 * struct variant_data - MMCI variant-specific quirks
49 * @clkreg: default value for MCICLOCK register
50 * @clkreg_enable: enable value for MMCICLOCK register
51 * @datalength_bits: number of bits in the MMCIDATALENGTH register
52 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
53 * is asserted (likewise for RX)
54 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
55 * is asserted (likewise for RX)
56 * @sdio: variant supports SDIO
57 * @st_clkdiv: true if using a ST-specific clock divider algorithm
58 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
59 * @pwrreg_powerup: power up value for MMCIPOWER register
60 * @signal_direction: input/out direction of bus signals can be indicated
61 */
62struct variant_data {
63 unsigned int clkreg;
64 unsigned int clkreg_enable;
65 unsigned int datalength_bits;
66 unsigned int fifosize;
67 unsigned int fifohalfsize;
68 bool sdio;
69 bool st_clkdiv;
70 bool blksz_datactrl16;
71 u32 pwrreg_powerup;
72 bool signal_direction;
73};
74
75static struct variant_data variant_arm = {
76 .fifosize = 16 * 4,
77 .fifohalfsize = 8 * 4,
78 .datalength_bits = 16,
79 .pwrreg_powerup = MCI_PWR_UP,
80};
81
82static struct variant_data variant_arm_extended_fifo = {
83 .fifosize = 128 * 4,
84 .fifohalfsize = 64 * 4,
85 .datalength_bits = 16,
86 .pwrreg_powerup = MCI_PWR_UP,
87};
88
89static struct variant_data variant_u300 = {
90 .fifosize = 16 * 4,
91 .fifohalfsize = 8 * 4,
92 .clkreg_enable = MCI_ST_U300_HWFCEN,
93 .datalength_bits = 16,
94 .sdio = true,
95 .pwrreg_powerup = MCI_PWR_ON,
96 .signal_direction = true,
97};
98
99static struct variant_data variant_nomadik = {
100 .fifosize = 16 * 4,
101 .fifohalfsize = 8 * 4,
102 .clkreg = MCI_CLK_ENABLE,
103 .datalength_bits = 24,
104 .sdio = true,
105 .st_clkdiv = true,
106 .pwrreg_powerup = MCI_PWR_ON,
107 .signal_direction = true,
108};
109
110static struct variant_data variant_ux500 = {
111 .fifosize = 30 * 4,
112 .fifohalfsize = 8 * 4,
113 .clkreg = MCI_CLK_ENABLE,
114 .clkreg_enable = MCI_ST_UX500_HWFCEN,
115 .datalength_bits = 24,
116 .sdio = true,
117 .st_clkdiv = true,
118 .pwrreg_powerup = MCI_PWR_ON,
119 .signal_direction = true,
120};
121
122static struct variant_data variant_ux500v2 = {
123 .fifosize = 30 * 4,
124 .fifohalfsize = 8 * 4,
125 .clkreg = MCI_CLK_ENABLE,
126 .clkreg_enable = MCI_ST_UX500_HWFCEN,
127 .datalength_bits = 24,
128 .sdio = true,
129 .st_clkdiv = true,
130 .blksz_datactrl16 = true,
131 .pwrreg_powerup = MCI_PWR_ON,
132 .signal_direction = true,
133};
134
135/*
136 * This must be called with host->lock held
137 */
138static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
139{
140 if (host->clk_reg != clk) {
141 host->clk_reg = clk;
142 writel(clk, host->base + MMCICLOCK);
143 }
144}
145
146/*
147 * This must be called with host->lock held
148 */
149static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
150{
151 if (host->pwr_reg != pwr) {
152 host->pwr_reg = pwr;
153 writel(pwr, host->base + MMCIPOWER);
154 }
155}
156
157/*
158 * This must be called with host->lock held
159 */
160static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
161{
162 struct variant_data *variant = host->variant;
163 u32 clk = variant->clkreg;
164
165 if (desired) {
166 if (desired >= host->mclk) {
167 clk = MCI_CLK_BYPASS;
168 if (variant->st_clkdiv)
169 clk |= MCI_ST_UX500_NEG_EDGE;
170 host->cclk = host->mclk;
171 } else if (variant->st_clkdiv) {
172 /*
173 * DB8500 TRM says f = mclk / (clkdiv + 2)
174 * => clkdiv = (mclk / f) - 2
175 * Round the divider up so we don't exceed the max
176 * frequency
177 */
178 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
179 if (clk >= 256)
180 clk = 255;
181 host->cclk = host->mclk / (clk + 2);
182 } else {
183 /*
184 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
185 * => clkdiv = mclk / (2 * f) - 1
186 */
187 clk = host->mclk / (2 * desired) - 1;
188 if (clk >= 256)
189 clk = 255;
190 host->cclk = host->mclk / (2 * (clk + 1));
191 }
192
193 clk |= variant->clkreg_enable;
194 clk |= MCI_CLK_ENABLE;
195 /* This hasn't proven to be worthwhile */
196 /* clk |= MCI_CLK_PWRSAVE; */
197 }
198
199 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
200 clk |= MCI_4BIT_BUS;
201 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
202 clk |= MCI_ST_8BIT_BUS;
203
204 mmci_write_clkreg(host, clk);
205}
206
207static void
208mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
209{
210 writel(0, host->base + MMCICOMMAND);
211
212 BUG_ON(host->data);
213
214 host->mrq = NULL;
215 host->cmd = NULL;
216
217 mmc_request_done(host->mmc, mrq);
218
219 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
220 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
221}
222
223static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
224{
225 void __iomem *base = host->base;
226
227 if (host->singleirq) {
228 unsigned int mask0 = readl(base + MMCIMASK0);
229
230 mask0 &= ~MCI_IRQ1MASK;
231 mask0 |= mask;
232
233 writel(mask0, base + MMCIMASK0);
234 }
235
236 writel(mask, base + MMCIMASK1);
237}
238
239static void mmci_stop_data(struct mmci_host *host)
240{
241 writel(0, host->base + MMCIDATACTRL);
242 mmci_set_mask1(host, 0);
243 host->data = NULL;
244}
245
246static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
247{
248 unsigned int flags = SG_MITER_ATOMIC;
249
250 if (data->flags & MMC_DATA_READ)
251 flags |= SG_MITER_TO_SG;
252 else
253 flags |= SG_MITER_FROM_SG;
254
255 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
256}
257
258/*
259 * All the DMA operation mode stuff goes inside this ifdef.
260 * This assumes that you have a generic DMA device interface,
261 * no custom DMA interfaces are supported.
262 */
263#ifdef CONFIG_DMA_ENGINE
264static void __devinit mmci_dma_setup(struct mmci_host *host)
265{
266 struct mmci_platform_data *plat = host->plat;
267 const char *rxname, *txname;
268 dma_cap_mask_t mask;
269
270 if (!plat || !plat->dma_filter) {
271 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
272 return;
273 }
274
275 /* initialize pre request cookie */
276 host->next_data.cookie = 1;
277
278 /* Try to acquire a generic DMA engine slave channel */
279 dma_cap_zero(mask);
280 dma_cap_set(DMA_SLAVE, mask);
281
282 /*
283 * If only an RX channel is specified, the driver will
284 * attempt to use it bidirectionally, however if it is
285 * is specified but cannot be located, DMA will be disabled.
286 */
287 if (plat->dma_rx_param) {
288 host->dma_rx_channel = dma_request_channel(mask,
289 plat->dma_filter,
290 plat->dma_rx_param);
291 /* E.g if no DMA hardware is present */
292 if (!host->dma_rx_channel)
293 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
294 }
295
296 if (plat->dma_tx_param) {
297 host->dma_tx_channel = dma_request_channel(mask,
298 plat->dma_filter,
299 plat->dma_tx_param);
300 if (!host->dma_tx_channel)
301 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
302 } else {
303 host->dma_tx_channel = host->dma_rx_channel;
304 }
305
306 if (host->dma_rx_channel)
307 rxname = dma_chan_name(host->dma_rx_channel);
308 else
309 rxname = "none";
310
311 if (host->dma_tx_channel)
312 txname = dma_chan_name(host->dma_tx_channel);
313 else
314 txname = "none";
315
316 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
317 rxname, txname);
318
319 /*
320 * Limit the maximum segment size in any SG entry according to
321 * the parameters of the DMA engine device.
322 */
323 if (host->dma_tx_channel) {
324 struct device *dev = host->dma_tx_channel->device->dev;
325 unsigned int max_seg_size = dma_get_max_seg_size(dev);
326
327 if (max_seg_size < host->mmc->max_seg_size)
328 host->mmc->max_seg_size = max_seg_size;
329 }
330 if (host->dma_rx_channel) {
331 struct device *dev = host->dma_rx_channel->device->dev;
332 unsigned int max_seg_size = dma_get_max_seg_size(dev);
333
334 if (max_seg_size < host->mmc->max_seg_size)
335 host->mmc->max_seg_size = max_seg_size;
336 }
337}
338
339/*
340 * This is used in __devinit or __devexit so inline it
341 * so it can be discarded.
342 */
343static inline void mmci_dma_release(struct mmci_host *host)
344{
345 struct mmci_platform_data *plat = host->plat;
346
347 if (host->dma_rx_channel)
348 dma_release_channel(host->dma_rx_channel);
349 if (host->dma_tx_channel && plat->dma_tx_param)
350 dma_release_channel(host->dma_tx_channel);
351 host->dma_rx_channel = host->dma_tx_channel = NULL;
352}
353
354static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
355{
356 struct dma_chan *chan = host->dma_current;
357 enum dma_data_direction dir;
358 u32 status;
359 int i;
360
361 /* Wait up to 1ms for the DMA to complete */
362 for (i = 0; ; i++) {
363 status = readl(host->base + MMCISTATUS);
364 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
365 break;
366 udelay(10);
367 }
368
369 /*
370 * Check to see whether we still have some data left in the FIFO -
371 * this catches DMA controllers which are unable to monitor the
372 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
373 * contiguous buffers. On TX, we'll get a FIFO underrun error.
374 */
375 if (status & MCI_RXDATAAVLBLMASK) {
376 dmaengine_terminate_all(chan);
377 if (!data->error)
378 data->error = -EIO;
379 }
380
381 if (data->flags & MMC_DATA_WRITE) {
382 dir = DMA_TO_DEVICE;
383 } else {
384 dir = DMA_FROM_DEVICE;
385 }
386
387 if (!data->host_cookie)
388 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
389
390 /*
391 * Use of DMA with scatter-gather is impossible.
392 * Give up with DMA and switch back to PIO mode.
393 */
394 if (status & MCI_RXDATAAVLBLMASK) {
395 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
396 mmci_dma_release(host);
397 }
398}
399
400static void mmci_dma_data_error(struct mmci_host *host)
401{
402 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
403 dmaengine_terminate_all(host->dma_current);
404}
405
406static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
407 struct mmci_host_next *next)
408{
409 struct variant_data *variant = host->variant;
410 struct dma_slave_config conf = {
411 .src_addr = host->phybase + MMCIFIFO,
412 .dst_addr = host->phybase + MMCIFIFO,
413 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
414 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
415 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
416 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
417 .device_fc = false,
418 };
419 struct dma_chan *chan;
420 struct dma_device *device;
421 struct dma_async_tx_descriptor *desc;
422 enum dma_data_direction buffer_dirn;
423 int nr_sg;
424
425 /* Check if next job is already prepared */
426 if (data->host_cookie && !next &&
427 host->dma_current && host->dma_desc_current)
428 return 0;
429
430 if (!next) {
431 host->dma_current = NULL;
432 host->dma_desc_current = NULL;
433 }
434
435 if (data->flags & MMC_DATA_READ) {
436 conf.direction = DMA_DEV_TO_MEM;
437 buffer_dirn = DMA_FROM_DEVICE;
438 chan = host->dma_rx_channel;
439 } else {
440 conf.direction = DMA_MEM_TO_DEV;
441 buffer_dirn = DMA_TO_DEVICE;
442 chan = host->dma_tx_channel;
443 }
444
445 /* If there's no DMA channel, fall back to PIO */
446 if (!chan)
447 return -EINVAL;
448
449 /* If less than or equal to the fifo size, don't bother with DMA */
450 if (data->blksz * data->blocks <= variant->fifosize)
451 return -EINVAL;
452
453 device = chan->device;
454 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
455 if (nr_sg == 0)
456 return -EINVAL;
457
458 dmaengine_slave_config(chan, &conf);
459 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
460 conf.direction, DMA_CTRL_ACK);
461 if (!desc)
462 goto unmap_exit;
463
464 if (next) {
465 next->dma_chan = chan;
466 next->dma_desc = desc;
467 } else {
468 host->dma_current = chan;
469 host->dma_desc_current = desc;
470 }
471
472 return 0;
473
474 unmap_exit:
475 if (!next)
476 dmaengine_terminate_all(chan);
477 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
478 return -ENOMEM;
479}
480
481static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
482{
483 int ret;
484 struct mmc_data *data = host->data;
485
486 ret = mmci_dma_prep_data(host, host->data, NULL);
487 if (ret)
488 return ret;
489
490 /* Okay, go for it. */
491 dev_vdbg(mmc_dev(host->mmc),
492 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
493 data->sg_len, data->blksz, data->blocks, data->flags);
494 dmaengine_submit(host->dma_desc_current);
495 dma_async_issue_pending(host->dma_current);
496
497 datactrl |= MCI_DPSM_DMAENABLE;
498
499 /* Trigger the DMA transfer */
500 writel(datactrl, host->base + MMCIDATACTRL);
501
502 /*
503 * Let the MMCI say when the data is ended and it's time
504 * to fire next DMA request. When that happens, MMCI will
505 * call mmci_data_end()
506 */
507 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
508 host->base + MMCIMASK0);
509 return 0;
510}
511
512static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
513{
514 struct mmci_host_next *next = &host->next_data;
515
516 if (data->host_cookie && data->host_cookie != next->cookie) {
517 pr_warning("[%s] invalid cookie: data->host_cookie %d"
518 " host->next_data.cookie %d\n",
519 __func__, data->host_cookie, host->next_data.cookie);
520 data->host_cookie = 0;
521 }
522
523 if (!data->host_cookie)
524 return;
525
526 host->dma_desc_current = next->dma_desc;
527 host->dma_current = next->dma_chan;
528
529 next->dma_desc = NULL;
530 next->dma_chan = NULL;
531}
532
533static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
534 bool is_first_req)
535{
536 struct mmci_host *host = mmc_priv(mmc);
537 struct mmc_data *data = mrq->data;
538 struct mmci_host_next *nd = &host->next_data;
539
540 if (!data)
541 return;
542
543 if (data->host_cookie) {
544 data->host_cookie = 0;
545 return;
546 }
547
548 /* if config for dma */
549 if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) ||
550 ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) {
551 if (mmci_dma_prep_data(host, data, nd))
552 data->host_cookie = 0;
553 else
554 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
555 }
556}
557
558static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
559 int err)
560{
561 struct mmci_host *host = mmc_priv(mmc);
562 struct mmc_data *data = mrq->data;
563 struct dma_chan *chan;
564 enum dma_data_direction dir;
565
566 if (!data)
567 return;
568
569 if (data->flags & MMC_DATA_READ) {
570 dir = DMA_FROM_DEVICE;
571 chan = host->dma_rx_channel;
572 } else {
573 dir = DMA_TO_DEVICE;
574 chan = host->dma_tx_channel;
575 }
576
577
578 /* if config for dma */
579 if (chan) {
580 if (err)
581 dmaengine_terminate_all(chan);
582 if (data->host_cookie)
583 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
584 data->sg_len, dir);
585 mrq->data->host_cookie = 0;
586 }
587}
588
589#else
590/* Blank functions if the DMA engine is not available */
591static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
592{
593}
594static inline void mmci_dma_setup(struct mmci_host *host)
595{
596}
597
598static inline void mmci_dma_release(struct mmci_host *host)
599{
600}
601
602static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
603{
604}
605
606static inline void mmci_dma_data_error(struct mmci_host *host)
607{
608}
609
610static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
611{
612 return -ENOSYS;
613}
614
615#define mmci_pre_request NULL
616#define mmci_post_request NULL
617
618#endif
619
620static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
621{
622 struct variant_data *variant = host->variant;
623 unsigned int datactrl, timeout, irqmask;
624 unsigned long long clks;
625 void __iomem *base;
626 int blksz_bits;
627
628 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
629 data->blksz, data->blocks, data->flags);
630
631 host->data = data;
632 host->size = data->blksz * data->blocks;
633 data->bytes_xfered = 0;
634
635 clks = (unsigned long long)data->timeout_ns * host->cclk;
636 do_div(clks, 1000000000UL);
637
638 timeout = data->timeout_clks + (unsigned int)clks;
639
640 base = host->base;
641 writel(timeout, base + MMCIDATATIMER);
642 writel(host->size, base + MMCIDATALENGTH);
643
644 blksz_bits = ffs(data->blksz) - 1;
645 BUG_ON(1 << blksz_bits != data->blksz);
646
647 if (variant->blksz_datactrl16)
648 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
649 else
650 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
651
652 if (data->flags & MMC_DATA_READ)
653 datactrl |= MCI_DPSM_DIRECTION;
654
655 /* The ST Micro variants has a special bit to enable SDIO */
656 if (variant->sdio && host->mmc->card)
657 if (mmc_card_sdio(host->mmc->card))
658 datactrl |= MCI_ST_DPSM_SDIOEN;
659
660 /*
661 * Attempt to use DMA operation mode, if this
662 * should fail, fall back to PIO mode
663 */
664 if (!mmci_dma_start_data(host, datactrl))
665 return;
666
667 /* IRQ mode, map the SG list for CPU reading/writing */
668 mmci_init_sg(host, data);
669
670 if (data->flags & MMC_DATA_READ) {
671 irqmask = MCI_RXFIFOHALFFULLMASK;
672
673 /*
674 * If we have less than the fifo 'half-full' threshold to
675 * transfer, trigger a PIO interrupt as soon as any data
676 * is available.
677 */
678 if (host->size < variant->fifohalfsize)
679 irqmask |= MCI_RXDATAAVLBLMASK;
680 } else {
681 /*
682 * We don't actually need to include "FIFO empty" here
683 * since its implicit in "FIFO half empty".
684 */
685 irqmask = MCI_TXFIFOHALFEMPTYMASK;
686 }
687
688 writel(datactrl, base + MMCIDATACTRL);
689 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
690 mmci_set_mask1(host, irqmask);
691}
692
693static void
694mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
695{
696 void __iomem *base = host->base;
697
698 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
699 cmd->opcode, cmd->arg, cmd->flags);
700
701 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
702 writel(0, base + MMCICOMMAND);
703 udelay(1);
704 }
705
706 c |= cmd->opcode | MCI_CPSM_ENABLE;
707 if (cmd->flags & MMC_RSP_PRESENT) {
708 if (cmd->flags & MMC_RSP_136)
709 c |= MCI_CPSM_LONGRSP;
710 c |= MCI_CPSM_RESPONSE;
711 }
712 if (/*interrupt*/0)
713 c |= MCI_CPSM_INTERRUPT;
714
715 host->cmd = cmd;
716
717 writel(cmd->arg, base + MMCIARGUMENT);
718 writel(c, base + MMCICOMMAND);
719}
720
721static void
722mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
723 unsigned int status)
724{
725 /* First check for errors */
726 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
727 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
728 u32 remain, success;
729
730 /* Terminate the DMA transfer */
731 if (dma_inprogress(host))
732 mmci_dma_data_error(host);
733
734 /*
735 * Calculate how far we are into the transfer. Note that
736 * the data counter gives the number of bytes transferred
737 * on the MMC bus, not on the host side. On reads, this
738 * can be as much as a FIFO-worth of data ahead. This
739 * matters for FIFO overruns only.
740 */
741 remain = readl(host->base + MMCIDATACNT);
742 success = data->blksz * data->blocks - remain;
743
744 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
745 status, success);
746 if (status & MCI_DATACRCFAIL) {
747 /* Last block was not successful */
748 success -= 1;
749 data->error = -EILSEQ;
750 } else if (status & MCI_DATATIMEOUT) {
751 data->error = -ETIMEDOUT;
752 } else if (status & MCI_STARTBITERR) {
753 data->error = -ECOMM;
754 } else if (status & MCI_TXUNDERRUN) {
755 data->error = -EIO;
756 } else if (status & MCI_RXOVERRUN) {
757 if (success > host->variant->fifosize)
758 success -= host->variant->fifosize;
759 else
760 success = 0;
761 data->error = -EIO;
762 }
763 data->bytes_xfered = round_down(success, data->blksz);
764 }
765
766 if (status & MCI_DATABLOCKEND)
767 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
768
769 if (status & MCI_DATAEND || data->error) {
770 if (dma_inprogress(host))
771 mmci_dma_unmap(host, data);
772 mmci_stop_data(host);
773
774 if (!data->error)
775 /* The error clause is handled above, success! */
776 data->bytes_xfered = data->blksz * data->blocks;
777
778 if (!data->stop) {
779 mmci_request_end(host, data->mrq);
780 } else {
781 mmci_start_command(host, data->stop, 0);
782 }
783 }
784}
785
786static void
787mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
788 unsigned int status)
789{
790 void __iomem *base = host->base;
791
792 host->cmd = NULL;
793
794 if (status & MCI_CMDTIMEOUT) {
795 cmd->error = -ETIMEDOUT;
796 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
797 cmd->error = -EILSEQ;
798 } else {
799 cmd->resp[0] = readl(base + MMCIRESPONSE0);
800 cmd->resp[1] = readl(base + MMCIRESPONSE1);
801 cmd->resp[2] = readl(base + MMCIRESPONSE2);
802 cmd->resp[3] = readl(base + MMCIRESPONSE3);
803 }
804
805 if (!cmd->data || cmd->error) {
806 if (host->data) {
807 /* Terminate the DMA transfer */
808 if (dma_inprogress(host))
809 mmci_dma_data_error(host);
810 mmci_stop_data(host);
811 }
812 mmci_request_end(host, cmd->mrq);
813 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
814 mmci_start_data(host, cmd->data);
815 }
816}
817
818static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
819{
820 void __iomem *base = host->base;
821 char *ptr = buffer;
822 u32 status;
823 int host_remain = host->size;
824
825 do {
826 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
827
828 if (count > remain)
829 count = remain;
830
831 if (count <= 0)
832 break;
833
834 /*
835 * SDIO especially may want to send something that is
836 * not divisible by 4 (as opposed to card sectors
837 * etc). Therefore make sure to always read the last bytes
838 * while only doing full 32-bit reads towards the FIFO.
839 */
840 if (unlikely(count & 0x3)) {
841 if (count < 4) {
842 unsigned char buf[4];
843 readsl(base + MMCIFIFO, buf, 1);
844 memcpy(ptr, buf, count);
845 } else {
846 readsl(base + MMCIFIFO, ptr, count >> 2);
847 count &= ~0x3;
848 }
849 } else {
850 readsl(base + MMCIFIFO, ptr, count >> 2);
851 }
852
853 ptr += count;
854 remain -= count;
855 host_remain -= count;
856
857 if (remain == 0)
858 break;
859
860 status = readl(base + MMCISTATUS);
861 } while (status & MCI_RXDATAAVLBL);
862
863 return ptr - buffer;
864}
865
866static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
867{
868 struct variant_data *variant = host->variant;
869 void __iomem *base = host->base;
870 char *ptr = buffer;
871
872 do {
873 unsigned int count, maxcnt;
874
875 maxcnt = status & MCI_TXFIFOEMPTY ?
876 variant->fifosize : variant->fifohalfsize;
877 count = min(remain, maxcnt);
878
879 /*
880 * The ST Micro variant for SDIO transfer sizes
881 * less then 8 bytes should have clock H/W flow
882 * control disabled.
883 */
884 if (variant->sdio &&
885 mmc_card_sdio(host->mmc->card)) {
886 u32 clk;
887 if (count < 8)
888 clk = host->clk_reg & ~variant->clkreg_enable;
889 else
890 clk = host->clk_reg | variant->clkreg_enable;
891
892 mmci_write_clkreg(host, clk);
893 }
894
895 /*
896 * SDIO especially may want to send something that is
897 * not divisible by 4 (as opposed to card sectors
898 * etc), and the FIFO only accept full 32-bit writes.
899 * So compensate by adding +3 on the count, a single
900 * byte become a 32bit write, 7 bytes will be two
901 * 32bit writes etc.
902 */
903 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
904
905 ptr += count;
906 remain -= count;
907
908 if (remain == 0)
909 break;
910
911 status = readl(base + MMCISTATUS);
912 } while (status & MCI_TXFIFOHALFEMPTY);
913
914 return ptr - buffer;
915}
916
917/*
918 * PIO data transfer IRQ handler.
919 */
920static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
921{
922 struct mmci_host *host = dev_id;
923 struct sg_mapping_iter *sg_miter = &host->sg_miter;
924 struct variant_data *variant = host->variant;
925 void __iomem *base = host->base;
926 unsigned long flags;
927 u32 status;
928
929 status = readl(base + MMCISTATUS);
930
931 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
932
933 local_irq_save(flags);
934
935 do {
936 unsigned int remain, len;
937 char *buffer;
938
939 /*
940 * For write, we only need to test the half-empty flag
941 * here - if the FIFO is completely empty, then by
942 * definition it is more than half empty.
943 *
944 * For read, check for data available.
945 */
946 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
947 break;
948
949 if (!sg_miter_next(sg_miter))
950 break;
951
952 buffer = sg_miter->addr;
953 remain = sg_miter->length;
954
955 len = 0;
956 if (status & MCI_RXACTIVE)
957 len = mmci_pio_read(host, buffer, remain);
958 if (status & MCI_TXACTIVE)
959 len = mmci_pio_write(host, buffer, remain, status);
960
961 sg_miter->consumed = len;
962
963 host->size -= len;
964 remain -= len;
965
966 if (remain)
967 break;
968
969 status = readl(base + MMCISTATUS);
970 } while (1);
971
972 sg_miter_stop(sg_miter);
973
974 local_irq_restore(flags);
975
976 /*
977 * If we have less than the fifo 'half-full' threshold to transfer,
978 * trigger a PIO interrupt as soon as any data is available.
979 */
980 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
981 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
982
983 /*
984 * If we run out of data, disable the data IRQs; this
985 * prevents a race where the FIFO becomes empty before
986 * the chip itself has disabled the data path, and
987 * stops us racing with our data end IRQ.
988 */
989 if (host->size == 0) {
990 mmci_set_mask1(host, 0);
991 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
992 }
993
994 return IRQ_HANDLED;
995}
996
997/*
998 * Handle completion of command and data transfers.
999 */
1000static irqreturn_t mmci_irq(int irq, void *dev_id)
1001{
1002 struct mmci_host *host = dev_id;
1003 u32 status;
1004 int ret = 0;
1005
1006 spin_lock(&host->lock);
1007
1008 do {
1009 struct mmc_command *cmd;
1010 struct mmc_data *data;
1011
1012 status = readl(host->base + MMCISTATUS);
1013
1014 if (host->singleirq) {
1015 if (status & readl(host->base + MMCIMASK1))
1016 mmci_pio_irq(irq, dev_id);
1017
1018 status &= ~MCI_IRQ1MASK;
1019 }
1020
1021 status &= readl(host->base + MMCIMASK0);
1022 writel(status, host->base + MMCICLEAR);
1023
1024 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1025
1026 data = host->data;
1027 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1028 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1029 MCI_DATABLOCKEND) && data)
1030 mmci_data_irq(host, data, status);
1031
1032 cmd = host->cmd;
1033 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1034 mmci_cmd_irq(host, cmd, status);
1035
1036 ret = 1;
1037 } while (status);
1038
1039 spin_unlock(&host->lock);
1040
1041 return IRQ_RETVAL(ret);
1042}
1043
1044static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1045{
1046 struct mmci_host *host = mmc_priv(mmc);
1047 unsigned long flags;
1048
1049 WARN_ON(host->mrq != NULL);
1050
1051 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
1052 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
1053 mrq->data->blksz);
1054 mrq->cmd->error = -EINVAL;
1055 mmc_request_done(mmc, mrq);
1056 return;
1057 }
1058
1059 pm_runtime_get_sync(mmc_dev(mmc));
1060
1061 spin_lock_irqsave(&host->lock, flags);
1062
1063 host->mrq = mrq;
1064
1065 if (mrq->data)
1066 mmci_get_next_data(host, mrq->data);
1067
1068 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1069 mmci_start_data(host, mrq->data);
1070
1071 mmci_start_command(host, mrq->cmd, 0);
1072
1073 spin_unlock_irqrestore(&host->lock, flags);
1074}
1075
1076static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1077{
1078 struct mmci_host *host = mmc_priv(mmc);
1079 struct variant_data *variant = host->variant;
1080 u32 pwr = 0;
1081 unsigned long flags;
1082 int ret;
1083
1084 pm_runtime_get_sync(mmc_dev(mmc));
1085
1086 if (host->plat->ios_handler &&
1087 host->plat->ios_handler(mmc_dev(mmc), ios))
1088 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1089
1090 switch (ios->power_mode) {
1091 case MMC_POWER_OFF:
1092 if (host->vcc)
1093 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
1094 break;
1095 case MMC_POWER_UP:
1096 if (host->vcc) {
1097 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
1098 if (ret) {
1099 dev_err(mmc_dev(mmc), "unable to set OCR\n");
1100 /*
1101 * The .set_ios() function in the mmc_host_ops
1102 * struct return void, and failing to set the
1103 * power should be rare so we print an error
1104 * and return here.
1105 */
1106 goto out;
1107 }
1108 }
1109 /*
1110 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1111 * and instead uses MCI_PWR_ON so apply whatever value is
1112 * configured in the variant data.
1113 */
1114 pwr |= variant->pwrreg_powerup;
1115
1116 break;
1117 case MMC_POWER_ON:
1118 pwr |= MCI_PWR_ON;
1119 break;
1120 }
1121
1122 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1123 /*
1124 * The ST Micro variant has some additional bits
1125 * indicating signal direction for the signals in
1126 * the SD/MMC bus and feedback-clock usage.
1127 */
1128 pwr |= host->plat->sigdir;
1129
1130 if (ios->bus_width == MMC_BUS_WIDTH_4)
1131 pwr &= ~MCI_ST_DATA74DIREN;
1132 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1133 pwr &= (~MCI_ST_DATA74DIREN &
1134 ~MCI_ST_DATA31DIREN &
1135 ~MCI_ST_DATA2DIREN);
1136 }
1137
1138 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1139 if (host->hw_designer != AMBA_VENDOR_ST)
1140 pwr |= MCI_ROD;
1141 else {
1142 /*
1143 * The ST Micro variant use the ROD bit for something
1144 * else and only has OD (Open Drain).
1145 */
1146 pwr |= MCI_OD;
1147 }
1148 }
1149
1150 spin_lock_irqsave(&host->lock, flags);
1151
1152 mmci_set_clkreg(host, ios->clock);
1153 mmci_write_pwrreg(host, pwr);
1154
1155 spin_unlock_irqrestore(&host->lock, flags);
1156
1157 out:
1158 pm_runtime_mark_last_busy(mmc_dev(mmc));
1159 pm_runtime_put_autosuspend(mmc_dev(mmc));
1160}
1161
1162static int mmci_get_ro(struct mmc_host *mmc)
1163{
1164 struct mmci_host *host = mmc_priv(mmc);
1165
1166 if (host->gpio_wp == -ENOSYS)
1167 return -ENOSYS;
1168
1169 return gpio_get_value_cansleep(host->gpio_wp);
1170}
1171
1172static int mmci_get_cd(struct mmc_host *mmc)
1173{
1174 struct mmci_host *host = mmc_priv(mmc);
1175 struct mmci_platform_data *plat = host->plat;
1176 unsigned int status;
1177
1178 if (host->gpio_cd == -ENOSYS) {
1179 if (!plat->status)
1180 return 1; /* Assume always present */
1181
1182 status = plat->status(mmc_dev(host->mmc));
1183 } else
1184 status = !!gpio_get_value_cansleep(host->gpio_cd)
1185 ^ plat->cd_invert;
1186
1187 /*
1188 * Use positive logic throughout - status is zero for no card,
1189 * non-zero for card inserted.
1190 */
1191 return status;
1192}
1193
1194static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1195{
1196 struct mmci_host *host = dev_id;
1197
1198 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1199
1200 return IRQ_HANDLED;
1201}
1202
1203static const struct mmc_host_ops mmci_ops = {
1204 .request = mmci_request,
1205 .pre_req = mmci_pre_request,
1206 .post_req = mmci_post_request,
1207 .set_ios = mmci_set_ios,
1208 .get_ro = mmci_get_ro,
1209 .get_cd = mmci_get_cd,
1210};
1211
1212#ifdef CONFIG_OF
1213static void mmci_dt_populate_generic_pdata(struct device_node *np,
1214 struct mmci_platform_data *pdata)
1215{
1216 int bus_width = 0;
1217
1218 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1219 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0);
1220
1221 if (of_get_property(np, "cd-inverted", NULL))
1222 pdata->cd_invert = true;
1223 else
1224 pdata->cd_invert = false;
1225
1226 of_property_read_u32(np, "max-frequency", &pdata->f_max);
1227 if (!pdata->f_max)
1228 pr_warn("%s has no 'max-frequency' property\n", np->full_name);
1229
1230 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1231 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1232 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1233 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED;
1234
1235 of_property_read_u32(np, "bus-width", &bus_width);
1236 switch (bus_width) {
1237 case 0 :
1238 /* No bus-width supplied. */
1239 break;
1240 case 4 :
1241 pdata->capabilities |= MMC_CAP_4_BIT_DATA;
1242 break;
1243 case 8 :
1244 pdata->capabilities |= MMC_CAP_8_BIT_DATA;
1245 break;
1246 default :
1247 pr_warn("%s: Unsupported bus width\n", np->full_name);
1248 }
1249}
1250#else
1251static void mmci_dt_populate_generic_pdata(struct device_node *np,
1252 struct mmci_platform_data *pdata)
1253{
1254 return;
1255}
1256#endif
1257
1258static int __devinit mmci_probe(struct amba_device *dev,
1259 const struct amba_id *id)
1260{
1261 struct mmci_platform_data *plat = dev->dev.platform_data;
1262 struct device_node *np = dev->dev.of_node;
1263 struct variant_data *variant = id->data;
1264 struct mmci_host *host;
1265 struct mmc_host *mmc;
1266 int ret;
1267
1268 /* Must have platform data or Device Tree. */
1269 if (!plat && !np) {
1270 dev_err(&dev->dev, "No plat data or DT found\n");
1271 return -EINVAL;
1272 }
1273
1274 if (!plat) {
1275 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1276 if (!plat)
1277 return -ENOMEM;
1278 }
1279
1280 if (np)
1281 mmci_dt_populate_generic_pdata(np, plat);
1282
1283 ret = amba_request_regions(dev, DRIVER_NAME);
1284 if (ret)
1285 goto out;
1286
1287 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1288 if (!mmc) {
1289 ret = -ENOMEM;
1290 goto rel_regions;
1291 }
1292
1293 host = mmc_priv(mmc);
1294 host->mmc = mmc;
1295
1296 host->gpio_wp = -ENOSYS;
1297 host->gpio_cd = -ENOSYS;
1298 host->gpio_cd_irq = -1;
1299
1300 host->hw_designer = amba_manf(dev);
1301 host->hw_revision = amba_rev(dev);
1302 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1303 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1304
1305 host->clk = clk_get(&dev->dev, NULL);
1306 if (IS_ERR(host->clk)) {
1307 ret = PTR_ERR(host->clk);
1308 host->clk = NULL;
1309 goto host_free;
1310 }
1311
1312 ret = clk_prepare(host->clk);
1313 if (ret)
1314 goto clk_free;
1315
1316 ret = clk_enable(host->clk);
1317 if (ret)
1318 goto clk_unprep;
1319
1320 host->plat = plat;
1321 host->variant = variant;
1322 host->mclk = clk_get_rate(host->clk);
1323 /*
1324 * According to the spec, mclk is max 100 MHz,
1325 * so we try to adjust the clock down to this,
1326 * (if possible).
1327 */
1328 if (host->mclk > 100000000) {
1329 ret = clk_set_rate(host->clk, 100000000);
1330 if (ret < 0)
1331 goto clk_disable;
1332 host->mclk = clk_get_rate(host->clk);
1333 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1334 host->mclk);
1335 }
1336 host->phybase = dev->res.start;
1337 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1338 if (!host->base) {
1339 ret = -ENOMEM;
1340 goto clk_disable;
1341 }
1342
1343 mmc->ops = &mmci_ops;
1344 /*
1345 * The ARM and ST versions of the block have slightly different
1346 * clock divider equations which means that the minimum divider
1347 * differs too.
1348 */
1349 if (variant->st_clkdiv)
1350 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1351 else
1352 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1353 /*
1354 * If the platform data supplies a maximum operating
1355 * frequency, this takes precedence. Else, we fall back
1356 * to using the module parameter, which has a (low)
1357 * default value in case it is not specified. Either
1358 * value must not exceed the clock rate into the block,
1359 * of course.
1360 */
1361 if (plat->f_max)
1362 mmc->f_max = min(host->mclk, plat->f_max);
1363 else
1364 mmc->f_max = min(host->mclk, fmax);
1365 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1366
1367#ifdef CONFIG_REGULATOR
1368 /* If we're using the regulator framework, try to fetch a regulator */
1369 host->vcc = regulator_get(&dev->dev, "vmmc");
1370 if (IS_ERR(host->vcc))
1371 host->vcc = NULL;
1372 else {
1373 int mask = mmc_regulator_get_ocrmask(host->vcc);
1374
1375 if (mask < 0)
1376 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
1377 mask);
1378 else {
1379 host->mmc->ocr_avail = (u32) mask;
1380 if (plat->ocr_mask)
1381 dev_warn(&dev->dev,
1382 "Provided ocr_mask/setpower will not be used "
1383 "(using regulator instead)\n");
1384 }
1385 }
1386#endif
1387 /* Fall back to platform data if no regulator is found */
1388 if (host->vcc == NULL)
1389 mmc->ocr_avail = plat->ocr_mask;
1390 mmc->caps = plat->capabilities;
1391 mmc->caps2 = plat->capabilities2;
1392
1393 /*
1394 * We can do SGIO
1395 */
1396 mmc->max_segs = NR_SG;
1397
1398 /*
1399 * Since only a certain number of bits are valid in the data length
1400 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1401 * single request.
1402 */
1403 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1404
1405 /*
1406 * Set the maximum segment size. Since we aren't doing DMA
1407 * (yet) we are only limited by the data length register.
1408 */
1409 mmc->max_seg_size = mmc->max_req_size;
1410
1411 /*
1412 * Block size can be up to 2048 bytes, but must be a power of two.
1413 */
1414 mmc->max_blk_size = 1 << 11;
1415
1416 /*
1417 * Limit the number of blocks transferred so that we don't overflow
1418 * the maximum request size.
1419 */
1420 mmc->max_blk_count = mmc->max_req_size >> 11;
1421
1422 spin_lock_init(&host->lock);
1423
1424 writel(0, host->base + MMCIMASK0);
1425 writel(0, host->base + MMCIMASK1);
1426 writel(0xfff, host->base + MMCICLEAR);
1427
1428 if (plat->gpio_cd == -EPROBE_DEFER) {
1429 ret = -EPROBE_DEFER;
1430 goto err_gpio_cd;
1431 }
1432 if (gpio_is_valid(plat->gpio_cd)) {
1433 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1434 if (ret == 0)
1435 ret = gpio_direction_input(plat->gpio_cd);
1436 if (ret == 0)
1437 host->gpio_cd = plat->gpio_cd;
1438 else if (ret != -ENOSYS)
1439 goto err_gpio_cd;
1440
1441 /*
1442 * A gpio pin that will detect cards when inserted and removed
1443 * will most likely want to trigger on the edges if it is
1444 * 0 when ejected and 1 when inserted (or mutatis mutandis
1445 * for the inverted case) so we request triggers on both
1446 * edges.
1447 */
1448 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1449 mmci_cd_irq,
1450 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1451 DRIVER_NAME " (cd)", host);
1452 if (ret >= 0)
1453 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1454 }
1455 if (plat->gpio_wp == -EPROBE_DEFER) {
1456 ret = -EPROBE_DEFER;
1457 goto err_gpio_wp;
1458 }
1459 if (gpio_is_valid(plat->gpio_wp)) {
1460 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1461 if (ret == 0)
1462 ret = gpio_direction_input(plat->gpio_wp);
1463 if (ret == 0)
1464 host->gpio_wp = plat->gpio_wp;
1465 else if (ret != -ENOSYS)
1466 goto err_gpio_wp;
1467 }
1468
1469 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1470 && host->gpio_cd_irq < 0)
1471 mmc->caps |= MMC_CAP_NEEDS_POLL;
1472
1473 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1474 if (ret)
1475 goto unmap;
1476
1477 if (!dev->irq[1])
1478 host->singleirq = true;
1479 else {
1480 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1481 DRIVER_NAME " (pio)", host);
1482 if (ret)
1483 goto irq0_free;
1484 }
1485
1486 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1487
1488 amba_set_drvdata(dev, mmc);
1489
1490 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1491 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1492 amba_rev(dev), (unsigned long long)dev->res.start,
1493 dev->irq[0], dev->irq[1]);
1494
1495 mmci_dma_setup(host);
1496
1497 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1498 pm_runtime_use_autosuspend(&dev->dev);
1499 pm_runtime_put(&dev->dev);
1500
1501 mmc_add_host(mmc);
1502
1503 return 0;
1504
1505 irq0_free:
1506 free_irq(dev->irq[0], host);
1507 unmap:
1508 if (host->gpio_wp != -ENOSYS)
1509 gpio_free(host->gpio_wp);
1510 err_gpio_wp:
1511 if (host->gpio_cd_irq >= 0)
1512 free_irq(host->gpio_cd_irq, host);
1513 if (host->gpio_cd != -ENOSYS)
1514 gpio_free(host->gpio_cd);
1515 err_gpio_cd:
1516 iounmap(host->base);
1517 clk_disable:
1518 clk_disable(host->clk);
1519 clk_unprep:
1520 clk_unprepare(host->clk);
1521 clk_free:
1522 clk_put(host->clk);
1523 host_free:
1524 mmc_free_host(mmc);
1525 rel_regions:
1526 amba_release_regions(dev);
1527 out:
1528 return ret;
1529}
1530
1531static int __devexit mmci_remove(struct amba_device *dev)
1532{
1533 struct mmc_host *mmc = amba_get_drvdata(dev);
1534
1535 amba_set_drvdata(dev, NULL);
1536
1537 if (mmc) {
1538 struct mmci_host *host = mmc_priv(mmc);
1539
1540 /*
1541 * Undo pm_runtime_put() in probe. We use the _sync
1542 * version here so that we can access the primecell.
1543 */
1544 pm_runtime_get_sync(&dev->dev);
1545
1546 mmc_remove_host(mmc);
1547
1548 writel(0, host->base + MMCIMASK0);
1549 writel(0, host->base + MMCIMASK1);
1550
1551 writel(0, host->base + MMCICOMMAND);
1552 writel(0, host->base + MMCIDATACTRL);
1553
1554 mmci_dma_release(host);
1555 free_irq(dev->irq[0], host);
1556 if (!host->singleirq)
1557 free_irq(dev->irq[1], host);
1558
1559 if (host->gpio_wp != -ENOSYS)
1560 gpio_free(host->gpio_wp);
1561 if (host->gpio_cd_irq >= 0)
1562 free_irq(host->gpio_cd_irq, host);
1563 if (host->gpio_cd != -ENOSYS)
1564 gpio_free(host->gpio_cd);
1565
1566 iounmap(host->base);
1567 clk_disable(host->clk);
1568 clk_unprepare(host->clk);
1569 clk_put(host->clk);
1570
1571 if (host->vcc)
1572 mmc_regulator_set_ocr(mmc, host->vcc, 0);
1573 regulator_put(host->vcc);
1574
1575 mmc_free_host(mmc);
1576
1577 amba_release_regions(dev);
1578 }
1579
1580 return 0;
1581}
1582
1583#ifdef CONFIG_SUSPEND
1584static int mmci_suspend(struct device *dev)
1585{
1586 struct amba_device *adev = to_amba_device(dev);
1587 struct mmc_host *mmc = amba_get_drvdata(adev);
1588 int ret = 0;
1589
1590 if (mmc) {
1591 struct mmci_host *host = mmc_priv(mmc);
1592
1593 ret = mmc_suspend_host(mmc);
1594 if (ret == 0) {
1595 pm_runtime_get_sync(dev);
1596 writel(0, host->base + MMCIMASK0);
1597 }
1598 }
1599
1600 return ret;
1601}
1602
1603static int mmci_resume(struct device *dev)
1604{
1605 struct amba_device *adev = to_amba_device(dev);
1606 struct mmc_host *mmc = amba_get_drvdata(adev);
1607 int ret = 0;
1608
1609 if (mmc) {
1610 struct mmci_host *host = mmc_priv(mmc);
1611
1612 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1613 pm_runtime_put(dev);
1614
1615 ret = mmc_resume_host(mmc);
1616 }
1617
1618 return ret;
1619}
1620#endif
1621
1622static const struct dev_pm_ops mmci_dev_pm_ops = {
1623 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume)
1624};
1625
1626static struct amba_id mmci_ids[] = {
1627 {
1628 .id = 0x00041180,
1629 .mask = 0xff0fffff,
1630 .data = &variant_arm,
1631 },
1632 {
1633 .id = 0x01041180,
1634 .mask = 0xff0fffff,
1635 .data = &variant_arm_extended_fifo,
1636 },
1637 {
1638 .id = 0x00041181,
1639 .mask = 0x000fffff,
1640 .data = &variant_arm,
1641 },
1642 /* ST Micro variants */
1643 {
1644 .id = 0x00180180,
1645 .mask = 0x00ffffff,
1646 .data = &variant_u300,
1647 },
1648 {
1649 .id = 0x10180180,
1650 .mask = 0xf0ffffff,
1651 .data = &variant_nomadik,
1652 },
1653 {
1654 .id = 0x00280180,
1655 .mask = 0x00ffffff,
1656 .data = &variant_u300,
1657 },
1658 {
1659 .id = 0x00480180,
1660 .mask = 0xf0ffffff,
1661 .data = &variant_ux500,
1662 },
1663 {
1664 .id = 0x10480180,
1665 .mask = 0xf0ffffff,
1666 .data = &variant_ux500v2,
1667 },
1668 { 0, 0 },
1669};
1670
1671MODULE_DEVICE_TABLE(amba, mmci_ids);
1672
1673static struct amba_driver mmci_driver = {
1674 .drv = {
1675 .name = DRIVER_NAME,
1676 .pm = &mmci_dev_pm_ops,
1677 },
1678 .probe = mmci_probe,
1679 .remove = __devexit_p(mmci_remove),
1680 .id_table = mmci_ids,
1681};
1682
1683module_amba_driver(mmci_driver);
1684
1685module_param(fmax, uint, 0444);
1686
1687MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1688MODULE_LICENSE("GPL");
1/*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/highmem.h>
21#include <linux/log2.h>
22#include <linux/mmc/host.h>
23#include <linux/mmc/card.h>
24#include <linux/amba/bus.h>
25#include <linux/clk.h>
26#include <linux/scatterlist.h>
27#include <linux/gpio.h>
28#include <linux/regulator/consumer.h>
29#include <linux/dmaengine.h>
30#include <linux/dma-mapping.h>
31#include <linux/amba/mmci.h>
32
33#include <asm/div64.h>
34#include <asm/io.h>
35#include <asm/sizes.h>
36
37#include "mmci.h"
38
39#define DRIVER_NAME "mmci-pl18x"
40
41static unsigned int fmax = 515633;
42
43/**
44 * struct variant_data - MMCI variant-specific quirks
45 * @clkreg: default value for MCICLOCK register
46 * @clkreg_enable: enable value for MMCICLOCK register
47 * @datalength_bits: number of bits in the MMCIDATALENGTH register
48 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
49 * is asserted (likewise for RX)
50 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
51 * is asserted (likewise for RX)
52 * @sdio: variant supports SDIO
53 * @st_clkdiv: true if using a ST-specific clock divider algorithm
54 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
55 */
56struct variant_data {
57 unsigned int clkreg;
58 unsigned int clkreg_enable;
59 unsigned int datalength_bits;
60 unsigned int fifosize;
61 unsigned int fifohalfsize;
62 bool sdio;
63 bool st_clkdiv;
64 bool blksz_datactrl16;
65};
66
67static struct variant_data variant_arm = {
68 .fifosize = 16 * 4,
69 .fifohalfsize = 8 * 4,
70 .datalength_bits = 16,
71};
72
73static struct variant_data variant_arm_extended_fifo = {
74 .fifosize = 128 * 4,
75 .fifohalfsize = 64 * 4,
76 .datalength_bits = 16,
77};
78
79static struct variant_data variant_u300 = {
80 .fifosize = 16 * 4,
81 .fifohalfsize = 8 * 4,
82 .clkreg_enable = MCI_ST_U300_HWFCEN,
83 .datalength_bits = 16,
84 .sdio = true,
85};
86
87static struct variant_data variant_ux500 = {
88 .fifosize = 30 * 4,
89 .fifohalfsize = 8 * 4,
90 .clkreg = MCI_CLK_ENABLE,
91 .clkreg_enable = MCI_ST_UX500_HWFCEN,
92 .datalength_bits = 24,
93 .sdio = true,
94 .st_clkdiv = true,
95};
96
97static struct variant_data variant_ux500v2 = {
98 .fifosize = 30 * 4,
99 .fifohalfsize = 8 * 4,
100 .clkreg = MCI_CLK_ENABLE,
101 .clkreg_enable = MCI_ST_UX500_HWFCEN,
102 .datalength_bits = 24,
103 .sdio = true,
104 .st_clkdiv = true,
105 .blksz_datactrl16 = true,
106};
107
108/*
109 * This must be called with host->lock held
110 */
111static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
112{
113 struct variant_data *variant = host->variant;
114 u32 clk = variant->clkreg;
115
116 if (desired) {
117 if (desired >= host->mclk) {
118 clk = MCI_CLK_BYPASS;
119 if (variant->st_clkdiv)
120 clk |= MCI_ST_UX500_NEG_EDGE;
121 host->cclk = host->mclk;
122 } else if (variant->st_clkdiv) {
123 /*
124 * DB8500 TRM says f = mclk / (clkdiv + 2)
125 * => clkdiv = (mclk / f) - 2
126 * Round the divider up so we don't exceed the max
127 * frequency
128 */
129 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
130 if (clk >= 256)
131 clk = 255;
132 host->cclk = host->mclk / (clk + 2);
133 } else {
134 /*
135 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
136 * => clkdiv = mclk / (2 * f) - 1
137 */
138 clk = host->mclk / (2 * desired) - 1;
139 if (clk >= 256)
140 clk = 255;
141 host->cclk = host->mclk / (2 * (clk + 1));
142 }
143
144 clk |= variant->clkreg_enable;
145 clk |= MCI_CLK_ENABLE;
146 /* This hasn't proven to be worthwhile */
147 /* clk |= MCI_CLK_PWRSAVE; */
148 }
149
150 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
151 clk |= MCI_4BIT_BUS;
152 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
153 clk |= MCI_ST_8BIT_BUS;
154
155 writel(clk, host->base + MMCICLOCK);
156}
157
158static void
159mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
160{
161 writel(0, host->base + MMCICOMMAND);
162
163 BUG_ON(host->data);
164
165 host->mrq = NULL;
166 host->cmd = NULL;
167
168 /*
169 * Need to drop the host lock here; mmc_request_done may call
170 * back into the driver...
171 */
172 spin_unlock(&host->lock);
173 mmc_request_done(host->mmc, mrq);
174 spin_lock(&host->lock);
175}
176
177static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
178{
179 void __iomem *base = host->base;
180
181 if (host->singleirq) {
182 unsigned int mask0 = readl(base + MMCIMASK0);
183
184 mask0 &= ~MCI_IRQ1MASK;
185 mask0 |= mask;
186
187 writel(mask0, base + MMCIMASK0);
188 }
189
190 writel(mask, base + MMCIMASK1);
191}
192
193static void mmci_stop_data(struct mmci_host *host)
194{
195 writel(0, host->base + MMCIDATACTRL);
196 mmci_set_mask1(host, 0);
197 host->data = NULL;
198}
199
200static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
201{
202 unsigned int flags = SG_MITER_ATOMIC;
203
204 if (data->flags & MMC_DATA_READ)
205 flags |= SG_MITER_TO_SG;
206 else
207 flags |= SG_MITER_FROM_SG;
208
209 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
210}
211
212/*
213 * All the DMA operation mode stuff goes inside this ifdef.
214 * This assumes that you have a generic DMA device interface,
215 * no custom DMA interfaces are supported.
216 */
217#ifdef CONFIG_DMA_ENGINE
218static void __devinit mmci_dma_setup(struct mmci_host *host)
219{
220 struct mmci_platform_data *plat = host->plat;
221 const char *rxname, *txname;
222 dma_cap_mask_t mask;
223
224 if (!plat || !plat->dma_filter) {
225 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
226 return;
227 }
228
229 /* initialize pre request cookie */
230 host->next_data.cookie = 1;
231
232 /* Try to acquire a generic DMA engine slave channel */
233 dma_cap_zero(mask);
234 dma_cap_set(DMA_SLAVE, mask);
235
236 /*
237 * If only an RX channel is specified, the driver will
238 * attempt to use it bidirectionally, however if it is
239 * is specified but cannot be located, DMA will be disabled.
240 */
241 if (plat->dma_rx_param) {
242 host->dma_rx_channel = dma_request_channel(mask,
243 plat->dma_filter,
244 plat->dma_rx_param);
245 /* E.g if no DMA hardware is present */
246 if (!host->dma_rx_channel)
247 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
248 }
249
250 if (plat->dma_tx_param) {
251 host->dma_tx_channel = dma_request_channel(mask,
252 plat->dma_filter,
253 plat->dma_tx_param);
254 if (!host->dma_tx_channel)
255 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
256 } else {
257 host->dma_tx_channel = host->dma_rx_channel;
258 }
259
260 if (host->dma_rx_channel)
261 rxname = dma_chan_name(host->dma_rx_channel);
262 else
263 rxname = "none";
264
265 if (host->dma_tx_channel)
266 txname = dma_chan_name(host->dma_tx_channel);
267 else
268 txname = "none";
269
270 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
271 rxname, txname);
272
273 /*
274 * Limit the maximum segment size in any SG entry according to
275 * the parameters of the DMA engine device.
276 */
277 if (host->dma_tx_channel) {
278 struct device *dev = host->dma_tx_channel->device->dev;
279 unsigned int max_seg_size = dma_get_max_seg_size(dev);
280
281 if (max_seg_size < host->mmc->max_seg_size)
282 host->mmc->max_seg_size = max_seg_size;
283 }
284 if (host->dma_rx_channel) {
285 struct device *dev = host->dma_rx_channel->device->dev;
286 unsigned int max_seg_size = dma_get_max_seg_size(dev);
287
288 if (max_seg_size < host->mmc->max_seg_size)
289 host->mmc->max_seg_size = max_seg_size;
290 }
291}
292
293/*
294 * This is used in __devinit or __devexit so inline it
295 * so it can be discarded.
296 */
297static inline void mmci_dma_release(struct mmci_host *host)
298{
299 struct mmci_platform_data *plat = host->plat;
300
301 if (host->dma_rx_channel)
302 dma_release_channel(host->dma_rx_channel);
303 if (host->dma_tx_channel && plat->dma_tx_param)
304 dma_release_channel(host->dma_tx_channel);
305 host->dma_rx_channel = host->dma_tx_channel = NULL;
306}
307
308static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
309{
310 struct dma_chan *chan = host->dma_current;
311 enum dma_data_direction dir;
312 u32 status;
313 int i;
314
315 /* Wait up to 1ms for the DMA to complete */
316 for (i = 0; ; i++) {
317 status = readl(host->base + MMCISTATUS);
318 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
319 break;
320 udelay(10);
321 }
322
323 /*
324 * Check to see whether we still have some data left in the FIFO -
325 * this catches DMA controllers which are unable to monitor the
326 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
327 * contiguous buffers. On TX, we'll get a FIFO underrun error.
328 */
329 if (status & MCI_RXDATAAVLBLMASK) {
330 dmaengine_terminate_all(chan);
331 if (!data->error)
332 data->error = -EIO;
333 }
334
335 if (data->flags & MMC_DATA_WRITE) {
336 dir = DMA_TO_DEVICE;
337 } else {
338 dir = DMA_FROM_DEVICE;
339 }
340
341 if (!data->host_cookie)
342 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
343
344 /*
345 * Use of DMA with scatter-gather is impossible.
346 * Give up with DMA and switch back to PIO mode.
347 */
348 if (status & MCI_RXDATAAVLBLMASK) {
349 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
350 mmci_dma_release(host);
351 }
352}
353
354static void mmci_dma_data_error(struct mmci_host *host)
355{
356 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
357 dmaengine_terminate_all(host->dma_current);
358}
359
360static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
361 struct mmci_host_next *next)
362{
363 struct variant_data *variant = host->variant;
364 struct dma_slave_config conf = {
365 .src_addr = host->phybase + MMCIFIFO,
366 .dst_addr = host->phybase + MMCIFIFO,
367 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
368 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
369 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
370 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
371 };
372 struct dma_chan *chan;
373 struct dma_device *device;
374 struct dma_async_tx_descriptor *desc;
375 int nr_sg;
376
377 /* Check if next job is already prepared */
378 if (data->host_cookie && !next &&
379 host->dma_current && host->dma_desc_current)
380 return 0;
381
382 if (!next) {
383 host->dma_current = NULL;
384 host->dma_desc_current = NULL;
385 }
386
387 if (data->flags & MMC_DATA_READ) {
388 conf.direction = DMA_FROM_DEVICE;
389 chan = host->dma_rx_channel;
390 } else {
391 conf.direction = DMA_TO_DEVICE;
392 chan = host->dma_tx_channel;
393 }
394
395 /* If there's no DMA channel, fall back to PIO */
396 if (!chan)
397 return -EINVAL;
398
399 /* If less than or equal to the fifo size, don't bother with DMA */
400 if (data->blksz * data->blocks <= variant->fifosize)
401 return -EINVAL;
402
403 device = chan->device;
404 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction);
405 if (nr_sg == 0)
406 return -EINVAL;
407
408 dmaengine_slave_config(chan, &conf);
409 desc = device->device_prep_slave_sg(chan, data->sg, nr_sg,
410 conf.direction, DMA_CTRL_ACK);
411 if (!desc)
412 goto unmap_exit;
413
414 if (next) {
415 next->dma_chan = chan;
416 next->dma_desc = desc;
417 } else {
418 host->dma_current = chan;
419 host->dma_desc_current = desc;
420 }
421
422 return 0;
423
424 unmap_exit:
425 if (!next)
426 dmaengine_terminate_all(chan);
427 dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction);
428 return -ENOMEM;
429}
430
431static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
432{
433 int ret;
434 struct mmc_data *data = host->data;
435
436 ret = mmci_dma_prep_data(host, host->data, NULL);
437 if (ret)
438 return ret;
439
440 /* Okay, go for it. */
441 dev_vdbg(mmc_dev(host->mmc),
442 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
443 data->sg_len, data->blksz, data->blocks, data->flags);
444 dmaengine_submit(host->dma_desc_current);
445 dma_async_issue_pending(host->dma_current);
446
447 datactrl |= MCI_DPSM_DMAENABLE;
448
449 /* Trigger the DMA transfer */
450 writel(datactrl, host->base + MMCIDATACTRL);
451
452 /*
453 * Let the MMCI say when the data is ended and it's time
454 * to fire next DMA request. When that happens, MMCI will
455 * call mmci_data_end()
456 */
457 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
458 host->base + MMCIMASK0);
459 return 0;
460}
461
462static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
463{
464 struct mmci_host_next *next = &host->next_data;
465
466 if (data->host_cookie && data->host_cookie != next->cookie) {
467 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
468 " host->next_data.cookie %d\n",
469 __func__, data->host_cookie, host->next_data.cookie);
470 data->host_cookie = 0;
471 }
472
473 if (!data->host_cookie)
474 return;
475
476 host->dma_desc_current = next->dma_desc;
477 host->dma_current = next->dma_chan;
478
479 next->dma_desc = NULL;
480 next->dma_chan = NULL;
481}
482
483static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
484 bool is_first_req)
485{
486 struct mmci_host *host = mmc_priv(mmc);
487 struct mmc_data *data = mrq->data;
488 struct mmci_host_next *nd = &host->next_data;
489
490 if (!data)
491 return;
492
493 if (data->host_cookie) {
494 data->host_cookie = 0;
495 return;
496 }
497
498 /* if config for dma */
499 if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) ||
500 ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) {
501 if (mmci_dma_prep_data(host, data, nd))
502 data->host_cookie = 0;
503 else
504 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
505 }
506}
507
508static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
509 int err)
510{
511 struct mmci_host *host = mmc_priv(mmc);
512 struct mmc_data *data = mrq->data;
513 struct dma_chan *chan;
514 enum dma_data_direction dir;
515
516 if (!data)
517 return;
518
519 if (data->flags & MMC_DATA_READ) {
520 dir = DMA_FROM_DEVICE;
521 chan = host->dma_rx_channel;
522 } else {
523 dir = DMA_TO_DEVICE;
524 chan = host->dma_tx_channel;
525 }
526
527
528 /* if config for dma */
529 if (chan) {
530 if (err)
531 dmaengine_terminate_all(chan);
532 if (err || data->host_cookie)
533 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
534 data->sg_len, dir);
535 mrq->data->host_cookie = 0;
536 }
537}
538
539#else
540/* Blank functions if the DMA engine is not available */
541static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
542{
543}
544static inline void mmci_dma_setup(struct mmci_host *host)
545{
546}
547
548static inline void mmci_dma_release(struct mmci_host *host)
549{
550}
551
552static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
553{
554}
555
556static inline void mmci_dma_data_error(struct mmci_host *host)
557{
558}
559
560static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
561{
562 return -ENOSYS;
563}
564
565#define mmci_pre_request NULL
566#define mmci_post_request NULL
567
568#endif
569
570static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
571{
572 struct variant_data *variant = host->variant;
573 unsigned int datactrl, timeout, irqmask;
574 unsigned long long clks;
575 void __iomem *base;
576 int blksz_bits;
577
578 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
579 data->blksz, data->blocks, data->flags);
580
581 host->data = data;
582 host->size = data->blksz * data->blocks;
583 data->bytes_xfered = 0;
584
585 clks = (unsigned long long)data->timeout_ns * host->cclk;
586 do_div(clks, 1000000000UL);
587
588 timeout = data->timeout_clks + (unsigned int)clks;
589
590 base = host->base;
591 writel(timeout, base + MMCIDATATIMER);
592 writel(host->size, base + MMCIDATALENGTH);
593
594 blksz_bits = ffs(data->blksz) - 1;
595 BUG_ON(1 << blksz_bits != data->blksz);
596
597 if (variant->blksz_datactrl16)
598 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
599 else
600 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
601
602 if (data->flags & MMC_DATA_READ)
603 datactrl |= MCI_DPSM_DIRECTION;
604
605 /*
606 * Attempt to use DMA operation mode, if this
607 * should fail, fall back to PIO mode
608 */
609 if (!mmci_dma_start_data(host, datactrl))
610 return;
611
612 /* IRQ mode, map the SG list for CPU reading/writing */
613 mmci_init_sg(host, data);
614
615 if (data->flags & MMC_DATA_READ) {
616 irqmask = MCI_RXFIFOHALFFULLMASK;
617
618 /*
619 * If we have less than the fifo 'half-full' threshold to
620 * transfer, trigger a PIO interrupt as soon as any data
621 * is available.
622 */
623 if (host->size < variant->fifohalfsize)
624 irqmask |= MCI_RXDATAAVLBLMASK;
625 } else {
626 /*
627 * We don't actually need to include "FIFO empty" here
628 * since its implicit in "FIFO half empty".
629 */
630 irqmask = MCI_TXFIFOHALFEMPTYMASK;
631 }
632
633 /* The ST Micro variants has a special bit to enable SDIO */
634 if (variant->sdio && host->mmc->card)
635 if (mmc_card_sdio(host->mmc->card))
636 datactrl |= MCI_ST_DPSM_SDIOEN;
637
638 writel(datactrl, base + MMCIDATACTRL);
639 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
640 mmci_set_mask1(host, irqmask);
641}
642
643static void
644mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
645{
646 void __iomem *base = host->base;
647
648 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
649 cmd->opcode, cmd->arg, cmd->flags);
650
651 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
652 writel(0, base + MMCICOMMAND);
653 udelay(1);
654 }
655
656 c |= cmd->opcode | MCI_CPSM_ENABLE;
657 if (cmd->flags & MMC_RSP_PRESENT) {
658 if (cmd->flags & MMC_RSP_136)
659 c |= MCI_CPSM_LONGRSP;
660 c |= MCI_CPSM_RESPONSE;
661 }
662 if (/*interrupt*/0)
663 c |= MCI_CPSM_INTERRUPT;
664
665 host->cmd = cmd;
666
667 writel(cmd->arg, base + MMCIARGUMENT);
668 writel(c, base + MMCICOMMAND);
669}
670
671static void
672mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
673 unsigned int status)
674{
675 /* First check for errors */
676 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
677 u32 remain, success;
678
679 /* Terminate the DMA transfer */
680 if (dma_inprogress(host))
681 mmci_dma_data_error(host);
682
683 /*
684 * Calculate how far we are into the transfer. Note that
685 * the data counter gives the number of bytes transferred
686 * on the MMC bus, not on the host side. On reads, this
687 * can be as much as a FIFO-worth of data ahead. This
688 * matters for FIFO overruns only.
689 */
690 remain = readl(host->base + MMCIDATACNT);
691 success = data->blksz * data->blocks - remain;
692
693 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
694 status, success);
695 if (status & MCI_DATACRCFAIL) {
696 /* Last block was not successful */
697 success -= 1;
698 data->error = -EILSEQ;
699 } else if (status & MCI_DATATIMEOUT) {
700 data->error = -ETIMEDOUT;
701 } else if (status & MCI_STARTBITERR) {
702 data->error = -ECOMM;
703 } else if (status & MCI_TXUNDERRUN) {
704 data->error = -EIO;
705 } else if (status & MCI_RXOVERRUN) {
706 if (success > host->variant->fifosize)
707 success -= host->variant->fifosize;
708 else
709 success = 0;
710 data->error = -EIO;
711 }
712 data->bytes_xfered = round_down(success, data->blksz);
713 }
714
715 if (status & MCI_DATABLOCKEND)
716 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
717
718 if (status & MCI_DATAEND || data->error) {
719 if (dma_inprogress(host))
720 mmci_dma_unmap(host, data);
721 mmci_stop_data(host);
722
723 if (!data->error)
724 /* The error clause is handled above, success! */
725 data->bytes_xfered = data->blksz * data->blocks;
726
727 if (!data->stop) {
728 mmci_request_end(host, data->mrq);
729 } else {
730 mmci_start_command(host, data->stop, 0);
731 }
732 }
733}
734
735static void
736mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
737 unsigned int status)
738{
739 void __iomem *base = host->base;
740
741 host->cmd = NULL;
742
743 if (status & MCI_CMDTIMEOUT) {
744 cmd->error = -ETIMEDOUT;
745 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
746 cmd->error = -EILSEQ;
747 } else {
748 cmd->resp[0] = readl(base + MMCIRESPONSE0);
749 cmd->resp[1] = readl(base + MMCIRESPONSE1);
750 cmd->resp[2] = readl(base + MMCIRESPONSE2);
751 cmd->resp[3] = readl(base + MMCIRESPONSE3);
752 }
753
754 if (!cmd->data || cmd->error) {
755 if (host->data)
756 mmci_stop_data(host);
757 mmci_request_end(host, cmd->mrq);
758 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
759 mmci_start_data(host, cmd->data);
760 }
761}
762
763static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
764{
765 void __iomem *base = host->base;
766 char *ptr = buffer;
767 u32 status;
768 int host_remain = host->size;
769
770 do {
771 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
772
773 if (count > remain)
774 count = remain;
775
776 if (count <= 0)
777 break;
778
779 readsl(base + MMCIFIFO, ptr, count >> 2);
780
781 ptr += count;
782 remain -= count;
783 host_remain -= count;
784
785 if (remain == 0)
786 break;
787
788 status = readl(base + MMCISTATUS);
789 } while (status & MCI_RXDATAAVLBL);
790
791 return ptr - buffer;
792}
793
794static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
795{
796 struct variant_data *variant = host->variant;
797 void __iomem *base = host->base;
798 char *ptr = buffer;
799
800 do {
801 unsigned int count, maxcnt;
802
803 maxcnt = status & MCI_TXFIFOEMPTY ?
804 variant->fifosize : variant->fifohalfsize;
805 count = min(remain, maxcnt);
806
807 /*
808 * The ST Micro variant for SDIO transfer sizes
809 * less then 8 bytes should have clock H/W flow
810 * control disabled.
811 */
812 if (variant->sdio &&
813 mmc_card_sdio(host->mmc->card)) {
814 if (count < 8)
815 writel(readl(host->base + MMCICLOCK) &
816 ~variant->clkreg_enable,
817 host->base + MMCICLOCK);
818 else
819 writel(readl(host->base + MMCICLOCK) |
820 variant->clkreg_enable,
821 host->base + MMCICLOCK);
822 }
823
824 /*
825 * SDIO especially may want to send something that is
826 * not divisible by 4 (as opposed to card sectors
827 * etc), and the FIFO only accept full 32-bit writes.
828 * So compensate by adding +3 on the count, a single
829 * byte become a 32bit write, 7 bytes will be two
830 * 32bit writes etc.
831 */
832 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
833
834 ptr += count;
835 remain -= count;
836
837 if (remain == 0)
838 break;
839
840 status = readl(base + MMCISTATUS);
841 } while (status & MCI_TXFIFOHALFEMPTY);
842
843 return ptr - buffer;
844}
845
846/*
847 * PIO data transfer IRQ handler.
848 */
849static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
850{
851 struct mmci_host *host = dev_id;
852 struct sg_mapping_iter *sg_miter = &host->sg_miter;
853 struct variant_data *variant = host->variant;
854 void __iomem *base = host->base;
855 unsigned long flags;
856 u32 status;
857
858 status = readl(base + MMCISTATUS);
859
860 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
861
862 local_irq_save(flags);
863
864 do {
865 unsigned int remain, len;
866 char *buffer;
867
868 /*
869 * For write, we only need to test the half-empty flag
870 * here - if the FIFO is completely empty, then by
871 * definition it is more than half empty.
872 *
873 * For read, check for data available.
874 */
875 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
876 break;
877
878 if (!sg_miter_next(sg_miter))
879 break;
880
881 buffer = sg_miter->addr;
882 remain = sg_miter->length;
883
884 len = 0;
885 if (status & MCI_RXACTIVE)
886 len = mmci_pio_read(host, buffer, remain);
887 if (status & MCI_TXACTIVE)
888 len = mmci_pio_write(host, buffer, remain, status);
889
890 sg_miter->consumed = len;
891
892 host->size -= len;
893 remain -= len;
894
895 if (remain)
896 break;
897
898 status = readl(base + MMCISTATUS);
899 } while (1);
900
901 sg_miter_stop(sg_miter);
902
903 local_irq_restore(flags);
904
905 /*
906 * If we have less than the fifo 'half-full' threshold to transfer,
907 * trigger a PIO interrupt as soon as any data is available.
908 */
909 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
910 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
911
912 /*
913 * If we run out of data, disable the data IRQs; this
914 * prevents a race where the FIFO becomes empty before
915 * the chip itself has disabled the data path, and
916 * stops us racing with our data end IRQ.
917 */
918 if (host->size == 0) {
919 mmci_set_mask1(host, 0);
920 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
921 }
922
923 return IRQ_HANDLED;
924}
925
926/*
927 * Handle completion of command and data transfers.
928 */
929static irqreturn_t mmci_irq(int irq, void *dev_id)
930{
931 struct mmci_host *host = dev_id;
932 u32 status;
933 int ret = 0;
934
935 spin_lock(&host->lock);
936
937 do {
938 struct mmc_command *cmd;
939 struct mmc_data *data;
940
941 status = readl(host->base + MMCISTATUS);
942
943 if (host->singleirq) {
944 if (status & readl(host->base + MMCIMASK1))
945 mmci_pio_irq(irq, dev_id);
946
947 status &= ~MCI_IRQ1MASK;
948 }
949
950 status &= readl(host->base + MMCIMASK0);
951 writel(status, host->base + MMCICLEAR);
952
953 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
954
955 data = host->data;
956 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
957 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
958 mmci_data_irq(host, data, status);
959
960 cmd = host->cmd;
961 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
962 mmci_cmd_irq(host, cmd, status);
963
964 ret = 1;
965 } while (status);
966
967 spin_unlock(&host->lock);
968
969 return IRQ_RETVAL(ret);
970}
971
972static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
973{
974 struct mmci_host *host = mmc_priv(mmc);
975 unsigned long flags;
976
977 WARN_ON(host->mrq != NULL);
978
979 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
980 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
981 mrq->data->blksz);
982 mrq->cmd->error = -EINVAL;
983 mmc_request_done(mmc, mrq);
984 return;
985 }
986
987 spin_lock_irqsave(&host->lock, flags);
988
989 host->mrq = mrq;
990
991 if (mrq->data)
992 mmci_get_next_data(host, mrq->data);
993
994 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
995 mmci_start_data(host, mrq->data);
996
997 mmci_start_command(host, mrq->cmd, 0);
998
999 spin_unlock_irqrestore(&host->lock, flags);
1000}
1001
1002static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1003{
1004 struct mmci_host *host = mmc_priv(mmc);
1005 u32 pwr = 0;
1006 unsigned long flags;
1007 int ret;
1008
1009 switch (ios->power_mode) {
1010 case MMC_POWER_OFF:
1011 if (host->vcc)
1012 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
1013 break;
1014 case MMC_POWER_UP:
1015 if (host->vcc) {
1016 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
1017 if (ret) {
1018 dev_err(mmc_dev(mmc), "unable to set OCR\n");
1019 /*
1020 * The .set_ios() function in the mmc_host_ops
1021 * struct return void, and failing to set the
1022 * power should be rare so we print an error
1023 * and return here.
1024 */
1025 return;
1026 }
1027 }
1028 if (host->plat->vdd_handler)
1029 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
1030 ios->power_mode);
1031 /* The ST version does not have this, fall through to POWER_ON */
1032 if (host->hw_designer != AMBA_VENDOR_ST) {
1033 pwr |= MCI_PWR_UP;
1034 break;
1035 }
1036 case MMC_POWER_ON:
1037 pwr |= MCI_PWR_ON;
1038 break;
1039 }
1040
1041 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1042 if (host->hw_designer != AMBA_VENDOR_ST)
1043 pwr |= MCI_ROD;
1044 else {
1045 /*
1046 * The ST Micro variant use the ROD bit for something
1047 * else and only has OD (Open Drain).
1048 */
1049 pwr |= MCI_OD;
1050 }
1051 }
1052
1053 spin_lock_irqsave(&host->lock, flags);
1054
1055 mmci_set_clkreg(host, ios->clock);
1056
1057 if (host->pwr != pwr) {
1058 host->pwr = pwr;
1059 writel(pwr, host->base + MMCIPOWER);
1060 }
1061
1062 spin_unlock_irqrestore(&host->lock, flags);
1063}
1064
1065static int mmci_get_ro(struct mmc_host *mmc)
1066{
1067 struct mmci_host *host = mmc_priv(mmc);
1068
1069 if (host->gpio_wp == -ENOSYS)
1070 return -ENOSYS;
1071
1072 return gpio_get_value_cansleep(host->gpio_wp);
1073}
1074
1075static int mmci_get_cd(struct mmc_host *mmc)
1076{
1077 struct mmci_host *host = mmc_priv(mmc);
1078 struct mmci_platform_data *plat = host->plat;
1079 unsigned int status;
1080
1081 if (host->gpio_cd == -ENOSYS) {
1082 if (!plat->status)
1083 return 1; /* Assume always present */
1084
1085 status = plat->status(mmc_dev(host->mmc));
1086 } else
1087 status = !!gpio_get_value_cansleep(host->gpio_cd)
1088 ^ plat->cd_invert;
1089
1090 /*
1091 * Use positive logic throughout - status is zero for no card,
1092 * non-zero for card inserted.
1093 */
1094 return status;
1095}
1096
1097static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1098{
1099 struct mmci_host *host = dev_id;
1100
1101 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1102
1103 return IRQ_HANDLED;
1104}
1105
1106static const struct mmc_host_ops mmci_ops = {
1107 .request = mmci_request,
1108 .pre_req = mmci_pre_request,
1109 .post_req = mmci_post_request,
1110 .set_ios = mmci_set_ios,
1111 .get_ro = mmci_get_ro,
1112 .get_cd = mmci_get_cd,
1113};
1114
1115static int __devinit mmci_probe(struct amba_device *dev,
1116 const struct amba_id *id)
1117{
1118 struct mmci_platform_data *plat = dev->dev.platform_data;
1119 struct variant_data *variant = id->data;
1120 struct mmci_host *host;
1121 struct mmc_host *mmc;
1122 int ret;
1123
1124 /* must have platform data */
1125 if (!plat) {
1126 ret = -EINVAL;
1127 goto out;
1128 }
1129
1130 ret = amba_request_regions(dev, DRIVER_NAME);
1131 if (ret)
1132 goto out;
1133
1134 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1135 if (!mmc) {
1136 ret = -ENOMEM;
1137 goto rel_regions;
1138 }
1139
1140 host = mmc_priv(mmc);
1141 host->mmc = mmc;
1142
1143 host->gpio_wp = -ENOSYS;
1144 host->gpio_cd = -ENOSYS;
1145 host->gpio_cd_irq = -1;
1146
1147 host->hw_designer = amba_manf(dev);
1148 host->hw_revision = amba_rev(dev);
1149 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1150 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1151
1152 host->clk = clk_get(&dev->dev, NULL);
1153 if (IS_ERR(host->clk)) {
1154 ret = PTR_ERR(host->clk);
1155 host->clk = NULL;
1156 goto host_free;
1157 }
1158
1159 ret = clk_enable(host->clk);
1160 if (ret)
1161 goto clk_free;
1162
1163 host->plat = plat;
1164 host->variant = variant;
1165 host->mclk = clk_get_rate(host->clk);
1166 /*
1167 * According to the spec, mclk is max 100 MHz,
1168 * so we try to adjust the clock down to this,
1169 * (if possible).
1170 */
1171 if (host->mclk > 100000000) {
1172 ret = clk_set_rate(host->clk, 100000000);
1173 if (ret < 0)
1174 goto clk_disable;
1175 host->mclk = clk_get_rate(host->clk);
1176 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1177 host->mclk);
1178 }
1179 host->phybase = dev->res.start;
1180 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1181 if (!host->base) {
1182 ret = -ENOMEM;
1183 goto clk_disable;
1184 }
1185
1186 mmc->ops = &mmci_ops;
1187 /*
1188 * The ARM and ST versions of the block have slightly different
1189 * clock divider equations which means that the minimum divider
1190 * differs too.
1191 */
1192 if (variant->st_clkdiv)
1193 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1194 else
1195 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1196 /*
1197 * If the platform data supplies a maximum operating
1198 * frequency, this takes precedence. Else, we fall back
1199 * to using the module parameter, which has a (low)
1200 * default value in case it is not specified. Either
1201 * value must not exceed the clock rate into the block,
1202 * of course.
1203 */
1204 if (plat->f_max)
1205 mmc->f_max = min(host->mclk, plat->f_max);
1206 else
1207 mmc->f_max = min(host->mclk, fmax);
1208 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1209
1210#ifdef CONFIG_REGULATOR
1211 /* If we're using the regulator framework, try to fetch a regulator */
1212 host->vcc = regulator_get(&dev->dev, "vmmc");
1213 if (IS_ERR(host->vcc))
1214 host->vcc = NULL;
1215 else {
1216 int mask = mmc_regulator_get_ocrmask(host->vcc);
1217
1218 if (mask < 0)
1219 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
1220 mask);
1221 else {
1222 host->mmc->ocr_avail = (u32) mask;
1223 if (plat->ocr_mask)
1224 dev_warn(&dev->dev,
1225 "Provided ocr_mask/setpower will not be used "
1226 "(using regulator instead)\n");
1227 }
1228 }
1229#endif
1230 /* Fall back to platform data if no regulator is found */
1231 if (host->vcc == NULL)
1232 mmc->ocr_avail = plat->ocr_mask;
1233 mmc->caps = plat->capabilities;
1234
1235 /*
1236 * We can do SGIO
1237 */
1238 mmc->max_segs = NR_SG;
1239
1240 /*
1241 * Since only a certain number of bits are valid in the data length
1242 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1243 * single request.
1244 */
1245 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1246
1247 /*
1248 * Set the maximum segment size. Since we aren't doing DMA
1249 * (yet) we are only limited by the data length register.
1250 */
1251 mmc->max_seg_size = mmc->max_req_size;
1252
1253 /*
1254 * Block size can be up to 2048 bytes, but must be a power of two.
1255 */
1256 mmc->max_blk_size = 2048;
1257
1258 /*
1259 * No limit on the number of blocks transferred.
1260 */
1261 mmc->max_blk_count = mmc->max_req_size;
1262
1263 spin_lock_init(&host->lock);
1264
1265 writel(0, host->base + MMCIMASK0);
1266 writel(0, host->base + MMCIMASK1);
1267 writel(0xfff, host->base + MMCICLEAR);
1268
1269 if (gpio_is_valid(plat->gpio_cd)) {
1270 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1271 if (ret == 0)
1272 ret = gpio_direction_input(plat->gpio_cd);
1273 if (ret == 0)
1274 host->gpio_cd = plat->gpio_cd;
1275 else if (ret != -ENOSYS)
1276 goto err_gpio_cd;
1277
1278 /*
1279 * A gpio pin that will detect cards when inserted and removed
1280 * will most likely want to trigger on the edges if it is
1281 * 0 when ejected and 1 when inserted (or mutatis mutandis
1282 * for the inverted case) so we request triggers on both
1283 * edges.
1284 */
1285 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1286 mmci_cd_irq,
1287 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1288 DRIVER_NAME " (cd)", host);
1289 if (ret >= 0)
1290 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1291 }
1292 if (gpio_is_valid(plat->gpio_wp)) {
1293 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1294 if (ret == 0)
1295 ret = gpio_direction_input(plat->gpio_wp);
1296 if (ret == 0)
1297 host->gpio_wp = plat->gpio_wp;
1298 else if (ret != -ENOSYS)
1299 goto err_gpio_wp;
1300 }
1301
1302 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1303 && host->gpio_cd_irq < 0)
1304 mmc->caps |= MMC_CAP_NEEDS_POLL;
1305
1306 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1307 if (ret)
1308 goto unmap;
1309
1310 if (dev->irq[1] == NO_IRQ)
1311 host->singleirq = true;
1312 else {
1313 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1314 DRIVER_NAME " (pio)", host);
1315 if (ret)
1316 goto irq0_free;
1317 }
1318
1319 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1320
1321 amba_set_drvdata(dev, mmc);
1322
1323 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1324 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1325 amba_rev(dev), (unsigned long long)dev->res.start,
1326 dev->irq[0], dev->irq[1]);
1327
1328 mmci_dma_setup(host);
1329
1330 mmc_add_host(mmc);
1331
1332 return 0;
1333
1334 irq0_free:
1335 free_irq(dev->irq[0], host);
1336 unmap:
1337 if (host->gpio_wp != -ENOSYS)
1338 gpio_free(host->gpio_wp);
1339 err_gpio_wp:
1340 if (host->gpio_cd_irq >= 0)
1341 free_irq(host->gpio_cd_irq, host);
1342 if (host->gpio_cd != -ENOSYS)
1343 gpio_free(host->gpio_cd);
1344 err_gpio_cd:
1345 iounmap(host->base);
1346 clk_disable:
1347 clk_disable(host->clk);
1348 clk_free:
1349 clk_put(host->clk);
1350 host_free:
1351 mmc_free_host(mmc);
1352 rel_regions:
1353 amba_release_regions(dev);
1354 out:
1355 return ret;
1356}
1357
1358static int __devexit mmci_remove(struct amba_device *dev)
1359{
1360 struct mmc_host *mmc = amba_get_drvdata(dev);
1361
1362 amba_set_drvdata(dev, NULL);
1363
1364 if (mmc) {
1365 struct mmci_host *host = mmc_priv(mmc);
1366
1367 mmc_remove_host(mmc);
1368
1369 writel(0, host->base + MMCIMASK0);
1370 writel(0, host->base + MMCIMASK1);
1371
1372 writel(0, host->base + MMCICOMMAND);
1373 writel(0, host->base + MMCIDATACTRL);
1374
1375 mmci_dma_release(host);
1376 free_irq(dev->irq[0], host);
1377 if (!host->singleirq)
1378 free_irq(dev->irq[1], host);
1379
1380 if (host->gpio_wp != -ENOSYS)
1381 gpio_free(host->gpio_wp);
1382 if (host->gpio_cd_irq >= 0)
1383 free_irq(host->gpio_cd_irq, host);
1384 if (host->gpio_cd != -ENOSYS)
1385 gpio_free(host->gpio_cd);
1386
1387 iounmap(host->base);
1388 clk_disable(host->clk);
1389 clk_put(host->clk);
1390
1391 if (host->vcc)
1392 mmc_regulator_set_ocr(mmc, host->vcc, 0);
1393 regulator_put(host->vcc);
1394
1395 mmc_free_host(mmc);
1396
1397 amba_release_regions(dev);
1398 }
1399
1400 return 0;
1401}
1402
1403#ifdef CONFIG_PM
1404static int mmci_suspend(struct amba_device *dev, pm_message_t state)
1405{
1406 struct mmc_host *mmc = amba_get_drvdata(dev);
1407 int ret = 0;
1408
1409 if (mmc) {
1410 struct mmci_host *host = mmc_priv(mmc);
1411
1412 ret = mmc_suspend_host(mmc);
1413 if (ret == 0)
1414 writel(0, host->base + MMCIMASK0);
1415 }
1416
1417 return ret;
1418}
1419
1420static int mmci_resume(struct amba_device *dev)
1421{
1422 struct mmc_host *mmc = amba_get_drvdata(dev);
1423 int ret = 0;
1424
1425 if (mmc) {
1426 struct mmci_host *host = mmc_priv(mmc);
1427
1428 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1429
1430 ret = mmc_resume_host(mmc);
1431 }
1432
1433 return ret;
1434}
1435#else
1436#define mmci_suspend NULL
1437#define mmci_resume NULL
1438#endif
1439
1440static struct amba_id mmci_ids[] = {
1441 {
1442 .id = 0x00041180,
1443 .mask = 0xff0fffff,
1444 .data = &variant_arm,
1445 },
1446 {
1447 .id = 0x01041180,
1448 .mask = 0xff0fffff,
1449 .data = &variant_arm_extended_fifo,
1450 },
1451 {
1452 .id = 0x00041181,
1453 .mask = 0x000fffff,
1454 .data = &variant_arm,
1455 },
1456 /* ST Micro variants */
1457 {
1458 .id = 0x00180180,
1459 .mask = 0x00ffffff,
1460 .data = &variant_u300,
1461 },
1462 {
1463 .id = 0x00280180,
1464 .mask = 0x00ffffff,
1465 .data = &variant_u300,
1466 },
1467 {
1468 .id = 0x00480180,
1469 .mask = 0xf0ffffff,
1470 .data = &variant_ux500,
1471 },
1472 {
1473 .id = 0x10480180,
1474 .mask = 0xf0ffffff,
1475 .data = &variant_ux500v2,
1476 },
1477 { 0, 0 },
1478};
1479
1480static struct amba_driver mmci_driver = {
1481 .drv = {
1482 .name = DRIVER_NAME,
1483 },
1484 .probe = mmci_probe,
1485 .remove = __devexit_p(mmci_remove),
1486 .suspend = mmci_suspend,
1487 .resume = mmci_resume,
1488 .id_table = mmci_ids,
1489};
1490
1491static int __init mmci_init(void)
1492{
1493 return amba_driver_register(&mmci_driver);
1494}
1495
1496static void __exit mmci_exit(void)
1497{
1498 amba_driver_unregister(&mmci_driver);
1499}
1500
1501module_init(mmci_init);
1502module_exit(mmci_exit);
1503module_param(fmax, uint, 0444);
1504
1505MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1506MODULE_LICENSE("GPL");