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1#include <linux/init.h>
2#include <linux/kernel.h>
3
4#include <linux/string.h>
5#include <linux/bitops.h>
6#include <linux/smp.h>
7#include <linux/sched.h>
8#include <linux/thread_info.h>
9#include <linux/module.h>
10#include <linux/uaccess.h>
11
12#include <asm/processor.h>
13#include <asm/pgtable.h>
14#include <asm/msr.h>
15#include <asm/bugs.h>
16#include <asm/cpu.h>
17
18#ifdef CONFIG_X86_64
19#include <linux/topology.h>
20#include <asm/numa_64.h>
21#endif
22
23#include "cpu.h"
24
25#ifdef CONFIG_X86_LOCAL_APIC
26#include <asm/mpspec.h>
27#include <asm/apic.h>
28#endif
29
30static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
31{
32 u64 misc_enable;
33
34 /* Unmask CPUID levels if masked: */
35 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
36 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
37
38 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
39 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
40 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
41 c->cpuid_level = cpuid_eax(0);
42 get_cpu_cap(c);
43 }
44 }
45
46 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
47 (c->x86 == 0x6 && c->x86_model >= 0x0e))
48 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
49
50 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
51 unsigned lower_word;
52
53 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
54 /* Required by the SDM */
55 sync_core();
56 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
57 }
58
59 /*
60 * Atom erratum AAE44/AAF40/AAG38/AAH41:
61 *
62 * A race condition between speculative fetches and invalidating
63 * a large page. This is worked around in microcode, but we
64 * need the microcode to have already been loaded... so if it is
65 * not, recommend a BIOS update and disable large pages.
66 */
67 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
68 c->microcode < 0x20e) {
69 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
70 clear_cpu_cap(c, X86_FEATURE_PSE);
71 }
72
73#ifdef CONFIG_X86_64
74 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
75#else
76 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
77 if (c->x86 == 15 && c->x86_cache_alignment == 64)
78 c->x86_cache_alignment = 128;
79#endif
80
81 /* CPUID workaround for 0F33/0F34 CPU */
82 if (c->x86 == 0xF && c->x86_model == 0x3
83 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
84 c->x86_phys_bits = 36;
85
86 /*
87 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
88 * with P/T states and does not stop in deep C-states.
89 *
90 * It is also reliable across cores and sockets. (but not across
91 * cabinets - we turn it off in that case explicitly.)
92 */
93 if (c->x86_power & (1 << 8)) {
94 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
95 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
96 if (!check_tsc_unstable())
97 sched_clock_stable = 1;
98 }
99
100 /*
101 * There is a known erratum on Pentium III and Core Solo
102 * and Core Duo CPUs.
103 * " Page with PAT set to WC while associated MTRR is UC
104 * may consolidate to UC "
105 * Because of this erratum, it is better to stick with
106 * setting WC in MTRR rather than using PAT on these CPUs.
107 *
108 * Enable PAT WC only on P4, Core 2 or later CPUs.
109 */
110 if (c->x86 == 6 && c->x86_model < 15)
111 clear_cpu_cap(c, X86_FEATURE_PAT);
112
113#ifdef CONFIG_KMEMCHECK
114 /*
115 * P4s have a "fast strings" feature which causes single-
116 * stepping REP instructions to only generate a #DB on
117 * cache-line boundaries.
118 *
119 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
120 * (model 2) with the same problem.
121 */
122 if (c->x86 == 15) {
123 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
124
125 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
126 printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
127
128 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
129 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
130 }
131 }
132#endif
133
134 /*
135 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
136 * clear the fast string and enhanced fast string CPU capabilities.
137 */
138 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
139 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
140 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
141 printk(KERN_INFO "Disabled fast string operations\n");
142 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
143 setup_clear_cpu_cap(X86_FEATURE_ERMS);
144 }
145 }
146}
147
148#ifdef CONFIG_X86_32
149/*
150 * Early probe support logic for ppro memory erratum #50
151 *
152 * This is called before we do cpu ident work
153 */
154
155int __cpuinit ppro_with_ram_bug(void)
156{
157 /* Uses data from early_cpu_detect now */
158 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
159 boot_cpu_data.x86 == 6 &&
160 boot_cpu_data.x86_model == 1 &&
161 boot_cpu_data.x86_mask < 8) {
162 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
163 return 1;
164 }
165 return 0;
166}
167
168#ifdef CONFIG_X86_F00F_BUG
169static void __cpuinit trap_init_f00f_bug(void)
170{
171 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
172
173 /*
174 * Update the IDT descriptor and reload the IDT so that
175 * it uses the read-only mapped virtual address.
176 */
177 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
178 load_idt(&idt_descr);
179}
180#endif
181
182static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
183{
184 /* calling is from identify_secondary_cpu() ? */
185 if (!c->cpu_index)
186 return;
187
188 /*
189 * Mask B, Pentium, but not Pentium MMX
190 */
191 if (c->x86 == 5 &&
192 c->x86_mask >= 1 && c->x86_mask <= 4 &&
193 c->x86_model <= 3) {
194 /*
195 * Remember we have B step Pentia with bugs
196 */
197 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
198 "with B stepping processors.\n");
199 }
200}
201
202static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
203{
204 unsigned long lo, hi;
205
206#ifdef CONFIG_X86_F00F_BUG
207 /*
208 * All current models of Pentium and Pentium with MMX technology CPUs
209 * have the F0 0F bug, which lets nonprivileged users lock up the
210 * system.
211 * Note that the workaround only should be initialized once...
212 */
213 c->f00f_bug = 0;
214 if (!paravirt_enabled() && c->x86 == 5) {
215 static int f00f_workaround_enabled;
216
217 c->f00f_bug = 1;
218 if (!f00f_workaround_enabled) {
219 trap_init_f00f_bug();
220 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
221 f00f_workaround_enabled = 1;
222 }
223 }
224#endif
225
226 /*
227 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
228 * model 3 mask 3
229 */
230 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
231 clear_cpu_cap(c, X86_FEATURE_SEP);
232
233 /*
234 * P4 Xeon errata 037 workaround.
235 * Hardware prefetcher may cause stale data to be loaded into the cache.
236 */
237 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
238 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
239 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
240 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
241 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
242 lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
243 wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
244 }
245 }
246
247 /*
248 * See if we have a good local APIC by checking for buggy Pentia,
249 * i.e. all B steppings and the C2 stepping of P54C when using their
250 * integrated APIC (see 11AP erratum in "Pentium Processor
251 * Specification Update").
252 */
253 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
254 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
255 set_cpu_cap(c, X86_FEATURE_11AP);
256
257
258#ifdef CONFIG_X86_INTEL_USERCOPY
259 /*
260 * Set up the preferred alignment for movsl bulk memory moves
261 */
262 switch (c->x86) {
263 case 4: /* 486: untested */
264 break;
265 case 5: /* Old Pentia: untested */
266 break;
267 case 6: /* PII/PIII only like movsl with 8-byte alignment */
268 movsl_mask.mask = 7;
269 break;
270 case 15: /* P4 is OK down to 8-byte alignment */
271 movsl_mask.mask = 7;
272 break;
273 }
274#endif
275
276#ifdef CONFIG_X86_NUMAQ
277 numaq_tsc_disable();
278#endif
279
280 intel_smp_check(c);
281}
282#else
283static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
284{
285}
286#endif
287
288static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
289{
290#ifdef CONFIG_NUMA
291 unsigned node;
292 int cpu = smp_processor_id();
293
294 /* Don't do the funky fallback heuristics the AMD version employs
295 for now. */
296 node = numa_cpu_node(cpu);
297 if (node == NUMA_NO_NODE || !node_online(node)) {
298 /* reuse the value from init_cpu_to_node() */
299 node = cpu_to_node(cpu);
300 }
301 numa_set_node(cpu, node);
302#endif
303}
304
305/*
306 * find out the number of processor cores on the die
307 */
308static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
309{
310 unsigned int eax, ebx, ecx, edx;
311
312 if (c->cpuid_level < 4)
313 return 1;
314
315 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
316 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
317 if (eax & 0x1f)
318 return (eax >> 26) + 1;
319 else
320 return 1;
321}
322
323static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
324{
325 /* Intel VMX MSR indicated features */
326#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
327#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
328#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
329#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
330#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
331#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
332
333 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
334
335 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
336 clear_cpu_cap(c, X86_FEATURE_VNMI);
337 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
338 clear_cpu_cap(c, X86_FEATURE_EPT);
339 clear_cpu_cap(c, X86_FEATURE_VPID);
340
341 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
342 msr_ctl = vmx_msr_high | vmx_msr_low;
343 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
344 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
345 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
346 set_cpu_cap(c, X86_FEATURE_VNMI);
347 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
348 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
349 vmx_msr_low, vmx_msr_high);
350 msr_ctl2 = vmx_msr_high | vmx_msr_low;
351 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
352 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
353 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
354 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
355 set_cpu_cap(c, X86_FEATURE_EPT);
356 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
357 set_cpu_cap(c, X86_FEATURE_VPID);
358 }
359}
360
361static void __cpuinit init_intel(struct cpuinfo_x86 *c)
362{
363 unsigned int l2 = 0;
364
365 early_init_intel(c);
366
367 intel_workarounds(c);
368
369 /*
370 * Detect the extended topology information if available. This
371 * will reinitialise the initial_apicid which will be used
372 * in init_intel_cacheinfo()
373 */
374 detect_extended_topology(c);
375
376 l2 = init_intel_cacheinfo(c);
377 if (c->cpuid_level > 9) {
378 unsigned eax = cpuid_eax(10);
379 /* Check for version and the number of counters */
380 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
381 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
382 }
383
384 if (cpu_has_xmm2)
385 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
386 if (cpu_has_ds) {
387 unsigned int l1;
388 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
389 if (!(l1 & (1<<11)))
390 set_cpu_cap(c, X86_FEATURE_BTS);
391 if (!(l1 & (1<<12)))
392 set_cpu_cap(c, X86_FEATURE_PEBS);
393 }
394
395 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
396 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
397
398#ifdef CONFIG_X86_64
399 if (c->x86 == 15)
400 c->x86_cache_alignment = c->x86_clflush_size * 2;
401 if (c->x86 == 6)
402 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
403#else
404 /*
405 * Names for the Pentium II/Celeron processors
406 * detectable only by also checking the cache size.
407 * Dixon is NOT a Celeron.
408 */
409 if (c->x86 == 6) {
410 char *p = NULL;
411
412 switch (c->x86_model) {
413 case 5:
414 if (l2 == 0)
415 p = "Celeron (Covington)";
416 else if (l2 == 256)
417 p = "Mobile Pentium II (Dixon)";
418 break;
419
420 case 6:
421 if (l2 == 128)
422 p = "Celeron (Mendocino)";
423 else if (c->x86_mask == 0 || c->x86_mask == 5)
424 p = "Celeron-A";
425 break;
426
427 case 8:
428 if (l2 == 128)
429 p = "Celeron (Coppermine)";
430 break;
431 }
432
433 if (p)
434 strcpy(c->x86_model_id, p);
435 }
436
437 if (c->x86 == 15)
438 set_cpu_cap(c, X86_FEATURE_P4);
439 if (c->x86 == 6)
440 set_cpu_cap(c, X86_FEATURE_P3);
441#endif
442
443 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
444 /*
445 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
446 * detection.
447 */
448 c->x86_max_cores = intel_num_cpu_cores(c);
449#ifdef CONFIG_X86_32
450 detect_ht(c);
451#endif
452 }
453
454 /* Work around errata */
455 srat_detect_node(c);
456
457 if (cpu_has(c, X86_FEATURE_VMX))
458 detect_vmx_virtcap(c);
459
460 /*
461 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
462 * x86_energy_perf_policy(8) is available to change it at run-time
463 */
464 if (cpu_has(c, X86_FEATURE_EPB)) {
465 u64 epb;
466
467 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
468 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
469 printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
470 " Set to 'normal', was 'performance'\n"
471 "ENERGY_PERF_BIAS: View and update with"
472 " x86_energy_perf_policy(8)\n");
473 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
474 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
475 }
476 }
477}
478
479#ifdef CONFIG_X86_32
480static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
481{
482 /*
483 * Intel PIII Tualatin. This comes in two flavours.
484 * One has 256kb of cache, the other 512. We have no way
485 * to determine which, so we use a boottime override
486 * for the 512kb model, and assume 256 otherwise.
487 */
488 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
489 size = 256;
490 return size;
491}
492#endif
493
494static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
495 .c_vendor = "Intel",
496 .c_ident = { "GenuineIntel" },
497#ifdef CONFIG_X86_32
498 .c_models = {
499 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
500 {
501 [0] = "486 DX-25/33",
502 [1] = "486 DX-50",
503 [2] = "486 SX",
504 [3] = "486 DX/2",
505 [4] = "486 SL",
506 [5] = "486 SX/2",
507 [7] = "486 DX/2-WB",
508 [8] = "486 DX/4",
509 [9] = "486 DX/4-WB"
510 }
511 },
512 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
513 {
514 [0] = "Pentium 60/66 A-step",
515 [1] = "Pentium 60/66",
516 [2] = "Pentium 75 - 200",
517 [3] = "OverDrive PODP5V83",
518 [4] = "Pentium MMX",
519 [7] = "Mobile Pentium 75 - 200",
520 [8] = "Mobile Pentium MMX"
521 }
522 },
523 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
524 {
525 [0] = "Pentium Pro A-step",
526 [1] = "Pentium Pro",
527 [3] = "Pentium II (Klamath)",
528 [4] = "Pentium II (Deschutes)",
529 [5] = "Pentium II (Deschutes)",
530 [6] = "Mobile Pentium II",
531 [7] = "Pentium III (Katmai)",
532 [8] = "Pentium III (Coppermine)",
533 [10] = "Pentium III (Cascades)",
534 [11] = "Pentium III (Tualatin)",
535 }
536 },
537 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
538 {
539 [0] = "Pentium 4 (Unknown)",
540 [1] = "Pentium 4 (Willamette)",
541 [2] = "Pentium 4 (Northwood)",
542 [4] = "Pentium 4 (Foster)",
543 [5] = "Pentium 4 (Foster)",
544 }
545 },
546 },
547 .c_size_cache = intel_size_cache,
548#endif
549 .c_early_init = early_init_intel,
550 .c_init = init_intel,
551 .c_x86_vendor = X86_VENDOR_INTEL,
552};
553
554cpu_dev_register(intel_cpu_dev);
555
1#include <linux/init.h>
2#include <linux/kernel.h>
3
4#include <linux/string.h>
5#include <linux/bitops.h>
6#include <linux/smp.h>
7#include <linux/sched.h>
8#include <linux/thread_info.h>
9#include <linux/module.h>
10#include <linux/uaccess.h>
11
12#include <asm/processor.h>
13#include <asm/pgtable.h>
14#include <asm/msr.h>
15#include <asm/bugs.h>
16#include <asm/cpu.h>
17
18#ifdef CONFIG_X86_64
19#include <linux/topology.h>
20#include <asm/numa_64.h>
21#endif
22
23#include "cpu.h"
24
25#ifdef CONFIG_X86_LOCAL_APIC
26#include <asm/mpspec.h>
27#include <asm/apic.h>
28#endif
29
30static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
31{
32 u64 misc_enable;
33
34 /* Unmask CPUID levels if masked: */
35 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
36 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
37
38 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
39 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
40 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
41 c->cpuid_level = cpuid_eax(0);
42 get_cpu_cap(c);
43 }
44 }
45
46 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
47 (c->x86 == 0x6 && c->x86_model >= 0x0e))
48 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
49
50 /*
51 * Atom erratum AAE44/AAF40/AAG38/AAH41:
52 *
53 * A race condition between speculative fetches and invalidating
54 * a large page. This is worked around in microcode, but we
55 * need the microcode to have already been loaded... so if it is
56 * not, recommend a BIOS update and disable large pages.
57 */
58 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
59 u32 ucode, junk;
60
61 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
62 sync_core();
63 rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
64
65 if (ucode < 0x20e) {
66 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
67 clear_cpu_cap(c, X86_FEATURE_PSE);
68 }
69 }
70
71#ifdef CONFIG_X86_64
72 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
73#else
74 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
75 if (c->x86 == 15 && c->x86_cache_alignment == 64)
76 c->x86_cache_alignment = 128;
77#endif
78
79 /* CPUID workaround for 0F33/0F34 CPU */
80 if (c->x86 == 0xF && c->x86_model == 0x3
81 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
82 c->x86_phys_bits = 36;
83
84 /*
85 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
86 * with P/T states and does not stop in deep C-states.
87 *
88 * It is also reliable across cores and sockets. (but not across
89 * cabinets - we turn it off in that case explicitly.)
90 */
91 if (c->x86_power & (1 << 8)) {
92 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
93 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
94 if (!check_tsc_unstable())
95 sched_clock_stable = 1;
96 }
97
98 /*
99 * There is a known erratum on Pentium III and Core Solo
100 * and Core Duo CPUs.
101 * " Page with PAT set to WC while associated MTRR is UC
102 * may consolidate to UC "
103 * Because of this erratum, it is better to stick with
104 * setting WC in MTRR rather than using PAT on these CPUs.
105 *
106 * Enable PAT WC only on P4, Core 2 or later CPUs.
107 */
108 if (c->x86 == 6 && c->x86_model < 15)
109 clear_cpu_cap(c, X86_FEATURE_PAT);
110
111#ifdef CONFIG_KMEMCHECK
112 /*
113 * P4s have a "fast strings" feature which causes single-
114 * stepping REP instructions to only generate a #DB on
115 * cache-line boundaries.
116 *
117 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
118 * (model 2) with the same problem.
119 */
120 if (c->x86 == 15) {
121 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
122
123 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
124 printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
125
126 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
127 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
128 }
129 }
130#endif
131
132 /*
133 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
134 * clear the fast string and enhanced fast string CPU capabilities.
135 */
136 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
137 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
138 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
139 printk(KERN_INFO "Disabled fast string operations\n");
140 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
141 setup_clear_cpu_cap(X86_FEATURE_ERMS);
142 }
143 }
144}
145
146#ifdef CONFIG_X86_32
147/*
148 * Early probe support logic for ppro memory erratum #50
149 *
150 * This is called before we do cpu ident work
151 */
152
153int __cpuinit ppro_with_ram_bug(void)
154{
155 /* Uses data from early_cpu_detect now */
156 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
157 boot_cpu_data.x86 == 6 &&
158 boot_cpu_data.x86_model == 1 &&
159 boot_cpu_data.x86_mask < 8) {
160 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
161 return 1;
162 }
163 return 0;
164}
165
166#ifdef CONFIG_X86_F00F_BUG
167static void __cpuinit trap_init_f00f_bug(void)
168{
169 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
170
171 /*
172 * Update the IDT descriptor and reload the IDT so that
173 * it uses the read-only mapped virtual address.
174 */
175 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
176 load_idt(&idt_descr);
177}
178#endif
179
180static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
181{
182#ifdef CONFIG_SMP
183 /* calling is from identify_secondary_cpu() ? */
184 if (!c->cpu_index)
185 return;
186
187 /*
188 * Mask B, Pentium, but not Pentium MMX
189 */
190 if (c->x86 == 5 &&
191 c->x86_mask >= 1 && c->x86_mask <= 4 &&
192 c->x86_model <= 3) {
193 /*
194 * Remember we have B step Pentia with bugs
195 */
196 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
197 "with B stepping processors.\n");
198 }
199#endif
200}
201
202static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
203{
204 unsigned long lo, hi;
205
206#ifdef CONFIG_X86_F00F_BUG
207 /*
208 * All current models of Pentium and Pentium with MMX technology CPUs
209 * have the F0 0F bug, which lets nonprivileged users lock up the
210 * system.
211 * Note that the workaround only should be initialized once...
212 */
213 c->f00f_bug = 0;
214 if (!paravirt_enabled() && c->x86 == 5) {
215 static int f00f_workaround_enabled;
216
217 c->f00f_bug = 1;
218 if (!f00f_workaround_enabled) {
219 trap_init_f00f_bug();
220 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
221 f00f_workaround_enabled = 1;
222 }
223 }
224#endif
225
226 /*
227 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
228 * model 3 mask 3
229 */
230 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
231 clear_cpu_cap(c, X86_FEATURE_SEP);
232
233 /*
234 * P4 Xeon errata 037 workaround.
235 * Hardware prefetcher may cause stale data to be loaded into the cache.
236 */
237 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
238 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
239 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
240 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
241 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
242 lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
243 wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
244 }
245 }
246
247 /*
248 * See if we have a good local APIC by checking for buggy Pentia,
249 * i.e. all B steppings and the C2 stepping of P54C when using their
250 * integrated APIC (see 11AP erratum in "Pentium Processor
251 * Specification Update").
252 */
253 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
254 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
255 set_cpu_cap(c, X86_FEATURE_11AP);
256
257
258#ifdef CONFIG_X86_INTEL_USERCOPY
259 /*
260 * Set up the preferred alignment for movsl bulk memory moves
261 */
262 switch (c->x86) {
263 case 4: /* 486: untested */
264 break;
265 case 5: /* Old Pentia: untested */
266 break;
267 case 6: /* PII/PIII only like movsl with 8-byte alignment */
268 movsl_mask.mask = 7;
269 break;
270 case 15: /* P4 is OK down to 8-byte alignment */
271 movsl_mask.mask = 7;
272 break;
273 }
274#endif
275
276#ifdef CONFIG_X86_NUMAQ
277 numaq_tsc_disable();
278#endif
279
280 intel_smp_check(c);
281}
282#else
283static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
284{
285}
286#endif
287
288static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
289{
290#ifdef CONFIG_NUMA
291 unsigned node;
292 int cpu = smp_processor_id();
293
294 /* Don't do the funky fallback heuristics the AMD version employs
295 for now. */
296 node = numa_cpu_node(cpu);
297 if (node == NUMA_NO_NODE || !node_online(node)) {
298 /* reuse the value from init_cpu_to_node() */
299 node = cpu_to_node(cpu);
300 }
301 numa_set_node(cpu, node);
302#endif
303}
304
305/*
306 * find out the number of processor cores on the die
307 */
308static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
309{
310 unsigned int eax, ebx, ecx, edx;
311
312 if (c->cpuid_level < 4)
313 return 1;
314
315 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
316 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
317 if (eax & 0x1f)
318 return (eax >> 26) + 1;
319 else
320 return 1;
321}
322
323static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
324{
325 /* Intel VMX MSR indicated features */
326#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
327#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
328#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
329#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
330#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
331#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
332
333 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
334
335 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
336 clear_cpu_cap(c, X86_FEATURE_VNMI);
337 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
338 clear_cpu_cap(c, X86_FEATURE_EPT);
339 clear_cpu_cap(c, X86_FEATURE_VPID);
340
341 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
342 msr_ctl = vmx_msr_high | vmx_msr_low;
343 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
344 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
345 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
346 set_cpu_cap(c, X86_FEATURE_VNMI);
347 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
348 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
349 vmx_msr_low, vmx_msr_high);
350 msr_ctl2 = vmx_msr_high | vmx_msr_low;
351 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
352 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
353 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
354 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
355 set_cpu_cap(c, X86_FEATURE_EPT);
356 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
357 set_cpu_cap(c, X86_FEATURE_VPID);
358 }
359}
360
361static void __cpuinit init_intel(struct cpuinfo_x86 *c)
362{
363 unsigned int l2 = 0;
364
365 early_init_intel(c);
366
367 intel_workarounds(c);
368
369 /*
370 * Detect the extended topology information if available. This
371 * will reinitialise the initial_apicid which will be used
372 * in init_intel_cacheinfo()
373 */
374 detect_extended_topology(c);
375
376 l2 = init_intel_cacheinfo(c);
377 if (c->cpuid_level > 9) {
378 unsigned eax = cpuid_eax(10);
379 /* Check for version and the number of counters */
380 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
381 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
382 }
383
384 if (cpu_has_xmm2)
385 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
386 if (cpu_has_ds) {
387 unsigned int l1;
388 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
389 if (!(l1 & (1<<11)))
390 set_cpu_cap(c, X86_FEATURE_BTS);
391 if (!(l1 & (1<<12)))
392 set_cpu_cap(c, X86_FEATURE_PEBS);
393 }
394
395 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
396 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
397
398#ifdef CONFIG_X86_64
399 if (c->x86 == 15)
400 c->x86_cache_alignment = c->x86_clflush_size * 2;
401 if (c->x86 == 6)
402 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
403#else
404 /*
405 * Names for the Pentium II/Celeron processors
406 * detectable only by also checking the cache size.
407 * Dixon is NOT a Celeron.
408 */
409 if (c->x86 == 6) {
410 char *p = NULL;
411
412 switch (c->x86_model) {
413 case 5:
414 if (l2 == 0)
415 p = "Celeron (Covington)";
416 else if (l2 == 256)
417 p = "Mobile Pentium II (Dixon)";
418 break;
419
420 case 6:
421 if (l2 == 128)
422 p = "Celeron (Mendocino)";
423 else if (c->x86_mask == 0 || c->x86_mask == 5)
424 p = "Celeron-A";
425 break;
426
427 case 8:
428 if (l2 == 128)
429 p = "Celeron (Coppermine)";
430 break;
431 }
432
433 if (p)
434 strcpy(c->x86_model_id, p);
435 }
436
437 if (c->x86 == 15)
438 set_cpu_cap(c, X86_FEATURE_P4);
439 if (c->x86 == 6)
440 set_cpu_cap(c, X86_FEATURE_P3);
441#endif
442
443 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
444 /*
445 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
446 * detection.
447 */
448 c->x86_max_cores = intel_num_cpu_cores(c);
449#ifdef CONFIG_X86_32
450 detect_ht(c);
451#endif
452 }
453
454 /* Work around errata */
455 srat_detect_node(c);
456
457 if (cpu_has(c, X86_FEATURE_VMX))
458 detect_vmx_virtcap(c);
459
460 /*
461 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
462 * x86_energy_perf_policy(8) is available to change it at run-time
463 */
464 if (cpu_has(c, X86_FEATURE_EPB)) {
465 u64 epb;
466
467 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
468 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
469 printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
470 " Set to 'normal', was 'performance'\n"
471 "ENERGY_PERF_BIAS: View and update with"
472 " x86_energy_perf_policy(8)\n");
473 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
474 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
475 }
476 }
477}
478
479#ifdef CONFIG_X86_32
480static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
481{
482 /*
483 * Intel PIII Tualatin. This comes in two flavours.
484 * One has 256kb of cache, the other 512. We have no way
485 * to determine which, so we use a boottime override
486 * for the 512kb model, and assume 256 otherwise.
487 */
488 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
489 size = 256;
490 return size;
491}
492#endif
493
494static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
495 .c_vendor = "Intel",
496 .c_ident = { "GenuineIntel" },
497#ifdef CONFIG_X86_32
498 .c_models = {
499 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
500 {
501 [0] = "486 DX-25/33",
502 [1] = "486 DX-50",
503 [2] = "486 SX",
504 [3] = "486 DX/2",
505 [4] = "486 SL",
506 [5] = "486 SX/2",
507 [7] = "486 DX/2-WB",
508 [8] = "486 DX/4",
509 [9] = "486 DX/4-WB"
510 }
511 },
512 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
513 {
514 [0] = "Pentium 60/66 A-step",
515 [1] = "Pentium 60/66",
516 [2] = "Pentium 75 - 200",
517 [3] = "OverDrive PODP5V83",
518 [4] = "Pentium MMX",
519 [7] = "Mobile Pentium 75 - 200",
520 [8] = "Mobile Pentium MMX"
521 }
522 },
523 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
524 {
525 [0] = "Pentium Pro A-step",
526 [1] = "Pentium Pro",
527 [3] = "Pentium II (Klamath)",
528 [4] = "Pentium II (Deschutes)",
529 [5] = "Pentium II (Deschutes)",
530 [6] = "Mobile Pentium II",
531 [7] = "Pentium III (Katmai)",
532 [8] = "Pentium III (Coppermine)",
533 [10] = "Pentium III (Cascades)",
534 [11] = "Pentium III (Tualatin)",
535 }
536 },
537 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
538 {
539 [0] = "Pentium 4 (Unknown)",
540 [1] = "Pentium 4 (Willamette)",
541 [2] = "Pentium 4 (Northwood)",
542 [4] = "Pentium 4 (Foster)",
543 [5] = "Pentium 4 (Foster)",
544 }
545 },
546 },
547 .c_size_cache = intel_size_cache,
548#endif
549 .c_early_init = early_init_intel,
550 .c_init = init_intel,
551 .c_x86_vendor = X86_VENDOR_INTEL,
552};
553
554cpu_dev_register(intel_cpu_dev);
555