1/*
  2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
  3 *
  4 * Copyright (C) 2009-2011 Nokia Corporation
  5 * Copyright (C) 2012 Texas Instruments, Inc.
  6 * Paul Walmsley
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License version 2 as
 10 * published by the Free Software Foundation.
 11 *
 12 * XXX handle crossbar/shared link difference for L3?
 13 * XXX these should be marked initdata for multi-OMAP kernels
 14 */
 15#include <plat/omap_hwmod.h>
 16#include <mach/irqs.h>
 17#include <plat/cpu.h>
 18#include <plat/dma.h>
 19#include <plat/serial.h>
 20#include <plat/i2c.h>
 21#include <plat/gpio.h>
 22#include <plat/mcbsp.h>
 23#include <plat/mcspi.h>
 24#include <plat/dmtimer.h>
 25#include <plat/mmc.h>
 26#include <plat/l3_2xxx.h>
 27
 28#include "omap_hwmod_common_data.h"
 29
 30#include "prm-regbits-24xx.h"
 31#include "cm-regbits-24xx.h"
 32#include "wd_timer.h"
 33
 34/*
 35 * OMAP2430 hardware module integration data
 36 *
 37 * All of the data in this section should be autogeneratable from the
 38 * TI hardware database or other technical documentation.  Data that
 39 * is driver-specific or driver-kernel integration-specific belongs
 40 * elsewhere.
 41 */
 42
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 43/*
 44 * IP blocks
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 45 */
 46
 47/* IVA2 (IVA2) */
 48static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
 49	{ .name = "logic", .rst_shift = 0 },
 50	{ .name = "mmu", .rst_shift = 1 },
 
 
 51};
 52
 
 
 
 
 
 
 
 
 53static struct omap_hwmod omap2430_iva_hwmod = {
 54	.name		= "iva",
 55	.class		= &iva_hwmod_class,
 56	.clkdm_name	= "dsp_clkdm",
 57	.rst_lines	= omap2430_iva_resets,
 58	.rst_lines_cnt	= ARRAY_SIZE(omap2430_iva_resets),
 59	.main_clk	= "dsp_fck",
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 60};
 61
 62/* I2C common */
 63static struct omap_hwmod_class_sysconfig i2c_sysc = {
 64	.rev_offs	= 0x00,
 65	.sysc_offs	= 0x20,
 66	.syss_offs	= 0x10,
 67	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 68			   SYSS_HAS_RESET_STATUS),
 69	.sysc_fields	= &omap_hwmod_sysc_type1,
 70};
 71
 72static struct omap_hwmod_class i2c_class = {
 73	.name		= "i2c",
 74	.sysc		= &i2c_sysc,
 75	.rev		= OMAP_I2C_IP_VERSION_1,
 76	.reset		= &omap_i2c_reset,
 77};
 78
 79static struct omap_i2c_dev_attr i2c_dev_attr = {
 80	.fifo_depth	= 8, /* bytes */
 81	.flags		= OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 82			  OMAP_I2C_FLAG_BUS_SHIFT_2 |
 83			  OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
 84};
 85
 86/* I2C1 */
 
 
 
 
 
 87static struct omap_hwmod omap2430_i2c1_hwmod = {
 88	.name		= "i2c1",
 89	.flags		= HWMOD_16BIT_REG,
 90	.mpu_irqs	= omap2_i2c1_mpu_irqs,
 91	.sdma_reqs	= omap2_i2c1_sdma_reqs,
 92	.main_clk	= "i2chs1_fck",
 93	.prcm		= {
 94		.omap2 = {
 95			/*
 96			 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
 97			 * I2CHS IP's do not follow the usual pattern.
 98			 * prcm_reg_id alone cannot be used to program
 99			 * the iclk and fclk. Needs to be handled using
100			 * additional flags when clk handling is moved
101			 * to hwmod framework.
102			 */
103			.module_offs = CORE_MOD,
104			.prcm_reg_id = 1,
105			.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
106			.idlest_reg_id = 1,
107			.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
108		},
109	},
 
 
110	.class		= &i2c_class,
111	.dev_attr	= &i2c_dev_attr,
 
112};
113
114/* I2C2 */
 
 
 
 
 
115static struct omap_hwmod omap2430_i2c2_hwmod = {
116	.name		= "i2c2",
117	.flags		= HWMOD_16BIT_REG,
118	.mpu_irqs	= omap2_i2c2_mpu_irqs,
119	.sdma_reqs	= omap2_i2c2_sdma_reqs,
120	.main_clk	= "i2chs2_fck",
121	.prcm		= {
122		.omap2 = {
123			.module_offs = CORE_MOD,
124			.prcm_reg_id = 1,
125			.module_bit = OMAP2430_EN_I2CHS2_SHIFT,
126			.idlest_reg_id = 1,
127			.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
128		},
129	},
 
 
130	.class		= &i2c_class,
131	.dev_attr	= &i2c_dev_attr,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
132};
133
134/* gpio5 */
135static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
136	{ .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
137	{ .irq = -1 }
138};
139
 
 
 
 
140static struct omap_hwmod omap2430_gpio5_hwmod = {
141	.name		= "gpio5",
142	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
143	.mpu_irqs	= omap243x_gpio5_irqs,
144	.main_clk	= "gpio5_fck",
145	.prcm		= {
146		.omap2 = {
147			.prcm_reg_id = 2,
148			.module_bit = OMAP2430_EN_GPIO5_SHIFT,
149			.module_offs = CORE_MOD,
150			.idlest_reg_id = 2,
151			.idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
152		},
153	},
 
 
154	.class		= &omap2xxx_gpio_hwmod_class,
155	.dev_attr	= &omap2xxx_gpio_dev_attr,
 
156};
157
158/* dma attributes */
159static struct omap_dma_dev_attr dma_dev_attr = {
160	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
161				IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
162	.lch_count = 32,
163};
164
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
165static struct omap_hwmod omap2430_dma_system_hwmod = {
166	.name		= "dma",
167	.class		= &omap2xxx_dma_hwmod_class,
168	.mpu_irqs	= omap2_dma_system_irqs,
169	.main_clk	= "core_l3_ck",
 
 
 
 
170	.dev_attr	= &dma_dev_attr,
 
171	.flags		= HWMOD_NO_IDLEST,
172};
173
174/* mailbox */
 
175static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
176	{ .irq = 26 },
177	{ .irq = -1 }
178};
179
 
 
 
 
 
 
 
 
 
 
 
 
 
180static struct omap_hwmod omap2430_mailbox_hwmod = {
181	.name		= "mailbox",
182	.class		= &omap2xxx_mailbox_hwmod_class,
183	.mpu_irqs	= omap2430_mailbox_irqs,
184	.main_clk	= "mailboxes_ick",
185	.prcm		= {
186		.omap2 = {
187			.prcm_reg_id = 1,
188			.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
189			.module_offs = CORE_MOD,
190			.idlest_reg_id = 1,
191			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
192		},
193	},
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
194};
195
196/* mcspi3 */
197static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
198	{ .irq = 91 },
199	{ .irq = -1 }
200};
201
202static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
203	{ .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
204	{ .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
205	{ .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
206	{ .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
207	{ .dma_req = -1 }
208};
209
 
 
 
 
210static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
211	.num_chipselect = 2,
212};
213
214static struct omap_hwmod omap2430_mcspi3_hwmod = {
215	.name		= "mcspi3",
216	.mpu_irqs	= omap2430_mcspi3_mpu_irqs,
217	.sdma_reqs	= omap2430_mcspi3_sdma_reqs,
218	.main_clk	= "mcspi3_fck",
219	.prcm		= {
220		.omap2 = {
221			.module_offs = CORE_MOD,
222			.prcm_reg_id = 2,
223			.module_bit = OMAP2430_EN_MCSPI3_SHIFT,
224			.idlest_reg_id = 2,
225			.idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
226		},
227	},
 
 
228	.class		= &omap2xxx_mcspi_class,
229	.dev_attr	= &omap_mcspi3_dev_attr,
 
230};
231
232/* usbhsotg */
 
 
233static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
234	.rev_offs	= 0x0400,
235	.sysc_offs	= 0x0404,
236	.syss_offs	= 0x0408,
237	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
238			  SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
239			  SYSC_HAS_AUTOIDLE),
240	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
241			  MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
242	.sysc_fields	= &omap_hwmod_sysc_type1,
243};
244
245static struct omap_hwmod_class usbotg_class = {
246	.name = "usbotg",
247	.sysc = &omap2430_usbhsotg_sysc,
248};
249
250/* usb_otg_hs */
251static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
252
253	{ .name = "mc", .irq = 92 },
254	{ .name = "dma", .irq = 93 },
255	{ .irq = -1 }
256};
257
258static struct omap_hwmod omap2430_usbhsotg_hwmod = {
259	.name		= "usb_otg_hs",
260	.mpu_irqs	= omap2430_usbhsotg_mpu_irqs,
261	.main_clk	= "usbhs_ick",
262	.prcm		= {
263		.omap2 = {
264			.prcm_reg_id = 1,
265			.module_bit = OMAP2430_EN_USBHS_MASK,
266			.module_offs = CORE_MOD,
267			.idlest_reg_id = 1,
268			.idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
269		},
270	},
 
 
 
 
271	.class		= &usbotg_class,
272	/*
273	 * Erratum ID: i479  idle_req / idle_ack mechanism potentially
274	 * broken when autoidle is enabled
275	 * workaround is to disable the autoidle bit at module level.
276	 */
277	.flags		= HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
278				| HWMOD_SWSUP_MSTANDBY,
 
279};
280
281/*
282 * 'mcbsp' class
283 * multi channel buffered serial port controller
284 */
285
286static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
287	.rev_offs	= 0x007C,
288	.sysc_offs	= 0x008C,
289	.sysc_flags	= (SYSC_HAS_SOFTRESET),
290	.sysc_fields    = &omap_hwmod_sysc_type1,
291};
292
293static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
294	.name = "mcbsp",
295	.sysc = &omap2430_mcbsp_sysc,
296	.rev  = MCBSP_CONFIG_TYPE2,
297};
298
299/* mcbsp1 */
300static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
301	{ .name = "tx",		.irq = 59 },
302	{ .name = "rx",		.irq = 60 },
303	{ .name = "ovr",	.irq = 61 },
304	{ .name = "common",	.irq = 64 },
305	{ .irq = -1 }
306};
307
 
 
 
 
 
 
 
 
 
 
 
 
 
 
308static struct omap_hwmod omap2430_mcbsp1_hwmod = {
309	.name		= "mcbsp1",
310	.class		= &omap2430_mcbsp_hwmod_class,
311	.mpu_irqs	= omap2430_mcbsp1_irqs,
312	.sdma_reqs	= omap2_mcbsp1_sdma_reqs,
313	.main_clk	= "mcbsp1_fck",
314	.prcm		= {
315		.omap2 = {
316			.prcm_reg_id = 1,
317			.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
318			.module_offs = CORE_MOD,
319			.idlest_reg_id = 1,
320			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
321		},
322	},
 
 
 
323};
324
325/* mcbsp2 */
326static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
327	{ .name = "tx",		.irq = 62 },
328	{ .name = "rx",		.irq = 63 },
329	{ .name = "common",	.irq = 16 },
330	{ .irq = -1 }
331};
332
 
 
 
 
 
 
 
 
 
 
 
 
 
 
333static struct omap_hwmod omap2430_mcbsp2_hwmod = {
334	.name		= "mcbsp2",
335	.class		= &omap2430_mcbsp_hwmod_class,
336	.mpu_irqs	= omap2430_mcbsp2_irqs,
337	.sdma_reqs	= omap2_mcbsp2_sdma_reqs,
338	.main_clk	= "mcbsp2_fck",
339	.prcm		= {
340		.omap2 = {
341			.prcm_reg_id = 1,
342			.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
343			.module_offs = CORE_MOD,
344			.idlest_reg_id = 1,
345			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
346		},
347	},
 
 
 
348};
349
350/* mcbsp3 */
351static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
352	{ .name = "tx",		.irq = 89 },
353	{ .name = "rx",		.irq = 90 },
354	{ .name = "common",	.irq = 17 },
355	{ .irq = -1 }
356};
357
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
358static struct omap_hwmod omap2430_mcbsp3_hwmod = {
359	.name		= "mcbsp3",
360	.class		= &omap2430_mcbsp_hwmod_class,
361	.mpu_irqs	= omap2430_mcbsp3_irqs,
362	.sdma_reqs	= omap2_mcbsp3_sdma_reqs,
363	.main_clk	= "mcbsp3_fck",
364	.prcm		= {
365		.omap2 = {
366			.prcm_reg_id = 1,
367			.module_bit = OMAP2430_EN_MCBSP3_SHIFT,
368			.module_offs = CORE_MOD,
369			.idlest_reg_id = 2,
370			.idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
371		},
372	},
 
 
 
373};
374
375/* mcbsp4 */
376static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
377	{ .name = "tx",		.irq = 54 },
378	{ .name = "rx",		.irq = 55 },
379	{ .name = "common",	.irq = 18 },
380	{ .irq = -1 }
381};
382
383static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
384	{ .name = "rx", .dma_req = 20 },
385	{ .name = "tx", .dma_req = 19 },
386	{ .dma_req = -1 }
387};
388
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
389static struct omap_hwmod omap2430_mcbsp4_hwmod = {
390	.name		= "mcbsp4",
391	.class		= &omap2430_mcbsp_hwmod_class,
392	.mpu_irqs	= omap2430_mcbsp4_irqs,
393	.sdma_reqs	= omap2430_mcbsp4_sdma_chs,
394	.main_clk	= "mcbsp4_fck",
395	.prcm		= {
396		.omap2 = {
397			.prcm_reg_id = 1,
398			.module_bit = OMAP2430_EN_MCBSP4_SHIFT,
399			.module_offs = CORE_MOD,
400			.idlest_reg_id = 2,
401			.idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
402		},
403	},
 
 
 
404};
405
406/* mcbsp5 */
407static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
408	{ .name = "tx",		.irq = 81 },
409	{ .name = "rx",		.irq = 82 },
410	{ .name = "common",	.irq = 19 },
411	{ .irq = -1 }
412};
413
414static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
415	{ .name = "rx", .dma_req = 22 },
416	{ .name = "tx", .dma_req = 21 },
417	{ .dma_req = -1 }
418};
419
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
420static struct omap_hwmod omap2430_mcbsp5_hwmod = {
421	.name		= "mcbsp5",
422	.class		= &omap2430_mcbsp_hwmod_class,
423	.mpu_irqs	= omap2430_mcbsp5_irqs,
424	.sdma_reqs	= omap2430_mcbsp5_sdma_chs,
425	.main_clk	= "mcbsp5_fck",
426	.prcm		= {
427		.omap2 = {
428			.prcm_reg_id = 1,
429			.module_bit = OMAP2430_EN_MCBSP5_SHIFT,
430			.module_offs = CORE_MOD,
431			.idlest_reg_id = 2,
432			.idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
433		},
434	},
 
 
 
435};
436
437/* MMC/SD/SDIO common */
 
438static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
439	.rev_offs	= 0x1fc,
440	.sysc_offs	= 0x10,
441	.syss_offs	= 0x14,
442	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
443			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
444			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
445	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
446	.sysc_fields    = &omap_hwmod_sysc_type1,
447};
448
449static struct omap_hwmod_class omap2430_mmc_class = {
450	.name = "mmc",
451	.sysc = &omap2430_mmc_sysc,
452};
453
454/* MMC/SD/SDIO1 */
 
455static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
456	{ .irq = 83 },
457	{ .irq = -1 }
458};
459
460static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
461	{ .name = "tx",	.dma_req = 61 }, /* DMA_MMC1_TX */
462	{ .name = "rx",	.dma_req = 62 }, /* DMA_MMC1_RX */
463	{ .dma_req = -1 }
464};
465
466static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
467	{ .role = "dbck", .clk = "mmchsdb1_fck" },
468};
469
 
 
 
 
470static struct omap_mmc_dev_attr mmc1_dev_attr = {
471	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
472};
473
474static struct omap_hwmod omap2430_mmc1_hwmod = {
475	.name		= "mmc1",
476	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
477	.mpu_irqs	= omap2430_mmc1_mpu_irqs,
478	.sdma_reqs	= omap2430_mmc1_sdma_reqs,
479	.opt_clks	= omap2430_mmc1_opt_clks,
480	.opt_clks_cnt	= ARRAY_SIZE(omap2430_mmc1_opt_clks),
481	.main_clk	= "mmchs1_fck",
482	.prcm		= {
483		.omap2 = {
484			.module_offs = CORE_MOD,
485			.prcm_reg_id = 2,
486			.module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
487			.idlest_reg_id = 2,
488			.idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
489		},
490	},
491	.dev_attr	= &mmc1_dev_attr,
 
 
492	.class		= &omap2430_mmc_class,
 
493};
494
495/* MMC/SD/SDIO2 */
 
496static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
497	{ .irq = 86 },
498	{ .irq = -1 }
499};
500
501static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
502	{ .name = "tx",	.dma_req = 47 }, /* DMA_MMC2_TX */
503	{ .name = "rx",	.dma_req = 48 }, /* DMA_MMC2_RX */
504	{ .dma_req = -1 }
505};
506
507static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
508	{ .role = "dbck", .clk = "mmchsdb2_fck" },
509};
510
 
 
 
 
511static struct omap_hwmod omap2430_mmc2_hwmod = {
512	.name		= "mmc2",
513	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
514	.mpu_irqs	= omap2430_mmc2_mpu_irqs,
515	.sdma_reqs	= omap2430_mmc2_sdma_reqs,
516	.opt_clks	= omap2430_mmc2_opt_clks,
517	.opt_clks_cnt	= ARRAY_SIZE(omap2430_mmc2_opt_clks),
518	.main_clk	= "mmchs2_fck",
519	.prcm		= {
520		.omap2 = {
521			.module_offs = CORE_MOD,
522			.prcm_reg_id = 2,
523			.module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
524			.idlest_reg_id = 2,
525			.idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
526		},
527	},
 
 
528	.class		= &omap2430_mmc_class,
 
529};
530
531/* HDQ1W/1-wire */
532static struct omap_hwmod omap2430_hdq1w_hwmod = {
533	.name		= "hdq1w",
534	.mpu_irqs	= omap2_hdq1w_mpu_irqs,
535	.main_clk	= "hdq_fck",
536	.prcm		= {
537		.omap2 = {
538			.module_offs = CORE_MOD,
539			.prcm_reg_id = 1,
540			.module_bit = OMAP24XX_EN_HDQ_SHIFT,
541			.idlest_reg_id = 1,
542			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
543		},
544	},
545	.class		= &omap2_hdq1w_class,
546};
547
548/*
549 * interfaces
550 */
551
552/* L3 -> L4_CORE interface */
553/* l3_core -> usbhsotg  interface */
554static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
555	.master		= &omap2430_usbhsotg_hwmod,
556	.slave		= &omap2xxx_l3_main_hwmod,
557	.clk		= "core_l3_ck",
558	.user		= OCP_USER_MPU,
559};
560
561/* L4 CORE -> I2C1 interface */
562static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
563	.master		= &omap2xxx_l4_core_hwmod,
564	.slave		= &omap2430_i2c1_hwmod,
565	.clk		= "i2c1_ick",
566	.addr		= omap2_i2c1_addr_space,
567	.user		= OCP_USER_MPU | OCP_USER_SDMA,
568};
569
570/* L4 CORE -> I2C2 interface */
571static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
572	.master		= &omap2xxx_l4_core_hwmod,
573	.slave		= &omap2430_i2c2_hwmod,
574	.clk		= "i2c2_ick",
575	.addr		= omap2_i2c2_addr_space,
576	.user		= OCP_USER_MPU | OCP_USER_SDMA,
577};
578
579static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
580	{
581		.pa_start	= OMAP243X_HS_BASE,
582		.pa_end		= OMAP243X_HS_BASE + SZ_4K - 1,
583		.flags		= ADDR_TYPE_RT
584	},
585	{ }
586};
587
588/*  l4_core ->usbhsotg  interface */
589static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
590	.master		= &omap2xxx_l4_core_hwmod,
591	.slave		= &omap2430_usbhsotg_hwmod,
592	.clk		= "usb_l4_ick",
593	.addr		= omap2430_usbhsotg_addrs,
594	.user		= OCP_USER_MPU,
595};
596
597/* L4 CORE -> MMC1 interface */
598static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
599	.master		= &omap2xxx_l4_core_hwmod,
600	.slave		= &omap2430_mmc1_hwmod,
601	.clk		= "mmchs1_ick",
602	.addr		= omap2430_mmc1_addr_space,
603	.user		= OCP_USER_MPU | OCP_USER_SDMA,
604};
605
606/* L4 CORE -> MMC2 interface */
607static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
608	.master		= &omap2xxx_l4_core_hwmod,
609	.slave		= &omap2430_mmc2_hwmod,
610	.clk		= "mmchs2_ick",
611	.addr		= omap2430_mmc2_addr_space,
612	.user		= OCP_USER_MPU | OCP_USER_SDMA,
613};
614
615/* l4 core -> mcspi3 interface */
616static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
617	.master		= &omap2xxx_l4_core_hwmod,
618	.slave		= &omap2430_mcspi3_hwmod,
619	.clk		= "mcspi3_ick",
620	.addr		= omap2430_mcspi3_addr_space,
621	.user		= OCP_USER_MPU | OCP_USER_SDMA,
622};
623
624/* IVA2 <- L3 interface */
625static struct omap_hwmod_ocp_if omap2430_l3__iva = {
626	.master		= &omap2xxx_l3_main_hwmod,
627	.slave		= &omap2430_iva_hwmod,
628	.clk		= "core_l3_ck",
629	.user		= OCP_USER_MPU | OCP_USER_SDMA,
630};
631
632static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
633	{
634		.pa_start	= 0x49018000,
635		.pa_end		= 0x49018000 + SZ_1K - 1,
636		.flags		= ADDR_TYPE_RT
637	},
638	{ }
639};
640
641/* l4_wkup -> timer1 */
642static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
643	.master		= &omap2xxx_l4_wkup_hwmod,
644	.slave		= &omap2xxx_timer1_hwmod,
645	.clk		= "gpt1_ick",
646	.addr		= omap2430_timer1_addrs,
647	.user		= OCP_USER_MPU | OCP_USER_SDMA,
648};
649
650/* l4_wkup -> wd_timer2 */
651static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
652	{
653		.pa_start	= 0x49016000,
654		.pa_end		= 0x4901607f,
655		.flags		= ADDR_TYPE_RT
656	},
657	{ }
658};
659
660static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
661	.master		= &omap2xxx_l4_wkup_hwmod,
662	.slave		= &omap2xxx_wd_timer2_hwmod,
663	.clk		= "mpu_wdt_ick",
664	.addr		= omap2430_wd_timer2_addrs,
665	.user		= OCP_USER_MPU | OCP_USER_SDMA,
666};
667
668/* l4_wkup -> gpio1 */
669static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
670	{
671		.pa_start	= 0x4900C000,
672		.pa_end		= 0x4900C1ff,
673		.flags		= ADDR_TYPE_RT
674	},
675	{ }
676};
677
678static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
679	.master		= &omap2xxx_l4_wkup_hwmod,
680	.slave		= &omap2xxx_gpio1_hwmod,
681	.clk		= "gpios_ick",
682	.addr		= omap2430_gpio1_addr_space,
683	.user		= OCP_USER_MPU | OCP_USER_SDMA,
684};
685
686/* l4_wkup -> gpio2 */
687static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
688	{
689		.pa_start	= 0x4900E000,
690		.pa_end		= 0x4900E1ff,
691		.flags		= ADDR_TYPE_RT
692	},
693	{ }
694};
695
696static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
697	.master		= &omap2xxx_l4_wkup_hwmod,
698	.slave		= &omap2xxx_gpio2_hwmod,
699	.clk		= "gpios_ick",
700	.addr		= omap2430_gpio2_addr_space,
701	.user		= OCP_USER_MPU | OCP_USER_SDMA,
702};
703
704/* l4_wkup -> gpio3 */
705static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
706	{
707		.pa_start	= 0x49010000,
708		.pa_end		= 0x490101ff,
709		.flags		= ADDR_TYPE_RT
710	},
711	{ }
712};
713
714static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
715	.master		= &omap2xxx_l4_wkup_hwmod,
716	.slave		= &omap2xxx_gpio3_hwmod,
717	.clk		= "gpios_ick",
718	.addr		= omap2430_gpio3_addr_space,
719	.user		= OCP_USER_MPU | OCP_USER_SDMA,
720};
721
722/* l4_wkup -> gpio4 */
723static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
724	{
725		.pa_start	= 0x49012000,
726		.pa_end		= 0x490121ff,
727		.flags		= ADDR_TYPE_RT
728	},
729	{ }
730};
731
732static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
733	.master		= &omap2xxx_l4_wkup_hwmod,
734	.slave		= &omap2xxx_gpio4_hwmod,
735	.clk		= "gpios_ick",
736	.addr		= omap2430_gpio4_addr_space,
737	.user		= OCP_USER_MPU | OCP_USER_SDMA,
738};
739
740/* l4_core -> gpio5 */
741static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
742	{
743		.pa_start	= 0x480B6000,
744		.pa_end		= 0x480B61ff,
745		.flags		= ADDR_TYPE_RT
746	},
747	{ }
748};
749
750static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
751	.master		= &omap2xxx_l4_core_hwmod,
752	.slave		= &omap2430_gpio5_hwmod,
753	.clk		= "gpio5_ick",
754	.addr		= omap2430_gpio5_addr_space,
755	.user		= OCP_USER_MPU | OCP_USER_SDMA,
756};
757
758/* dma_system -> L3 */
759static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
760	.master		= &omap2430_dma_system_hwmod,
761	.slave		= &omap2xxx_l3_main_hwmod,
762	.clk		= "core_l3_ck",
763	.user		= OCP_USER_MPU | OCP_USER_SDMA,
764};
765
766/* l4_core -> dma_system */
767static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
768	.master		= &omap2xxx_l4_core_hwmod,
769	.slave		= &omap2430_dma_system_hwmod,
770	.clk		= "sdma_ick",
771	.addr		= omap2_dma_system_addrs,
772	.user		= OCP_USER_MPU | OCP_USER_SDMA,
773};
774
775/* l4_core -> mailbox */
776static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
777	.master		= &omap2xxx_l4_core_hwmod,
778	.slave		= &omap2430_mailbox_hwmod,
779	.addr		= omap2_mailbox_addrs,
780	.user		= OCP_USER_MPU | OCP_USER_SDMA,
781};
782
783/* l4_core -> mcbsp1 */
784static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
785	.master		= &omap2xxx_l4_core_hwmod,
786	.slave		= &omap2430_mcbsp1_hwmod,
787	.clk		= "mcbsp1_ick",
788	.addr		= omap2_mcbsp1_addrs,
789	.user		= OCP_USER_MPU | OCP_USER_SDMA,
790};
791
792/* l4_core -> mcbsp2 */
793static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
794	.master		= &omap2xxx_l4_core_hwmod,
795	.slave		= &omap2430_mcbsp2_hwmod,
796	.clk		= "mcbsp2_ick",
797	.addr		= omap2xxx_mcbsp2_addrs,
798	.user		= OCP_USER_MPU | OCP_USER_SDMA,
799};
800
801static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
802	{
803		.name		= "mpu",
804		.pa_start	= 0x4808C000,
805		.pa_end		= 0x4808C0ff,
806		.flags		= ADDR_TYPE_RT
807	},
808	{ }
809};
810
811/* l4_core -> mcbsp3 */
812static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
813	.master		= &omap2xxx_l4_core_hwmod,
814	.slave		= &omap2430_mcbsp3_hwmod,
815	.clk		= "mcbsp3_ick",
816	.addr		= omap2430_mcbsp3_addrs,
817	.user		= OCP_USER_MPU | OCP_USER_SDMA,
818};
819
820static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
821	{
822		.name		= "mpu",
823		.pa_start	= 0x4808E000,
824		.pa_end		= 0x4808E0ff,
825		.flags		= ADDR_TYPE_RT
826	},
827	{ }
828};
829
830/* l4_core -> mcbsp4 */
831static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
832	.master		= &omap2xxx_l4_core_hwmod,
833	.slave		= &omap2430_mcbsp4_hwmod,
834	.clk		= "mcbsp4_ick",
835	.addr		= omap2430_mcbsp4_addrs,
836	.user		= OCP_USER_MPU | OCP_USER_SDMA,
837};
838
839static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
840	{
841		.name		= "mpu",
842		.pa_start	= 0x48096000,
843		.pa_end		= 0x480960ff,
844		.flags		= ADDR_TYPE_RT
845	},
846	{ }
847};
848
849/* l4_core -> mcbsp5 */
850static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
851	.master		= &omap2xxx_l4_core_hwmod,
852	.slave		= &omap2430_mcbsp5_hwmod,
853	.clk		= "mcbsp5_ick",
854	.addr		= omap2430_mcbsp5_addrs,
855	.user		= OCP_USER_MPU | OCP_USER_SDMA,
856};
857
858/* l4_core -> hdq1w */
859static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
860	.master		= &omap2xxx_l4_core_hwmod,
861	.slave		= &omap2430_hdq1w_hwmod,
862	.clk		= "hdq_ick",
863	.addr		= omap2_hdq1w_addr_space,
864	.user		= OCP_USER_MPU | OCP_USER_SDMA,
865	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
866};
867
868/* l4_wkup -> 32ksync_counter */
869static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
870	{
871		.pa_start	= 0x49020000,
872		.pa_end		= 0x4902001f,
873		.flags		= ADDR_TYPE_RT
874	},
875	{ }
876};
877
878static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
879	.master		= &omap2xxx_l4_wkup_hwmod,
880	.slave		= &omap2xxx_counter_32k_hwmod,
881	.clk		= "sync_32k_ick",
882	.addr		= omap2430_counter_32k_addrs,
883	.user		= OCP_USER_MPU | OCP_USER_SDMA,
884};
885
886static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
887	&omap2xxx_l3_main__l4_core,
888	&omap2xxx_mpu__l3_main,
889	&omap2xxx_dss__l3,
890	&omap2430_usbhsotg__l3,
891	&omap2430_l4_core__i2c1,
892	&omap2430_l4_core__i2c2,
893	&omap2xxx_l4_core__l4_wkup,
894	&omap2_l4_core__uart1,
895	&omap2_l4_core__uart2,
896	&omap2_l4_core__uart3,
897	&omap2430_l4_core__usbhsotg,
898	&omap2430_l4_core__mmc1,
899	&omap2430_l4_core__mmc2,
900	&omap2xxx_l4_core__mcspi1,
901	&omap2xxx_l4_core__mcspi2,
902	&omap2430_l4_core__mcspi3,
903	&omap2430_l3__iva,
904	&omap2430_l4_wkup__timer1,
905	&omap2xxx_l4_core__timer2,
906	&omap2xxx_l4_core__timer3,
907	&omap2xxx_l4_core__timer4,
908	&omap2xxx_l4_core__timer5,
909	&omap2xxx_l4_core__timer6,
910	&omap2xxx_l4_core__timer7,
911	&omap2xxx_l4_core__timer8,
912	&omap2xxx_l4_core__timer9,
913	&omap2xxx_l4_core__timer10,
914	&omap2xxx_l4_core__timer11,
915	&omap2xxx_l4_core__timer12,
916	&omap2430_l4_wkup__wd_timer2,
917	&omap2xxx_l4_core__dss,
918	&omap2xxx_l4_core__dss_dispc,
919	&omap2xxx_l4_core__dss_rfbi,
920	&omap2xxx_l4_core__dss_venc,
921	&omap2430_l4_wkup__gpio1,
922	&omap2430_l4_wkup__gpio2,
923	&omap2430_l4_wkup__gpio3,
924	&omap2430_l4_wkup__gpio4,
925	&omap2430_l4_core__gpio5,
926	&omap2430_dma_system__l3,
927	&omap2430_l4_core__dma_system,
928	&omap2430_l4_core__mailbox,
929	&omap2430_l4_core__mcbsp1,
930	&omap2430_l4_core__mcbsp2,
931	&omap2430_l4_core__mcbsp3,
932	&omap2430_l4_core__mcbsp4,
933	&omap2430_l4_core__mcbsp5,
934	&omap2430_l4_core__hdq1w,
935	&omap2430_l4_wkup__counter_32k,
936	NULL,
937};
938
939int __init omap2430_hwmod_init(void)
940{
941	return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
942}