1#
 2# Memory devices
 3#
 4
 5menuconfig MEMORY
 6	bool "Memory Controller drivers"
 
 
 
 
 
 
 7
 8if MEMORY
 9
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
10config TI_AEMIF
11	tristate "Texas Instruments AEMIF driver"
12	depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
 
13	help
14	  This driver is for the AEMIF module available in Texas Instruments
15	  SoCs. AEMIF stands for Asynchronous External Memory Interface and
16	  is intended to provide a glue-less interface to a variety of
17	  asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
18	  of 256M bytes of any of these memories can be accessed at a given
19	  time via four chip selects with 64M byte access per chip select.
20
21config TI_EMIF
22	tristate "Texas Instruments EMIF driver"
23	depends on ARCH_OMAP2PLUS
24	select DDR
25	help
26	  This driver is for the EMIF module available in Texas Instruments
27	  SoCs. EMIF is an SDRAM controller that, based on its revision,
28	  supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
29	  This driver takes care of only LPDDR2 memories presently. The
30	  functions of the driver includes re-configuring AC timing
31	  parameters and other settings during frequency, voltage and
32	  temperature changes
33
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
34config MVEBU_DEVBUS
35	bool "Marvell EBU Device Bus Controller"
36	default y
37	depends on PLAT_ORION && OF
 
38	help
39	  This driver is for the Device Bus controller available in some
40	  Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
41	  Armada 370 and Armada XP. This controller allows to handle flash
42	  devices such as NOR, NAND, SRAM, and FPGA.
43
44config TEGRA20_MC
45	bool "Tegra20 Memory Controller(MC) driver"
46	default y
47	depends on ARCH_TEGRA_2x_SOC
48	help
49	  This driver is for the Memory Controller(MC) module available
50	  in Tegra20 SoCs, mainly for a address translation fault
51	  analysis, especially for IOMMU/GART(Graphics Address
52	  Relocation Table) module.
53
54config TEGRA30_MC
55	bool "Tegra30 Memory Controller(MC) driver"
56	default y
57	depends on ARCH_TEGRA_3x_SOC
58	help
59	  This driver is for the Memory Controller(MC) module available
60	  in Tegra30 SoCs, mainly for a address translation fault
61	  analysis, especially for IOMMU/SMMU(System Memory Management
62	  Unit) module.
63
64config FSL_IFC
65	bool
66	depends on FSL_SOC
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
67
68endif

  1# SPDX-License-Identifier: GPL-2.0-only
  2#
  3# Memory devices
  4#
  5
  6menuconfig MEMORY
  7	bool "Memory Controller drivers"
  8	help
  9	  This option allows to enable specific memory controller drivers,
 10	  useful mostly on embedded systems.  These could be controllers
 11	  for DRAM (SDR, DDR), ROM, SRAM and others.  The drivers features
 12	  vary from memory tuning and frequency scaling to enabling
 13	  access to attached peripherals through memory bus.
 14
 15if MEMORY
 16
 17config DDR
 18	bool
 19	help
 20	  Data from JEDEC specs for DDR SDRAM memories,
 21	  particularly the AC timing parameters and addressing
 22	  information. This data is useful for drivers handling
 23	  DDR SDRAM controllers.
 24
 25config ARM_PL172_MPMC
 26	tristate "ARM PL172 MPMC driver"
 27	depends on ARM_AMBA && OF
 28	help
 29	  This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
 30	  If you have an embedded system with an AMBA bus and a PL172
 31	  controller, say Y or M here.
 32
 33config ATMEL_EBI
 34	bool "Atmel EBI driver"
 35	default y if ARCH_AT91
 36	depends on ARCH_AT91 || COMPILE_TEST
 37	depends on OF
 38	select MFD_SYSCON
 39	select MFD_ATMEL_SMC
 40	help
 41	  Driver for Atmel EBI controller.
 42	  Used to configure the EBI (external bus interface) when the device-
 43	  tree is used. This bus supports NANDs, external ethernet controller,
 44	  SRAMs, ATA devices, etc.
 45
 46config BRCMSTB_DPFE
 47	tristate "Broadcom STB DPFE driver"
 48	default ARCH_BRCMSTB
 49	depends on ARCH_BRCMSTB || COMPILE_TEST
 50	help
 51	  This driver provides access to the DPFE interface of Broadcom
 52	  STB SoCs. The firmware running on the DCPU inside the DDR PHY can
 53	  provide current information about the system's RAM, for instance
 54	  the DRAM refresh rate. This can be used as an indirect indicator
 55	  for the DRAM's temperature. Slower refresh rate means cooler RAM,
 56	  higher refresh rate means hotter RAM.
 57
 58config BRCMSTB_MEMC
 59	tristate "Broadcom STB MEMC driver"
 60	default ARCH_BRCMSTB
 61	depends on ARCH_BRCMSTB || COMPILE_TEST
 62	help
 63	  This driver provides a way to configure the Broadcom STB memory
 64	  controller and specifically control the Self Refresh Power Down
 65	  (SRPD) inactivity timeout.
 66
 67config BT1_L2_CTL
 68	bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
 69	depends on MIPS_BAIKAL_T1 || COMPILE_TEST
 70	select MFD_SYSCON
 71	help
 72	  Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
 73	  resides Coherency Manager v2 with embedded 1MB L2-cache. It's
 74	  possible to tune the L2 cache performance up by setting the data,
 75	  tags and way-select latencies of RAM access. This driver provides a
 76	  dt properties-based and sysfs interface for it.
 77
 78config TI_AEMIF
 79	tristate "Texas Instruments AEMIF driver"
 80	depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST
 81	depends on OF
 82	help
 83	  This driver is for the AEMIF module available in Texas Instruments
 84	  SoCs. AEMIF stands for Asynchronous External Memory Interface and
 85	  is intended to provide a glue-less interface to a variety of
 86	  asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
 87	  of 256M bytes of any of these memories can be accessed at a given
 88	  time via four chip selects with 64M byte access per chip select.
 89
 90config TI_EMIF
 91	tristate "Texas Instruments EMIF driver"
 92	depends on ARCH_OMAP2PLUS || COMPILE_TEST
 93	select DDR
 94	help
 95	  This driver is for the EMIF module available in Texas Instruments
 96	  SoCs. EMIF is an SDRAM controller that, based on its revision,
 97	  supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
 98	  This driver takes care of only LPDDR2 memories presently. The
 99	  functions of the driver includes re-configuring AC timing
100	  parameters and other settings during frequency, voltage and
101	  temperature changes
102
103config OMAP_GPMC
104	tristate "Texas Instruments OMAP SoC GPMC driver"
105	depends on OF_ADDRESS
106	depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
107	select GPIOLIB
108	help
109	  This driver is for the General Purpose Memory Controller (GPMC)
110	  present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
111	  interfacing to a variety of asynchronous as well as synchronous
112	  memory drives like NOR, NAND, OneNAND, SRAM.
113
114config OMAP_GPMC_DEBUG
115	bool "Enable GPMC debug output and skip reset of GPMC during init"
116	depends on OMAP_GPMC
117	help
118	  Enables verbose debugging mostly to decode the bootloader provided
119	  timings. To preserve the bootloader provided timings, the reset
120	  of GPMC is skipped during init. Enable this during development to
121	  configure devices connected to the GPMC bus.
122
123	  NOTE: In addition to matching the register setup with the bootloader
124	  you also need to match the GPMC FCLK frequency used by the
125	  bootloader or else the GPMC timings won't be identical with the
126	  bootloader timings.
127
128config TI_EMIF_SRAM
129	tristate "Texas Instruments EMIF SRAM driver"
130	depends on SOC_AM33XX || SOC_AM43XX || (ARM && CPU_V7 && COMPILE_TEST)
131	depends on SRAM
132	help
133	  This driver is for the EMIF module available on Texas Instruments
134	  AM33XX and AM43XX SoCs and is required for PM. Certain parts of
135	  the EMIF PM code must run from on-chip SRAM late in the suspend
136	  sequence so this driver provides several relocatable PM functions
137	  for the SoC PM code to use.
138
139config FPGA_DFL_EMIF
140	tristate "FPGA DFL EMIF Driver"
141	depends on FPGA_DFL && HAS_IOMEM
142	help
143	  This driver is for the EMIF private feature implemented under
144	  FPGA Device Feature List (DFL) framework. It is used to expose
145	  memory interface status information as well as memory clearing
146	  control.
147
148config MVEBU_DEVBUS
149	bool "Marvell EBU Device Bus Controller"
150	default y if PLAT_ORION
151	depends on PLAT_ORION || COMPILE_TEST
152	depends on OF
153	help
154	  This driver is for the Device Bus controller available in some
155	  Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
156	  Armada 370 and Armada XP. This controller allows to handle flash
157	  devices such as NOR, NAND, SRAM, and FPGA.
158
159config FSL_CORENET_CF
160	tristate "Freescale CoreNet Error Reporting"
161	depends on FSL_SOC_BOOKE || COMPILE_TEST
162	help
163	  Say Y for reporting of errors from the Freescale CoreNet
164	  Coherency Fabric.  Errors reported include accesses to
165	  physical addresses that mapped by no local access window
166	  (LAW) or an invalid LAW, as well as bad cache state that
167	  represents a coherency violation.
 
 
 
 
 
 
 
 
 
 
168
169config FSL_IFC
170	bool "Freescale IFC driver" if COMPILE_TEST
171	depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
172	depends on HAS_IOMEM
173
174config JZ4780_NEMC
175	bool "Ingenic JZ4780 SoC NEMC driver"
176	depends on MIPS || COMPILE_TEST
177	depends on HAS_IOMEM && OF
178	help
179	  This driver is for the NAND/External Memory Controller (NEMC) in
180	  the Ingenic JZ4780. This controller is used to handle external
181	  memory devices such as NAND and SRAM.
182
183config MTK_SMI
184	tristate "MediaTek SoC Memory Controller driver" if COMPILE_TEST
185	depends on ARCH_MEDIATEK || COMPILE_TEST
186	help
187	  This driver is for the Memory Controller module in MediaTek SoCs,
188	  mainly help enable/disable iommu and control the power domain and
189	  clocks for each local arbiter.
190
191config DA8XX_DDRCTL
192	bool "Texas Instruments da8xx DDR2/mDDR driver"
193	depends on ARCH_DAVINCI_DA8XX || COMPILE_TEST
194	help
195	  This driver is for the DDR2/mDDR Memory Controller present on
196	  Texas Instruments da8xx SoCs. It's used to tweak various memory
197	  controller configuration options.
198
199config PL353_SMC
200	tristate "ARM PL35X Static Memory Controller(SMC) driver"
201	default y if ARM
202	depends on ARM || COMPILE_TEST
203	depends on ARM_AMBA
204	help
205	  This driver is for the ARM PL351/PL353 Static Memory
206	  Controller(SMC) module.
207
208config RENESAS_RPCIF
209	tristate "Renesas RPC-IF driver"
210	depends on ARCH_RENESAS || COMPILE_TEST
211	select REGMAP_MMIO
212	select RESET_CONTROLLER
213	help
214	  This supports Renesas R-Car Gen3 or RZ/G2 RPC-IF which provides
215	  either SPI host or HyperFlash. You'll have to select individual
216	  components under the corresponding menu.
217
218config STM32_FMC2_EBI
219	tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
220	depends on ARCH_STM32 || COMPILE_TEST
221	select MFD_SYSCON
222	help
223	  Select this option to enable the STM32 FMC2 External Bus Interface
224	  controller. This driver configures the transactions with external
225	  devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
226	  SOCs containing the FMC2 External Bus Interface.
227
228source "drivers/memory/samsung/Kconfig"
229source "drivers/memory/tegra/Kconfig"
230
231endif