1#
 2# Memory devices
 3#
 4
 5menuconfig MEMORY
 6	bool "Memory Controller drivers"
 7
 8if MEMORY
 9
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
10config TI_AEMIF
11	tristate "Texas Instruments AEMIF driver"
12	depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
13	help
14	  This driver is for the AEMIF module available in Texas Instruments
15	  SoCs. AEMIF stands for Asynchronous External Memory Interface and
16	  is intended to provide a glue-less interface to a variety of
17	  asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
18	  of 256M bytes of any of these memories can be accessed at a given
19	  time via four chip selects with 64M byte access per chip select.
20
21config TI_EMIF
22	tristate "Texas Instruments EMIF driver"
23	depends on ARCH_OMAP2PLUS
24	select DDR
25	help
26	  This driver is for the EMIF module available in Texas Instruments
27	  SoCs. EMIF is an SDRAM controller that, based on its revision,
28	  supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
29	  This driver takes care of only LPDDR2 memories presently. The
30	  functions of the driver includes re-configuring AC timing
31	  parameters and other settings during frequency, voltage and
32	  temperature changes
33
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
34config MVEBU_DEVBUS
35	bool "Marvell EBU Device Bus Controller"
36	default y
37	depends on PLAT_ORION && OF
38	help
39	  This driver is for the Device Bus controller available in some
40	  Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
41	  Armada 370 and Armada XP. This controller allows to handle flash
42	  devices such as NOR, NAND, SRAM, and FPGA.
43
44config TEGRA20_MC
45	bool "Tegra20 Memory Controller(MC) driver"
46	default y
47	depends on ARCH_TEGRA_2x_SOC
48	help
49	  This driver is for the Memory Controller(MC) module available
50	  in Tegra20 SoCs, mainly for a address translation fault
51	  analysis, especially for IOMMU/GART(Graphics Address
52	  Relocation Table) module.
53
54config TEGRA30_MC
55	bool "Tegra30 Memory Controller(MC) driver"
56	default y
57	depends on ARCH_TEGRA_3x_SOC
58	help
59	  This driver is for the Memory Controller(MC) module available
60	  in Tegra30 SoCs, mainly for a address translation fault
61	  analysis, especially for IOMMU/SMMU(System Memory Management
62	  Unit) module.
 
63
64config FSL_IFC
65	bool
66	depends on FSL_SOC
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
67
68endif

  1#
  2# Memory devices
  3#
  4
  5menuconfig MEMORY
  6	bool "Memory Controller drivers"
  7
  8if MEMORY
  9
 10config ARM_PL172_MPMC
 11	tristate "ARM PL172 MPMC driver"
 12	depends on ARM_AMBA && OF
 13	help
 14	  This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
 15	  If you have an embedded system with an AMBA bus and a PL172
 16	  controller, say Y or M here.
 17
 18config ATMEL_SDRAMC
 19	bool "Atmel (Multi-port DDR-)SDRAM Controller"
 20	default y
 21	depends on ARCH_AT91 && OF
 22	help
 23	  This driver is for Atmel SDRAM Controller or Atmel Multi-port
 24	  DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
 25	  Starting with the at91sam9g45, this controller supports SDR, DDR and
 26	  LP-DDR memories.
 27
 28config TI_AEMIF
 29	tristate "Texas Instruments AEMIF driver"
 30	depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
 31	help
 32	  This driver is for the AEMIF module available in Texas Instruments
 33	  SoCs. AEMIF stands for Asynchronous External Memory Interface and
 34	  is intended to provide a glue-less interface to a variety of
 35	  asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
 36	  of 256M bytes of any of these memories can be accessed at a given
 37	  time via four chip selects with 64M byte access per chip select.
 38
 39config TI_EMIF
 40	tristate "Texas Instruments EMIF driver"
 41	depends on ARCH_OMAP2PLUS
 42	select DDR
 43	help
 44	  This driver is for the EMIF module available in Texas Instruments
 45	  SoCs. EMIF is an SDRAM controller that, based on its revision,
 46	  supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
 47	  This driver takes care of only LPDDR2 memories presently. The
 48	  functions of the driver includes re-configuring AC timing
 49	  parameters and other settings during frequency, voltage and
 50	  temperature changes
 51
 52config OMAP_GPMC
 53	bool
 54	help
 55	  This driver is for the General Purpose Memory Controller (GPMC)
 56	  present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
 57	  interfacing to a variety of asynchronous as well as synchronous
 58	  memory drives like NOR, NAND, OneNAND, SRAM.
 59
 60config OMAP_GPMC_DEBUG
 61	bool "Enable GPMC debug output and skip reset of GPMC during init"
 62	depends on OMAP_GPMC
 63	help
 64	  Enables verbose debugging mostly to decode the bootloader provided
 65	  timings. To preserve the bootloader provided timings, the reset
 66	  of GPMC is skipped during init. Enable this during development to
 67	  configure devices connected to the GPMC bus.
 68
 69	  NOTE: In addition to matching the register setup with the bootloader
 70	  you also need to match the GPMC FCLK frequency used by the
 71	  bootloader or else the GPMC timings won't be identical with the
 72	  bootloader timings.
 73
 74config MVEBU_DEVBUS
 75	bool "Marvell EBU Device Bus Controller"
 76	default y
 77	depends on PLAT_ORION && OF
 78	help
 79	  This driver is for the Device Bus controller available in some
 80	  Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
 81	  Armada 370 and Armada XP. This controller allows to handle flash
 82	  devices such as NOR, NAND, SRAM, and FPGA.
 83
 84config TEGRA20_MC
 85	bool "Tegra20 Memory Controller(MC) driver"
 86	default y
 87	depends on ARCH_TEGRA_2x_SOC
 88	help
 89	  This driver is for the Memory Controller(MC) module available
 90	  in Tegra20 SoCs, mainly for a address translation fault
 91	  analysis, especially for IOMMU/GART(Graphics Address
 92	  Relocation Table) module.
 93
 94config FSL_CORENET_CF
 95	tristate "Freescale CoreNet Error Reporting"
 96	depends on FSL_SOC_BOOKE
 
 97	help
 98	  Say Y for reporting of errors from the Freescale CoreNet
 99	  Coherency Fabric.  Errors reported include accesses to
100	  physical addresses that mapped by no local access window
101	  (LAW) or an invalid LAW, as well as bad cache state that
102	  represents a coherency violation.
103
104config FSL_IFC
105	bool
106	depends on FSL_SOC
107
108config JZ4780_NEMC
109	bool "Ingenic JZ4780 SoC NEMC driver"
110	default y
111	depends on MACH_JZ4780
112	help
113	  This driver is for the NAND/External Memory Controller (NEMC) in
114	  the Ingenic JZ4780. This controller is used to handle external
115	  memory devices such as NAND and SRAM.
116
117config MTK_SMI
118	bool
119	depends on ARCH_MEDIATEK || COMPILE_TEST
120	help
121	  This driver is for the Memory Controller module in MediaTek SoCs,
122	  mainly help enable/disable iommu and control the power domain and
123	  clocks for each local arbiter.
124
125source "drivers/memory/tegra/Kconfig"
126
127endif