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1/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __ARM64_KVM_MMU_H__
19#define __ARM64_KVM_MMU_H__
20
21#include <asm/page.h>
22#include <asm/memory.h>
23
24/*
25 * As we only have the TTBR0_EL2 register, we cannot express
26 * "negative" addresses. This makes it impossible to directly share
27 * mappings with the kernel.
28 *
29 * Instead, give the HYP mode its own VA region at a fixed offset from
30 * the kernel by just masking the top bits (which are all ones for a
31 * kernel address).
32 */
33#define HYP_PAGE_OFFSET_SHIFT VA_BITS
34#define HYP_PAGE_OFFSET_MASK ((UL(1) << HYP_PAGE_OFFSET_SHIFT) - 1)
35#define HYP_PAGE_OFFSET (PAGE_OFFSET & HYP_PAGE_OFFSET_MASK)
36
37/*
38 * Our virtual mapping for the idmap-ed MMU-enable code. Must be
39 * shared across all the page-tables. Conveniently, we use the last
40 * possible page, where no kernel mapping will ever exist.
41 */
42#define TRAMPOLINE_VA (HYP_PAGE_OFFSET_MASK & PAGE_MASK)
43
44#ifdef __ASSEMBLY__
45
46/*
47 * Convert a kernel VA into a HYP VA.
48 * reg: VA to be converted.
49 */
50.macro kern_hyp_va reg
51 and \reg, \reg, #HYP_PAGE_OFFSET_MASK
52.endm
53
54#else
55
56#include <asm/cachetype.h>
57#include <asm/cacheflush.h>
58
59#define KERN_TO_HYP(kva) ((unsigned long)kva - PAGE_OFFSET + HYP_PAGE_OFFSET)
60
61/*
62 * Align KVM with the kernel's view of physical memory. Should be
63 * 40bit IPA, with PGD being 8kB aligned in the 4KB page configuration.
64 */
65#define KVM_PHYS_SHIFT PHYS_MASK_SHIFT
66#define KVM_PHYS_SIZE (1UL << KVM_PHYS_SHIFT)
67#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1UL)
68
69/* Make sure we get the right size, and thus the right alignment */
70#define PTRS_PER_S2_PGD (1 << (KVM_PHYS_SHIFT - PGDIR_SHIFT))
71#define S2_PGD_ORDER get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
72
73int create_hyp_mappings(void *from, void *to);
74int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
75void free_boot_hyp_pgd(void);
76void free_hyp_pgds(void);
77
78int kvm_alloc_stage2_pgd(struct kvm *kvm);
79void kvm_free_stage2_pgd(struct kvm *kvm);
80int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
81 phys_addr_t pa, unsigned long size);
82
83int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
84
85void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
86
87phys_addr_t kvm_mmu_get_httbr(void);
88phys_addr_t kvm_mmu_get_boot_httbr(void);
89phys_addr_t kvm_get_idmap_vector(void);
90int kvm_mmu_init(void);
91void kvm_clear_hyp_idmap(void);
92
93#define kvm_set_pte(ptep, pte) set_pte(ptep, pte)
94#define kvm_set_pmd(pmdp, pmd) set_pmd(pmdp, pmd)
95
96static inline bool kvm_is_write_fault(unsigned long esr)
97{
98 unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
99
100 if (esr_ec == ESR_EL2_EC_IABT)
101 return false;
102
103 if ((esr & ESR_EL2_ISV) && !(esr & ESR_EL2_WNR))
104 return false;
105
106 return true;
107}
108
109static inline void kvm_clean_pgd(pgd_t *pgd) {}
110static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
111static inline void kvm_clean_pte(pte_t *pte) {}
112static inline void kvm_clean_pte_entry(pte_t *pte) {}
113
114static inline void kvm_set_s2pte_writable(pte_t *pte)
115{
116 pte_val(*pte) |= PTE_S2_RDWR;
117}
118
119static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
120{
121 pmd_val(*pmd) |= PMD_S2_RDWR;
122}
123
124#define kvm_pgd_addr_end(addr, end) pgd_addr_end(addr, end)
125#define kvm_pud_addr_end(addr, end) pud_addr_end(addr, end)
126#define kvm_pmd_addr_end(addr, end) pmd_addr_end(addr, end)
127
128struct kvm;
129
130#define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
131
132static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
133{
134 return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
135}
136
137static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
138 unsigned long size)
139{
140 if (!vcpu_has_cache_enabled(vcpu))
141 kvm_flush_dcache_to_poc((void *)hva, size);
142
143 if (!icache_is_aliasing()) { /* PIPT */
144 flush_icache_range(hva, hva + size);
145 } else if (!icache_is_aivivt()) { /* non ASID-tagged VIVT */
146 /* any kind of VIPT cache */
147 __flush_icache_all();
148 }
149}
150
151#define kvm_virt_to_phys(x) __virt_to_phys((unsigned long)(x))
152
153void stage2_flush_vm(struct kvm *kvm);
154
155#endif /* __ASSEMBLY__ */
156#endif /* __ARM64_KVM_MMU_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#ifndef __ARM64_KVM_MMU_H__
8#define __ARM64_KVM_MMU_H__
9
10#include <asm/page.h>
11#include <asm/memory.h>
12#include <asm/mmu.h>
13#include <asm/cpufeature.h>
14
15/*
16 * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express
17 * "negative" addresses. This makes it impossible to directly share
18 * mappings with the kernel.
19 *
20 * Instead, give the HYP mode its own VA region at a fixed offset from
21 * the kernel by just masking the top bits (which are all ones for a
22 * kernel address). We need to find out how many bits to mask.
23 *
24 * We want to build a set of page tables that cover both parts of the
25 * idmap (the trampoline page used to initialize EL2), and our normal
26 * runtime VA space, at the same time.
27 *
28 * Given that the kernel uses VA_BITS for its entire address space,
29 * and that half of that space (VA_BITS - 1) is used for the linear
30 * mapping, we can also limit the EL2 space to (VA_BITS - 1).
31 *
32 * The main question is "Within the VA_BITS space, does EL2 use the
33 * top or the bottom half of that space to shadow the kernel's linear
34 * mapping?". As we need to idmap the trampoline page, this is
35 * determined by the range in which this page lives.
36 *
37 * If the page is in the bottom half, we have to use the top half. If
38 * the page is in the top half, we have to use the bottom half:
39 *
40 * T = __pa_symbol(__hyp_idmap_text_start)
41 * if (T & BIT(VA_BITS - 1))
42 * HYP_VA_MIN = 0 //idmap in upper half
43 * else
44 * HYP_VA_MIN = 1 << (VA_BITS - 1)
45 * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1
46 *
47 * When using VHE, there are no separate hyp mappings and all KVM
48 * functionality is already mapped as part of the main kernel
49 * mappings, and none of this applies in that case.
50 */
51
52#ifdef __ASSEMBLY__
53
54#include <asm/alternative.h>
55
56/*
57 * Convert a kernel VA into a HYP VA.
58 * reg: VA to be converted.
59 *
60 * The actual code generation takes place in kvm_update_va_mask, and
61 * the instructions below are only there to reserve the space and
62 * perform the register allocation (kvm_update_va_mask uses the
63 * specific registers encoded in the instructions).
64 */
65.macro kern_hyp_va reg
66#ifndef __KVM_VHE_HYPERVISOR__
67alternative_cb ARM64_ALWAYS_SYSTEM, kvm_update_va_mask
68 and \reg, \reg, #1 /* mask with va_mask */
69 ror \reg, \reg, #1 /* rotate to the first tag bit */
70 add \reg, \reg, #0 /* insert the low 12 bits of the tag */
71 add \reg, \reg, #0, lsl 12 /* insert the top 12 bits of the tag */
72 ror \reg, \reg, #63 /* rotate back */
73alternative_cb_end
74#endif
75.endm
76
77/*
78 * Convert a hypervisor VA to a PA
79 * reg: hypervisor address to be converted in place
80 * tmp: temporary register
81 */
82.macro hyp_pa reg, tmp
83 ldr_l \tmp, hyp_physvirt_offset
84 add \reg, \reg, \tmp
85.endm
86
87/*
88 * Convert a hypervisor VA to a kernel image address
89 * reg: hypervisor address to be converted in place
90 * tmp: temporary register
91 *
92 * The actual code generation takes place in kvm_get_kimage_voffset, and
93 * the instructions below are only there to reserve the space and
94 * perform the register allocation (kvm_get_kimage_voffset uses the
95 * specific registers encoded in the instructions).
96 */
97.macro hyp_kimg_va reg, tmp
98 /* Convert hyp VA -> PA. */
99 hyp_pa \reg, \tmp
100
101 /* Load kimage_voffset. */
102alternative_cb ARM64_ALWAYS_SYSTEM, kvm_get_kimage_voffset
103 movz \tmp, #0
104 movk \tmp, #0, lsl #16
105 movk \tmp, #0, lsl #32
106 movk \tmp, #0, lsl #48
107alternative_cb_end
108
109 /* Convert PA -> kimg VA. */
110 add \reg, \reg, \tmp
111.endm
112
113#else
114
115#include <linux/pgtable.h>
116#include <asm/pgalloc.h>
117#include <asm/cache.h>
118#include <asm/cacheflush.h>
119#include <asm/mmu_context.h>
120#include <asm/kvm_emulate.h>
121#include <asm/kvm_host.h>
122
123void kvm_update_va_mask(struct alt_instr *alt,
124 __le32 *origptr, __le32 *updptr, int nr_inst);
125void kvm_compute_layout(void);
126void kvm_apply_hyp_relocations(void);
127
128#define __hyp_pa(x) (((phys_addr_t)(x)) + hyp_physvirt_offset)
129
130static __always_inline unsigned long __kern_hyp_va(unsigned long v)
131{
132#ifndef __KVM_VHE_HYPERVISOR__
133 asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n"
134 "ror %0, %0, #1\n"
135 "add %0, %0, #0\n"
136 "add %0, %0, #0, lsl 12\n"
137 "ror %0, %0, #63\n",
138 ARM64_ALWAYS_SYSTEM,
139 kvm_update_va_mask)
140 : "+r" (v));
141#endif
142 return v;
143}
144
145#define kern_hyp_va(v) ((typeof(v))(__kern_hyp_va((unsigned long)(v))))
146
147/*
148 * We currently support using a VM-specified IPA size. For backward
149 * compatibility, the default IPA size is fixed to 40bits.
150 */
151#define KVM_PHYS_SHIFT (40)
152
153#define kvm_phys_shift(mmu) VTCR_EL2_IPA((mmu)->vtcr)
154#define kvm_phys_size(mmu) (_AC(1, ULL) << kvm_phys_shift(mmu))
155#define kvm_phys_mask(mmu) (kvm_phys_size(mmu) - _AC(1, ULL))
156
157#include <asm/kvm_pgtable.h>
158#include <asm/stage2_pgtable.h>
159
160int kvm_share_hyp(void *from, void *to);
161void kvm_unshare_hyp(void *from, void *to);
162int create_hyp_mappings(void *from, void *to, enum kvm_pgtable_prot prot);
163int __create_hyp_mappings(unsigned long start, unsigned long size,
164 unsigned long phys, enum kvm_pgtable_prot prot);
165int hyp_alloc_private_va_range(size_t size, unsigned long *haddr);
166int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
167 void __iomem **kaddr,
168 void __iomem **haddr);
169int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
170 void **haddr);
171int create_hyp_stack(phys_addr_t phys_addr, unsigned long *haddr);
172void __init free_hyp_pgds(void);
173
174void stage2_unmap_vm(struct kvm *kvm);
175int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu, unsigned long type);
176void kvm_uninit_stage2_mmu(struct kvm *kvm);
177void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu);
178int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
179 phys_addr_t pa, unsigned long size, bool writable);
180
181int kvm_handle_guest_abort(struct kvm_vcpu *vcpu);
182
183phys_addr_t kvm_mmu_get_httbr(void);
184phys_addr_t kvm_get_idmap_vector(void);
185int __init kvm_mmu_init(u32 *hyp_va_bits);
186
187static inline void *__kvm_vector_slot2addr(void *base,
188 enum arm64_hyp_spectre_vector slot)
189{
190 int idx = slot - (slot != HYP_VECTOR_DIRECT);
191
192 return base + (idx * SZ_2K);
193}
194
195struct kvm;
196
197#define kvm_flush_dcache_to_poc(a,l) \
198 dcache_clean_inval_poc((unsigned long)(a), (unsigned long)(a)+(l))
199
200static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
201{
202 u64 cache_bits = SCTLR_ELx_M | SCTLR_ELx_C;
203 int reg;
204
205 if (vcpu_is_el2(vcpu))
206 reg = SCTLR_EL2;
207 else
208 reg = SCTLR_EL1;
209
210 return (vcpu_read_sys_reg(vcpu, reg) & cache_bits) == cache_bits;
211}
212
213static inline void __clean_dcache_guest_page(void *va, size_t size)
214{
215 /*
216 * With FWB, we ensure that the guest always accesses memory using
217 * cacheable attributes, and we don't have to clean to PoC when
218 * faulting in pages. Furthermore, FWB implies IDC, so cleaning to
219 * PoU is not required either in this case.
220 */
221 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
222 return;
223
224 kvm_flush_dcache_to_poc(va, size);
225}
226
227static inline size_t __invalidate_icache_max_range(void)
228{
229 u8 iminline;
230 u64 ctr;
231
232 asm volatile(ALTERNATIVE_CB("movz %0, #0\n"
233 "movk %0, #0, lsl #16\n"
234 "movk %0, #0, lsl #32\n"
235 "movk %0, #0, lsl #48\n",
236 ARM64_ALWAYS_SYSTEM,
237 kvm_compute_final_ctr_el0)
238 : "=r" (ctr));
239
240 iminline = SYS_FIELD_GET(CTR_EL0, IminLine, ctr) + 2;
241 return MAX_DVM_OPS << iminline;
242}
243
244static inline void __invalidate_icache_guest_page(void *va, size_t size)
245{
246 /*
247 * Blow the whole I-cache if it is aliasing (i.e. VIPT) or the
248 * invalidation range exceeds our arbitrary limit on invadations by
249 * cache line.
250 */
251 if (icache_is_aliasing() || size > __invalidate_icache_max_range())
252 icache_inval_all_pou();
253 else
254 icache_inval_pou((unsigned long)va, (unsigned long)va + size);
255}
256
257void kvm_set_way_flush(struct kvm_vcpu *vcpu);
258void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
259
260static inline unsigned int kvm_get_vmid_bits(void)
261{
262 int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
263
264 return get_vmid_bits(reg);
265}
266
267/*
268 * We are not in the kvm->srcu critical section most of the time, so we take
269 * the SRCU read lock here. Since we copy the data from the user page, we
270 * can immediately drop the lock again.
271 */
272static inline int kvm_read_guest_lock(struct kvm *kvm,
273 gpa_t gpa, void *data, unsigned long len)
274{
275 int srcu_idx = srcu_read_lock(&kvm->srcu);
276 int ret = kvm_read_guest(kvm, gpa, data, len);
277
278 srcu_read_unlock(&kvm->srcu, srcu_idx);
279
280 return ret;
281}
282
283static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa,
284 const void *data, unsigned long len)
285{
286 int srcu_idx = srcu_read_lock(&kvm->srcu);
287 int ret = kvm_write_guest(kvm, gpa, data, len);
288
289 srcu_read_unlock(&kvm->srcu, srcu_idx);
290
291 return ret;
292}
293
294#define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr)
295
296/*
297 * When this is (directly or indirectly) used on the TLB invalidation
298 * path, we rely on a previously issued DSB so that page table updates
299 * and VMID reads are correctly ordered.
300 */
301static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu)
302{
303 struct kvm_vmid *vmid = &mmu->vmid;
304 u64 vmid_field, baddr;
305 u64 cnp = system_supports_cnp() ? VTTBR_CNP_BIT : 0;
306
307 baddr = mmu->pgd_phys;
308 vmid_field = atomic64_read(&vmid->id) << VTTBR_VMID_SHIFT;
309 vmid_field &= VTTBR_VMID_MASK(kvm_arm_vmid_bits);
310 return kvm_phys_to_vttbr(baddr) | vmid_field | cnp;
311}
312
313/*
314 * Must be called from hyp code running at EL2 with an updated VTTBR
315 * and interrupts disabled.
316 */
317static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu,
318 struct kvm_arch *arch)
319{
320 write_sysreg(mmu->vtcr, vtcr_el2);
321 write_sysreg(kvm_get_vttbr(mmu), vttbr_el2);
322
323 /*
324 * ARM errata 1165522 and 1530923 require the actual execution of the
325 * above before we can switch to the EL1/EL0 translation regime used by
326 * the guest.
327 */
328 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
329}
330
331static inline struct kvm *kvm_s2_mmu_to_kvm(struct kvm_s2_mmu *mmu)
332{
333 return container_of(mmu->arch, struct kvm, arch);
334}
335#endif /* __ASSEMBLY__ */
336#endif /* __ARM64_KVM_MMU_H__ */