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1/*
2 * Copyright (C) 2012-2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/of_device.h>
19#include <linux/of_irq.h>
20#include <linux/module.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip/chained_irq.h>
23
24#define BCM_GPIO_PASSWD 0x00a5a501
25#define GPIO_PER_BANK 32
26#define GPIO_MAX_BANK_NUM 8
27
28#define GPIO_BANK(gpio) ((gpio) >> 5)
29#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
30
31/* There is a GPIO control register for each GPIO */
32#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
33
34/* The remaining registers are per GPIO bank */
35#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
36#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
37#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
38#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
39#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
40#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
41#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
42#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
43
44#define GPIO_GPPWR_OFFSET 0x00000520
45
46#define GPIO_GPCTR0_DBR_SHIFT 5
47#define GPIO_GPCTR0_DBR_MASK 0x000001e0
48
49#define GPIO_GPCTR0_ITR_SHIFT 3
50#define GPIO_GPCTR0_ITR_MASK 0x00000018
51#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
52#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
53#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
54
55#define GPIO_GPCTR0_IOTR_MASK 0x00000001
56#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
57#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
58
59#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
60
61#define LOCK_CODE 0xffffffff
62#define UNLOCK_CODE 0x00000000
63
64struct bcm_kona_gpio {
65 void __iomem *reg_base;
66 int num_bank;
67 spinlock_t lock;
68 struct gpio_chip gpio_chip;
69 struct irq_domain *irq_domain;
70 struct bcm_kona_gpio_bank *banks;
71 struct platform_device *pdev;
72};
73
74struct bcm_kona_gpio_bank {
75 int id;
76 int irq;
77 /* Used in the interrupt handler */
78 struct bcm_kona_gpio *kona_gpio;
79};
80
81static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
82{
83 return container_of(chip, struct bcm_kona_gpio, gpio_chip);
84}
85
86static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
87 int bank_id, u32 lockcode)
88{
89 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
90 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
91}
92
93static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
94 unsigned gpio)
95{
96 u32 val;
97 unsigned long flags;
98 int bank_id = GPIO_BANK(gpio);
99
100 spin_lock_irqsave(&kona_gpio->lock, flags);
101
102 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
103 val |= BIT(gpio);
104 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
105
106 spin_unlock_irqrestore(&kona_gpio->lock, flags);
107}
108
109static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
110 unsigned gpio)
111{
112 u32 val;
113 unsigned long flags;
114 int bank_id = GPIO_BANK(gpio);
115
116 spin_lock_irqsave(&kona_gpio->lock, flags);
117
118 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
119 val &= ~BIT(gpio);
120 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
121
122 spin_unlock_irqrestore(&kona_gpio->lock, flags);
123}
124
125static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
126{
127 struct bcm_kona_gpio *kona_gpio;
128 void __iomem *reg_base;
129 int bank_id = GPIO_BANK(gpio);
130 int bit = GPIO_BIT(gpio);
131 u32 val, reg_offset;
132 unsigned long flags;
133
134 kona_gpio = to_kona_gpio(chip);
135 reg_base = kona_gpio->reg_base;
136 spin_lock_irqsave(&kona_gpio->lock, flags);
137
138 /* determine the GPIO pin direction */
139 val = readl(reg_base + GPIO_CONTROL(gpio));
140 val &= GPIO_GPCTR0_IOTR_MASK;
141
142 /* this function only applies to output pin */
143 if (GPIO_GPCTR0_IOTR_CMD_INPUT == val)
144 goto out;
145
146 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
147
148 val = readl(reg_base + reg_offset);
149 val |= BIT(bit);
150 writel(val, reg_base + reg_offset);
151
152out:
153 spin_unlock_irqrestore(&kona_gpio->lock, flags);
154}
155
156static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
157{
158 struct bcm_kona_gpio *kona_gpio;
159 void __iomem *reg_base;
160 int bank_id = GPIO_BANK(gpio);
161 int bit = GPIO_BIT(gpio);
162 u32 val, reg_offset;
163 unsigned long flags;
164
165 kona_gpio = to_kona_gpio(chip);
166 reg_base = kona_gpio->reg_base;
167 spin_lock_irqsave(&kona_gpio->lock, flags);
168
169 /* determine the GPIO pin direction */
170 val = readl(reg_base + GPIO_CONTROL(gpio));
171 val &= GPIO_GPCTR0_IOTR_MASK;
172
173 /* read the GPIO bank status */
174 reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
175 GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
176 val = readl(reg_base + reg_offset);
177
178 spin_unlock_irqrestore(&kona_gpio->lock, flags);
179
180 /* return the specified bit status */
181 return !!(val & BIT(bit));
182}
183
184static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
185{
186 struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
187
188 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
189 return 0;
190}
191
192static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
193{
194 struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
195
196 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
197}
198
199static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
200{
201 struct bcm_kona_gpio *kona_gpio;
202 void __iomem *reg_base;
203 u32 val;
204 unsigned long flags;
205
206 kona_gpio = to_kona_gpio(chip);
207 reg_base = kona_gpio->reg_base;
208 spin_lock_irqsave(&kona_gpio->lock, flags);
209
210 val = readl(reg_base + GPIO_CONTROL(gpio));
211 val &= ~GPIO_GPCTR0_IOTR_MASK;
212 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
213 writel(val, reg_base + GPIO_CONTROL(gpio));
214
215 spin_unlock_irqrestore(&kona_gpio->lock, flags);
216
217 return 0;
218}
219
220static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
221 unsigned gpio, int value)
222{
223 struct bcm_kona_gpio *kona_gpio;
224 void __iomem *reg_base;
225 int bank_id = GPIO_BANK(gpio);
226 int bit = GPIO_BIT(gpio);
227 u32 val, reg_offset;
228 unsigned long flags;
229
230 kona_gpio = to_kona_gpio(chip);
231 reg_base = kona_gpio->reg_base;
232 spin_lock_irqsave(&kona_gpio->lock, flags);
233
234 val = readl(reg_base + GPIO_CONTROL(gpio));
235 val &= ~GPIO_GPCTR0_IOTR_MASK;
236 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
237 writel(val, reg_base + GPIO_CONTROL(gpio));
238 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
239
240 val = readl(reg_base + reg_offset);
241 val |= BIT(bit);
242 writel(val, reg_base + reg_offset);
243
244 spin_unlock_irqrestore(&kona_gpio->lock, flags);
245
246 return 0;
247}
248
249static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
250{
251 struct bcm_kona_gpio *kona_gpio;
252
253 kona_gpio = to_kona_gpio(chip);
254 if (gpio >= kona_gpio->gpio_chip.ngpio)
255 return -ENXIO;
256 return irq_create_mapping(kona_gpio->irq_domain, gpio);
257}
258
259static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
260 unsigned debounce)
261{
262 struct bcm_kona_gpio *kona_gpio;
263 void __iomem *reg_base;
264 u32 val, res;
265 unsigned long flags;
266
267 kona_gpio = to_kona_gpio(chip);
268 reg_base = kona_gpio->reg_base;
269 /* debounce must be 1-128ms (or 0) */
270 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
271 dev_err(chip->dev, "Debounce value %u not in range\n",
272 debounce);
273 return -EINVAL;
274 }
275
276 /* calculate debounce bit value */
277 if (debounce != 0) {
278 /* Convert to ms */
279 debounce /= 1000;
280 /* find the MSB */
281 res = fls(debounce) - 1;
282 /* Check if MSB-1 is set (round up or down) */
283 if (res > 0 && (debounce & BIT(res - 1)))
284 res++;
285 }
286
287 /* spin lock for read-modify-write of the GPIO register */
288 spin_lock_irqsave(&kona_gpio->lock, flags);
289
290 val = readl(reg_base + GPIO_CONTROL(gpio));
291 val &= ~GPIO_GPCTR0_DBR_MASK;
292
293 if (debounce == 0) {
294 /* disable debounce */
295 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
296 } else {
297 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
298 (res << GPIO_GPCTR0_DBR_SHIFT);
299 }
300
301 writel(val, reg_base + GPIO_CONTROL(gpio));
302
303 spin_unlock_irqrestore(&kona_gpio->lock, flags);
304
305 return 0;
306}
307
308static struct gpio_chip template_chip = {
309 .label = "bcm-kona-gpio",
310 .owner = THIS_MODULE,
311 .request = bcm_kona_gpio_request,
312 .free = bcm_kona_gpio_free,
313 .direction_input = bcm_kona_gpio_direction_input,
314 .get = bcm_kona_gpio_get,
315 .direction_output = bcm_kona_gpio_direction_output,
316 .set = bcm_kona_gpio_set,
317 .set_debounce = bcm_kona_gpio_set_debounce,
318 .to_irq = bcm_kona_gpio_to_irq,
319 .base = 0,
320};
321
322static void bcm_kona_gpio_irq_ack(struct irq_data *d)
323{
324 struct bcm_kona_gpio *kona_gpio;
325 void __iomem *reg_base;
326 unsigned gpio = d->hwirq;
327 int bank_id = GPIO_BANK(gpio);
328 int bit = GPIO_BIT(gpio);
329 u32 val;
330 unsigned long flags;
331
332 kona_gpio = irq_data_get_irq_chip_data(d);
333 reg_base = kona_gpio->reg_base;
334 spin_lock_irqsave(&kona_gpio->lock, flags);
335
336 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
337 val |= BIT(bit);
338 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
339
340 spin_unlock_irqrestore(&kona_gpio->lock, flags);
341}
342
343static void bcm_kona_gpio_irq_mask(struct irq_data *d)
344{
345 struct bcm_kona_gpio *kona_gpio;
346 void __iomem *reg_base;
347 unsigned gpio = d->hwirq;
348 int bank_id = GPIO_BANK(gpio);
349 int bit = GPIO_BIT(gpio);
350 u32 val;
351 unsigned long flags;
352
353 kona_gpio = irq_data_get_irq_chip_data(d);
354 reg_base = kona_gpio->reg_base;
355 spin_lock_irqsave(&kona_gpio->lock, flags);
356
357 val = readl(reg_base + GPIO_INT_MASK(bank_id));
358 val |= BIT(bit);
359 writel(val, reg_base + GPIO_INT_MASK(bank_id));
360
361 spin_unlock_irqrestore(&kona_gpio->lock, flags);
362}
363
364static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
365{
366 struct bcm_kona_gpio *kona_gpio;
367 void __iomem *reg_base;
368 unsigned gpio = d->hwirq;
369 int bank_id = GPIO_BANK(gpio);
370 int bit = GPIO_BIT(gpio);
371 u32 val;
372 unsigned long flags;
373
374 kona_gpio = irq_data_get_irq_chip_data(d);
375 reg_base = kona_gpio->reg_base;
376 spin_lock_irqsave(&kona_gpio->lock, flags);
377
378 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
379 val |= BIT(bit);
380 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
381
382 spin_unlock_irqrestore(&kona_gpio->lock, flags);
383}
384
385static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
386{
387 struct bcm_kona_gpio *kona_gpio;
388 void __iomem *reg_base;
389 unsigned gpio = d->hwirq;
390 u32 lvl_type;
391 u32 val;
392 unsigned long flags;
393
394 kona_gpio = irq_data_get_irq_chip_data(d);
395 reg_base = kona_gpio->reg_base;
396 switch (type & IRQ_TYPE_SENSE_MASK) {
397 case IRQ_TYPE_EDGE_RISING:
398 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
399 break;
400
401 case IRQ_TYPE_EDGE_FALLING:
402 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
403 break;
404
405 case IRQ_TYPE_EDGE_BOTH:
406 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
407 break;
408
409 case IRQ_TYPE_LEVEL_HIGH:
410 case IRQ_TYPE_LEVEL_LOW:
411 /* BCM GPIO doesn't support level triggering */
412 default:
413 dev_err(kona_gpio->gpio_chip.dev,
414 "Invalid BCM GPIO irq type 0x%x\n", type);
415 return -EINVAL;
416 }
417
418 spin_lock_irqsave(&kona_gpio->lock, flags);
419
420 val = readl(reg_base + GPIO_CONTROL(gpio));
421 val &= ~GPIO_GPCTR0_ITR_MASK;
422 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
423 writel(val, reg_base + GPIO_CONTROL(gpio));
424
425 spin_unlock_irqrestore(&kona_gpio->lock, flags);
426
427 return 0;
428}
429
430static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
431{
432 void __iomem *reg_base;
433 int bit, bank_id;
434 unsigned long sta;
435 struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq);
436 struct irq_chip *chip = irq_desc_get_chip(desc);
437
438 chained_irq_enter(chip, desc);
439
440 /*
441 * For bank interrupts, we can't use chip_data to store the kona_gpio
442 * pointer, since GIC needs it for its own purposes. Therefore, we get
443 * our pointer from the bank structure.
444 */
445 reg_base = bank->kona_gpio->reg_base;
446 bank_id = bank->id;
447
448 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
449 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
450 for_each_set_bit(bit, &sta, 32) {
451 int hwirq = GPIO_PER_BANK * bank_id + bit;
452 int child_irq =
453 irq_find_mapping(bank->kona_gpio->irq_domain,
454 hwirq);
455 /*
456 * Clear interrupt before handler is called so we don't
457 * miss any interrupt occurred during executing them.
458 */
459 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
460 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
461 /* Invoke interrupt handler */
462 generic_handle_irq(child_irq);
463 }
464 }
465
466 chained_irq_exit(chip, desc);
467}
468
469static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
470{
471 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
472
473 if (gpio_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) {
474 dev_err(kona_gpio->gpio_chip.dev,
475 "unable to lock HW IRQ %lu for IRQ\n",
476 d->hwirq);
477 return -EINVAL;
478 }
479 return 0;
480}
481
482static void bcm_kona_gpio_irq_relres(struct irq_data *d)
483{
484 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
485
486 gpio_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
487}
488
489static struct irq_chip bcm_gpio_irq_chip = {
490 .name = "bcm-kona-gpio",
491 .irq_ack = bcm_kona_gpio_irq_ack,
492 .irq_mask = bcm_kona_gpio_irq_mask,
493 .irq_unmask = bcm_kona_gpio_irq_unmask,
494 .irq_set_type = bcm_kona_gpio_irq_set_type,
495 .irq_request_resources = bcm_kona_gpio_irq_reqres,
496 .irq_release_resources = bcm_kona_gpio_irq_relres,
497};
498
499static struct __initconst of_device_id bcm_kona_gpio_of_match[] = {
500 { .compatible = "brcm,kona-gpio" },
501 {}
502};
503
504MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
505
506/*
507 * This lock class tells lockdep that GPIO irqs are in a different
508 * category than their parents, so it won't report false recursion.
509 */
510static struct lock_class_key gpio_lock_class;
511
512static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
513 irq_hw_number_t hwirq)
514{
515 int ret;
516
517 ret = irq_set_chip_data(irq, d->host_data);
518 if (ret < 0)
519 return ret;
520 irq_set_lockdep_class(irq, &gpio_lock_class);
521 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
522#ifdef CONFIG_ARM
523 set_irq_flags(irq, IRQF_VALID);
524#else
525 irq_set_noprobe(irq);
526#endif
527
528 return 0;
529}
530
531static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
532{
533 irq_set_chip_and_handler(irq, NULL, NULL);
534 irq_set_chip_data(irq, NULL);
535}
536
537static struct irq_domain_ops bcm_kona_irq_ops = {
538 .map = bcm_kona_gpio_irq_map,
539 .unmap = bcm_kona_gpio_irq_unmap,
540 .xlate = irq_domain_xlate_twocell,
541};
542
543static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
544{
545 void __iomem *reg_base;
546 int i;
547
548 reg_base = kona_gpio->reg_base;
549 /* disable interrupts and clear status */
550 for (i = 0; i < kona_gpio->num_bank; i++) {
551 /* Unlock the entire bank first */
552 bcm_kona_gpio_write_lock_regs(kona_gpio, i, UNLOCK_CODE);
553 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
554 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
555 /* Now re-lock the bank */
556 bcm_kona_gpio_write_lock_regs(kona_gpio, i, LOCK_CODE);
557 }
558}
559
560static int bcm_kona_gpio_probe(struct platform_device *pdev)
561{
562 struct device *dev = &pdev->dev;
563 const struct of_device_id *match;
564 struct resource *res;
565 struct bcm_kona_gpio_bank *bank;
566 struct bcm_kona_gpio *kona_gpio;
567 struct gpio_chip *chip;
568 int ret;
569 int i;
570
571 match = of_match_device(bcm_kona_gpio_of_match, dev);
572 if (!match) {
573 dev_err(dev, "Failed to find gpio controller\n");
574 return -ENODEV;
575 }
576
577 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
578 if (!kona_gpio)
579 return -ENOMEM;
580
581 kona_gpio->gpio_chip = template_chip;
582 chip = &kona_gpio->gpio_chip;
583 kona_gpio->num_bank = of_irq_count(dev->of_node);
584 if (kona_gpio->num_bank == 0) {
585 dev_err(dev, "Couldn't determine # GPIO banks\n");
586 return -ENOENT;
587 }
588 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
589 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
590 GPIO_MAX_BANK_NUM);
591 return -ENXIO;
592 }
593 kona_gpio->banks = devm_kzalloc(dev,
594 kona_gpio->num_bank *
595 sizeof(*kona_gpio->banks), GFP_KERNEL);
596 if (!kona_gpio->banks)
597 return -ENOMEM;
598
599 kona_gpio->pdev = pdev;
600 platform_set_drvdata(pdev, kona_gpio);
601 chip->of_node = dev->of_node;
602 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
603
604 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
605 chip->ngpio,
606 &bcm_kona_irq_ops,
607 kona_gpio);
608 if (!kona_gpio->irq_domain) {
609 dev_err(dev, "Couldn't allocate IRQ domain\n");
610 return -ENXIO;
611 }
612
613 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
614 kona_gpio->reg_base = devm_ioremap_resource(dev, res);
615 if (IS_ERR(kona_gpio->reg_base)) {
616 ret = -ENXIO;
617 goto err_irq_domain;
618 }
619
620 for (i = 0; i < kona_gpio->num_bank; i++) {
621 bank = &kona_gpio->banks[i];
622 bank->id = i;
623 bank->irq = platform_get_irq(pdev, i);
624 bank->kona_gpio = kona_gpio;
625 if (bank->irq < 0) {
626 dev_err(dev, "Couldn't get IRQ for bank %d", i);
627 ret = -ENOENT;
628 goto err_irq_domain;
629 }
630 }
631
632 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
633
634 bcm_kona_gpio_reset(kona_gpio);
635
636 ret = gpiochip_add(chip);
637 if (ret < 0) {
638 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
639 goto err_irq_domain;
640 }
641 for (i = 0; i < chip->ngpio; i++) {
642 int irq = bcm_kona_gpio_to_irq(chip, i);
643 irq_set_lockdep_class(irq, &gpio_lock_class);
644 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip,
645 handle_simple_irq);
646#ifdef CONFIG_ARM
647 set_irq_flags(irq, IRQF_VALID);
648#else
649 irq_set_noprobe(irq);
650#endif
651 }
652 for (i = 0; i < kona_gpio->num_bank; i++) {
653 bank = &kona_gpio->banks[i];
654 irq_set_chained_handler(bank->irq, bcm_kona_gpio_irq_handler);
655 irq_set_handler_data(bank->irq, bank);
656 }
657
658 spin_lock_init(&kona_gpio->lock);
659
660 return 0;
661
662err_irq_domain:
663 irq_domain_remove(kona_gpio->irq_domain);
664
665 return ret;
666}
667
668static struct platform_driver bcm_kona_gpio_driver = {
669 .driver = {
670 .name = "bcm-kona-gpio",
671 .owner = THIS_MODULE,
672 .of_match_table = bcm_kona_gpio_of_match,
673 },
674 .probe = bcm_kona_gpio_probe,
675};
676
677module_platform_driver(bcm_kona_gpio_driver);
678
679MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
680MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
681MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Broadcom Kona GPIO Driver
4 *
5 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
6 * Copyright (C) 2012-2014 Broadcom Corporation
7 */
8
9#include <linux/bitops.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/gpio/driver.h>
13#include <linux/of_device.h>
14#include <linux/init.h>
15#include <linux/irqdomain.h>
16#include <linux/irqchip/chained_irq.h>
17
18#define BCM_GPIO_PASSWD 0x00a5a501
19#define GPIO_PER_BANK 32
20#define GPIO_MAX_BANK_NUM 8
21
22#define GPIO_BANK(gpio) ((gpio) >> 5)
23#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
24
25/* There is a GPIO control register for each GPIO */
26#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
27
28/* The remaining registers are per GPIO bank */
29#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
30#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
31#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
32#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
33#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
34#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
35#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
36#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
37
38#define GPIO_GPPWR_OFFSET 0x00000520
39
40#define GPIO_GPCTR0_DBR_SHIFT 5
41#define GPIO_GPCTR0_DBR_MASK 0x000001e0
42
43#define GPIO_GPCTR0_ITR_SHIFT 3
44#define GPIO_GPCTR0_ITR_MASK 0x00000018
45#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
46#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
47#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
48
49#define GPIO_GPCTR0_IOTR_MASK 0x00000001
50#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
51#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
52
53#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
54
55#define LOCK_CODE 0xffffffff
56#define UNLOCK_CODE 0x00000000
57
58struct bcm_kona_gpio {
59 void __iomem *reg_base;
60 int num_bank;
61 raw_spinlock_t lock;
62 struct gpio_chip gpio_chip;
63 struct irq_domain *irq_domain;
64 struct bcm_kona_gpio_bank *banks;
65 struct platform_device *pdev;
66};
67
68struct bcm_kona_gpio_bank {
69 int id;
70 int irq;
71 /* Used in the interrupt handler */
72 struct bcm_kona_gpio *kona_gpio;
73};
74
75static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
76 int bank_id, u32 lockcode)
77{
78 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
79 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
80}
81
82static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
83 unsigned gpio)
84{
85 u32 val;
86 unsigned long flags;
87 int bank_id = GPIO_BANK(gpio);
88
89 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
90
91 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
92 val |= BIT(gpio);
93 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
94
95 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
96}
97
98static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
99 unsigned gpio)
100{
101 u32 val;
102 unsigned long flags;
103 int bank_id = GPIO_BANK(gpio);
104
105 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
106
107 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
108 val &= ~BIT(gpio);
109 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
110
111 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
112}
113
114static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
115{
116 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
117 void __iomem *reg_base = kona_gpio->reg_base;
118 u32 val;
119
120 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
121 return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
122}
123
124static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
125{
126 struct bcm_kona_gpio *kona_gpio;
127 void __iomem *reg_base;
128 int bank_id = GPIO_BANK(gpio);
129 int bit = GPIO_BIT(gpio);
130 u32 val, reg_offset;
131 unsigned long flags;
132
133 kona_gpio = gpiochip_get_data(chip);
134 reg_base = kona_gpio->reg_base;
135 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
136
137 /* this function only applies to output pin */
138 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
139 goto out;
140
141 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
142
143 val = readl(reg_base + reg_offset);
144 val |= BIT(bit);
145 writel(val, reg_base + reg_offset);
146
147out:
148 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
149}
150
151static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
152{
153 struct bcm_kona_gpio *kona_gpio;
154 void __iomem *reg_base;
155 int bank_id = GPIO_BANK(gpio);
156 int bit = GPIO_BIT(gpio);
157 u32 val, reg_offset;
158 unsigned long flags;
159
160 kona_gpio = gpiochip_get_data(chip);
161 reg_base = kona_gpio->reg_base;
162 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
163
164 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
165 reg_offset = GPIO_IN_STATUS(bank_id);
166 else
167 reg_offset = GPIO_OUT_STATUS(bank_id);
168
169 /* read the GPIO bank status */
170 val = readl(reg_base + reg_offset);
171
172 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
173
174 /* return the specified bit status */
175 return !!(val & BIT(bit));
176}
177
178static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
179{
180 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
181
182 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
183 return 0;
184}
185
186static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
187{
188 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
189
190 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
191}
192
193static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
194{
195 struct bcm_kona_gpio *kona_gpio;
196 void __iomem *reg_base;
197 u32 val;
198 unsigned long flags;
199
200 kona_gpio = gpiochip_get_data(chip);
201 reg_base = kona_gpio->reg_base;
202 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
203
204 val = readl(reg_base + GPIO_CONTROL(gpio));
205 val &= ~GPIO_GPCTR0_IOTR_MASK;
206 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
207 writel(val, reg_base + GPIO_CONTROL(gpio));
208
209 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
210
211 return 0;
212}
213
214static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
215 unsigned gpio, int value)
216{
217 struct bcm_kona_gpio *kona_gpio;
218 void __iomem *reg_base;
219 int bank_id = GPIO_BANK(gpio);
220 int bit = GPIO_BIT(gpio);
221 u32 val, reg_offset;
222 unsigned long flags;
223
224 kona_gpio = gpiochip_get_data(chip);
225 reg_base = kona_gpio->reg_base;
226 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
227
228 val = readl(reg_base + GPIO_CONTROL(gpio));
229 val &= ~GPIO_GPCTR0_IOTR_MASK;
230 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
231 writel(val, reg_base + GPIO_CONTROL(gpio));
232 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
233
234 val = readl(reg_base + reg_offset);
235 val |= BIT(bit);
236 writel(val, reg_base + reg_offset);
237
238 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
239
240 return 0;
241}
242
243static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
244{
245 struct bcm_kona_gpio *kona_gpio;
246
247 kona_gpio = gpiochip_get_data(chip);
248 if (gpio >= kona_gpio->gpio_chip.ngpio)
249 return -ENXIO;
250 return irq_create_mapping(kona_gpio->irq_domain, gpio);
251}
252
253static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
254 unsigned debounce)
255{
256 struct bcm_kona_gpio *kona_gpio;
257 void __iomem *reg_base;
258 u32 val, res;
259 unsigned long flags;
260
261 kona_gpio = gpiochip_get_data(chip);
262 reg_base = kona_gpio->reg_base;
263 /* debounce must be 1-128ms (or 0) */
264 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
265 dev_err(chip->parent, "Debounce value %u not in range\n",
266 debounce);
267 return -EINVAL;
268 }
269
270 /* calculate debounce bit value */
271 if (debounce != 0) {
272 /* Convert to ms */
273 debounce /= 1000;
274 /* find the MSB */
275 res = fls(debounce) - 1;
276 /* Check if MSB-1 is set (round up or down) */
277 if (res > 0 && (debounce & BIT(res - 1)))
278 res++;
279 }
280
281 /* spin lock for read-modify-write of the GPIO register */
282 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
283
284 val = readl(reg_base + GPIO_CONTROL(gpio));
285 val &= ~GPIO_GPCTR0_DBR_MASK;
286
287 if (debounce == 0) {
288 /* disable debounce */
289 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
290 } else {
291 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
292 (res << GPIO_GPCTR0_DBR_SHIFT);
293 }
294
295 writel(val, reg_base + GPIO_CONTROL(gpio));
296
297 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
298
299 return 0;
300}
301
302static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
303 unsigned long config)
304{
305 u32 debounce;
306
307 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
308 return -ENOTSUPP;
309
310 debounce = pinconf_to_config_argument(config);
311 return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
312}
313
314static const struct gpio_chip template_chip = {
315 .label = "bcm-kona-gpio",
316 .owner = THIS_MODULE,
317 .request = bcm_kona_gpio_request,
318 .free = bcm_kona_gpio_free,
319 .get_direction = bcm_kona_gpio_get_dir,
320 .direction_input = bcm_kona_gpio_direction_input,
321 .get = bcm_kona_gpio_get,
322 .direction_output = bcm_kona_gpio_direction_output,
323 .set = bcm_kona_gpio_set,
324 .set_config = bcm_kona_gpio_set_config,
325 .to_irq = bcm_kona_gpio_to_irq,
326 .base = 0,
327};
328
329static void bcm_kona_gpio_irq_ack(struct irq_data *d)
330{
331 struct bcm_kona_gpio *kona_gpio;
332 void __iomem *reg_base;
333 unsigned gpio = d->hwirq;
334 int bank_id = GPIO_BANK(gpio);
335 int bit = GPIO_BIT(gpio);
336 u32 val;
337 unsigned long flags;
338
339 kona_gpio = irq_data_get_irq_chip_data(d);
340 reg_base = kona_gpio->reg_base;
341 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
342
343 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
344 val |= BIT(bit);
345 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
346
347 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
348}
349
350static void bcm_kona_gpio_irq_mask(struct irq_data *d)
351{
352 struct bcm_kona_gpio *kona_gpio;
353 void __iomem *reg_base;
354 unsigned gpio = d->hwirq;
355 int bank_id = GPIO_BANK(gpio);
356 int bit = GPIO_BIT(gpio);
357 u32 val;
358 unsigned long flags;
359
360 kona_gpio = irq_data_get_irq_chip_data(d);
361 reg_base = kona_gpio->reg_base;
362 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
363
364 val = readl(reg_base + GPIO_INT_MASK(bank_id));
365 val |= BIT(bit);
366 writel(val, reg_base + GPIO_INT_MASK(bank_id));
367 gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
368
369 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
370}
371
372static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
373{
374 struct bcm_kona_gpio *kona_gpio;
375 void __iomem *reg_base;
376 unsigned gpio = d->hwirq;
377 int bank_id = GPIO_BANK(gpio);
378 int bit = GPIO_BIT(gpio);
379 u32 val;
380 unsigned long flags;
381
382 kona_gpio = irq_data_get_irq_chip_data(d);
383 reg_base = kona_gpio->reg_base;
384 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
385
386 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
387 val |= BIT(bit);
388 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
389 gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
390
391 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
392}
393
394static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
395{
396 struct bcm_kona_gpio *kona_gpio;
397 void __iomem *reg_base;
398 unsigned gpio = d->hwirq;
399 u32 lvl_type;
400 u32 val;
401 unsigned long flags;
402
403 kona_gpio = irq_data_get_irq_chip_data(d);
404 reg_base = kona_gpio->reg_base;
405 switch (type & IRQ_TYPE_SENSE_MASK) {
406 case IRQ_TYPE_EDGE_RISING:
407 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
408 break;
409
410 case IRQ_TYPE_EDGE_FALLING:
411 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
412 break;
413
414 case IRQ_TYPE_EDGE_BOTH:
415 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
416 break;
417
418 case IRQ_TYPE_LEVEL_HIGH:
419 case IRQ_TYPE_LEVEL_LOW:
420 /* BCM GPIO doesn't support level triggering */
421 default:
422 dev_err(kona_gpio->gpio_chip.parent,
423 "Invalid BCM GPIO irq type 0x%x\n", type);
424 return -EINVAL;
425 }
426
427 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
428
429 val = readl(reg_base + GPIO_CONTROL(gpio));
430 val &= ~GPIO_GPCTR0_ITR_MASK;
431 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
432 writel(val, reg_base + GPIO_CONTROL(gpio));
433
434 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
435
436 return 0;
437}
438
439static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
440{
441 void __iomem *reg_base;
442 int bit, bank_id;
443 unsigned long sta;
444 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
445 struct irq_chip *chip = irq_desc_get_chip(desc);
446
447 chained_irq_enter(chip, desc);
448
449 /*
450 * For bank interrupts, we can't use chip_data to store the kona_gpio
451 * pointer, since GIC needs it for its own purposes. Therefore, we get
452 * our pointer from the bank structure.
453 */
454 reg_base = bank->kona_gpio->reg_base;
455 bank_id = bank->id;
456
457 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
458 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
459 for_each_set_bit(bit, &sta, 32) {
460 int hwirq = GPIO_PER_BANK * bank_id + bit;
461 /*
462 * Clear interrupt before handler is called so we don't
463 * miss any interrupt occurred during executing them.
464 */
465 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
466 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
467 /* Invoke interrupt handler */
468 generic_handle_domain_irq(bank->kona_gpio->irq_domain,
469 hwirq);
470 }
471 }
472
473 chained_irq_exit(chip, desc);
474}
475
476static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
477{
478 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
479
480 return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
481}
482
483static void bcm_kona_gpio_irq_relres(struct irq_data *d)
484{
485 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
486
487 gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
488}
489
490static struct irq_chip bcm_gpio_irq_chip = {
491 .name = "bcm-kona-gpio",
492 .irq_ack = bcm_kona_gpio_irq_ack,
493 .irq_mask = bcm_kona_gpio_irq_mask,
494 .irq_unmask = bcm_kona_gpio_irq_unmask,
495 .irq_set_type = bcm_kona_gpio_irq_set_type,
496 .irq_request_resources = bcm_kona_gpio_irq_reqres,
497 .irq_release_resources = bcm_kona_gpio_irq_relres,
498};
499
500static struct of_device_id const bcm_kona_gpio_of_match[] = {
501 { .compatible = "brcm,kona-gpio" },
502 {}
503};
504
505/*
506 * This lock class tells lockdep that GPIO irqs are in a different
507 * category than their parents, so it won't report false recursion.
508 */
509static struct lock_class_key gpio_lock_class;
510static struct lock_class_key gpio_request_class;
511
512static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
513 irq_hw_number_t hwirq)
514{
515 int ret;
516
517 ret = irq_set_chip_data(irq, d->host_data);
518 if (ret < 0)
519 return ret;
520 irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
521 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
522 irq_set_noprobe(irq);
523
524 return 0;
525}
526
527static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
528{
529 irq_set_chip_and_handler(irq, NULL, NULL);
530 irq_set_chip_data(irq, NULL);
531}
532
533static const struct irq_domain_ops bcm_kona_irq_ops = {
534 .map = bcm_kona_gpio_irq_map,
535 .unmap = bcm_kona_gpio_irq_unmap,
536 .xlate = irq_domain_xlate_twocell,
537};
538
539static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
540{
541 void __iomem *reg_base;
542 int i;
543
544 reg_base = kona_gpio->reg_base;
545 /* disable interrupts and clear status */
546 for (i = 0; i < kona_gpio->num_bank; i++) {
547 /* Unlock the entire bank first */
548 bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
549 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
550 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
551 /* Now re-lock the bank */
552 bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
553 }
554}
555
556static int bcm_kona_gpio_probe(struct platform_device *pdev)
557{
558 struct device *dev = &pdev->dev;
559 const struct of_device_id *match;
560 struct bcm_kona_gpio_bank *bank;
561 struct bcm_kona_gpio *kona_gpio;
562 struct gpio_chip *chip;
563 int ret;
564 int i;
565
566 match = of_match_device(bcm_kona_gpio_of_match, dev);
567 if (!match) {
568 dev_err(dev, "Failed to find gpio controller\n");
569 return -ENODEV;
570 }
571
572 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
573 if (!kona_gpio)
574 return -ENOMEM;
575
576 kona_gpio->gpio_chip = template_chip;
577 chip = &kona_gpio->gpio_chip;
578 ret = platform_irq_count(pdev);
579 if (!ret) {
580 dev_err(dev, "Couldn't determine # GPIO banks\n");
581 return -ENOENT;
582 } else if (ret < 0) {
583 return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
584 }
585 kona_gpio->num_bank = ret;
586
587 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
588 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
589 GPIO_MAX_BANK_NUM);
590 return -ENXIO;
591 }
592 kona_gpio->banks = devm_kcalloc(dev,
593 kona_gpio->num_bank,
594 sizeof(*kona_gpio->banks),
595 GFP_KERNEL);
596 if (!kona_gpio->banks)
597 return -ENOMEM;
598
599 kona_gpio->pdev = pdev;
600 platform_set_drvdata(pdev, kona_gpio);
601 chip->parent = dev;
602 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
603
604 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
605 chip->ngpio,
606 &bcm_kona_irq_ops,
607 kona_gpio);
608 if (!kona_gpio->irq_domain) {
609 dev_err(dev, "Couldn't allocate IRQ domain\n");
610 return -ENXIO;
611 }
612
613 kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
614 if (IS_ERR(kona_gpio->reg_base)) {
615 ret = PTR_ERR(kona_gpio->reg_base);
616 goto err_irq_domain;
617 }
618
619 for (i = 0; i < kona_gpio->num_bank; i++) {
620 bank = &kona_gpio->banks[i];
621 bank->id = i;
622 bank->irq = platform_get_irq(pdev, i);
623 bank->kona_gpio = kona_gpio;
624 if (bank->irq < 0) {
625 dev_err(dev, "Couldn't get IRQ for bank %d", i);
626 ret = -ENOENT;
627 goto err_irq_domain;
628 }
629 }
630
631 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
632
633 bcm_kona_gpio_reset(kona_gpio);
634
635 ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
636 if (ret < 0) {
637 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
638 goto err_irq_domain;
639 }
640 for (i = 0; i < kona_gpio->num_bank; i++) {
641 bank = &kona_gpio->banks[i];
642 irq_set_chained_handler_and_data(bank->irq,
643 bcm_kona_gpio_irq_handler,
644 bank);
645 }
646
647 raw_spin_lock_init(&kona_gpio->lock);
648
649 return 0;
650
651err_irq_domain:
652 irq_domain_remove(kona_gpio->irq_domain);
653
654 return ret;
655}
656
657static struct platform_driver bcm_kona_gpio_driver = {
658 .driver = {
659 .name = "bcm-kona-gpio",
660 .of_match_table = bcm_kona_gpio_of_match,
661 },
662 .probe = bcm_kona_gpio_probe,
663};
664builtin_platform_driver(bcm_kona_gpio_driver);