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1/*
2 * Copyright (C) 2012-2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/of_device.h>
19#include <linux/of_irq.h>
20#include <linux/module.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip/chained_irq.h>
23
24#define BCM_GPIO_PASSWD 0x00a5a501
25#define GPIO_PER_BANK 32
26#define GPIO_MAX_BANK_NUM 8
27
28#define GPIO_BANK(gpio) ((gpio) >> 5)
29#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
30
31/* There is a GPIO control register for each GPIO */
32#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
33
34/* The remaining registers are per GPIO bank */
35#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
36#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
37#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
38#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
39#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
40#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
41#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
42#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
43
44#define GPIO_GPPWR_OFFSET 0x00000520
45
46#define GPIO_GPCTR0_DBR_SHIFT 5
47#define GPIO_GPCTR0_DBR_MASK 0x000001e0
48
49#define GPIO_GPCTR0_ITR_SHIFT 3
50#define GPIO_GPCTR0_ITR_MASK 0x00000018
51#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
52#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
53#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
54
55#define GPIO_GPCTR0_IOTR_MASK 0x00000001
56#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
57#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
58
59#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
60
61#define LOCK_CODE 0xffffffff
62#define UNLOCK_CODE 0x00000000
63
64struct bcm_kona_gpio {
65 void __iomem *reg_base;
66 int num_bank;
67 spinlock_t lock;
68 struct gpio_chip gpio_chip;
69 struct irq_domain *irq_domain;
70 struct bcm_kona_gpio_bank *banks;
71 struct platform_device *pdev;
72};
73
74struct bcm_kona_gpio_bank {
75 int id;
76 int irq;
77 /* Used in the interrupt handler */
78 struct bcm_kona_gpio *kona_gpio;
79};
80
81static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
82{
83 return container_of(chip, struct bcm_kona_gpio, gpio_chip);
84}
85
86static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
87 int bank_id, u32 lockcode)
88{
89 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
90 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
91}
92
93static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
94 unsigned gpio)
95{
96 u32 val;
97 unsigned long flags;
98 int bank_id = GPIO_BANK(gpio);
99
100 spin_lock_irqsave(&kona_gpio->lock, flags);
101
102 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
103 val |= BIT(gpio);
104 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
105
106 spin_unlock_irqrestore(&kona_gpio->lock, flags);
107}
108
109static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
110 unsigned gpio)
111{
112 u32 val;
113 unsigned long flags;
114 int bank_id = GPIO_BANK(gpio);
115
116 spin_lock_irqsave(&kona_gpio->lock, flags);
117
118 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
119 val &= ~BIT(gpio);
120 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
121
122 spin_unlock_irqrestore(&kona_gpio->lock, flags);
123}
124
125static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
126{
127 struct bcm_kona_gpio *kona_gpio;
128 void __iomem *reg_base;
129 int bank_id = GPIO_BANK(gpio);
130 int bit = GPIO_BIT(gpio);
131 u32 val, reg_offset;
132 unsigned long flags;
133
134 kona_gpio = to_kona_gpio(chip);
135 reg_base = kona_gpio->reg_base;
136 spin_lock_irqsave(&kona_gpio->lock, flags);
137
138 /* determine the GPIO pin direction */
139 val = readl(reg_base + GPIO_CONTROL(gpio));
140 val &= GPIO_GPCTR0_IOTR_MASK;
141
142 /* this function only applies to output pin */
143 if (GPIO_GPCTR0_IOTR_CMD_INPUT == val)
144 goto out;
145
146 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
147
148 val = readl(reg_base + reg_offset);
149 val |= BIT(bit);
150 writel(val, reg_base + reg_offset);
151
152out:
153 spin_unlock_irqrestore(&kona_gpio->lock, flags);
154}
155
156static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
157{
158 struct bcm_kona_gpio *kona_gpio;
159 void __iomem *reg_base;
160 int bank_id = GPIO_BANK(gpio);
161 int bit = GPIO_BIT(gpio);
162 u32 val, reg_offset;
163 unsigned long flags;
164
165 kona_gpio = to_kona_gpio(chip);
166 reg_base = kona_gpio->reg_base;
167 spin_lock_irqsave(&kona_gpio->lock, flags);
168
169 /* determine the GPIO pin direction */
170 val = readl(reg_base + GPIO_CONTROL(gpio));
171 val &= GPIO_GPCTR0_IOTR_MASK;
172
173 /* read the GPIO bank status */
174 reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
175 GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
176 val = readl(reg_base + reg_offset);
177
178 spin_unlock_irqrestore(&kona_gpio->lock, flags);
179
180 /* return the specified bit status */
181 return !!(val & BIT(bit));
182}
183
184static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
185{
186 struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
187
188 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
189 return 0;
190}
191
192static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
193{
194 struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
195
196 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
197}
198
199static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
200{
201 struct bcm_kona_gpio *kona_gpio;
202 void __iomem *reg_base;
203 u32 val;
204 unsigned long flags;
205
206 kona_gpio = to_kona_gpio(chip);
207 reg_base = kona_gpio->reg_base;
208 spin_lock_irqsave(&kona_gpio->lock, flags);
209
210 val = readl(reg_base + GPIO_CONTROL(gpio));
211 val &= ~GPIO_GPCTR0_IOTR_MASK;
212 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
213 writel(val, reg_base + GPIO_CONTROL(gpio));
214
215 spin_unlock_irqrestore(&kona_gpio->lock, flags);
216
217 return 0;
218}
219
220static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
221 unsigned gpio, int value)
222{
223 struct bcm_kona_gpio *kona_gpio;
224 void __iomem *reg_base;
225 int bank_id = GPIO_BANK(gpio);
226 int bit = GPIO_BIT(gpio);
227 u32 val, reg_offset;
228 unsigned long flags;
229
230 kona_gpio = to_kona_gpio(chip);
231 reg_base = kona_gpio->reg_base;
232 spin_lock_irqsave(&kona_gpio->lock, flags);
233
234 val = readl(reg_base + GPIO_CONTROL(gpio));
235 val &= ~GPIO_GPCTR0_IOTR_MASK;
236 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
237 writel(val, reg_base + GPIO_CONTROL(gpio));
238 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
239
240 val = readl(reg_base + reg_offset);
241 val |= BIT(bit);
242 writel(val, reg_base + reg_offset);
243
244 spin_unlock_irqrestore(&kona_gpio->lock, flags);
245
246 return 0;
247}
248
249static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
250{
251 struct bcm_kona_gpio *kona_gpio;
252
253 kona_gpio = to_kona_gpio(chip);
254 if (gpio >= kona_gpio->gpio_chip.ngpio)
255 return -ENXIO;
256 return irq_create_mapping(kona_gpio->irq_domain, gpio);
257}
258
259static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
260 unsigned debounce)
261{
262 struct bcm_kona_gpio *kona_gpio;
263 void __iomem *reg_base;
264 u32 val, res;
265 unsigned long flags;
266
267 kona_gpio = to_kona_gpio(chip);
268 reg_base = kona_gpio->reg_base;
269 /* debounce must be 1-128ms (or 0) */
270 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
271 dev_err(chip->dev, "Debounce value %u not in range\n",
272 debounce);
273 return -EINVAL;
274 }
275
276 /* calculate debounce bit value */
277 if (debounce != 0) {
278 /* Convert to ms */
279 debounce /= 1000;
280 /* find the MSB */
281 res = fls(debounce) - 1;
282 /* Check if MSB-1 is set (round up or down) */
283 if (res > 0 && (debounce & BIT(res - 1)))
284 res++;
285 }
286
287 /* spin lock for read-modify-write of the GPIO register */
288 spin_lock_irqsave(&kona_gpio->lock, flags);
289
290 val = readl(reg_base + GPIO_CONTROL(gpio));
291 val &= ~GPIO_GPCTR0_DBR_MASK;
292
293 if (debounce == 0) {
294 /* disable debounce */
295 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
296 } else {
297 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
298 (res << GPIO_GPCTR0_DBR_SHIFT);
299 }
300
301 writel(val, reg_base + GPIO_CONTROL(gpio));
302
303 spin_unlock_irqrestore(&kona_gpio->lock, flags);
304
305 return 0;
306}
307
308static struct gpio_chip template_chip = {
309 .label = "bcm-kona-gpio",
310 .owner = THIS_MODULE,
311 .request = bcm_kona_gpio_request,
312 .free = bcm_kona_gpio_free,
313 .direction_input = bcm_kona_gpio_direction_input,
314 .get = bcm_kona_gpio_get,
315 .direction_output = bcm_kona_gpio_direction_output,
316 .set = bcm_kona_gpio_set,
317 .set_debounce = bcm_kona_gpio_set_debounce,
318 .to_irq = bcm_kona_gpio_to_irq,
319 .base = 0,
320};
321
322static void bcm_kona_gpio_irq_ack(struct irq_data *d)
323{
324 struct bcm_kona_gpio *kona_gpio;
325 void __iomem *reg_base;
326 unsigned gpio = d->hwirq;
327 int bank_id = GPIO_BANK(gpio);
328 int bit = GPIO_BIT(gpio);
329 u32 val;
330 unsigned long flags;
331
332 kona_gpio = irq_data_get_irq_chip_data(d);
333 reg_base = kona_gpio->reg_base;
334 spin_lock_irqsave(&kona_gpio->lock, flags);
335
336 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
337 val |= BIT(bit);
338 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
339
340 spin_unlock_irqrestore(&kona_gpio->lock, flags);
341}
342
343static void bcm_kona_gpio_irq_mask(struct irq_data *d)
344{
345 struct bcm_kona_gpio *kona_gpio;
346 void __iomem *reg_base;
347 unsigned gpio = d->hwirq;
348 int bank_id = GPIO_BANK(gpio);
349 int bit = GPIO_BIT(gpio);
350 u32 val;
351 unsigned long flags;
352
353 kona_gpio = irq_data_get_irq_chip_data(d);
354 reg_base = kona_gpio->reg_base;
355 spin_lock_irqsave(&kona_gpio->lock, flags);
356
357 val = readl(reg_base + GPIO_INT_MASK(bank_id));
358 val |= BIT(bit);
359 writel(val, reg_base + GPIO_INT_MASK(bank_id));
360
361 spin_unlock_irqrestore(&kona_gpio->lock, flags);
362}
363
364static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
365{
366 struct bcm_kona_gpio *kona_gpio;
367 void __iomem *reg_base;
368 unsigned gpio = d->hwirq;
369 int bank_id = GPIO_BANK(gpio);
370 int bit = GPIO_BIT(gpio);
371 u32 val;
372 unsigned long flags;
373
374 kona_gpio = irq_data_get_irq_chip_data(d);
375 reg_base = kona_gpio->reg_base;
376 spin_lock_irqsave(&kona_gpio->lock, flags);
377
378 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
379 val |= BIT(bit);
380 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
381
382 spin_unlock_irqrestore(&kona_gpio->lock, flags);
383}
384
385static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
386{
387 struct bcm_kona_gpio *kona_gpio;
388 void __iomem *reg_base;
389 unsigned gpio = d->hwirq;
390 u32 lvl_type;
391 u32 val;
392 unsigned long flags;
393
394 kona_gpio = irq_data_get_irq_chip_data(d);
395 reg_base = kona_gpio->reg_base;
396 switch (type & IRQ_TYPE_SENSE_MASK) {
397 case IRQ_TYPE_EDGE_RISING:
398 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
399 break;
400
401 case IRQ_TYPE_EDGE_FALLING:
402 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
403 break;
404
405 case IRQ_TYPE_EDGE_BOTH:
406 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
407 break;
408
409 case IRQ_TYPE_LEVEL_HIGH:
410 case IRQ_TYPE_LEVEL_LOW:
411 /* BCM GPIO doesn't support level triggering */
412 default:
413 dev_err(kona_gpio->gpio_chip.dev,
414 "Invalid BCM GPIO irq type 0x%x\n", type);
415 return -EINVAL;
416 }
417
418 spin_lock_irqsave(&kona_gpio->lock, flags);
419
420 val = readl(reg_base + GPIO_CONTROL(gpio));
421 val &= ~GPIO_GPCTR0_ITR_MASK;
422 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
423 writel(val, reg_base + GPIO_CONTROL(gpio));
424
425 spin_unlock_irqrestore(&kona_gpio->lock, flags);
426
427 return 0;
428}
429
430static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
431{
432 void __iomem *reg_base;
433 int bit, bank_id;
434 unsigned long sta;
435 struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq);
436 struct irq_chip *chip = irq_desc_get_chip(desc);
437
438 chained_irq_enter(chip, desc);
439
440 /*
441 * For bank interrupts, we can't use chip_data to store the kona_gpio
442 * pointer, since GIC needs it for its own purposes. Therefore, we get
443 * our pointer from the bank structure.
444 */
445 reg_base = bank->kona_gpio->reg_base;
446 bank_id = bank->id;
447
448 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
449 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
450 for_each_set_bit(bit, &sta, 32) {
451 int hwirq = GPIO_PER_BANK * bank_id + bit;
452 int child_irq =
453 irq_find_mapping(bank->kona_gpio->irq_domain,
454 hwirq);
455 /*
456 * Clear interrupt before handler is called so we don't
457 * miss any interrupt occurred during executing them.
458 */
459 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
460 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
461 /* Invoke interrupt handler */
462 generic_handle_irq(child_irq);
463 }
464 }
465
466 chained_irq_exit(chip, desc);
467}
468
469static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
470{
471 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
472
473 if (gpio_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) {
474 dev_err(kona_gpio->gpio_chip.dev,
475 "unable to lock HW IRQ %lu for IRQ\n",
476 d->hwirq);
477 return -EINVAL;
478 }
479 return 0;
480}
481
482static void bcm_kona_gpio_irq_relres(struct irq_data *d)
483{
484 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
485
486 gpio_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
487}
488
489static struct irq_chip bcm_gpio_irq_chip = {
490 .name = "bcm-kona-gpio",
491 .irq_ack = bcm_kona_gpio_irq_ack,
492 .irq_mask = bcm_kona_gpio_irq_mask,
493 .irq_unmask = bcm_kona_gpio_irq_unmask,
494 .irq_set_type = bcm_kona_gpio_irq_set_type,
495 .irq_request_resources = bcm_kona_gpio_irq_reqres,
496 .irq_release_resources = bcm_kona_gpio_irq_relres,
497};
498
499static struct __initconst of_device_id bcm_kona_gpio_of_match[] = {
500 { .compatible = "brcm,kona-gpio" },
501 {}
502};
503
504MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
505
506/*
507 * This lock class tells lockdep that GPIO irqs are in a different
508 * category than their parents, so it won't report false recursion.
509 */
510static struct lock_class_key gpio_lock_class;
511
512static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
513 irq_hw_number_t hwirq)
514{
515 int ret;
516
517 ret = irq_set_chip_data(irq, d->host_data);
518 if (ret < 0)
519 return ret;
520 irq_set_lockdep_class(irq, &gpio_lock_class);
521 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
522#ifdef CONFIG_ARM
523 set_irq_flags(irq, IRQF_VALID);
524#else
525 irq_set_noprobe(irq);
526#endif
527
528 return 0;
529}
530
531static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
532{
533 irq_set_chip_and_handler(irq, NULL, NULL);
534 irq_set_chip_data(irq, NULL);
535}
536
537static struct irq_domain_ops bcm_kona_irq_ops = {
538 .map = bcm_kona_gpio_irq_map,
539 .unmap = bcm_kona_gpio_irq_unmap,
540 .xlate = irq_domain_xlate_twocell,
541};
542
543static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
544{
545 void __iomem *reg_base;
546 int i;
547
548 reg_base = kona_gpio->reg_base;
549 /* disable interrupts and clear status */
550 for (i = 0; i < kona_gpio->num_bank; i++) {
551 /* Unlock the entire bank first */
552 bcm_kona_gpio_write_lock_regs(kona_gpio, i, UNLOCK_CODE);
553 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
554 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
555 /* Now re-lock the bank */
556 bcm_kona_gpio_write_lock_regs(kona_gpio, i, LOCK_CODE);
557 }
558}
559
560static int bcm_kona_gpio_probe(struct platform_device *pdev)
561{
562 struct device *dev = &pdev->dev;
563 const struct of_device_id *match;
564 struct resource *res;
565 struct bcm_kona_gpio_bank *bank;
566 struct bcm_kona_gpio *kona_gpio;
567 struct gpio_chip *chip;
568 int ret;
569 int i;
570
571 match = of_match_device(bcm_kona_gpio_of_match, dev);
572 if (!match) {
573 dev_err(dev, "Failed to find gpio controller\n");
574 return -ENODEV;
575 }
576
577 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
578 if (!kona_gpio)
579 return -ENOMEM;
580
581 kona_gpio->gpio_chip = template_chip;
582 chip = &kona_gpio->gpio_chip;
583 kona_gpio->num_bank = of_irq_count(dev->of_node);
584 if (kona_gpio->num_bank == 0) {
585 dev_err(dev, "Couldn't determine # GPIO banks\n");
586 return -ENOENT;
587 }
588 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
589 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
590 GPIO_MAX_BANK_NUM);
591 return -ENXIO;
592 }
593 kona_gpio->banks = devm_kzalloc(dev,
594 kona_gpio->num_bank *
595 sizeof(*kona_gpio->banks), GFP_KERNEL);
596 if (!kona_gpio->banks)
597 return -ENOMEM;
598
599 kona_gpio->pdev = pdev;
600 platform_set_drvdata(pdev, kona_gpio);
601 chip->of_node = dev->of_node;
602 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
603
604 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
605 chip->ngpio,
606 &bcm_kona_irq_ops,
607 kona_gpio);
608 if (!kona_gpio->irq_domain) {
609 dev_err(dev, "Couldn't allocate IRQ domain\n");
610 return -ENXIO;
611 }
612
613 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
614 kona_gpio->reg_base = devm_ioremap_resource(dev, res);
615 if (IS_ERR(kona_gpio->reg_base)) {
616 ret = -ENXIO;
617 goto err_irq_domain;
618 }
619
620 for (i = 0; i < kona_gpio->num_bank; i++) {
621 bank = &kona_gpio->banks[i];
622 bank->id = i;
623 bank->irq = platform_get_irq(pdev, i);
624 bank->kona_gpio = kona_gpio;
625 if (bank->irq < 0) {
626 dev_err(dev, "Couldn't get IRQ for bank %d", i);
627 ret = -ENOENT;
628 goto err_irq_domain;
629 }
630 }
631
632 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
633
634 bcm_kona_gpio_reset(kona_gpio);
635
636 ret = gpiochip_add(chip);
637 if (ret < 0) {
638 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
639 goto err_irq_domain;
640 }
641 for (i = 0; i < chip->ngpio; i++) {
642 int irq = bcm_kona_gpio_to_irq(chip, i);
643 irq_set_lockdep_class(irq, &gpio_lock_class);
644 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip,
645 handle_simple_irq);
646#ifdef CONFIG_ARM
647 set_irq_flags(irq, IRQF_VALID);
648#else
649 irq_set_noprobe(irq);
650#endif
651 }
652 for (i = 0; i < kona_gpio->num_bank; i++) {
653 bank = &kona_gpio->banks[i];
654 irq_set_chained_handler(bank->irq, bcm_kona_gpio_irq_handler);
655 irq_set_handler_data(bank->irq, bank);
656 }
657
658 spin_lock_init(&kona_gpio->lock);
659
660 return 0;
661
662err_irq_domain:
663 irq_domain_remove(kona_gpio->irq_domain);
664
665 return ret;
666}
667
668static struct platform_driver bcm_kona_gpio_driver = {
669 .driver = {
670 .name = "bcm-kona-gpio",
671 .owner = THIS_MODULE,
672 .of_match_table = bcm_kona_gpio_of_match,
673 },
674 .probe = bcm_kona_gpio_probe,
675};
676
677module_platform_driver(bcm_kona_gpio_driver);
678
679MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
680MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
681MODULE_LICENSE("GPL v2");
1/*
2 * Broadcom Kona GPIO Driver
3 *
4 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
5 * Copyright (C) 2012-2014 Broadcom Corporation
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/gpio/driver.h>
21#include <linux/of_device.h>
22#include <linux/of_irq.h>
23#include <linux/init.h>
24#include <linux/irqdomain.h>
25#include <linux/irqchip/chained_irq.h>
26
27#define BCM_GPIO_PASSWD 0x00a5a501
28#define GPIO_PER_BANK 32
29#define GPIO_MAX_BANK_NUM 8
30
31#define GPIO_BANK(gpio) ((gpio) >> 5)
32#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
33
34/* There is a GPIO control register for each GPIO */
35#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
36
37/* The remaining registers are per GPIO bank */
38#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
39#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
40#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
41#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
42#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
43#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
44#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
45#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
46
47#define GPIO_GPPWR_OFFSET 0x00000520
48
49#define GPIO_GPCTR0_DBR_SHIFT 5
50#define GPIO_GPCTR0_DBR_MASK 0x000001e0
51
52#define GPIO_GPCTR0_ITR_SHIFT 3
53#define GPIO_GPCTR0_ITR_MASK 0x00000018
54#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
55#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
56#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
57
58#define GPIO_GPCTR0_IOTR_MASK 0x00000001
59#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
60#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
61
62#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
63
64#define LOCK_CODE 0xffffffff
65#define UNLOCK_CODE 0x00000000
66
67struct bcm_kona_gpio {
68 void __iomem *reg_base;
69 int num_bank;
70 raw_spinlock_t lock;
71 struct gpio_chip gpio_chip;
72 struct irq_domain *irq_domain;
73 struct bcm_kona_gpio_bank *banks;
74 struct platform_device *pdev;
75};
76
77struct bcm_kona_gpio_bank {
78 int id;
79 int irq;
80 /* Used in the interrupt handler */
81 struct bcm_kona_gpio *kona_gpio;
82};
83
84static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
85 int bank_id, u32 lockcode)
86{
87 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
88 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
89}
90
91static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
92 unsigned gpio)
93{
94 u32 val;
95 unsigned long flags;
96 int bank_id = GPIO_BANK(gpio);
97
98 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
99
100 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
101 val |= BIT(gpio);
102 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
103
104 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
105}
106
107static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
108 unsigned gpio)
109{
110 u32 val;
111 unsigned long flags;
112 int bank_id = GPIO_BANK(gpio);
113
114 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
115
116 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
117 val &= ~BIT(gpio);
118 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
119
120 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
121}
122
123static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
124{
125 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
126 void __iomem *reg_base = kona_gpio->reg_base;
127 u32 val;
128
129 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
130 return !!val;
131}
132
133static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
134{
135 struct bcm_kona_gpio *kona_gpio;
136 void __iomem *reg_base;
137 int bank_id = GPIO_BANK(gpio);
138 int bit = GPIO_BIT(gpio);
139 u32 val, reg_offset;
140 unsigned long flags;
141
142 kona_gpio = gpiochip_get_data(chip);
143 reg_base = kona_gpio->reg_base;
144 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
145
146 /* this function only applies to output pin */
147 if (bcm_kona_gpio_get_dir(chip, gpio) == 1)
148 goto out;
149
150 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
151
152 val = readl(reg_base + reg_offset);
153 val |= BIT(bit);
154 writel(val, reg_base + reg_offset);
155
156out:
157 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
158}
159
160static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
161{
162 struct bcm_kona_gpio *kona_gpio;
163 void __iomem *reg_base;
164 int bank_id = GPIO_BANK(gpio);
165 int bit = GPIO_BIT(gpio);
166 u32 val, reg_offset;
167 unsigned long flags;
168
169 kona_gpio = gpiochip_get_data(chip);
170 reg_base = kona_gpio->reg_base;
171 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
172
173 if (bcm_kona_gpio_get_dir(chip, gpio) == 1)
174 reg_offset = GPIO_IN_STATUS(bank_id);
175 else
176 reg_offset = GPIO_OUT_STATUS(bank_id);
177
178 /* read the GPIO bank status */
179 val = readl(reg_base + reg_offset);
180
181 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
182
183 /* return the specified bit status */
184 return !!(val & BIT(bit));
185}
186
187static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
188{
189 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
190
191 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
192 return 0;
193}
194
195static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
196{
197 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
198
199 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
200}
201
202static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
203{
204 struct bcm_kona_gpio *kona_gpio;
205 void __iomem *reg_base;
206 u32 val;
207 unsigned long flags;
208
209 kona_gpio = gpiochip_get_data(chip);
210 reg_base = kona_gpio->reg_base;
211 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
212
213 val = readl(reg_base + GPIO_CONTROL(gpio));
214 val &= ~GPIO_GPCTR0_IOTR_MASK;
215 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
216 writel(val, reg_base + GPIO_CONTROL(gpio));
217
218 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
219
220 return 0;
221}
222
223static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
224 unsigned gpio, int value)
225{
226 struct bcm_kona_gpio *kona_gpio;
227 void __iomem *reg_base;
228 int bank_id = GPIO_BANK(gpio);
229 int bit = GPIO_BIT(gpio);
230 u32 val, reg_offset;
231 unsigned long flags;
232
233 kona_gpio = gpiochip_get_data(chip);
234 reg_base = kona_gpio->reg_base;
235 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
236
237 val = readl(reg_base + GPIO_CONTROL(gpio));
238 val &= ~GPIO_GPCTR0_IOTR_MASK;
239 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
240 writel(val, reg_base + GPIO_CONTROL(gpio));
241 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
242
243 val = readl(reg_base + reg_offset);
244 val |= BIT(bit);
245 writel(val, reg_base + reg_offset);
246
247 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
248
249 return 0;
250}
251
252static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
253{
254 struct bcm_kona_gpio *kona_gpio;
255
256 kona_gpio = gpiochip_get_data(chip);
257 if (gpio >= kona_gpio->gpio_chip.ngpio)
258 return -ENXIO;
259 return irq_create_mapping(kona_gpio->irq_domain, gpio);
260}
261
262static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
263 unsigned debounce)
264{
265 struct bcm_kona_gpio *kona_gpio;
266 void __iomem *reg_base;
267 u32 val, res;
268 unsigned long flags;
269
270 kona_gpio = gpiochip_get_data(chip);
271 reg_base = kona_gpio->reg_base;
272 /* debounce must be 1-128ms (or 0) */
273 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
274 dev_err(chip->parent, "Debounce value %u not in range\n",
275 debounce);
276 return -EINVAL;
277 }
278
279 /* calculate debounce bit value */
280 if (debounce != 0) {
281 /* Convert to ms */
282 debounce /= 1000;
283 /* find the MSB */
284 res = fls(debounce) - 1;
285 /* Check if MSB-1 is set (round up or down) */
286 if (res > 0 && (debounce & BIT(res - 1)))
287 res++;
288 }
289
290 /* spin lock for read-modify-write of the GPIO register */
291 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
292
293 val = readl(reg_base + GPIO_CONTROL(gpio));
294 val &= ~GPIO_GPCTR0_DBR_MASK;
295
296 if (debounce == 0) {
297 /* disable debounce */
298 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
299 } else {
300 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
301 (res << GPIO_GPCTR0_DBR_SHIFT);
302 }
303
304 writel(val, reg_base + GPIO_CONTROL(gpio));
305
306 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
307
308 return 0;
309}
310
311static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
312 unsigned long config)
313{
314 u32 debounce;
315
316 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
317 return -ENOTSUPP;
318
319 debounce = pinconf_to_config_argument(config);
320 return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
321}
322
323static const struct gpio_chip template_chip = {
324 .label = "bcm-kona-gpio",
325 .owner = THIS_MODULE,
326 .request = bcm_kona_gpio_request,
327 .free = bcm_kona_gpio_free,
328 .get_direction = bcm_kona_gpio_get_dir,
329 .direction_input = bcm_kona_gpio_direction_input,
330 .get = bcm_kona_gpio_get,
331 .direction_output = bcm_kona_gpio_direction_output,
332 .set = bcm_kona_gpio_set,
333 .set_config = bcm_kona_gpio_set_config,
334 .to_irq = bcm_kona_gpio_to_irq,
335 .base = 0,
336};
337
338static void bcm_kona_gpio_irq_ack(struct irq_data *d)
339{
340 struct bcm_kona_gpio *kona_gpio;
341 void __iomem *reg_base;
342 unsigned gpio = d->hwirq;
343 int bank_id = GPIO_BANK(gpio);
344 int bit = GPIO_BIT(gpio);
345 u32 val;
346 unsigned long flags;
347
348 kona_gpio = irq_data_get_irq_chip_data(d);
349 reg_base = kona_gpio->reg_base;
350 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
351
352 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
353 val |= BIT(bit);
354 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
355
356 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
357}
358
359static void bcm_kona_gpio_irq_mask(struct irq_data *d)
360{
361 struct bcm_kona_gpio *kona_gpio;
362 void __iomem *reg_base;
363 unsigned gpio = d->hwirq;
364 int bank_id = GPIO_BANK(gpio);
365 int bit = GPIO_BIT(gpio);
366 u32 val;
367 unsigned long flags;
368
369 kona_gpio = irq_data_get_irq_chip_data(d);
370 reg_base = kona_gpio->reg_base;
371 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
372
373 val = readl(reg_base + GPIO_INT_MASK(bank_id));
374 val |= BIT(bit);
375 writel(val, reg_base + GPIO_INT_MASK(bank_id));
376 gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
377
378 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
379}
380
381static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
382{
383 struct bcm_kona_gpio *kona_gpio;
384 void __iomem *reg_base;
385 unsigned gpio = d->hwirq;
386 int bank_id = GPIO_BANK(gpio);
387 int bit = GPIO_BIT(gpio);
388 u32 val;
389 unsigned long flags;
390
391 kona_gpio = irq_data_get_irq_chip_data(d);
392 reg_base = kona_gpio->reg_base;
393 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
394
395 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
396 val |= BIT(bit);
397 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
398 gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
399
400 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
401}
402
403static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
404{
405 struct bcm_kona_gpio *kona_gpio;
406 void __iomem *reg_base;
407 unsigned gpio = d->hwirq;
408 u32 lvl_type;
409 u32 val;
410 unsigned long flags;
411
412 kona_gpio = irq_data_get_irq_chip_data(d);
413 reg_base = kona_gpio->reg_base;
414 switch (type & IRQ_TYPE_SENSE_MASK) {
415 case IRQ_TYPE_EDGE_RISING:
416 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
417 break;
418
419 case IRQ_TYPE_EDGE_FALLING:
420 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
421 break;
422
423 case IRQ_TYPE_EDGE_BOTH:
424 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
425 break;
426
427 case IRQ_TYPE_LEVEL_HIGH:
428 case IRQ_TYPE_LEVEL_LOW:
429 /* BCM GPIO doesn't support level triggering */
430 default:
431 dev_err(kona_gpio->gpio_chip.parent,
432 "Invalid BCM GPIO irq type 0x%x\n", type);
433 return -EINVAL;
434 }
435
436 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
437
438 val = readl(reg_base + GPIO_CONTROL(gpio));
439 val &= ~GPIO_GPCTR0_ITR_MASK;
440 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
441 writel(val, reg_base + GPIO_CONTROL(gpio));
442
443 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
444
445 return 0;
446}
447
448static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
449{
450 void __iomem *reg_base;
451 int bit, bank_id;
452 unsigned long sta;
453 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
454 struct irq_chip *chip = irq_desc_get_chip(desc);
455
456 chained_irq_enter(chip, desc);
457
458 /*
459 * For bank interrupts, we can't use chip_data to store the kona_gpio
460 * pointer, since GIC needs it for its own purposes. Therefore, we get
461 * our pointer from the bank structure.
462 */
463 reg_base = bank->kona_gpio->reg_base;
464 bank_id = bank->id;
465
466 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
467 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
468 for_each_set_bit(bit, &sta, 32) {
469 int hwirq = GPIO_PER_BANK * bank_id + bit;
470 int child_irq =
471 irq_find_mapping(bank->kona_gpio->irq_domain,
472 hwirq);
473 /*
474 * Clear interrupt before handler is called so we don't
475 * miss any interrupt occurred during executing them.
476 */
477 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
478 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
479 /* Invoke interrupt handler */
480 generic_handle_irq(child_irq);
481 }
482 }
483
484 chained_irq_exit(chip, desc);
485}
486
487static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
488{
489 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
490
491 return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
492}
493
494static void bcm_kona_gpio_irq_relres(struct irq_data *d)
495{
496 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
497
498 gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
499}
500
501static struct irq_chip bcm_gpio_irq_chip = {
502 .name = "bcm-kona-gpio",
503 .irq_ack = bcm_kona_gpio_irq_ack,
504 .irq_mask = bcm_kona_gpio_irq_mask,
505 .irq_unmask = bcm_kona_gpio_irq_unmask,
506 .irq_set_type = bcm_kona_gpio_irq_set_type,
507 .irq_request_resources = bcm_kona_gpio_irq_reqres,
508 .irq_release_resources = bcm_kona_gpio_irq_relres,
509};
510
511static struct of_device_id const bcm_kona_gpio_of_match[] = {
512 { .compatible = "brcm,kona-gpio" },
513 {}
514};
515
516/*
517 * This lock class tells lockdep that GPIO irqs are in a different
518 * category than their parents, so it won't report false recursion.
519 */
520static struct lock_class_key gpio_lock_class;
521static struct lock_class_key gpio_request_class;
522
523static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
524 irq_hw_number_t hwirq)
525{
526 int ret;
527
528 ret = irq_set_chip_data(irq, d->host_data);
529 if (ret < 0)
530 return ret;
531 irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
532 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
533 irq_set_noprobe(irq);
534
535 return 0;
536}
537
538static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
539{
540 irq_set_chip_and_handler(irq, NULL, NULL);
541 irq_set_chip_data(irq, NULL);
542}
543
544static const struct irq_domain_ops bcm_kona_irq_ops = {
545 .map = bcm_kona_gpio_irq_map,
546 .unmap = bcm_kona_gpio_irq_unmap,
547 .xlate = irq_domain_xlate_twocell,
548};
549
550static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
551{
552 void __iomem *reg_base;
553 int i;
554
555 reg_base = kona_gpio->reg_base;
556 /* disable interrupts and clear status */
557 for (i = 0; i < kona_gpio->num_bank; i++) {
558 /* Unlock the entire bank first */
559 bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
560 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
561 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
562 /* Now re-lock the bank */
563 bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
564 }
565}
566
567static int bcm_kona_gpio_probe(struct platform_device *pdev)
568{
569 struct device *dev = &pdev->dev;
570 const struct of_device_id *match;
571 struct bcm_kona_gpio_bank *bank;
572 struct bcm_kona_gpio *kona_gpio;
573 struct gpio_chip *chip;
574 int ret;
575 int i;
576
577 match = of_match_device(bcm_kona_gpio_of_match, dev);
578 if (!match) {
579 dev_err(dev, "Failed to find gpio controller\n");
580 return -ENODEV;
581 }
582
583 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
584 if (!kona_gpio)
585 return -ENOMEM;
586
587 kona_gpio->gpio_chip = template_chip;
588 chip = &kona_gpio->gpio_chip;
589 kona_gpio->num_bank = of_irq_count(dev->of_node);
590 if (kona_gpio->num_bank == 0) {
591 dev_err(dev, "Couldn't determine # GPIO banks\n");
592 return -ENOENT;
593 }
594 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
595 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
596 GPIO_MAX_BANK_NUM);
597 return -ENXIO;
598 }
599 kona_gpio->banks = devm_kcalloc(dev,
600 kona_gpio->num_bank,
601 sizeof(*kona_gpio->banks),
602 GFP_KERNEL);
603 if (!kona_gpio->banks)
604 return -ENOMEM;
605
606 kona_gpio->pdev = pdev;
607 platform_set_drvdata(pdev, kona_gpio);
608 chip->of_node = dev->of_node;
609 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
610
611 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
612 chip->ngpio,
613 &bcm_kona_irq_ops,
614 kona_gpio);
615 if (!kona_gpio->irq_domain) {
616 dev_err(dev, "Couldn't allocate IRQ domain\n");
617 return -ENXIO;
618 }
619
620 kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
621 if (IS_ERR(kona_gpio->reg_base)) {
622 ret = -ENXIO;
623 goto err_irq_domain;
624 }
625
626 for (i = 0; i < kona_gpio->num_bank; i++) {
627 bank = &kona_gpio->banks[i];
628 bank->id = i;
629 bank->irq = platform_get_irq(pdev, i);
630 bank->kona_gpio = kona_gpio;
631 if (bank->irq < 0) {
632 dev_err(dev, "Couldn't get IRQ for bank %d", i);
633 ret = -ENOENT;
634 goto err_irq_domain;
635 }
636 }
637
638 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
639
640 bcm_kona_gpio_reset(kona_gpio);
641
642 ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
643 if (ret < 0) {
644 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
645 goto err_irq_domain;
646 }
647 for (i = 0; i < kona_gpio->num_bank; i++) {
648 bank = &kona_gpio->banks[i];
649 irq_set_chained_handler_and_data(bank->irq,
650 bcm_kona_gpio_irq_handler,
651 bank);
652 }
653
654 raw_spin_lock_init(&kona_gpio->lock);
655
656 return 0;
657
658err_irq_domain:
659 irq_domain_remove(kona_gpio->irq_domain);
660
661 return ret;
662}
663
664static struct platform_driver bcm_kona_gpio_driver = {
665 .driver = {
666 .name = "bcm-kona-gpio",
667 .of_match_table = bcm_kona_gpio_of_match,
668 },
669 .probe = bcm_kona_gpio_probe,
670};
671builtin_platform_driver(bcm_kona_gpio_driver);