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1/*
2 * linux/arch/arm/mach-omap1/clock_data.c
3 *
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * To do:
13 * - Clocks that are only available on some chips should be marked with the
14 * chips that they are present on.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/cpufreq.h>
21#include <linux/delay.h>
22
23#include <asm/mach-types.h> /* for machine_is_* */
24
25#include "soc.h"
26
27#include <mach/hardware.h>
28#include <mach/usb.h> /* for OTG_BASE */
29
30#include "iomap.h"
31#include "clock.h"
32#include "sram.h"
33
34/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
35#define IDL_CLKOUT_ARM_SHIFT 12
36#define IDLTIM_ARM_SHIFT 9
37#define IDLAPI_ARM_SHIFT 8
38#define IDLIF_ARM_SHIFT 6
39#define IDLLB_ARM_SHIFT 4 /* undocumented? */
40#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
41#define IDLPER_ARM_SHIFT 2
42#define IDLXORP_ARM_SHIFT 1
43#define IDLWDT_ARM_SHIFT 0
44
45/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
46#define CONF_MOD_UART3_CLK_MODE_R 31
47#define CONF_MOD_UART2_CLK_MODE_R 30
48#define CONF_MOD_UART1_CLK_MODE_R 29
49#define CONF_MOD_MMC_SD_CLK_REQ_R 23
50#define CONF_MOD_MCBSP3_AUXON 20
51
52/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
53#define CONF_MOD_SOSSI_CLK_EN_R 16
54
55/* Some OTG_SYSCON_2-specific bit fields */
56#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
57
58/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
59#define SOFT_MMC2_DPLL_REQ_SHIFT 13
60#define SOFT_MMC_DPLL_REQ_SHIFT 12
61#define SOFT_UART3_DPLL_REQ_SHIFT 11
62#define SOFT_UART2_DPLL_REQ_SHIFT 10
63#define SOFT_UART1_DPLL_REQ_SHIFT 9
64#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
65#define SOFT_CAM_DPLL_REQ_SHIFT 7
66#define SOFT_COM_MCKO_REQ_SHIFT 6
67#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
68#define USB_REQ_EN_SHIFT 4
69#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
70#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
71#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
72#define SOFT_DPLL_REQ_SHIFT 0
73
74/*
75 * Omap1 clocks
76 */
77
78static struct clk ck_ref = {
79 .name = "ck_ref",
80 .ops = &clkops_null,
81 .rate = 12000000,
82};
83
84static struct clk ck_dpll1 = {
85 .name = "ck_dpll1",
86 .ops = &clkops_null,
87 .parent = &ck_ref,
88};
89
90/*
91 * FIXME: This clock seems to be necessary but no-one has asked for its
92 * activation. [ FIX: SoSSI, SSR ]
93 */
94static struct arm_idlect1_clk ck_dpll1out = {
95 .clk = {
96 .name = "ck_dpll1out",
97 .ops = &clkops_generic,
98 .parent = &ck_dpll1,
99 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
100 ENABLE_ON_INIT,
101 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
102 .enable_bit = EN_CKOUT_ARM,
103 .recalc = &followparent_recalc,
104 },
105 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
106};
107
108static struct clk sossi_ck = {
109 .name = "ck_sossi",
110 .ops = &clkops_generic,
111 .parent = &ck_dpll1out.clk,
112 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
113 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
114 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
115 .recalc = &omap1_sossi_recalc,
116 .set_rate = &omap1_set_sossi_rate,
117};
118
119static struct clk arm_ck = {
120 .name = "arm_ck",
121 .ops = &clkops_null,
122 .parent = &ck_dpll1,
123 .rate_offset = CKCTL_ARMDIV_OFFSET,
124 .recalc = &omap1_ckctl_recalc,
125 .round_rate = omap1_clk_round_rate_ckctl_arm,
126 .set_rate = omap1_clk_set_rate_ckctl_arm,
127};
128
129static struct arm_idlect1_clk armper_ck = {
130 .clk = {
131 .name = "armper_ck",
132 .ops = &clkops_generic,
133 .parent = &ck_dpll1,
134 .flags = CLOCK_IDLE_CONTROL,
135 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
136 .enable_bit = EN_PERCK,
137 .rate_offset = CKCTL_PERDIV_OFFSET,
138 .recalc = &omap1_ckctl_recalc,
139 .round_rate = omap1_clk_round_rate_ckctl_arm,
140 .set_rate = omap1_clk_set_rate_ckctl_arm,
141 },
142 .idlect_shift = IDLPER_ARM_SHIFT,
143};
144
145/*
146 * FIXME: This clock seems to be necessary but no-one has asked for its
147 * activation. [ GPIO code for 1510 ]
148 */
149static struct clk arm_gpio_ck = {
150 .name = "ick",
151 .ops = &clkops_generic,
152 .parent = &ck_dpll1,
153 .flags = ENABLE_ON_INIT,
154 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
155 .enable_bit = EN_GPIOCK,
156 .recalc = &followparent_recalc,
157};
158
159static struct arm_idlect1_clk armxor_ck = {
160 .clk = {
161 .name = "armxor_ck",
162 .ops = &clkops_generic,
163 .parent = &ck_ref,
164 .flags = CLOCK_IDLE_CONTROL,
165 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
166 .enable_bit = EN_XORPCK,
167 .recalc = &followparent_recalc,
168 },
169 .idlect_shift = IDLXORP_ARM_SHIFT,
170};
171
172static struct arm_idlect1_clk armtim_ck = {
173 .clk = {
174 .name = "armtim_ck",
175 .ops = &clkops_generic,
176 .parent = &ck_ref,
177 .flags = CLOCK_IDLE_CONTROL,
178 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
179 .enable_bit = EN_TIMCK,
180 .recalc = &followparent_recalc,
181 },
182 .idlect_shift = IDLTIM_ARM_SHIFT,
183};
184
185static struct arm_idlect1_clk armwdt_ck = {
186 .clk = {
187 .name = "armwdt_ck",
188 .ops = &clkops_generic,
189 .parent = &ck_ref,
190 .flags = CLOCK_IDLE_CONTROL,
191 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
192 .enable_bit = EN_WDTCK,
193 .fixed_div = 14,
194 .recalc = &omap_fixed_divisor_recalc,
195 },
196 .idlect_shift = IDLWDT_ARM_SHIFT,
197};
198
199static struct clk arminth_ck16xx = {
200 .name = "arminth_ck",
201 .ops = &clkops_null,
202 .parent = &arm_ck,
203 .recalc = &followparent_recalc,
204 /* Note: On 16xx the frequency can be divided by 2 by programming
205 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
206 *
207 * 1510 version is in TC clocks.
208 */
209};
210
211static struct clk dsp_ck = {
212 .name = "dsp_ck",
213 .ops = &clkops_generic,
214 .parent = &ck_dpll1,
215 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
216 .enable_bit = EN_DSPCK,
217 .rate_offset = CKCTL_DSPDIV_OFFSET,
218 .recalc = &omap1_ckctl_recalc,
219 .round_rate = omap1_clk_round_rate_ckctl_arm,
220 .set_rate = omap1_clk_set_rate_ckctl_arm,
221};
222
223static struct clk dspmmu_ck = {
224 .name = "dspmmu_ck",
225 .ops = &clkops_null,
226 .parent = &ck_dpll1,
227 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
228 .recalc = &omap1_ckctl_recalc,
229 .round_rate = omap1_clk_round_rate_ckctl_arm,
230 .set_rate = omap1_clk_set_rate_ckctl_arm,
231};
232
233static struct clk dspper_ck = {
234 .name = "dspper_ck",
235 .ops = &clkops_dspck,
236 .parent = &ck_dpll1,
237 .enable_reg = DSP_IDLECT2,
238 .enable_bit = EN_PERCK,
239 .rate_offset = CKCTL_PERDIV_OFFSET,
240 .recalc = &omap1_ckctl_recalc_dsp_domain,
241 .round_rate = omap1_clk_round_rate_ckctl_arm,
242 .set_rate = &omap1_clk_set_rate_dsp_domain,
243};
244
245static struct clk dspxor_ck = {
246 .name = "dspxor_ck",
247 .ops = &clkops_dspck,
248 .parent = &ck_ref,
249 .enable_reg = DSP_IDLECT2,
250 .enable_bit = EN_XORPCK,
251 .recalc = &followparent_recalc,
252};
253
254static struct clk dsptim_ck = {
255 .name = "dsptim_ck",
256 .ops = &clkops_dspck,
257 .parent = &ck_ref,
258 .enable_reg = DSP_IDLECT2,
259 .enable_bit = EN_DSPTIMCK,
260 .recalc = &followparent_recalc,
261};
262
263static struct arm_idlect1_clk tc_ck = {
264 .clk = {
265 .name = "tc_ck",
266 .ops = &clkops_null,
267 .parent = &ck_dpll1,
268 .flags = CLOCK_IDLE_CONTROL,
269 .rate_offset = CKCTL_TCDIV_OFFSET,
270 .recalc = &omap1_ckctl_recalc,
271 .round_rate = omap1_clk_round_rate_ckctl_arm,
272 .set_rate = omap1_clk_set_rate_ckctl_arm,
273 },
274 .idlect_shift = IDLIF_ARM_SHIFT,
275};
276
277static struct clk arminth_ck1510 = {
278 .name = "arminth_ck",
279 .ops = &clkops_null,
280 .parent = &tc_ck.clk,
281 .recalc = &followparent_recalc,
282 /* Note: On 1510 the frequency follows TC_CK
283 *
284 * 16xx version is in MPU clocks.
285 */
286};
287
288static struct clk tipb_ck = {
289 /* No-idle controlled by "tc_ck" */
290 .name = "tipb_ck",
291 .ops = &clkops_null,
292 .parent = &tc_ck.clk,
293 .recalc = &followparent_recalc,
294};
295
296static struct clk l3_ocpi_ck = {
297 /* No-idle controlled by "tc_ck" */
298 .name = "l3_ocpi_ck",
299 .ops = &clkops_generic,
300 .parent = &tc_ck.clk,
301 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
302 .enable_bit = EN_OCPI_CK,
303 .recalc = &followparent_recalc,
304};
305
306static struct clk tc1_ck = {
307 .name = "tc1_ck",
308 .ops = &clkops_generic,
309 .parent = &tc_ck.clk,
310 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
311 .enable_bit = EN_TC1_CK,
312 .recalc = &followparent_recalc,
313};
314
315/*
316 * FIXME: This clock seems to be necessary but no-one has asked for its
317 * activation. [ pm.c (SRAM), CCP, Camera ]
318 */
319static struct clk tc2_ck = {
320 .name = "tc2_ck",
321 .ops = &clkops_generic,
322 .parent = &tc_ck.clk,
323 .flags = ENABLE_ON_INIT,
324 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
325 .enable_bit = EN_TC2_CK,
326 .recalc = &followparent_recalc,
327};
328
329static struct clk dma_ck = {
330 /* No-idle controlled by "tc_ck" */
331 .name = "dma_ck",
332 .ops = &clkops_null,
333 .parent = &tc_ck.clk,
334 .recalc = &followparent_recalc,
335};
336
337static struct clk dma_lcdfree_ck = {
338 .name = "dma_lcdfree_ck",
339 .ops = &clkops_null,
340 .parent = &tc_ck.clk,
341 .recalc = &followparent_recalc,
342};
343
344static struct arm_idlect1_clk api_ck = {
345 .clk = {
346 .name = "api_ck",
347 .ops = &clkops_generic,
348 .parent = &tc_ck.clk,
349 .flags = CLOCK_IDLE_CONTROL,
350 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
351 .enable_bit = EN_APICK,
352 .recalc = &followparent_recalc,
353 },
354 .idlect_shift = IDLAPI_ARM_SHIFT,
355};
356
357static struct arm_idlect1_clk lb_ck = {
358 .clk = {
359 .name = "lb_ck",
360 .ops = &clkops_generic,
361 .parent = &tc_ck.clk,
362 .flags = CLOCK_IDLE_CONTROL,
363 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
364 .enable_bit = EN_LBCK,
365 .recalc = &followparent_recalc,
366 },
367 .idlect_shift = IDLLB_ARM_SHIFT,
368};
369
370static struct clk rhea1_ck = {
371 .name = "rhea1_ck",
372 .ops = &clkops_null,
373 .parent = &tc_ck.clk,
374 .recalc = &followparent_recalc,
375};
376
377static struct clk rhea2_ck = {
378 .name = "rhea2_ck",
379 .ops = &clkops_null,
380 .parent = &tc_ck.clk,
381 .recalc = &followparent_recalc,
382};
383
384static struct clk lcd_ck_16xx = {
385 .name = "lcd_ck",
386 .ops = &clkops_generic,
387 .parent = &ck_dpll1,
388 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
389 .enable_bit = EN_LCDCK,
390 .rate_offset = CKCTL_LCDDIV_OFFSET,
391 .recalc = &omap1_ckctl_recalc,
392 .round_rate = omap1_clk_round_rate_ckctl_arm,
393 .set_rate = omap1_clk_set_rate_ckctl_arm,
394};
395
396static struct arm_idlect1_clk lcd_ck_1510 = {
397 .clk = {
398 .name = "lcd_ck",
399 .ops = &clkops_generic,
400 .parent = &ck_dpll1,
401 .flags = CLOCK_IDLE_CONTROL,
402 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
403 .enable_bit = EN_LCDCK,
404 .rate_offset = CKCTL_LCDDIV_OFFSET,
405 .recalc = &omap1_ckctl_recalc,
406 .round_rate = omap1_clk_round_rate_ckctl_arm,
407 .set_rate = omap1_clk_set_rate_ckctl_arm,
408 },
409 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
410};
411
412/*
413 * XXX The enable_bit here is misused - it simply switches between 12MHz
414 * and 48MHz. Reimplement with clksel.
415 *
416 * XXX does this need SYSC register handling?
417 */
418static struct clk uart1_1510 = {
419 .name = "uart1_ck",
420 .ops = &clkops_null,
421 /* Direct from ULPD, no real parent */
422 .parent = &armper_ck.clk,
423 .rate = 12000000,
424 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
425 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
426 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
427 .set_rate = &omap1_set_uart_rate,
428 .recalc = &omap1_uart_recalc,
429};
430
431/*
432 * XXX The enable_bit here is misused - it simply switches between 12MHz
433 * and 48MHz. Reimplement with clksel.
434 *
435 * XXX SYSC register handling does not belong in the clock framework
436 */
437static struct uart_clk uart1_16xx = {
438 .clk = {
439 .name = "uart1_ck",
440 .ops = &clkops_uart_16xx,
441 /* Direct from ULPD, no real parent */
442 .parent = &armper_ck.clk,
443 .rate = 48000000,
444 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
445 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
446 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
447 },
448 .sysc_addr = 0xfffb0054,
449};
450
451/*
452 * XXX The enable_bit here is misused - it simply switches between 12MHz
453 * and 48MHz. Reimplement with clksel.
454 *
455 * XXX does this need SYSC register handling?
456 */
457static struct clk uart2_ck = {
458 .name = "uart2_ck",
459 .ops = &clkops_null,
460 /* Direct from ULPD, no real parent */
461 .parent = &armper_ck.clk,
462 .rate = 12000000,
463 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
464 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
465 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
466 .set_rate = &omap1_set_uart_rate,
467 .recalc = &omap1_uart_recalc,
468};
469
470/*
471 * XXX The enable_bit here is misused - it simply switches between 12MHz
472 * and 48MHz. Reimplement with clksel.
473 *
474 * XXX does this need SYSC register handling?
475 */
476static struct clk uart3_1510 = {
477 .name = "uart3_ck",
478 .ops = &clkops_null,
479 /* Direct from ULPD, no real parent */
480 .parent = &armper_ck.clk,
481 .rate = 12000000,
482 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
483 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
484 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
485 .set_rate = &omap1_set_uart_rate,
486 .recalc = &omap1_uart_recalc,
487};
488
489/*
490 * XXX The enable_bit here is misused - it simply switches between 12MHz
491 * and 48MHz. Reimplement with clksel.
492 *
493 * XXX SYSC register handling does not belong in the clock framework
494 */
495static struct uart_clk uart3_16xx = {
496 .clk = {
497 .name = "uart3_ck",
498 .ops = &clkops_uart_16xx,
499 /* Direct from ULPD, no real parent */
500 .parent = &armper_ck.clk,
501 .rate = 48000000,
502 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
503 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
504 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
505 },
506 .sysc_addr = 0xfffb9854,
507};
508
509static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
510 .name = "usb_clko",
511 .ops = &clkops_generic,
512 /* Direct from ULPD, no parent */
513 .rate = 6000000,
514 .flags = ENABLE_REG_32BIT,
515 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
516 .enable_bit = USB_MCLK_EN_BIT,
517};
518
519static struct clk usb_hhc_ck1510 = {
520 .name = "usb_hhc_ck",
521 .ops = &clkops_generic,
522 /* Direct from ULPD, no parent */
523 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
524 .flags = ENABLE_REG_32BIT,
525 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
526 .enable_bit = USB_HOST_HHC_UHOST_EN,
527};
528
529static struct clk usb_hhc_ck16xx = {
530 .name = "usb_hhc_ck",
531 .ops = &clkops_generic,
532 /* Direct from ULPD, no parent */
533 .rate = 48000000,
534 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
535 .flags = ENABLE_REG_32BIT,
536 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
537 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
538};
539
540static struct clk usb_dc_ck = {
541 .name = "usb_dc_ck",
542 .ops = &clkops_generic,
543 /* Direct from ULPD, no parent */
544 .rate = 48000000,
545 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
546 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
547};
548
549static struct clk uart1_7xx = {
550 .name = "uart1_ck",
551 .ops = &clkops_generic,
552 /* Direct from ULPD, no parent */
553 .rate = 12000000,
554 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
555 .enable_bit = 9,
556};
557
558static struct clk uart2_7xx = {
559 .name = "uart2_ck",
560 .ops = &clkops_generic,
561 /* Direct from ULPD, no parent */
562 .rate = 12000000,
563 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
564 .enable_bit = 11,
565};
566
567static struct clk mclk_1510 = {
568 .name = "mclk",
569 .ops = &clkops_generic,
570 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
571 .rate = 12000000,
572 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
573 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
574};
575
576static struct clk mclk_16xx = {
577 .name = "mclk",
578 .ops = &clkops_generic,
579 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
580 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
581 .enable_bit = COM_ULPD_PLL_CLK_REQ,
582 .set_rate = &omap1_set_ext_clk_rate,
583 .round_rate = &omap1_round_ext_clk_rate,
584 .init = &omap1_init_ext_clk,
585};
586
587static struct clk bclk_1510 = {
588 .name = "bclk",
589 .ops = &clkops_generic,
590 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
591 .rate = 12000000,
592};
593
594static struct clk bclk_16xx = {
595 .name = "bclk",
596 .ops = &clkops_generic,
597 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
598 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
599 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
600 .set_rate = &omap1_set_ext_clk_rate,
601 .round_rate = &omap1_round_ext_clk_rate,
602 .init = &omap1_init_ext_clk,
603};
604
605static struct clk mmc1_ck = {
606 .name = "mmc1_ck",
607 .ops = &clkops_generic,
608 /* Functional clock is direct from ULPD, interface clock is ARMPER */
609 .parent = &armper_ck.clk,
610 .rate = 48000000,
611 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
612 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
613 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
614};
615
616/*
617 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
618 * CONF_MOD_MCBSP3_AUXON ??
619 */
620static struct clk mmc2_ck = {
621 .name = "mmc2_ck",
622 .ops = &clkops_generic,
623 /* Functional clock is direct from ULPD, interface clock is ARMPER */
624 .parent = &armper_ck.clk,
625 .rate = 48000000,
626 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
627 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
628 .enable_bit = 20,
629};
630
631static struct clk mmc3_ck = {
632 .name = "mmc3_ck",
633 .ops = &clkops_generic,
634 /* Functional clock is direct from ULPD, interface clock is ARMPER */
635 .parent = &armper_ck.clk,
636 .rate = 48000000,
637 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
638 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
639 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
640};
641
642static struct clk virtual_ck_mpu = {
643 .name = "mpu",
644 .ops = &clkops_null,
645 .parent = &arm_ck, /* Is smarter alias for */
646 .recalc = &followparent_recalc,
647 .set_rate = &omap1_select_table_rate,
648 .round_rate = &omap1_round_to_table_rate,
649};
650
651/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
652remains active during MPU idle whenever this is enabled */
653static struct clk i2c_fck = {
654 .name = "i2c_fck",
655 .ops = &clkops_null,
656 .flags = CLOCK_NO_IDLE_PARENT,
657 .parent = &armxor_ck.clk,
658 .recalc = &followparent_recalc,
659};
660
661static struct clk i2c_ick = {
662 .name = "i2c_ick",
663 .ops = &clkops_null,
664 .flags = CLOCK_NO_IDLE_PARENT,
665 .parent = &armper_ck.clk,
666 .recalc = &followparent_recalc,
667};
668
669/*
670 * clkdev integration
671 */
672
673static struct omap_clk omap_clks[] = {
674 /* non-ULPD clocks */
675 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
676 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
677 /* CK_GEN1 clocks */
678 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
679 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
680 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
681 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
682 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
683 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
684 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
685 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
686 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
687 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
688 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
689 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
690 /* CK_GEN2 clocks */
691 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
692 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
693 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
694 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
695 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
696 /* CK_GEN3 clocks */
697 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
698 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
699 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
700 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
701 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
702 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
703 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
704 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
705 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
706 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
707 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
708 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
709 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
710 /* ULPD clocks */
711 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
712 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
713 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
714 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
715 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
716 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
717 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
718 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
719 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
720 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
721 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
722 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
723 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
724 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
725 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
726 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
727 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
728 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
729 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
730 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
731 /* Virtual clocks */
732 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
733 CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
734 CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
735 CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
736 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
737 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
738 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
739 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
740 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
741 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
742 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
743 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
744 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
745 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
746 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
747 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
748 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
749 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
750};
751
752/*
753 * init
754 */
755
756static void __init omap1_show_rates(void)
757{
758 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
759 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
760 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
761 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
762}
763
764u32 cpu_mask;
765
766int __init omap1_clk_init(void)
767{
768 struct omap_clk *c;
769 int crystal_type = 0; /* Default 12 MHz */
770 u32 reg;
771
772#ifdef CONFIG_DEBUG_LL
773 /*
774 * Resets some clocks that may be left on from bootloader,
775 * but leaves serial clocks on.
776 */
777 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
778#endif
779
780 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
781 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
782 omap_writew(reg, SOFT_REQ_REG);
783 if (!cpu_is_omap15xx())
784 omap_writew(0, SOFT_REQ_REG2);
785
786 /* By default all idlect1 clocks are allowed to idle */
787 arm_idlect1_mask = ~0;
788
789 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
790 clk_preinit(c->lk.clk);
791
792 cpu_mask = 0;
793 if (cpu_is_omap1710())
794 cpu_mask |= CK_1710;
795 if (cpu_is_omap16xx())
796 cpu_mask |= CK_16XX;
797 if (cpu_is_omap1510())
798 cpu_mask |= CK_1510;
799 if (cpu_is_omap7xx())
800 cpu_mask |= CK_7XX;
801 if (cpu_is_omap310())
802 cpu_mask |= CK_310;
803
804 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
805 if (c->cpu & cpu_mask) {
806 clkdev_add(&c->lk);
807 clk_register(c->lk.clk);
808 }
809
810 /* Pointers to these clocks are needed by code in clock.c */
811 api_ck_p = clk_get(NULL, "api_ck");
812 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
813 ck_ref_p = clk_get(NULL, "ck_ref");
814
815 if (cpu_is_omap7xx())
816 ck_ref.rate = 13000000;
817 if (cpu_is_omap16xx() && crystal_type == 2)
818 ck_ref.rate = 19200000;
819
820 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
821 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
822 omap_readw(ARM_CKCTL));
823
824 /* We want to be in syncronous scalable mode */
825 omap_writew(0x1000, ARM_SYSST);
826
827
828 /*
829 * Initially use the values set by bootloader. Determine PLL rate and
830 * recalculate dependent clocks as if kernel had changed PLL or
831 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
832 * after the SRAM is initialized.
833 */
834 {
835 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
836
837 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
838 if (pll_ctl_val & 0x10) {
839 /* PLL enabled, apply multiplier and divisor */
840 if (pll_ctl_val & 0xf80)
841 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
842 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
843 } else {
844 /* PLL disabled, apply bypass divisor */
845 switch (pll_ctl_val & 0xc) {
846 case 0:
847 break;
848 case 0x4:
849 ck_dpll1.rate /= 2;
850 break;
851 default:
852 ck_dpll1.rate /= 4;
853 break;
854 }
855 }
856 }
857 propagate_rate(&ck_dpll1);
858 /* Cache rates for clocks connected to ck_ref (not dpll1) */
859 propagate_rate(&ck_ref);
860 omap1_show_rates();
861 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
862 /* Select slicer output as OMAP input clock */
863 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
864 OMAP7XX_PCC_UPLD_CTRL);
865 }
866
867 /* Amstrad Delta wants BCLK high when inactive */
868 if (machine_is_ams_delta())
869 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
870 (1 << SDW_MCLK_INV_BIT),
871 ULPD_CLOCK_CTRL);
872
873 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
874 /* (on 730, bit 13 must not be cleared) */
875 if (cpu_is_omap7xx())
876 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
877 else
878 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
879
880 /* Put DSP/MPUI into reset until needed */
881 omap_writew(0, ARM_RSTCT1);
882 omap_writew(1, ARM_RSTCT2);
883 omap_writew(0x400, ARM_IDLECT1);
884
885 /*
886 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
887 * of the ARM_IDLECT2 register must be set to zero. The power-on
888 * default value of this bit is one.
889 */
890 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
891
892 /*
893 * Only enable those clocks we will need, let the drivers
894 * enable other clocks as necessary
895 */
896 clk_enable(&armper_ck.clk);
897 clk_enable(&armxor_ck.clk);
898 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
899
900 if (cpu_is_omap15xx())
901 clk_enable(&arm_gpio_ck);
902
903 return 0;
904}
905
906#define OMAP1_DPLL1_SANE_VALUE 60000000
907
908void __init omap1_clk_late_init(void)
909{
910 unsigned long rate = ck_dpll1.rate;
911
912 /* Find the highest supported frequency and enable it */
913 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
914 pr_err("System frequencies not set, using default. Check your config.\n");
915 /*
916 * Reprogramming the DPLL is tricky, it must be done from SRAM.
917 */
918 omap_sram_reprogram_clock(0x2290, 0x0005);
919 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
920 }
921 propagate_rate(&ck_dpll1);
922 omap1_show_rates();
923 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
924}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap1/clock_data.c
4 *
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 *
9 * To do:
10 * - Clocks that are only available on some chips should be marked with the
11 * chips that they are present on.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/clk.h>
17#include <linux/clkdev.h>
18#include <linux/clk-provider.h>
19#include <linux/cpufreq.h>
20#include <linux/delay.h>
21#include <linux/soc/ti/omap1-io.h>
22
23#include <asm/mach-types.h> /* for machine_is_* */
24
25#include "soc.h"
26#include "hardware.h"
27#include "usb.h" /* for OTG_BASE */
28#include "iomap.h"
29#include "clock.h"
30#include "sram.h"
31
32/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
33#define IDL_CLKOUT_ARM_SHIFT 12
34#define IDLTIM_ARM_SHIFT 9
35#define IDLAPI_ARM_SHIFT 8
36#define IDLIF_ARM_SHIFT 6
37#define IDLLB_ARM_SHIFT 4 /* undocumented? */
38#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
39#define IDLPER_ARM_SHIFT 2
40#define IDLXORP_ARM_SHIFT 1
41#define IDLWDT_ARM_SHIFT 0
42
43/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
44#define CONF_MOD_UART3_CLK_MODE_R 31
45#define CONF_MOD_UART2_CLK_MODE_R 30
46#define CONF_MOD_UART1_CLK_MODE_R 29
47#define CONF_MOD_MMC_SD_CLK_REQ_R 23
48#define CONF_MOD_MCBSP3_AUXON 20
49
50/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
51#define CONF_MOD_SOSSI_CLK_EN_R 16
52
53/* Some OTG_SYSCON_2-specific bit fields */
54#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
55
56/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
57#define SOFT_MMC2_DPLL_REQ_SHIFT 13
58#define SOFT_MMC_DPLL_REQ_SHIFT 12
59#define SOFT_UART3_DPLL_REQ_SHIFT 11
60#define SOFT_UART2_DPLL_REQ_SHIFT 10
61#define SOFT_UART1_DPLL_REQ_SHIFT 9
62#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
63#define SOFT_CAM_DPLL_REQ_SHIFT 7
64#define SOFT_COM_MCKO_REQ_SHIFT 6
65#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
66#define USB_REQ_EN_SHIFT 4
67#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
68#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
69#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
70#define SOFT_DPLL_REQ_SHIFT 0
71
72/*
73 * Omap1 clocks
74 */
75
76static struct omap1_clk ck_ref = {
77 .hw.init = CLK_HW_INIT_NO_PARENT("ck_ref", &omap1_clk_rate_ops, 0),
78 .rate = 12000000,
79};
80
81static struct omap1_clk ck_dpll1 = {
82 .hw.init = CLK_HW_INIT("ck_dpll1", "ck_ref", &omap1_clk_rate_ops,
83 /*
84 * force recursive refresh of rates of the clock
85 * and its children when clk_get_rate() is called
86 */
87 CLK_GET_RATE_NOCACHE),
88};
89
90/*
91 * FIXME: This clock seems to be necessary but no-one has asked for its
92 * activation. [ FIX: SoSSI, SSR ]
93 */
94static struct arm_idlect1_clk ck_dpll1out = {
95 .clk = {
96 .hw.init = CLK_HW_INIT("ck_dpll1out", "ck_dpll1", &omap1_clk_gate_ops, 0),
97 .ops = &clkops_generic,
98 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
99 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
100 .enable_bit = EN_CKOUT_ARM,
101 },
102 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
103};
104
105static struct omap1_clk sossi_ck = {
106 .hw.init = CLK_HW_INIT("ck_sossi", "ck_dpll1out", &omap1_clk_full_ops, 0),
107 .ops = &clkops_generic,
108 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
109 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
110 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
111 .recalc = &omap1_sossi_recalc,
112 .round_rate = &omap1_round_sossi_rate,
113 .set_rate = &omap1_set_sossi_rate,
114};
115
116static struct omap1_clk arm_ck = {
117 .hw.init = CLK_HW_INIT("arm_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
118 .rate_offset = CKCTL_ARMDIV_OFFSET,
119 .recalc = &omap1_ckctl_recalc,
120 .round_rate = omap1_clk_round_rate_ckctl_arm,
121 .set_rate = omap1_clk_set_rate_ckctl_arm,
122};
123
124static struct arm_idlect1_clk armper_ck = {
125 .clk = {
126 .hw.init = CLK_HW_INIT("armper_ck", "ck_dpll1", &omap1_clk_full_ops,
127 CLK_IS_CRITICAL),
128 .ops = &clkops_generic,
129 .flags = CLOCK_IDLE_CONTROL,
130 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
131 .enable_bit = EN_PERCK,
132 .rate_offset = CKCTL_PERDIV_OFFSET,
133 .recalc = &omap1_ckctl_recalc,
134 .round_rate = omap1_clk_round_rate_ckctl_arm,
135 .set_rate = omap1_clk_set_rate_ckctl_arm,
136 },
137 .idlect_shift = IDLPER_ARM_SHIFT,
138};
139
140/*
141 * FIXME: This clock seems to be necessary but no-one has asked for its
142 * activation. [ GPIO code for 1510 ]
143 */
144static struct omap1_clk arm_gpio_ck = {
145 .hw.init = CLK_HW_INIT("ick", "ck_dpll1", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
146 .ops = &clkops_generic,
147 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
148 .enable_bit = EN_GPIOCK,
149};
150
151static struct arm_idlect1_clk armxor_ck = {
152 .clk = {
153 .hw.init = CLK_HW_INIT("armxor_ck", "ck_ref", &omap1_clk_gate_ops,
154 CLK_IS_CRITICAL),
155 .ops = &clkops_generic,
156 .flags = CLOCK_IDLE_CONTROL,
157 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
158 .enable_bit = EN_XORPCK,
159 },
160 .idlect_shift = IDLXORP_ARM_SHIFT,
161};
162
163static struct arm_idlect1_clk armtim_ck = {
164 .clk = {
165 .hw.init = CLK_HW_INIT("armtim_ck", "ck_ref", &omap1_clk_gate_ops,
166 CLK_IS_CRITICAL),
167 .ops = &clkops_generic,
168 .flags = CLOCK_IDLE_CONTROL,
169 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
170 .enable_bit = EN_TIMCK,
171 },
172 .idlect_shift = IDLTIM_ARM_SHIFT,
173};
174
175static struct arm_idlect1_clk armwdt_ck = {
176 .clk = {
177 .hw.init = CLK_HW_INIT("armwdt_ck", "ck_ref", &omap1_clk_full_ops, 0),
178 .ops = &clkops_generic,
179 .flags = CLOCK_IDLE_CONTROL,
180 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
181 .enable_bit = EN_WDTCK,
182 .fixed_div = 14,
183 .recalc = &omap_fixed_divisor_recalc,
184 },
185 .idlect_shift = IDLWDT_ARM_SHIFT,
186};
187
188static struct omap1_clk arminth_ck16xx = {
189 .hw.init = CLK_HW_INIT("arminth_ck", "arm_ck", &omap1_clk_null_ops, 0),
190 /* Note: On 16xx the frequency can be divided by 2 by programming
191 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
192 *
193 * 1510 version is in TC clocks.
194 */
195};
196
197static struct omap1_clk dsp_ck = {
198 .hw.init = CLK_HW_INIT("dsp_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
199 .ops = &clkops_generic,
200 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
201 .enable_bit = EN_DSPCK,
202 .rate_offset = CKCTL_DSPDIV_OFFSET,
203 .recalc = &omap1_ckctl_recalc,
204 .round_rate = omap1_clk_round_rate_ckctl_arm,
205 .set_rate = omap1_clk_set_rate_ckctl_arm,
206};
207
208static struct omap1_clk dspmmu_ck = {
209 .hw.init = CLK_HW_INIT("dspmmu_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
210 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
211 .recalc = &omap1_ckctl_recalc,
212 .round_rate = omap1_clk_round_rate_ckctl_arm,
213 .set_rate = omap1_clk_set_rate_ckctl_arm,
214};
215
216static struct omap1_clk dspper_ck = {
217 .hw.init = CLK_HW_INIT("dspper_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
218 .ops = &clkops_dspck,
219 .enable_reg = DSP_IDLECT2,
220 .enable_bit = EN_PERCK,
221 .rate_offset = CKCTL_PERDIV_OFFSET,
222 .recalc = &omap1_ckctl_recalc_dsp_domain,
223 .round_rate = omap1_clk_round_rate_ckctl_arm,
224 .set_rate = &omap1_clk_set_rate_dsp_domain,
225};
226
227static struct omap1_clk dspxor_ck = {
228 .hw.init = CLK_HW_INIT("dspxor_ck", "ck_ref", &omap1_clk_gate_ops, 0),
229 .ops = &clkops_dspck,
230 .enable_reg = DSP_IDLECT2,
231 .enable_bit = EN_XORPCK,
232};
233
234static struct omap1_clk dsptim_ck = {
235 .hw.init = CLK_HW_INIT("dsptim_ck", "ck_ref", &omap1_clk_gate_ops, 0),
236 .ops = &clkops_dspck,
237 .enable_reg = DSP_IDLECT2,
238 .enable_bit = EN_DSPTIMCK,
239};
240
241static struct arm_idlect1_clk tc_ck = {
242 .clk = {
243 .hw.init = CLK_HW_INIT("tc_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
244 .flags = CLOCK_IDLE_CONTROL,
245 .rate_offset = CKCTL_TCDIV_OFFSET,
246 .recalc = &omap1_ckctl_recalc,
247 .round_rate = omap1_clk_round_rate_ckctl_arm,
248 .set_rate = omap1_clk_set_rate_ckctl_arm,
249 },
250 .idlect_shift = IDLIF_ARM_SHIFT,
251};
252
253static struct omap1_clk arminth_ck1510 = {
254 .hw.init = CLK_HW_INIT("arminth_ck", "tc_ck", &omap1_clk_null_ops, 0),
255 /* Note: On 1510 the frequency follows TC_CK
256 *
257 * 16xx version is in MPU clocks.
258 */
259};
260
261static struct omap1_clk tipb_ck = {
262 /* No-idle controlled by "tc_ck" */
263 .hw.init = CLK_HW_INIT("tipb_ck", "tc_ck", &omap1_clk_null_ops, 0),
264};
265
266static struct omap1_clk l3_ocpi_ck = {
267 /* No-idle controlled by "tc_ck" */
268 .hw.init = CLK_HW_INIT("l3_ocpi_ck", "tc_ck", &omap1_clk_gate_ops, 0),
269 .ops = &clkops_generic,
270 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
271 .enable_bit = EN_OCPI_CK,
272};
273
274static struct omap1_clk tc1_ck = {
275 .hw.init = CLK_HW_INIT("tc1_ck", "tc_ck", &omap1_clk_gate_ops, 0),
276 .ops = &clkops_generic,
277 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
278 .enable_bit = EN_TC1_CK,
279};
280
281/*
282 * FIXME: This clock seems to be necessary but no-one has asked for its
283 * activation. [ pm.c (SRAM), CCP, Camera ]
284 */
285
286static struct omap1_clk tc2_ck = {
287 .hw.init = CLK_HW_INIT("tc2_ck", "tc_ck", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
288 .ops = &clkops_generic,
289 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
290 .enable_bit = EN_TC2_CK,
291};
292
293static struct omap1_clk dma_ck = {
294 /* No-idle controlled by "tc_ck" */
295 .hw.init = CLK_HW_INIT("dma_ck", "tc_ck", &omap1_clk_null_ops, 0),
296};
297
298static struct omap1_clk dma_lcdfree_ck = {
299 .hw.init = CLK_HW_INIT("dma_lcdfree_ck", "tc_ck", &omap1_clk_null_ops, 0),
300};
301
302static struct arm_idlect1_clk api_ck = {
303 .clk = {
304 .hw.init = CLK_HW_INIT("api_ck", "tc_ck", &omap1_clk_gate_ops, 0),
305 .ops = &clkops_generic,
306 .flags = CLOCK_IDLE_CONTROL,
307 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
308 .enable_bit = EN_APICK,
309 },
310 .idlect_shift = IDLAPI_ARM_SHIFT,
311};
312
313static struct arm_idlect1_clk lb_ck = {
314 .clk = {
315 .hw.init = CLK_HW_INIT("lb_ck", "tc_ck", &omap1_clk_gate_ops, 0),
316 .ops = &clkops_generic,
317 .flags = CLOCK_IDLE_CONTROL,
318 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
319 .enable_bit = EN_LBCK,
320 },
321 .idlect_shift = IDLLB_ARM_SHIFT,
322};
323
324static struct omap1_clk rhea1_ck = {
325 .hw.init = CLK_HW_INIT("rhea1_ck", "tc_ck", &omap1_clk_null_ops, 0),
326};
327
328static struct omap1_clk rhea2_ck = {
329 .hw.init = CLK_HW_INIT("rhea2_ck", "tc_ck", &omap1_clk_null_ops, 0),
330};
331
332static struct omap1_clk lcd_ck_16xx = {
333 .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
334 .ops = &clkops_generic,
335 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
336 .enable_bit = EN_LCDCK,
337 .rate_offset = CKCTL_LCDDIV_OFFSET,
338 .recalc = &omap1_ckctl_recalc,
339 .round_rate = omap1_clk_round_rate_ckctl_arm,
340 .set_rate = omap1_clk_set_rate_ckctl_arm,
341};
342
343static struct arm_idlect1_clk lcd_ck_1510 = {
344 .clk = {
345 .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
346 .ops = &clkops_generic,
347 .flags = CLOCK_IDLE_CONTROL,
348 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
349 .enable_bit = EN_LCDCK,
350 .rate_offset = CKCTL_LCDDIV_OFFSET,
351 .recalc = &omap1_ckctl_recalc,
352 .round_rate = omap1_clk_round_rate_ckctl_arm,
353 .set_rate = omap1_clk_set_rate_ckctl_arm,
354 },
355 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
356};
357
358
359/*
360 * XXX The enable_bit here is misused - it simply switches between 12MHz
361 * and 48MHz. Reimplement with clk_mux.
362 *
363 * XXX does this need SYSC register handling?
364 */
365static struct omap1_clk uart1_1510 = {
366 /* Direct from ULPD, no real parent */
367 .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
368 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
369 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
370 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
371 .round_rate = &omap1_round_uart_rate,
372 .set_rate = &omap1_set_uart_rate,
373 .recalc = &omap1_uart_recalc,
374};
375
376/*
377 * XXX The enable_bit here is misused - it simply switches between 12MHz
378 * and 48MHz. Reimplement with clk_mux.
379 *
380 * XXX SYSC register handling does not belong in the clock framework
381 */
382static struct uart_clk uart1_16xx = {
383 .clk = {
384 .ops = &clkops_uart_16xx,
385 /* Direct from ULPD, no real parent */
386 .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
387 .rate = 48000000,
388 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
389 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
390 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
391 },
392 .sysc_addr = 0xfffb0054,
393};
394
395/*
396 * XXX The enable_bit here is misused - it simply switches between 12MHz
397 * and 48MHz. Reimplement with clk_mux.
398 *
399 * XXX does this need SYSC register handling?
400 */
401static struct omap1_clk uart2_ck = {
402 /* Direct from ULPD, no real parent */
403 .hw.init = CLK_HW_INIT("uart2_ck", "armper_ck", &omap1_clk_full_ops, 0),
404 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
405 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
406 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
407 .round_rate = &omap1_round_uart_rate,
408 .set_rate = &omap1_set_uart_rate,
409 .recalc = &omap1_uart_recalc,
410};
411
412/*
413 * XXX The enable_bit here is misused - it simply switches between 12MHz
414 * and 48MHz. Reimplement with clk_mux.
415 *
416 * XXX does this need SYSC register handling?
417 */
418static struct omap1_clk uart3_1510 = {
419 /* Direct from ULPD, no real parent */
420 .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
421 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
422 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
423 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
424 .round_rate = &omap1_round_uart_rate,
425 .set_rate = &omap1_set_uart_rate,
426 .recalc = &omap1_uart_recalc,
427};
428
429/*
430 * XXX The enable_bit here is misused - it simply switches between 12MHz
431 * and 48MHz. Reimplement with clk_mux.
432 *
433 * XXX SYSC register handling does not belong in the clock framework
434 */
435static struct uart_clk uart3_16xx = {
436 .clk = {
437 .ops = &clkops_uart_16xx,
438 /* Direct from ULPD, no real parent */
439 .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
440 .rate = 48000000,
441 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
442 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
443 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
444 },
445 .sysc_addr = 0xfffb9854,
446};
447
448static struct omap1_clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
449 .ops = &clkops_generic,
450 /* Direct from ULPD, no parent */
451 .hw.init = CLK_HW_INIT_NO_PARENT("usb_clko", &omap1_clk_full_ops, 0),
452 .rate = 6000000,
453 .flags = ENABLE_REG_32BIT,
454 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
455 .enable_bit = USB_MCLK_EN_BIT,
456};
457
458static struct omap1_clk usb_hhc_ck1510 = {
459 .ops = &clkops_generic,
460 /* Direct from ULPD, no parent */
461 .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
462 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
463 .flags = ENABLE_REG_32BIT,
464 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
465 .enable_bit = USB_HOST_HHC_UHOST_EN,
466};
467
468static struct omap1_clk usb_hhc_ck16xx = {
469 .ops = &clkops_generic,
470 /* Direct from ULPD, no parent */
471 .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
472 .rate = 48000000,
473 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
474 .flags = ENABLE_REG_32BIT,
475 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
476 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
477};
478
479static struct omap1_clk usb_dc_ck = {
480 .ops = &clkops_generic,
481 /* Direct from ULPD, no parent */
482 .hw.init = CLK_HW_INIT_NO_PARENT("usb_dc_ck", &omap1_clk_full_ops, 0),
483 .rate = 48000000,
484 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
485 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
486};
487
488static struct omap1_clk uart1_7xx = {
489 .ops = &clkops_generic,
490 /* Direct from ULPD, no parent */
491 .hw.init = CLK_HW_INIT_NO_PARENT("uart1_ck", &omap1_clk_full_ops, 0),
492 .rate = 12000000,
493 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
494 .enable_bit = 9,
495};
496
497static struct omap1_clk uart2_7xx = {
498 .ops = &clkops_generic,
499 /* Direct from ULPD, no parent */
500 .hw.init = CLK_HW_INIT_NO_PARENT("uart2_ck", &omap1_clk_full_ops, 0),
501 .rate = 12000000,
502 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
503 .enable_bit = 11,
504};
505
506static struct omap1_clk mclk_1510 = {
507 .ops = &clkops_generic,
508 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
509 .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
510 .rate = 12000000,
511 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
512 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
513};
514
515static struct omap1_clk mclk_16xx = {
516 .ops = &clkops_generic,
517 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
518 .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
519 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
520 .enable_bit = COM_ULPD_PLL_CLK_REQ,
521 .set_rate = &omap1_set_ext_clk_rate,
522 .round_rate = &omap1_round_ext_clk_rate,
523 .init = &omap1_init_ext_clk,
524};
525
526static struct omap1_clk bclk_1510 = {
527 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
528 .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_rate_ops, 0),
529 .rate = 12000000,
530};
531
532static struct omap1_clk bclk_16xx = {
533 .ops = &clkops_generic,
534 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
535 .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_full_ops, 0),
536 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
537 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
538 .set_rate = &omap1_set_ext_clk_rate,
539 .round_rate = &omap1_round_ext_clk_rate,
540 .init = &omap1_init_ext_clk,
541};
542
543static struct omap1_clk mmc1_ck = {
544 .ops = &clkops_generic,
545 /* Functional clock is direct from ULPD, interface clock is ARMPER */
546 .hw.init = CLK_HW_INIT("mmc1_ck", "armper_ck", &omap1_clk_full_ops, 0),
547 .rate = 48000000,
548 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
549 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
550 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
551};
552
553/*
554 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
555 * CONF_MOD_MCBSP3_AUXON ??
556 */
557static struct omap1_clk mmc2_ck = {
558 .ops = &clkops_generic,
559 /* Functional clock is direct from ULPD, interface clock is ARMPER */
560 .hw.init = CLK_HW_INIT("mmc2_ck", "armper_ck", &omap1_clk_full_ops, 0),
561 .rate = 48000000,
562 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
563 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
564 .enable_bit = 20,
565};
566
567static struct omap1_clk mmc3_ck = {
568 .ops = &clkops_generic,
569 /* Functional clock is direct from ULPD, interface clock is ARMPER */
570 .hw.init = CLK_HW_INIT("mmc3_ck", "armper_ck", &omap1_clk_full_ops, 0),
571 .rate = 48000000,
572 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
573 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
574 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
575};
576
577static struct omap1_clk virtual_ck_mpu = {
578 /* Is smarter alias for arm_ck */
579 .hw.init = CLK_HW_INIT("mpu", "arm_ck", &omap1_clk_rate_ops, 0),
580 .recalc = &followparent_recalc,
581 .set_rate = &omap1_select_table_rate,
582 .round_rate = &omap1_round_to_table_rate,
583};
584
585/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
586remains active during MPU idle whenever this is enabled */
587static struct omap1_clk i2c_fck = {
588 .hw.init = CLK_HW_INIT("i2c_fck", "armxor_ck", &omap1_clk_gate_ops, 0),
589 .flags = CLOCK_NO_IDLE_PARENT,
590};
591
592static struct omap1_clk i2c_ick = {
593 .hw.init = CLK_HW_INIT("i2c_ick", "armper_ck", &omap1_clk_gate_ops, 0),
594 .flags = CLOCK_NO_IDLE_PARENT,
595};
596
597/*
598 * clkdev integration
599 */
600
601static struct omap_clk omap_clks[] = {
602 /* non-ULPD clocks */
603 CLK(NULL, "ck_ref", &ck_ref.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
604 CLK(NULL, "ck_dpll1", &ck_dpll1.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
605 /* CK_GEN1 clocks */
606 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk.hw, CK_16XX),
607 CLK(NULL, "ck_sossi", &sossi_ck.hw, CK_16XX),
608 CLK(NULL, "arm_ck", &arm_ck.hw, CK_16XX | CK_1510 | CK_310),
609 CLK(NULL, "armper_ck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
610 CLK("omap_gpio.0", "ick", &arm_gpio_ck.hw, CK_1510 | CK_310),
611 CLK(NULL, "armxor_ck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
612 CLK(NULL, "armtim_ck", &armtim_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
613 CLK("omap_wdt", "fck", &armwdt_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
614 CLK("omap_wdt", "ick", &armper_ck.clk.hw, CK_16XX),
615 CLK("omap_wdt", "ick", &dummy_ck.hw, CK_1510 | CK_310),
616 CLK(NULL, "arminth_ck", &arminth_ck1510.hw, CK_1510 | CK_310),
617 CLK(NULL, "arminth_ck", &arminth_ck16xx.hw, CK_16XX),
618 /* CK_GEN2 clocks */
619 CLK(NULL, "dsp_ck", &dsp_ck.hw, CK_16XX | CK_1510 | CK_310),
620 CLK(NULL, "dspmmu_ck", &dspmmu_ck.hw, CK_16XX | CK_1510 | CK_310),
621 CLK(NULL, "dspper_ck", &dspper_ck.hw, CK_16XX | CK_1510 | CK_310),
622 CLK(NULL, "dspxor_ck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
623 CLK(NULL, "dsptim_ck", &dsptim_ck.hw, CK_16XX | CK_1510 | CK_310),
624 /* CK_GEN3 clocks */
625 CLK(NULL, "tc_ck", &tc_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
626 CLK(NULL, "tipb_ck", &tipb_ck.hw, CK_1510 | CK_310),
627 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck.hw, CK_16XX | CK_7XX),
628 CLK(NULL, "tc1_ck", &tc1_ck.hw, CK_16XX),
629 CLK(NULL, "tc2_ck", &tc2_ck.hw, CK_16XX),
630 CLK(NULL, "dma_ck", &dma_ck.hw, CK_16XX | CK_1510 | CK_310),
631 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck.hw, CK_16XX),
632 CLK(NULL, "api_ck", &api_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
633 CLK(NULL, "lb_ck", &lb_ck.clk.hw, CK_1510 | CK_310),
634 CLK(NULL, "rhea1_ck", &rhea1_ck.hw, CK_16XX),
635 CLK(NULL, "rhea2_ck", &rhea2_ck.hw, CK_16XX),
636 CLK(NULL, "lcd_ck", &lcd_ck_16xx.hw, CK_16XX | CK_7XX),
637 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk.hw, CK_1510 | CK_310),
638 /* ULPD clocks */
639 CLK(NULL, "uart1_ck", &uart1_1510.hw, CK_1510 | CK_310),
640 CLK(NULL, "uart1_ck", &uart1_16xx.clk.hw, CK_16XX),
641 CLK(NULL, "uart1_ck", &uart1_7xx.hw, CK_7XX),
642 CLK(NULL, "uart2_ck", &uart2_ck.hw, CK_16XX | CK_1510 | CK_310),
643 CLK(NULL, "uart2_ck", &uart2_7xx.hw, CK_7XX),
644 CLK(NULL, "uart3_ck", &uart3_1510.hw, CK_1510 | CK_310),
645 CLK(NULL, "uart3_ck", &uart3_16xx.clk.hw, CK_16XX),
646 CLK(NULL, "usb_clko", &usb_clko.hw, CK_16XX | CK_1510 | CK_310),
647 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510.hw, CK_1510 | CK_310),
648 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx.hw, CK_16XX),
649 CLK(NULL, "usb_dc_ck", &usb_dc_ck.hw, CK_16XX | CK_7XX),
650 CLK(NULL, "mclk", &mclk_1510.hw, CK_1510 | CK_310),
651 CLK(NULL, "mclk", &mclk_16xx.hw, CK_16XX),
652 CLK(NULL, "bclk", &bclk_1510.hw, CK_1510 | CK_310),
653 CLK(NULL, "bclk", &bclk_16xx.hw, CK_16XX),
654 CLK("mmci-omap.0", "fck", &mmc1_ck.hw, CK_16XX | CK_1510 | CK_310),
655 CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX),
656 CLK("mmci-omap.0", "ick", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
657 CLK("mmci-omap.1", "fck", &mmc2_ck.hw, CK_16XX),
658 CLK("mmci-omap.1", "ick", &armper_ck.clk.hw, CK_16XX),
659 /* Virtual clocks */
660 CLK(NULL, "mpu", &virtual_ck_mpu.hw, CK_16XX | CK_1510 | CK_310),
661 CLK("omap_i2c.1", "fck", &i2c_fck.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
662 CLK("omap_i2c.1", "ick", &i2c_ick.hw, CK_16XX),
663 CLK("omap_i2c.1", "ick", &dummy_ck.hw, CK_1510 | CK_310 | CK_7XX),
664 CLK("omap1_spi100k.1", "fck", &dummy_ck.hw, CK_7XX),
665 CLK("omap1_spi100k.1", "ick", &dummy_ck.hw, CK_7XX),
666 CLK("omap1_spi100k.2", "fck", &dummy_ck.hw, CK_7XX),
667 CLK("omap1_spi100k.2", "ick", &dummy_ck.hw, CK_7XX),
668 CLK("omap_uwire", "fck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
669 CLK("omap-mcbsp.1", "ick", &dspper_ck.hw, CK_16XX),
670 CLK("omap-mcbsp.1", "ick", &dummy_ck.hw, CK_1510 | CK_310),
671 CLK("omap-mcbsp.2", "ick", &armper_ck.clk.hw, CK_16XX),
672 CLK("omap-mcbsp.2", "ick", &dummy_ck.hw, CK_1510 | CK_310),
673 CLK("omap-mcbsp.3", "ick", &dspper_ck.hw, CK_16XX),
674 CLK("omap-mcbsp.3", "ick", &dummy_ck.hw, CK_1510 | CK_310),
675 CLK("omap-mcbsp.1", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
676 CLK("omap-mcbsp.2", "fck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
677 CLK("omap-mcbsp.3", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
678};
679
680/*
681 * init
682 */
683
684static void __init omap1_show_rates(void)
685{
686 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
687 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
688 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
689 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
690}
691
692u32 cpu_mask;
693
694int __init omap1_clk_init(void)
695{
696 struct omap_clk *c;
697 u32 reg;
698
699#ifdef CONFIG_DEBUG_LL
700 /* Make sure UART clocks are enabled early */
701 if (cpu_is_omap16xx())
702 omap_writel(omap_readl(MOD_CONF_CTRL_0) |
703 CONF_MOD_UART1_CLK_MODE_R |
704 CONF_MOD_UART3_CLK_MODE_R, MOD_CONF_CTRL_0);
705#endif
706
707 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
708 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
709 omap_writew(reg, SOFT_REQ_REG);
710 if (!cpu_is_omap15xx())
711 omap_writew(0, SOFT_REQ_REG2);
712
713 /* By default all idlect1 clocks are allowed to idle */
714 arm_idlect1_mask = ~0;
715
716 cpu_mask = 0;
717 if (cpu_is_omap1710())
718 cpu_mask |= CK_1710;
719 if (cpu_is_omap16xx())
720 cpu_mask |= CK_16XX;
721 if (cpu_is_omap1510())
722 cpu_mask |= CK_1510;
723 if (cpu_is_omap310())
724 cpu_mask |= CK_310;
725
726 /* Pointers to these clocks are needed by code in clock.c */
727 api_ck_p = &api_ck.clk;
728 ck_dpll1_p = &ck_dpll1;
729 ck_ref_p = &ck_ref;
730
731 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
732 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
733 omap_readw(ARM_CKCTL));
734
735 /* We want to be in synchronous scalable mode */
736 omap_writew(0x1000, ARM_SYSST);
737
738
739 /*
740 * Initially use the values set by bootloader. Determine PLL rate and
741 * recalculate dependent clocks as if kernel had changed PLL or
742 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
743 * after the SRAM is initialized.
744 */
745 {
746 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
747
748 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
749 if (pll_ctl_val & 0x10) {
750 /* PLL enabled, apply multiplier and divisor */
751 if (pll_ctl_val & 0xf80)
752 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
753 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
754 } else {
755 /* PLL disabled, apply bypass divisor */
756 switch (pll_ctl_val & 0xc) {
757 case 0:
758 break;
759 case 0x4:
760 ck_dpll1.rate /= 2;
761 break;
762 default:
763 ck_dpll1.rate /= 4;
764 break;
765 }
766 }
767 }
768
769 /* Amstrad Delta wants BCLK high when inactive */
770 if (machine_is_ams_delta())
771 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
772 (1 << SDW_MCLK_INV_BIT),
773 ULPD_CLOCK_CTRL);
774
775 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
776 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
777
778 /* Put DSP/MPUI into reset until needed */
779 omap_writew(0, ARM_RSTCT1);
780 omap_writew(1, ARM_RSTCT2);
781 omap_writew(0x400, ARM_IDLECT1);
782
783 /*
784 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
785 * of the ARM_IDLECT2 register must be set to zero. The power-on
786 * default value of this bit is one.
787 */
788 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
789
790 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) {
791 if (!(c->cpu & cpu_mask))
792 continue;
793
794 if (c->lk.clk_hw->init) { /* NULL if provider already registered */
795 const struct clk_init_data *init = c->lk.clk_hw->init;
796 const char *name = c->lk.clk_hw->init->name;
797 int err;
798
799 err = clk_hw_register(NULL, c->lk.clk_hw);
800 if (err < 0) {
801 pr_err("failed to register clock \"%s\"! (%d)\n", name, err);
802 /* may be tried again, restore init data */
803 c->lk.clk_hw->init = init;
804 continue;
805 }
806 }
807
808 clk_hw_register_clkdev(c->lk.clk_hw, c->lk.con_id, c->lk.dev_id);
809 }
810
811 omap1_show_rates();
812
813 return 0;
814}
815
816#define OMAP1_DPLL1_SANE_VALUE 60000000
817
818void __init omap1_clk_late_init(void)
819{
820 unsigned long rate = ck_dpll1.rate;
821
822 /* Find the highest supported frequency and enable it */
823 if (omap1_select_table_rate(&virtual_ck_mpu, ~0, arm_ck.rate)) {
824 pr_err("System frequencies not set, using default. Check your config.\n");
825 /*
826 * Reprogramming the DPLL is tricky, it must be done from SRAM.
827 */
828 omap_sram_reprogram_clock(0x2290, 0x0005);
829 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
830 }
831 propagate_rate(&ck_dpll1);
832 omap1_show_rates();
833 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
834}