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1/*
2 * linux/arch/arm/mach-omap1/clock_data.c
3 *
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * To do:
13 * - Clocks that are only available on some chips should be marked with the
14 * chips that they are present on.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/cpufreq.h>
21#include <linux/delay.h>
22
23#include <asm/mach-types.h> /* for machine_is_* */
24
25#include "soc.h"
26
27#include <mach/hardware.h>
28#include <mach/usb.h> /* for OTG_BASE */
29
30#include "iomap.h"
31#include "clock.h"
32#include "sram.h"
33
34/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
35#define IDL_CLKOUT_ARM_SHIFT 12
36#define IDLTIM_ARM_SHIFT 9
37#define IDLAPI_ARM_SHIFT 8
38#define IDLIF_ARM_SHIFT 6
39#define IDLLB_ARM_SHIFT 4 /* undocumented? */
40#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
41#define IDLPER_ARM_SHIFT 2
42#define IDLXORP_ARM_SHIFT 1
43#define IDLWDT_ARM_SHIFT 0
44
45/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
46#define CONF_MOD_UART3_CLK_MODE_R 31
47#define CONF_MOD_UART2_CLK_MODE_R 30
48#define CONF_MOD_UART1_CLK_MODE_R 29
49#define CONF_MOD_MMC_SD_CLK_REQ_R 23
50#define CONF_MOD_MCBSP3_AUXON 20
51
52/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
53#define CONF_MOD_SOSSI_CLK_EN_R 16
54
55/* Some OTG_SYSCON_2-specific bit fields */
56#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
57
58/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
59#define SOFT_MMC2_DPLL_REQ_SHIFT 13
60#define SOFT_MMC_DPLL_REQ_SHIFT 12
61#define SOFT_UART3_DPLL_REQ_SHIFT 11
62#define SOFT_UART2_DPLL_REQ_SHIFT 10
63#define SOFT_UART1_DPLL_REQ_SHIFT 9
64#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
65#define SOFT_CAM_DPLL_REQ_SHIFT 7
66#define SOFT_COM_MCKO_REQ_SHIFT 6
67#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
68#define USB_REQ_EN_SHIFT 4
69#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
70#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
71#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
72#define SOFT_DPLL_REQ_SHIFT 0
73
74/*
75 * Omap1 clocks
76 */
77
78static struct clk ck_ref = {
79 .name = "ck_ref",
80 .ops = &clkops_null,
81 .rate = 12000000,
82};
83
84static struct clk ck_dpll1 = {
85 .name = "ck_dpll1",
86 .ops = &clkops_null,
87 .parent = &ck_ref,
88};
89
90/*
91 * FIXME: This clock seems to be necessary but no-one has asked for its
92 * activation. [ FIX: SoSSI, SSR ]
93 */
94static struct arm_idlect1_clk ck_dpll1out = {
95 .clk = {
96 .name = "ck_dpll1out",
97 .ops = &clkops_generic,
98 .parent = &ck_dpll1,
99 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
100 ENABLE_ON_INIT,
101 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
102 .enable_bit = EN_CKOUT_ARM,
103 .recalc = &followparent_recalc,
104 },
105 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
106};
107
108static struct clk sossi_ck = {
109 .name = "ck_sossi",
110 .ops = &clkops_generic,
111 .parent = &ck_dpll1out.clk,
112 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
113 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
114 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
115 .recalc = &omap1_sossi_recalc,
116 .set_rate = &omap1_set_sossi_rate,
117};
118
119static struct clk arm_ck = {
120 .name = "arm_ck",
121 .ops = &clkops_null,
122 .parent = &ck_dpll1,
123 .rate_offset = CKCTL_ARMDIV_OFFSET,
124 .recalc = &omap1_ckctl_recalc,
125 .round_rate = omap1_clk_round_rate_ckctl_arm,
126 .set_rate = omap1_clk_set_rate_ckctl_arm,
127};
128
129static struct arm_idlect1_clk armper_ck = {
130 .clk = {
131 .name = "armper_ck",
132 .ops = &clkops_generic,
133 .parent = &ck_dpll1,
134 .flags = CLOCK_IDLE_CONTROL,
135 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
136 .enable_bit = EN_PERCK,
137 .rate_offset = CKCTL_PERDIV_OFFSET,
138 .recalc = &omap1_ckctl_recalc,
139 .round_rate = omap1_clk_round_rate_ckctl_arm,
140 .set_rate = omap1_clk_set_rate_ckctl_arm,
141 },
142 .idlect_shift = IDLPER_ARM_SHIFT,
143};
144
145/*
146 * FIXME: This clock seems to be necessary but no-one has asked for its
147 * activation. [ GPIO code for 1510 ]
148 */
149static struct clk arm_gpio_ck = {
150 .name = "ick",
151 .ops = &clkops_generic,
152 .parent = &ck_dpll1,
153 .flags = ENABLE_ON_INIT,
154 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
155 .enable_bit = EN_GPIOCK,
156 .recalc = &followparent_recalc,
157};
158
159static struct arm_idlect1_clk armxor_ck = {
160 .clk = {
161 .name = "armxor_ck",
162 .ops = &clkops_generic,
163 .parent = &ck_ref,
164 .flags = CLOCK_IDLE_CONTROL,
165 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
166 .enable_bit = EN_XORPCK,
167 .recalc = &followparent_recalc,
168 },
169 .idlect_shift = IDLXORP_ARM_SHIFT,
170};
171
172static struct arm_idlect1_clk armtim_ck = {
173 .clk = {
174 .name = "armtim_ck",
175 .ops = &clkops_generic,
176 .parent = &ck_ref,
177 .flags = CLOCK_IDLE_CONTROL,
178 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
179 .enable_bit = EN_TIMCK,
180 .recalc = &followparent_recalc,
181 },
182 .idlect_shift = IDLTIM_ARM_SHIFT,
183};
184
185static struct arm_idlect1_clk armwdt_ck = {
186 .clk = {
187 .name = "armwdt_ck",
188 .ops = &clkops_generic,
189 .parent = &ck_ref,
190 .flags = CLOCK_IDLE_CONTROL,
191 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
192 .enable_bit = EN_WDTCK,
193 .fixed_div = 14,
194 .recalc = &omap_fixed_divisor_recalc,
195 },
196 .idlect_shift = IDLWDT_ARM_SHIFT,
197};
198
199static struct clk arminth_ck16xx = {
200 .name = "arminth_ck",
201 .ops = &clkops_null,
202 .parent = &arm_ck,
203 .recalc = &followparent_recalc,
204 /* Note: On 16xx the frequency can be divided by 2 by programming
205 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
206 *
207 * 1510 version is in TC clocks.
208 */
209};
210
211static struct clk dsp_ck = {
212 .name = "dsp_ck",
213 .ops = &clkops_generic,
214 .parent = &ck_dpll1,
215 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
216 .enable_bit = EN_DSPCK,
217 .rate_offset = CKCTL_DSPDIV_OFFSET,
218 .recalc = &omap1_ckctl_recalc,
219 .round_rate = omap1_clk_round_rate_ckctl_arm,
220 .set_rate = omap1_clk_set_rate_ckctl_arm,
221};
222
223static struct clk dspmmu_ck = {
224 .name = "dspmmu_ck",
225 .ops = &clkops_null,
226 .parent = &ck_dpll1,
227 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
228 .recalc = &omap1_ckctl_recalc,
229 .round_rate = omap1_clk_round_rate_ckctl_arm,
230 .set_rate = omap1_clk_set_rate_ckctl_arm,
231};
232
233static struct clk dspper_ck = {
234 .name = "dspper_ck",
235 .ops = &clkops_dspck,
236 .parent = &ck_dpll1,
237 .enable_reg = DSP_IDLECT2,
238 .enable_bit = EN_PERCK,
239 .rate_offset = CKCTL_PERDIV_OFFSET,
240 .recalc = &omap1_ckctl_recalc_dsp_domain,
241 .round_rate = omap1_clk_round_rate_ckctl_arm,
242 .set_rate = &omap1_clk_set_rate_dsp_domain,
243};
244
245static struct clk dspxor_ck = {
246 .name = "dspxor_ck",
247 .ops = &clkops_dspck,
248 .parent = &ck_ref,
249 .enable_reg = DSP_IDLECT2,
250 .enable_bit = EN_XORPCK,
251 .recalc = &followparent_recalc,
252};
253
254static struct clk dsptim_ck = {
255 .name = "dsptim_ck",
256 .ops = &clkops_dspck,
257 .parent = &ck_ref,
258 .enable_reg = DSP_IDLECT2,
259 .enable_bit = EN_DSPTIMCK,
260 .recalc = &followparent_recalc,
261};
262
263static struct arm_idlect1_clk tc_ck = {
264 .clk = {
265 .name = "tc_ck",
266 .ops = &clkops_null,
267 .parent = &ck_dpll1,
268 .flags = CLOCK_IDLE_CONTROL,
269 .rate_offset = CKCTL_TCDIV_OFFSET,
270 .recalc = &omap1_ckctl_recalc,
271 .round_rate = omap1_clk_round_rate_ckctl_arm,
272 .set_rate = omap1_clk_set_rate_ckctl_arm,
273 },
274 .idlect_shift = IDLIF_ARM_SHIFT,
275};
276
277static struct clk arminth_ck1510 = {
278 .name = "arminth_ck",
279 .ops = &clkops_null,
280 .parent = &tc_ck.clk,
281 .recalc = &followparent_recalc,
282 /* Note: On 1510 the frequency follows TC_CK
283 *
284 * 16xx version is in MPU clocks.
285 */
286};
287
288static struct clk tipb_ck = {
289 /* No-idle controlled by "tc_ck" */
290 .name = "tipb_ck",
291 .ops = &clkops_null,
292 .parent = &tc_ck.clk,
293 .recalc = &followparent_recalc,
294};
295
296static struct clk l3_ocpi_ck = {
297 /* No-idle controlled by "tc_ck" */
298 .name = "l3_ocpi_ck",
299 .ops = &clkops_generic,
300 .parent = &tc_ck.clk,
301 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
302 .enable_bit = EN_OCPI_CK,
303 .recalc = &followparent_recalc,
304};
305
306static struct clk tc1_ck = {
307 .name = "tc1_ck",
308 .ops = &clkops_generic,
309 .parent = &tc_ck.clk,
310 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
311 .enable_bit = EN_TC1_CK,
312 .recalc = &followparent_recalc,
313};
314
315/*
316 * FIXME: This clock seems to be necessary but no-one has asked for its
317 * activation. [ pm.c (SRAM), CCP, Camera ]
318 */
319static struct clk tc2_ck = {
320 .name = "tc2_ck",
321 .ops = &clkops_generic,
322 .parent = &tc_ck.clk,
323 .flags = ENABLE_ON_INIT,
324 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
325 .enable_bit = EN_TC2_CK,
326 .recalc = &followparent_recalc,
327};
328
329static struct clk dma_ck = {
330 /* No-idle controlled by "tc_ck" */
331 .name = "dma_ck",
332 .ops = &clkops_null,
333 .parent = &tc_ck.clk,
334 .recalc = &followparent_recalc,
335};
336
337static struct clk dma_lcdfree_ck = {
338 .name = "dma_lcdfree_ck",
339 .ops = &clkops_null,
340 .parent = &tc_ck.clk,
341 .recalc = &followparent_recalc,
342};
343
344static struct arm_idlect1_clk api_ck = {
345 .clk = {
346 .name = "api_ck",
347 .ops = &clkops_generic,
348 .parent = &tc_ck.clk,
349 .flags = CLOCK_IDLE_CONTROL,
350 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
351 .enable_bit = EN_APICK,
352 .recalc = &followparent_recalc,
353 },
354 .idlect_shift = IDLAPI_ARM_SHIFT,
355};
356
357static struct arm_idlect1_clk lb_ck = {
358 .clk = {
359 .name = "lb_ck",
360 .ops = &clkops_generic,
361 .parent = &tc_ck.clk,
362 .flags = CLOCK_IDLE_CONTROL,
363 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
364 .enable_bit = EN_LBCK,
365 .recalc = &followparent_recalc,
366 },
367 .idlect_shift = IDLLB_ARM_SHIFT,
368};
369
370static struct clk rhea1_ck = {
371 .name = "rhea1_ck",
372 .ops = &clkops_null,
373 .parent = &tc_ck.clk,
374 .recalc = &followparent_recalc,
375};
376
377static struct clk rhea2_ck = {
378 .name = "rhea2_ck",
379 .ops = &clkops_null,
380 .parent = &tc_ck.clk,
381 .recalc = &followparent_recalc,
382};
383
384static struct clk lcd_ck_16xx = {
385 .name = "lcd_ck",
386 .ops = &clkops_generic,
387 .parent = &ck_dpll1,
388 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
389 .enable_bit = EN_LCDCK,
390 .rate_offset = CKCTL_LCDDIV_OFFSET,
391 .recalc = &omap1_ckctl_recalc,
392 .round_rate = omap1_clk_round_rate_ckctl_arm,
393 .set_rate = omap1_clk_set_rate_ckctl_arm,
394};
395
396static struct arm_idlect1_clk lcd_ck_1510 = {
397 .clk = {
398 .name = "lcd_ck",
399 .ops = &clkops_generic,
400 .parent = &ck_dpll1,
401 .flags = CLOCK_IDLE_CONTROL,
402 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
403 .enable_bit = EN_LCDCK,
404 .rate_offset = CKCTL_LCDDIV_OFFSET,
405 .recalc = &omap1_ckctl_recalc,
406 .round_rate = omap1_clk_round_rate_ckctl_arm,
407 .set_rate = omap1_clk_set_rate_ckctl_arm,
408 },
409 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
410};
411
412/*
413 * XXX The enable_bit here is misused - it simply switches between 12MHz
414 * and 48MHz. Reimplement with clksel.
415 *
416 * XXX does this need SYSC register handling?
417 */
418static struct clk uart1_1510 = {
419 .name = "uart1_ck",
420 .ops = &clkops_null,
421 /* Direct from ULPD, no real parent */
422 .parent = &armper_ck.clk,
423 .rate = 12000000,
424 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
425 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
426 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
427 .set_rate = &omap1_set_uart_rate,
428 .recalc = &omap1_uart_recalc,
429};
430
431/*
432 * XXX The enable_bit here is misused - it simply switches between 12MHz
433 * and 48MHz. Reimplement with clksel.
434 *
435 * XXX SYSC register handling does not belong in the clock framework
436 */
437static struct uart_clk uart1_16xx = {
438 .clk = {
439 .name = "uart1_ck",
440 .ops = &clkops_uart_16xx,
441 /* Direct from ULPD, no real parent */
442 .parent = &armper_ck.clk,
443 .rate = 48000000,
444 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
445 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
446 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
447 },
448 .sysc_addr = 0xfffb0054,
449};
450
451/*
452 * XXX The enable_bit here is misused - it simply switches between 12MHz
453 * and 48MHz. Reimplement with clksel.
454 *
455 * XXX does this need SYSC register handling?
456 */
457static struct clk uart2_ck = {
458 .name = "uart2_ck",
459 .ops = &clkops_null,
460 /* Direct from ULPD, no real parent */
461 .parent = &armper_ck.clk,
462 .rate = 12000000,
463 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
464 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
465 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
466 .set_rate = &omap1_set_uart_rate,
467 .recalc = &omap1_uart_recalc,
468};
469
470/*
471 * XXX The enable_bit here is misused - it simply switches between 12MHz
472 * and 48MHz. Reimplement with clksel.
473 *
474 * XXX does this need SYSC register handling?
475 */
476static struct clk uart3_1510 = {
477 .name = "uart3_ck",
478 .ops = &clkops_null,
479 /* Direct from ULPD, no real parent */
480 .parent = &armper_ck.clk,
481 .rate = 12000000,
482 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
483 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
484 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
485 .set_rate = &omap1_set_uart_rate,
486 .recalc = &omap1_uart_recalc,
487};
488
489/*
490 * XXX The enable_bit here is misused - it simply switches between 12MHz
491 * and 48MHz. Reimplement with clksel.
492 *
493 * XXX SYSC register handling does not belong in the clock framework
494 */
495static struct uart_clk uart3_16xx = {
496 .clk = {
497 .name = "uart3_ck",
498 .ops = &clkops_uart_16xx,
499 /* Direct from ULPD, no real parent */
500 .parent = &armper_ck.clk,
501 .rate = 48000000,
502 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
503 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
504 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
505 },
506 .sysc_addr = 0xfffb9854,
507};
508
509static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
510 .name = "usb_clko",
511 .ops = &clkops_generic,
512 /* Direct from ULPD, no parent */
513 .rate = 6000000,
514 .flags = ENABLE_REG_32BIT,
515 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
516 .enable_bit = USB_MCLK_EN_BIT,
517};
518
519static struct clk usb_hhc_ck1510 = {
520 .name = "usb_hhc_ck",
521 .ops = &clkops_generic,
522 /* Direct from ULPD, no parent */
523 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
524 .flags = ENABLE_REG_32BIT,
525 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
526 .enable_bit = USB_HOST_HHC_UHOST_EN,
527};
528
529static struct clk usb_hhc_ck16xx = {
530 .name = "usb_hhc_ck",
531 .ops = &clkops_generic,
532 /* Direct from ULPD, no parent */
533 .rate = 48000000,
534 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
535 .flags = ENABLE_REG_32BIT,
536 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
537 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
538};
539
540static struct clk usb_dc_ck = {
541 .name = "usb_dc_ck",
542 .ops = &clkops_generic,
543 /* Direct from ULPD, no parent */
544 .rate = 48000000,
545 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
546 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
547};
548
549static struct clk uart1_7xx = {
550 .name = "uart1_ck",
551 .ops = &clkops_generic,
552 /* Direct from ULPD, no parent */
553 .rate = 12000000,
554 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
555 .enable_bit = 9,
556};
557
558static struct clk uart2_7xx = {
559 .name = "uart2_ck",
560 .ops = &clkops_generic,
561 /* Direct from ULPD, no parent */
562 .rate = 12000000,
563 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
564 .enable_bit = 11,
565};
566
567static struct clk mclk_1510 = {
568 .name = "mclk",
569 .ops = &clkops_generic,
570 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
571 .rate = 12000000,
572 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
573 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
574};
575
576static struct clk mclk_16xx = {
577 .name = "mclk",
578 .ops = &clkops_generic,
579 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
580 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
581 .enable_bit = COM_ULPD_PLL_CLK_REQ,
582 .set_rate = &omap1_set_ext_clk_rate,
583 .round_rate = &omap1_round_ext_clk_rate,
584 .init = &omap1_init_ext_clk,
585};
586
587static struct clk bclk_1510 = {
588 .name = "bclk",
589 .ops = &clkops_generic,
590 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
591 .rate = 12000000,
592};
593
594static struct clk bclk_16xx = {
595 .name = "bclk",
596 .ops = &clkops_generic,
597 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
598 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
599 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
600 .set_rate = &omap1_set_ext_clk_rate,
601 .round_rate = &omap1_round_ext_clk_rate,
602 .init = &omap1_init_ext_clk,
603};
604
605static struct clk mmc1_ck = {
606 .name = "mmc1_ck",
607 .ops = &clkops_generic,
608 /* Functional clock is direct from ULPD, interface clock is ARMPER */
609 .parent = &armper_ck.clk,
610 .rate = 48000000,
611 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
612 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
613 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
614};
615
616/*
617 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
618 * CONF_MOD_MCBSP3_AUXON ??
619 */
620static struct clk mmc2_ck = {
621 .name = "mmc2_ck",
622 .ops = &clkops_generic,
623 /* Functional clock is direct from ULPD, interface clock is ARMPER */
624 .parent = &armper_ck.clk,
625 .rate = 48000000,
626 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
627 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
628 .enable_bit = 20,
629};
630
631static struct clk mmc3_ck = {
632 .name = "mmc3_ck",
633 .ops = &clkops_generic,
634 /* Functional clock is direct from ULPD, interface clock is ARMPER */
635 .parent = &armper_ck.clk,
636 .rate = 48000000,
637 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
638 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
639 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
640};
641
642static struct clk virtual_ck_mpu = {
643 .name = "mpu",
644 .ops = &clkops_null,
645 .parent = &arm_ck, /* Is smarter alias for */
646 .recalc = &followparent_recalc,
647 .set_rate = &omap1_select_table_rate,
648 .round_rate = &omap1_round_to_table_rate,
649};
650
651/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
652remains active during MPU idle whenever this is enabled */
653static struct clk i2c_fck = {
654 .name = "i2c_fck",
655 .ops = &clkops_null,
656 .flags = CLOCK_NO_IDLE_PARENT,
657 .parent = &armxor_ck.clk,
658 .recalc = &followparent_recalc,
659};
660
661static struct clk i2c_ick = {
662 .name = "i2c_ick",
663 .ops = &clkops_null,
664 .flags = CLOCK_NO_IDLE_PARENT,
665 .parent = &armper_ck.clk,
666 .recalc = &followparent_recalc,
667};
668
669/*
670 * clkdev integration
671 */
672
673static struct omap_clk omap_clks[] = {
674 /* non-ULPD clocks */
675 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
676 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
677 /* CK_GEN1 clocks */
678 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
679 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
680 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
681 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
682 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
683 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
684 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
685 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
686 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
687 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
688 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
689 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
690 /* CK_GEN2 clocks */
691 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
692 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
693 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
694 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
695 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
696 /* CK_GEN3 clocks */
697 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
698 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
699 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
700 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
701 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
702 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
703 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
704 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
705 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
706 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
707 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
708 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
709 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
710 /* ULPD clocks */
711 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
712 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
713 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
714 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
715 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
716 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
717 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
718 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
719 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
720 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
721 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
722 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
723 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
724 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
725 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
726 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
727 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
728 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
729 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
730 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
731 /* Virtual clocks */
732 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
733 CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
734 CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
735 CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
736 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
737 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
738 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
739 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
740 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
741 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
742 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
743 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
744 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
745 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
746 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
747 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
748 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
749 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
750};
751
752/*
753 * init
754 */
755
756static void __init omap1_show_rates(void)
757{
758 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
759 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
760 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
761 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
762}
763
764u32 cpu_mask;
765
766int __init omap1_clk_init(void)
767{
768 struct omap_clk *c;
769 int crystal_type = 0; /* Default 12 MHz */
770 u32 reg;
771
772#ifdef CONFIG_DEBUG_LL
773 /*
774 * Resets some clocks that may be left on from bootloader,
775 * but leaves serial clocks on.
776 */
777 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
778#endif
779
780 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
781 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
782 omap_writew(reg, SOFT_REQ_REG);
783 if (!cpu_is_omap15xx())
784 omap_writew(0, SOFT_REQ_REG2);
785
786 /* By default all idlect1 clocks are allowed to idle */
787 arm_idlect1_mask = ~0;
788
789 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
790 clk_preinit(c->lk.clk);
791
792 cpu_mask = 0;
793 if (cpu_is_omap1710())
794 cpu_mask |= CK_1710;
795 if (cpu_is_omap16xx())
796 cpu_mask |= CK_16XX;
797 if (cpu_is_omap1510())
798 cpu_mask |= CK_1510;
799 if (cpu_is_omap7xx())
800 cpu_mask |= CK_7XX;
801 if (cpu_is_omap310())
802 cpu_mask |= CK_310;
803
804 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
805 if (c->cpu & cpu_mask) {
806 clkdev_add(&c->lk);
807 clk_register(c->lk.clk);
808 }
809
810 /* Pointers to these clocks are needed by code in clock.c */
811 api_ck_p = clk_get(NULL, "api_ck");
812 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
813 ck_ref_p = clk_get(NULL, "ck_ref");
814
815 if (cpu_is_omap7xx())
816 ck_ref.rate = 13000000;
817 if (cpu_is_omap16xx() && crystal_type == 2)
818 ck_ref.rate = 19200000;
819
820 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
821 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
822 omap_readw(ARM_CKCTL));
823
824 /* We want to be in syncronous scalable mode */
825 omap_writew(0x1000, ARM_SYSST);
826
827
828 /*
829 * Initially use the values set by bootloader. Determine PLL rate and
830 * recalculate dependent clocks as if kernel had changed PLL or
831 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
832 * after the SRAM is initialized.
833 */
834 {
835 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
836
837 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
838 if (pll_ctl_val & 0x10) {
839 /* PLL enabled, apply multiplier and divisor */
840 if (pll_ctl_val & 0xf80)
841 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
842 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
843 } else {
844 /* PLL disabled, apply bypass divisor */
845 switch (pll_ctl_val & 0xc) {
846 case 0:
847 break;
848 case 0x4:
849 ck_dpll1.rate /= 2;
850 break;
851 default:
852 ck_dpll1.rate /= 4;
853 break;
854 }
855 }
856 }
857 propagate_rate(&ck_dpll1);
858 /* Cache rates for clocks connected to ck_ref (not dpll1) */
859 propagate_rate(&ck_ref);
860 omap1_show_rates();
861 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
862 /* Select slicer output as OMAP input clock */
863 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
864 OMAP7XX_PCC_UPLD_CTRL);
865 }
866
867 /* Amstrad Delta wants BCLK high when inactive */
868 if (machine_is_ams_delta())
869 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
870 (1 << SDW_MCLK_INV_BIT),
871 ULPD_CLOCK_CTRL);
872
873 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
874 /* (on 730, bit 13 must not be cleared) */
875 if (cpu_is_omap7xx())
876 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
877 else
878 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
879
880 /* Put DSP/MPUI into reset until needed */
881 omap_writew(0, ARM_RSTCT1);
882 omap_writew(1, ARM_RSTCT2);
883 omap_writew(0x400, ARM_IDLECT1);
884
885 /*
886 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
887 * of the ARM_IDLECT2 register must be set to zero. The power-on
888 * default value of this bit is one.
889 */
890 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
891
892 /*
893 * Only enable those clocks we will need, let the drivers
894 * enable other clocks as necessary
895 */
896 clk_enable(&armper_ck.clk);
897 clk_enable(&armxor_ck.clk);
898 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
899
900 if (cpu_is_omap15xx())
901 clk_enable(&arm_gpio_ck);
902
903 return 0;
904}
905
906#define OMAP1_DPLL1_SANE_VALUE 60000000
907
908void __init omap1_clk_late_init(void)
909{
910 unsigned long rate = ck_dpll1.rate;
911
912 /* Find the highest supported frequency and enable it */
913 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
914 pr_err("System frequencies not set, using default. Check your config.\n");
915 /*
916 * Reprogramming the DPLL is tricky, it must be done from SRAM.
917 */
918 omap_sram_reprogram_clock(0x2290, 0x0005);
919 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
920 }
921 propagate_rate(&ck_dpll1);
922 omap1_show_rates();
923 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
924}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap1/clock_data.c
4 *
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 *
9 * To do:
10 * - Clocks that are only available on some chips should be marked with the
11 * chips that they are present on.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/clk.h>
17#include <linux/cpufreq.h>
18#include <linux/delay.h>
19
20#include <asm/mach-types.h> /* for machine_is_* */
21
22#include "soc.h"
23
24#include <mach/hardware.h>
25#include <mach/usb.h> /* for OTG_BASE */
26
27#include "iomap.h"
28#include "clock.h"
29#include "sram.h"
30
31/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
32#define IDL_CLKOUT_ARM_SHIFT 12
33#define IDLTIM_ARM_SHIFT 9
34#define IDLAPI_ARM_SHIFT 8
35#define IDLIF_ARM_SHIFT 6
36#define IDLLB_ARM_SHIFT 4 /* undocumented? */
37#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
38#define IDLPER_ARM_SHIFT 2
39#define IDLXORP_ARM_SHIFT 1
40#define IDLWDT_ARM_SHIFT 0
41
42/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
43#define CONF_MOD_UART3_CLK_MODE_R 31
44#define CONF_MOD_UART2_CLK_MODE_R 30
45#define CONF_MOD_UART1_CLK_MODE_R 29
46#define CONF_MOD_MMC_SD_CLK_REQ_R 23
47#define CONF_MOD_MCBSP3_AUXON 20
48
49/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
50#define CONF_MOD_SOSSI_CLK_EN_R 16
51
52/* Some OTG_SYSCON_2-specific bit fields */
53#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
54
55/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
56#define SOFT_MMC2_DPLL_REQ_SHIFT 13
57#define SOFT_MMC_DPLL_REQ_SHIFT 12
58#define SOFT_UART3_DPLL_REQ_SHIFT 11
59#define SOFT_UART2_DPLL_REQ_SHIFT 10
60#define SOFT_UART1_DPLL_REQ_SHIFT 9
61#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
62#define SOFT_CAM_DPLL_REQ_SHIFT 7
63#define SOFT_COM_MCKO_REQ_SHIFT 6
64#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
65#define USB_REQ_EN_SHIFT 4
66#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
67#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
68#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
69#define SOFT_DPLL_REQ_SHIFT 0
70
71/*
72 * Omap1 clocks
73 */
74
75static struct clk ck_ref = {
76 .name = "ck_ref",
77 .ops = &clkops_null,
78 .rate = 12000000,
79};
80
81static struct clk ck_dpll1 = {
82 .name = "ck_dpll1",
83 .ops = &clkops_null,
84 .parent = &ck_ref,
85};
86
87/*
88 * FIXME: This clock seems to be necessary but no-one has asked for its
89 * activation. [ FIX: SoSSI, SSR ]
90 */
91static struct arm_idlect1_clk ck_dpll1out = {
92 .clk = {
93 .name = "ck_dpll1out",
94 .ops = &clkops_generic,
95 .parent = &ck_dpll1,
96 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
97 ENABLE_ON_INIT,
98 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
99 .enable_bit = EN_CKOUT_ARM,
100 .recalc = &followparent_recalc,
101 },
102 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
103};
104
105static struct clk sossi_ck = {
106 .name = "ck_sossi",
107 .ops = &clkops_generic,
108 .parent = &ck_dpll1out.clk,
109 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
110 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
111 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
112 .recalc = &omap1_sossi_recalc,
113 .set_rate = &omap1_set_sossi_rate,
114};
115
116static struct clk arm_ck = {
117 .name = "arm_ck",
118 .ops = &clkops_null,
119 .parent = &ck_dpll1,
120 .rate_offset = CKCTL_ARMDIV_OFFSET,
121 .recalc = &omap1_ckctl_recalc,
122 .round_rate = omap1_clk_round_rate_ckctl_arm,
123 .set_rate = omap1_clk_set_rate_ckctl_arm,
124};
125
126static struct arm_idlect1_clk armper_ck = {
127 .clk = {
128 .name = "armper_ck",
129 .ops = &clkops_generic,
130 .parent = &ck_dpll1,
131 .flags = CLOCK_IDLE_CONTROL,
132 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
133 .enable_bit = EN_PERCK,
134 .rate_offset = CKCTL_PERDIV_OFFSET,
135 .recalc = &omap1_ckctl_recalc,
136 .round_rate = omap1_clk_round_rate_ckctl_arm,
137 .set_rate = omap1_clk_set_rate_ckctl_arm,
138 },
139 .idlect_shift = IDLPER_ARM_SHIFT,
140};
141
142/*
143 * FIXME: This clock seems to be necessary but no-one has asked for its
144 * activation. [ GPIO code for 1510 ]
145 */
146static struct clk arm_gpio_ck = {
147 .name = "ick",
148 .ops = &clkops_generic,
149 .parent = &ck_dpll1,
150 .flags = ENABLE_ON_INIT,
151 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
152 .enable_bit = EN_GPIOCK,
153 .recalc = &followparent_recalc,
154};
155
156static struct arm_idlect1_clk armxor_ck = {
157 .clk = {
158 .name = "armxor_ck",
159 .ops = &clkops_generic,
160 .parent = &ck_ref,
161 .flags = CLOCK_IDLE_CONTROL,
162 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
163 .enable_bit = EN_XORPCK,
164 .recalc = &followparent_recalc,
165 },
166 .idlect_shift = IDLXORP_ARM_SHIFT,
167};
168
169static struct arm_idlect1_clk armtim_ck = {
170 .clk = {
171 .name = "armtim_ck",
172 .ops = &clkops_generic,
173 .parent = &ck_ref,
174 .flags = CLOCK_IDLE_CONTROL,
175 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
176 .enable_bit = EN_TIMCK,
177 .recalc = &followparent_recalc,
178 },
179 .idlect_shift = IDLTIM_ARM_SHIFT,
180};
181
182static struct arm_idlect1_clk armwdt_ck = {
183 .clk = {
184 .name = "armwdt_ck",
185 .ops = &clkops_generic,
186 .parent = &ck_ref,
187 .flags = CLOCK_IDLE_CONTROL,
188 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
189 .enable_bit = EN_WDTCK,
190 .fixed_div = 14,
191 .recalc = &omap_fixed_divisor_recalc,
192 },
193 .idlect_shift = IDLWDT_ARM_SHIFT,
194};
195
196static struct clk arminth_ck16xx = {
197 .name = "arminth_ck",
198 .ops = &clkops_null,
199 .parent = &arm_ck,
200 .recalc = &followparent_recalc,
201 /* Note: On 16xx the frequency can be divided by 2 by programming
202 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
203 *
204 * 1510 version is in TC clocks.
205 */
206};
207
208static struct clk dsp_ck = {
209 .name = "dsp_ck",
210 .ops = &clkops_generic,
211 .parent = &ck_dpll1,
212 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
213 .enable_bit = EN_DSPCK,
214 .rate_offset = CKCTL_DSPDIV_OFFSET,
215 .recalc = &omap1_ckctl_recalc,
216 .round_rate = omap1_clk_round_rate_ckctl_arm,
217 .set_rate = omap1_clk_set_rate_ckctl_arm,
218};
219
220static struct clk dspmmu_ck = {
221 .name = "dspmmu_ck",
222 .ops = &clkops_null,
223 .parent = &ck_dpll1,
224 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
225 .recalc = &omap1_ckctl_recalc,
226 .round_rate = omap1_clk_round_rate_ckctl_arm,
227 .set_rate = omap1_clk_set_rate_ckctl_arm,
228};
229
230static struct clk dspper_ck = {
231 .name = "dspper_ck",
232 .ops = &clkops_dspck,
233 .parent = &ck_dpll1,
234 .enable_reg = DSP_IDLECT2,
235 .enable_bit = EN_PERCK,
236 .rate_offset = CKCTL_PERDIV_OFFSET,
237 .recalc = &omap1_ckctl_recalc_dsp_domain,
238 .round_rate = omap1_clk_round_rate_ckctl_arm,
239 .set_rate = &omap1_clk_set_rate_dsp_domain,
240};
241
242static struct clk dspxor_ck = {
243 .name = "dspxor_ck",
244 .ops = &clkops_dspck,
245 .parent = &ck_ref,
246 .enable_reg = DSP_IDLECT2,
247 .enable_bit = EN_XORPCK,
248 .recalc = &followparent_recalc,
249};
250
251static struct clk dsptim_ck = {
252 .name = "dsptim_ck",
253 .ops = &clkops_dspck,
254 .parent = &ck_ref,
255 .enable_reg = DSP_IDLECT2,
256 .enable_bit = EN_DSPTIMCK,
257 .recalc = &followparent_recalc,
258};
259
260static struct arm_idlect1_clk tc_ck = {
261 .clk = {
262 .name = "tc_ck",
263 .ops = &clkops_null,
264 .parent = &ck_dpll1,
265 .flags = CLOCK_IDLE_CONTROL,
266 .rate_offset = CKCTL_TCDIV_OFFSET,
267 .recalc = &omap1_ckctl_recalc,
268 .round_rate = omap1_clk_round_rate_ckctl_arm,
269 .set_rate = omap1_clk_set_rate_ckctl_arm,
270 },
271 .idlect_shift = IDLIF_ARM_SHIFT,
272};
273
274static struct clk arminth_ck1510 = {
275 .name = "arminth_ck",
276 .ops = &clkops_null,
277 .parent = &tc_ck.clk,
278 .recalc = &followparent_recalc,
279 /* Note: On 1510 the frequency follows TC_CK
280 *
281 * 16xx version is in MPU clocks.
282 */
283};
284
285static struct clk tipb_ck = {
286 /* No-idle controlled by "tc_ck" */
287 .name = "tipb_ck",
288 .ops = &clkops_null,
289 .parent = &tc_ck.clk,
290 .recalc = &followparent_recalc,
291};
292
293static struct clk l3_ocpi_ck = {
294 /* No-idle controlled by "tc_ck" */
295 .name = "l3_ocpi_ck",
296 .ops = &clkops_generic,
297 .parent = &tc_ck.clk,
298 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
299 .enable_bit = EN_OCPI_CK,
300 .recalc = &followparent_recalc,
301};
302
303static struct clk tc1_ck = {
304 .name = "tc1_ck",
305 .ops = &clkops_generic,
306 .parent = &tc_ck.clk,
307 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
308 .enable_bit = EN_TC1_CK,
309 .recalc = &followparent_recalc,
310};
311
312/*
313 * FIXME: This clock seems to be necessary but no-one has asked for its
314 * activation. [ pm.c (SRAM), CCP, Camera ]
315 */
316static struct clk tc2_ck = {
317 .name = "tc2_ck",
318 .ops = &clkops_generic,
319 .parent = &tc_ck.clk,
320 .flags = ENABLE_ON_INIT,
321 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
322 .enable_bit = EN_TC2_CK,
323 .recalc = &followparent_recalc,
324};
325
326static struct clk dma_ck = {
327 /* No-idle controlled by "tc_ck" */
328 .name = "dma_ck",
329 .ops = &clkops_null,
330 .parent = &tc_ck.clk,
331 .recalc = &followparent_recalc,
332};
333
334static struct clk dma_lcdfree_ck = {
335 .name = "dma_lcdfree_ck",
336 .ops = &clkops_null,
337 .parent = &tc_ck.clk,
338 .recalc = &followparent_recalc,
339};
340
341static struct arm_idlect1_clk api_ck = {
342 .clk = {
343 .name = "api_ck",
344 .ops = &clkops_generic,
345 .parent = &tc_ck.clk,
346 .flags = CLOCK_IDLE_CONTROL,
347 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
348 .enable_bit = EN_APICK,
349 .recalc = &followparent_recalc,
350 },
351 .idlect_shift = IDLAPI_ARM_SHIFT,
352};
353
354static struct arm_idlect1_clk lb_ck = {
355 .clk = {
356 .name = "lb_ck",
357 .ops = &clkops_generic,
358 .parent = &tc_ck.clk,
359 .flags = CLOCK_IDLE_CONTROL,
360 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
361 .enable_bit = EN_LBCK,
362 .recalc = &followparent_recalc,
363 },
364 .idlect_shift = IDLLB_ARM_SHIFT,
365};
366
367static struct clk rhea1_ck = {
368 .name = "rhea1_ck",
369 .ops = &clkops_null,
370 .parent = &tc_ck.clk,
371 .recalc = &followparent_recalc,
372};
373
374static struct clk rhea2_ck = {
375 .name = "rhea2_ck",
376 .ops = &clkops_null,
377 .parent = &tc_ck.clk,
378 .recalc = &followparent_recalc,
379};
380
381static struct clk lcd_ck_16xx = {
382 .name = "lcd_ck",
383 .ops = &clkops_generic,
384 .parent = &ck_dpll1,
385 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
386 .enable_bit = EN_LCDCK,
387 .rate_offset = CKCTL_LCDDIV_OFFSET,
388 .recalc = &omap1_ckctl_recalc,
389 .round_rate = omap1_clk_round_rate_ckctl_arm,
390 .set_rate = omap1_clk_set_rate_ckctl_arm,
391};
392
393static struct arm_idlect1_clk lcd_ck_1510 = {
394 .clk = {
395 .name = "lcd_ck",
396 .ops = &clkops_generic,
397 .parent = &ck_dpll1,
398 .flags = CLOCK_IDLE_CONTROL,
399 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
400 .enable_bit = EN_LCDCK,
401 .rate_offset = CKCTL_LCDDIV_OFFSET,
402 .recalc = &omap1_ckctl_recalc,
403 .round_rate = omap1_clk_round_rate_ckctl_arm,
404 .set_rate = omap1_clk_set_rate_ckctl_arm,
405 },
406 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
407};
408
409/*
410 * XXX The enable_bit here is misused - it simply switches between 12MHz
411 * and 48MHz. Reimplement with clksel.
412 *
413 * XXX does this need SYSC register handling?
414 */
415static struct clk uart1_1510 = {
416 .name = "uart1_ck",
417 .ops = &clkops_null,
418 /* Direct from ULPD, no real parent */
419 .parent = &armper_ck.clk,
420 .rate = 12000000,
421 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
422 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
423 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
424 .set_rate = &omap1_set_uart_rate,
425 .recalc = &omap1_uart_recalc,
426};
427
428/*
429 * XXX The enable_bit here is misused - it simply switches between 12MHz
430 * and 48MHz. Reimplement with clksel.
431 *
432 * XXX SYSC register handling does not belong in the clock framework
433 */
434static struct uart_clk uart1_16xx = {
435 .clk = {
436 .name = "uart1_ck",
437 .ops = &clkops_uart_16xx,
438 /* Direct from ULPD, no real parent */
439 .parent = &armper_ck.clk,
440 .rate = 48000000,
441 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
442 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
443 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
444 },
445 .sysc_addr = 0xfffb0054,
446};
447
448/*
449 * XXX The enable_bit here is misused - it simply switches between 12MHz
450 * and 48MHz. Reimplement with clksel.
451 *
452 * XXX does this need SYSC register handling?
453 */
454static struct clk uart2_ck = {
455 .name = "uart2_ck",
456 .ops = &clkops_null,
457 /* Direct from ULPD, no real parent */
458 .parent = &armper_ck.clk,
459 .rate = 12000000,
460 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
461 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
462 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
463 .set_rate = &omap1_set_uart_rate,
464 .recalc = &omap1_uart_recalc,
465};
466
467/*
468 * XXX The enable_bit here is misused - it simply switches between 12MHz
469 * and 48MHz. Reimplement with clksel.
470 *
471 * XXX does this need SYSC register handling?
472 */
473static struct clk uart3_1510 = {
474 .name = "uart3_ck",
475 .ops = &clkops_null,
476 /* Direct from ULPD, no real parent */
477 .parent = &armper_ck.clk,
478 .rate = 12000000,
479 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
480 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
481 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
482 .set_rate = &omap1_set_uart_rate,
483 .recalc = &omap1_uart_recalc,
484};
485
486/*
487 * XXX The enable_bit here is misused - it simply switches between 12MHz
488 * and 48MHz. Reimplement with clksel.
489 *
490 * XXX SYSC register handling does not belong in the clock framework
491 */
492static struct uart_clk uart3_16xx = {
493 .clk = {
494 .name = "uart3_ck",
495 .ops = &clkops_uart_16xx,
496 /* Direct from ULPD, no real parent */
497 .parent = &armper_ck.clk,
498 .rate = 48000000,
499 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
500 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
501 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
502 },
503 .sysc_addr = 0xfffb9854,
504};
505
506static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
507 .name = "usb_clko",
508 .ops = &clkops_generic,
509 /* Direct from ULPD, no parent */
510 .rate = 6000000,
511 .flags = ENABLE_REG_32BIT,
512 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
513 .enable_bit = USB_MCLK_EN_BIT,
514};
515
516static struct clk usb_hhc_ck1510 = {
517 .name = "usb_hhc_ck",
518 .ops = &clkops_generic,
519 /* Direct from ULPD, no parent */
520 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
521 .flags = ENABLE_REG_32BIT,
522 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
523 .enable_bit = USB_HOST_HHC_UHOST_EN,
524};
525
526static struct clk usb_hhc_ck16xx = {
527 .name = "usb_hhc_ck",
528 .ops = &clkops_generic,
529 /* Direct from ULPD, no parent */
530 .rate = 48000000,
531 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
532 .flags = ENABLE_REG_32BIT,
533 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
534 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
535};
536
537static struct clk usb_dc_ck = {
538 .name = "usb_dc_ck",
539 .ops = &clkops_generic,
540 /* Direct from ULPD, no parent */
541 .rate = 48000000,
542 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
543 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
544};
545
546static struct clk uart1_7xx = {
547 .name = "uart1_ck",
548 .ops = &clkops_generic,
549 /* Direct from ULPD, no parent */
550 .rate = 12000000,
551 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
552 .enable_bit = 9,
553};
554
555static struct clk uart2_7xx = {
556 .name = "uart2_ck",
557 .ops = &clkops_generic,
558 /* Direct from ULPD, no parent */
559 .rate = 12000000,
560 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
561 .enable_bit = 11,
562};
563
564static struct clk mclk_1510 = {
565 .name = "mclk",
566 .ops = &clkops_generic,
567 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
568 .rate = 12000000,
569 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
570 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
571};
572
573static struct clk mclk_16xx = {
574 .name = "mclk",
575 .ops = &clkops_generic,
576 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
577 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
578 .enable_bit = COM_ULPD_PLL_CLK_REQ,
579 .set_rate = &omap1_set_ext_clk_rate,
580 .round_rate = &omap1_round_ext_clk_rate,
581 .init = &omap1_init_ext_clk,
582};
583
584static struct clk bclk_1510 = {
585 .name = "bclk",
586 .ops = &clkops_generic,
587 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
588 .rate = 12000000,
589};
590
591static struct clk bclk_16xx = {
592 .name = "bclk",
593 .ops = &clkops_generic,
594 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
595 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
596 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
597 .set_rate = &omap1_set_ext_clk_rate,
598 .round_rate = &omap1_round_ext_clk_rate,
599 .init = &omap1_init_ext_clk,
600};
601
602static struct clk mmc1_ck = {
603 .name = "mmc1_ck",
604 .ops = &clkops_generic,
605 /* Functional clock is direct from ULPD, interface clock is ARMPER */
606 .parent = &armper_ck.clk,
607 .rate = 48000000,
608 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
609 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
610 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
611};
612
613/*
614 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
615 * CONF_MOD_MCBSP3_AUXON ??
616 */
617static struct clk mmc2_ck = {
618 .name = "mmc2_ck",
619 .ops = &clkops_generic,
620 /* Functional clock is direct from ULPD, interface clock is ARMPER */
621 .parent = &armper_ck.clk,
622 .rate = 48000000,
623 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
624 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
625 .enable_bit = 20,
626};
627
628static struct clk mmc3_ck = {
629 .name = "mmc3_ck",
630 .ops = &clkops_generic,
631 /* Functional clock is direct from ULPD, interface clock is ARMPER */
632 .parent = &armper_ck.clk,
633 .rate = 48000000,
634 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
635 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
636 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
637};
638
639static struct clk virtual_ck_mpu = {
640 .name = "mpu",
641 .ops = &clkops_null,
642 .parent = &arm_ck, /* Is smarter alias for */
643 .recalc = &followparent_recalc,
644 .set_rate = &omap1_select_table_rate,
645 .round_rate = &omap1_round_to_table_rate,
646};
647
648/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
649remains active during MPU idle whenever this is enabled */
650static struct clk i2c_fck = {
651 .name = "i2c_fck",
652 .ops = &clkops_null,
653 .flags = CLOCK_NO_IDLE_PARENT,
654 .parent = &armxor_ck.clk,
655 .recalc = &followparent_recalc,
656};
657
658static struct clk i2c_ick = {
659 .name = "i2c_ick",
660 .ops = &clkops_null,
661 .flags = CLOCK_NO_IDLE_PARENT,
662 .parent = &armper_ck.clk,
663 .recalc = &followparent_recalc,
664};
665
666/*
667 * clkdev integration
668 */
669
670static struct omap_clk omap_clks[] = {
671 /* non-ULPD clocks */
672 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
673 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
674 /* CK_GEN1 clocks */
675 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
676 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
677 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
678 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
679 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
680 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
681 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
682 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
683 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
684 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
685 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
686 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
687 /* CK_GEN2 clocks */
688 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
689 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
690 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
691 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
692 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
693 /* CK_GEN3 clocks */
694 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
695 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
696 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
697 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
698 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
699 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
700 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
701 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
702 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
703 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
704 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
705 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
706 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
707 /* ULPD clocks */
708 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
709 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
710 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
711 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
712 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
713 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
714 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
715 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
716 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
717 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
718 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
719 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
720 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
721 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
722 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
723 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
724 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
725 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
726 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
727 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
728 /* Virtual clocks */
729 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
730 CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
731 CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
732 CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
733 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
734 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
735 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
736 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
737 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
738 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
739 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
740 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
741 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
742 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
743 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
744 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
745 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
746 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
747};
748
749/*
750 * init
751 */
752
753static void __init omap1_show_rates(void)
754{
755 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
756 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
757 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
758 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
759}
760
761u32 cpu_mask;
762
763int __init omap1_clk_init(void)
764{
765 struct omap_clk *c;
766 int crystal_type = 0; /* Default 12 MHz */
767 u32 reg;
768
769#ifdef CONFIG_DEBUG_LL
770 /*
771 * Resets some clocks that may be left on from bootloader,
772 * but leaves serial clocks on.
773 */
774 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
775#endif
776
777 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
778 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
779 omap_writew(reg, SOFT_REQ_REG);
780 if (!cpu_is_omap15xx())
781 omap_writew(0, SOFT_REQ_REG2);
782
783 /* By default all idlect1 clocks are allowed to idle */
784 arm_idlect1_mask = ~0;
785
786 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
787 clk_preinit(c->lk.clk);
788
789 cpu_mask = 0;
790 if (cpu_is_omap1710())
791 cpu_mask |= CK_1710;
792 if (cpu_is_omap16xx())
793 cpu_mask |= CK_16XX;
794 if (cpu_is_omap1510())
795 cpu_mask |= CK_1510;
796 if (cpu_is_omap7xx())
797 cpu_mask |= CK_7XX;
798 if (cpu_is_omap310())
799 cpu_mask |= CK_310;
800
801 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
802 if (c->cpu & cpu_mask) {
803 clkdev_add(&c->lk);
804 clk_register(c->lk.clk);
805 }
806
807 /* Pointers to these clocks are needed by code in clock.c */
808 api_ck_p = clk_get(NULL, "api_ck");
809 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
810 ck_ref_p = clk_get(NULL, "ck_ref");
811
812 if (cpu_is_omap7xx())
813 ck_ref.rate = 13000000;
814 if (cpu_is_omap16xx() && crystal_type == 2)
815 ck_ref.rate = 19200000;
816
817 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
818 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
819 omap_readw(ARM_CKCTL));
820
821 /* We want to be in syncronous scalable mode */
822 omap_writew(0x1000, ARM_SYSST);
823
824
825 /*
826 * Initially use the values set by bootloader. Determine PLL rate and
827 * recalculate dependent clocks as if kernel had changed PLL or
828 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
829 * after the SRAM is initialized.
830 */
831 {
832 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
833
834 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
835 if (pll_ctl_val & 0x10) {
836 /* PLL enabled, apply multiplier and divisor */
837 if (pll_ctl_val & 0xf80)
838 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
839 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
840 } else {
841 /* PLL disabled, apply bypass divisor */
842 switch (pll_ctl_val & 0xc) {
843 case 0:
844 break;
845 case 0x4:
846 ck_dpll1.rate /= 2;
847 break;
848 default:
849 ck_dpll1.rate /= 4;
850 break;
851 }
852 }
853 }
854 propagate_rate(&ck_dpll1);
855 /* Cache rates for clocks connected to ck_ref (not dpll1) */
856 propagate_rate(&ck_ref);
857 omap1_show_rates();
858 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
859 /* Select slicer output as OMAP input clock */
860 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
861 OMAP7XX_PCC_UPLD_CTRL);
862 }
863
864 /* Amstrad Delta wants BCLK high when inactive */
865 if (machine_is_ams_delta())
866 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
867 (1 << SDW_MCLK_INV_BIT),
868 ULPD_CLOCK_CTRL);
869
870 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
871 /* (on 730, bit 13 must not be cleared) */
872 if (cpu_is_omap7xx())
873 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
874 else
875 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
876
877 /* Put DSP/MPUI into reset until needed */
878 omap_writew(0, ARM_RSTCT1);
879 omap_writew(1, ARM_RSTCT2);
880 omap_writew(0x400, ARM_IDLECT1);
881
882 /*
883 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
884 * of the ARM_IDLECT2 register must be set to zero. The power-on
885 * default value of this bit is one.
886 */
887 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
888
889 /*
890 * Only enable those clocks we will need, let the drivers
891 * enable other clocks as necessary
892 */
893 clk_enable(&armper_ck.clk);
894 clk_enable(&armxor_ck.clk);
895 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
896
897 if (cpu_is_omap15xx())
898 clk_enable(&arm_gpio_ck);
899
900 return 0;
901}
902
903#define OMAP1_DPLL1_SANE_VALUE 60000000
904
905void __init omap1_clk_late_init(void)
906{
907 unsigned long rate = ck_dpll1.rate;
908
909 /* Find the highest supported frequency and enable it */
910 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
911 pr_err("System frequencies not set, using default. Check your config.\n");
912 /*
913 * Reprogramming the DPLL is tricky, it must be done from SRAM.
914 */
915 omap_sram_reprogram_clock(0x2290, 0x0005);
916 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
917 }
918 propagate_rate(&ck_dpll1);
919 omap1_show_rates();
920 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
921}