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1/*
2 * PCA953x 4/8/16/24/40 bit I/O ports
3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/gpio.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/i2c.h>
21#include <linux/platform_data/pca953x.h>
22#include <linux/slab.h>
23#ifdef CONFIG_OF_GPIO
24#include <linux/of_platform.h>
25#endif
26
27#define PCA953X_INPUT 0
28#define PCA953X_OUTPUT 1
29#define PCA953X_INVERT 2
30#define PCA953X_DIRECTION 3
31
32#define REG_ADDR_AI 0x80
33
34#define PCA957X_IN 0
35#define PCA957X_INVRT 1
36#define PCA957X_BKEN 2
37#define PCA957X_PUPD 3
38#define PCA957X_CFG 4
39#define PCA957X_OUT 5
40#define PCA957X_MSK 6
41#define PCA957X_INTS 7
42
43#define PCA_GPIO_MASK 0x00FF
44#define PCA_INT 0x0100
45#define PCA953X_TYPE 0x1000
46#define PCA957X_TYPE 0x2000
47
48static const struct i2c_device_id pca953x_id[] = {
49 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
50 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
51 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
52 { "pca9536", 4 | PCA953X_TYPE, },
53 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
54 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
55 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
56 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
57 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
58 { "pca9556", 8 | PCA953X_TYPE, },
59 { "pca9557", 8 | PCA953X_TYPE, },
60 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
61 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
62 { "pca9698", 40 | PCA953X_TYPE, },
63
64 { "max7310", 8 | PCA953X_TYPE, },
65 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
66 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
67 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
68 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
69 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
70 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
71 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
72 { "xra1202", 8 | PCA953X_TYPE },
73 { }
74};
75MODULE_DEVICE_TABLE(i2c, pca953x_id);
76
77#define MAX_BANK 5
78#define BANK_SZ 8
79
80#define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
81
82struct pca953x_chip {
83 unsigned gpio_start;
84 u8 reg_output[MAX_BANK];
85 u8 reg_direction[MAX_BANK];
86 struct mutex i2c_lock;
87
88#ifdef CONFIG_GPIO_PCA953X_IRQ
89 struct mutex irq_lock;
90 u8 irq_mask[MAX_BANK];
91 u8 irq_stat[MAX_BANK];
92 u8 irq_trig_raise[MAX_BANK];
93 u8 irq_trig_fall[MAX_BANK];
94 struct irq_domain *domain;
95#endif
96
97 struct i2c_client *client;
98 struct gpio_chip gpio_chip;
99 const char *const *names;
100 int chip_type;
101};
102
103static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
104 int off)
105{
106 int ret;
107 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
108 int offset = off / BANK_SZ;
109
110 ret = i2c_smbus_read_byte_data(chip->client,
111 (reg << bank_shift) + offset);
112 *val = ret;
113
114 if (ret < 0) {
115 dev_err(&chip->client->dev, "failed reading register\n");
116 return ret;
117 }
118
119 return 0;
120}
121
122static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
123 int off)
124{
125 int ret = 0;
126 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
127 int offset = off / BANK_SZ;
128
129 ret = i2c_smbus_write_byte_data(chip->client,
130 (reg << bank_shift) + offset, val);
131
132 if (ret < 0) {
133 dev_err(&chip->client->dev, "failed writing register\n");
134 return ret;
135 }
136
137 return 0;
138}
139
140static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
141{
142 int ret = 0;
143
144 if (chip->gpio_chip.ngpio <= 8)
145 ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
146 else if (chip->gpio_chip.ngpio >= 24) {
147 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
148 ret = i2c_smbus_write_i2c_block_data(chip->client,
149 (reg << bank_shift) | REG_ADDR_AI,
150 NBANK(chip), val);
151 } else {
152 switch (chip->chip_type) {
153 case PCA953X_TYPE:
154 ret = i2c_smbus_write_word_data(chip->client,
155 reg << 1, (u16) *val);
156 break;
157 case PCA957X_TYPE:
158 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
159 val[0]);
160 if (ret < 0)
161 break;
162 ret = i2c_smbus_write_byte_data(chip->client,
163 (reg << 1) + 1,
164 val[1]);
165 break;
166 }
167 }
168
169 if (ret < 0) {
170 dev_err(&chip->client->dev, "failed writing register\n");
171 return ret;
172 }
173
174 return 0;
175}
176
177static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
178{
179 int ret;
180
181 if (chip->gpio_chip.ngpio <= 8) {
182 ret = i2c_smbus_read_byte_data(chip->client, reg);
183 *val = ret;
184 } else if (chip->gpio_chip.ngpio >= 24) {
185 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
186
187 ret = i2c_smbus_read_i2c_block_data(chip->client,
188 (reg << bank_shift) | REG_ADDR_AI,
189 NBANK(chip), val);
190 } else {
191 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
192 val[0] = (u16)ret & 0xFF;
193 val[1] = (u16)ret >> 8;
194 }
195 if (ret < 0) {
196 dev_err(&chip->client->dev, "failed reading register\n");
197 return ret;
198 }
199
200 return 0;
201}
202
203static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
204{
205 struct pca953x_chip *chip;
206 u8 reg_val;
207 int ret, offset = 0;
208
209 chip = container_of(gc, struct pca953x_chip, gpio_chip);
210
211 mutex_lock(&chip->i2c_lock);
212 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
213
214 switch (chip->chip_type) {
215 case PCA953X_TYPE:
216 offset = PCA953X_DIRECTION;
217 break;
218 case PCA957X_TYPE:
219 offset = PCA957X_CFG;
220 break;
221 }
222 ret = pca953x_write_single(chip, offset, reg_val, off);
223 if (ret)
224 goto exit;
225
226 chip->reg_direction[off / BANK_SZ] = reg_val;
227 ret = 0;
228exit:
229 mutex_unlock(&chip->i2c_lock);
230 return ret;
231}
232
233static int pca953x_gpio_direction_output(struct gpio_chip *gc,
234 unsigned off, int val)
235{
236 struct pca953x_chip *chip;
237 u8 reg_val;
238 int ret, offset = 0;
239
240 chip = container_of(gc, struct pca953x_chip, gpio_chip);
241
242 mutex_lock(&chip->i2c_lock);
243 /* set output level */
244 if (val)
245 reg_val = chip->reg_output[off / BANK_SZ]
246 | (1u << (off % BANK_SZ));
247 else
248 reg_val = chip->reg_output[off / BANK_SZ]
249 & ~(1u << (off % BANK_SZ));
250
251 switch (chip->chip_type) {
252 case PCA953X_TYPE:
253 offset = PCA953X_OUTPUT;
254 break;
255 case PCA957X_TYPE:
256 offset = PCA957X_OUT;
257 break;
258 }
259 ret = pca953x_write_single(chip, offset, reg_val, off);
260 if (ret)
261 goto exit;
262
263 chip->reg_output[off / BANK_SZ] = reg_val;
264
265 /* then direction */
266 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
267 switch (chip->chip_type) {
268 case PCA953X_TYPE:
269 offset = PCA953X_DIRECTION;
270 break;
271 case PCA957X_TYPE:
272 offset = PCA957X_CFG;
273 break;
274 }
275 ret = pca953x_write_single(chip, offset, reg_val, off);
276 if (ret)
277 goto exit;
278
279 chip->reg_direction[off / BANK_SZ] = reg_val;
280 ret = 0;
281exit:
282 mutex_unlock(&chip->i2c_lock);
283 return ret;
284}
285
286static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
287{
288 struct pca953x_chip *chip;
289 u32 reg_val;
290 int ret, offset = 0;
291
292 chip = container_of(gc, struct pca953x_chip, gpio_chip);
293
294 mutex_lock(&chip->i2c_lock);
295 switch (chip->chip_type) {
296 case PCA953X_TYPE:
297 offset = PCA953X_INPUT;
298 break;
299 case PCA957X_TYPE:
300 offset = PCA957X_IN;
301 break;
302 }
303 ret = pca953x_read_single(chip, offset, ®_val, off);
304 mutex_unlock(&chip->i2c_lock);
305 if (ret < 0) {
306 /* NOTE: diagnostic already emitted; that's all we should
307 * do unless gpio_*_value_cansleep() calls become different
308 * from their nonsleeping siblings (and report faults).
309 */
310 return 0;
311 }
312
313 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
314}
315
316static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
317{
318 struct pca953x_chip *chip;
319 u8 reg_val;
320 int ret, offset = 0;
321
322 chip = container_of(gc, struct pca953x_chip, gpio_chip);
323
324 mutex_lock(&chip->i2c_lock);
325 if (val)
326 reg_val = chip->reg_output[off / BANK_SZ]
327 | (1u << (off % BANK_SZ));
328 else
329 reg_val = chip->reg_output[off / BANK_SZ]
330 & ~(1u << (off % BANK_SZ));
331
332 switch (chip->chip_type) {
333 case PCA953X_TYPE:
334 offset = PCA953X_OUTPUT;
335 break;
336 case PCA957X_TYPE:
337 offset = PCA957X_OUT;
338 break;
339 }
340 ret = pca953x_write_single(chip, offset, reg_val, off);
341 if (ret)
342 goto exit;
343
344 chip->reg_output[off / BANK_SZ] = reg_val;
345exit:
346 mutex_unlock(&chip->i2c_lock);
347}
348
349static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
350{
351 struct gpio_chip *gc;
352
353 gc = &chip->gpio_chip;
354
355 gc->direction_input = pca953x_gpio_direction_input;
356 gc->direction_output = pca953x_gpio_direction_output;
357 gc->get = pca953x_gpio_get_value;
358 gc->set = pca953x_gpio_set_value;
359 gc->can_sleep = true;
360
361 gc->base = chip->gpio_start;
362 gc->ngpio = gpios;
363 gc->label = chip->client->name;
364 gc->dev = &chip->client->dev;
365 gc->owner = THIS_MODULE;
366 gc->names = chip->names;
367}
368
369#ifdef CONFIG_GPIO_PCA953X_IRQ
370static int pca953x_gpio_to_irq(struct gpio_chip *gc, unsigned off)
371{
372 struct pca953x_chip *chip;
373
374 chip = container_of(gc, struct pca953x_chip, gpio_chip);
375 return irq_create_mapping(chip->domain, off);
376}
377
378static void pca953x_irq_mask(struct irq_data *d)
379{
380 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
381
382 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
383}
384
385static void pca953x_irq_unmask(struct irq_data *d)
386{
387 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
388
389 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
390}
391
392static void pca953x_irq_bus_lock(struct irq_data *d)
393{
394 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
395
396 mutex_lock(&chip->irq_lock);
397}
398
399static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
400{
401 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
402 u8 new_irqs;
403 int level, i;
404
405 /* Look for any newly setup interrupt */
406 for (i = 0; i < NBANK(chip); i++) {
407 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
408 new_irqs &= ~chip->reg_direction[i];
409
410 while (new_irqs) {
411 level = __ffs(new_irqs);
412 pca953x_gpio_direction_input(&chip->gpio_chip,
413 level + (BANK_SZ * i));
414 new_irqs &= ~(1 << level);
415 }
416 }
417
418 mutex_unlock(&chip->irq_lock);
419}
420
421static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
422{
423 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
424 int bank_nb = d->hwirq / BANK_SZ;
425 u8 mask = 1 << (d->hwirq % BANK_SZ);
426
427 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
428 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
429 d->irq, type);
430 return -EINVAL;
431 }
432
433 if (type & IRQ_TYPE_EDGE_FALLING)
434 chip->irq_trig_fall[bank_nb] |= mask;
435 else
436 chip->irq_trig_fall[bank_nb] &= ~mask;
437
438 if (type & IRQ_TYPE_EDGE_RISING)
439 chip->irq_trig_raise[bank_nb] |= mask;
440 else
441 chip->irq_trig_raise[bank_nb] &= ~mask;
442
443 return 0;
444}
445
446static struct irq_chip pca953x_irq_chip = {
447 .name = "pca953x",
448 .irq_mask = pca953x_irq_mask,
449 .irq_unmask = pca953x_irq_unmask,
450 .irq_bus_lock = pca953x_irq_bus_lock,
451 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
452 .irq_set_type = pca953x_irq_set_type,
453};
454
455static u8 pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
456{
457 u8 cur_stat[MAX_BANK];
458 u8 old_stat[MAX_BANK];
459 u8 pendings = 0;
460 u8 trigger[MAX_BANK], triggers = 0;
461 int ret, i, offset = 0;
462
463 switch (chip->chip_type) {
464 case PCA953X_TYPE:
465 offset = PCA953X_INPUT;
466 break;
467 case PCA957X_TYPE:
468 offset = PCA957X_IN;
469 break;
470 }
471 ret = pca953x_read_regs(chip, offset, cur_stat);
472 if (ret)
473 return 0;
474
475 /* Remove output pins from the equation */
476 for (i = 0; i < NBANK(chip); i++)
477 cur_stat[i] &= chip->reg_direction[i];
478
479 memcpy(old_stat, chip->irq_stat, NBANK(chip));
480
481 for (i = 0; i < NBANK(chip); i++) {
482 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
483 triggers += trigger[i];
484 }
485
486 if (!triggers)
487 return 0;
488
489 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
490
491 for (i = 0; i < NBANK(chip); i++) {
492 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
493 (cur_stat[i] & chip->irq_trig_raise[i]);
494 pending[i] &= trigger[i];
495 pendings += pending[i];
496 }
497
498 return pendings;
499}
500
501static irqreturn_t pca953x_irq_handler(int irq, void *devid)
502{
503 struct pca953x_chip *chip = devid;
504 u8 pending[MAX_BANK];
505 u8 level;
506 int i;
507
508 if (!pca953x_irq_pending(chip, pending))
509 return IRQ_HANDLED;
510
511 for (i = 0; i < NBANK(chip); i++) {
512 while (pending[i]) {
513 level = __ffs(pending[i]);
514 handle_nested_irq(irq_find_mapping(chip->domain,
515 level + (BANK_SZ * i)));
516 pending[i] &= ~(1 << level);
517 }
518 }
519
520 return IRQ_HANDLED;
521}
522
523static int pca953x_gpio_irq_map(struct irq_domain *d, unsigned int irq,
524 irq_hw_number_t hwirq)
525{
526 irq_clear_status_flags(irq, IRQ_NOREQUEST);
527 irq_set_chip_data(irq, d->host_data);
528 irq_set_chip(irq, &pca953x_irq_chip);
529 irq_set_nested_thread(irq, true);
530#ifdef CONFIG_ARM
531 set_irq_flags(irq, IRQF_VALID);
532#else
533 irq_set_noprobe(irq);
534#endif
535
536 return 0;
537}
538
539static const struct irq_domain_ops pca953x_irq_simple_ops = {
540 .map = pca953x_gpio_irq_map,
541 .xlate = irq_domain_xlate_twocell,
542};
543
544static int pca953x_irq_setup(struct pca953x_chip *chip,
545 const struct i2c_device_id *id,
546 int irq_base)
547{
548 struct i2c_client *client = chip->client;
549 int ret, i, offset = 0;
550
551 if (irq_base != -1
552 && (id->driver_data & PCA_INT)) {
553
554 switch (chip->chip_type) {
555 case PCA953X_TYPE:
556 offset = PCA953X_INPUT;
557 break;
558 case PCA957X_TYPE:
559 offset = PCA957X_IN;
560 break;
561 }
562 ret = pca953x_read_regs(chip, offset, chip->irq_stat);
563 if (ret)
564 return ret;
565
566 /*
567 * There is no way to know which GPIO line generated the
568 * interrupt. We have to rely on the previous read for
569 * this purpose.
570 */
571 for (i = 0; i < NBANK(chip); i++)
572 chip->irq_stat[i] &= chip->reg_direction[i];
573 mutex_init(&chip->irq_lock);
574
575 chip->domain = irq_domain_add_simple(client->dev.of_node,
576 chip->gpio_chip.ngpio,
577 irq_base,
578 &pca953x_irq_simple_ops,
579 chip);
580 if (!chip->domain)
581 return -ENODEV;
582
583 ret = devm_request_threaded_irq(&client->dev,
584 client->irq,
585 NULL,
586 pca953x_irq_handler,
587 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
588 dev_name(&client->dev), chip);
589 if (ret) {
590 dev_err(&client->dev, "failed to request irq %d\n",
591 client->irq);
592 return ret;
593 }
594
595 chip->gpio_chip.to_irq = pca953x_gpio_to_irq;
596 }
597
598 return 0;
599}
600
601#else /* CONFIG_GPIO_PCA953X_IRQ */
602static int pca953x_irq_setup(struct pca953x_chip *chip,
603 const struct i2c_device_id *id,
604 int irq_base)
605{
606 struct i2c_client *client = chip->client;
607
608 if (irq_base != -1 && (id->driver_data & PCA_INT))
609 dev_warn(&client->dev, "interrupt support not compiled in\n");
610
611 return 0;
612}
613#endif
614
615/*
616 * Handlers for alternative sources of platform_data
617 */
618#ifdef CONFIG_OF_GPIO
619/*
620 * Translate OpenFirmware node properties into platform_data
621 * WARNING: This is DEPRECATED and will be removed eventually!
622 */
623static void
624pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
625{
626 struct device_node *node;
627 const __be32 *val;
628 int size;
629
630 *gpio_base = -1;
631
632 node = client->dev.of_node;
633 if (node == NULL)
634 return;
635
636 val = of_get_property(node, "linux,gpio-base", &size);
637 WARN(val, "%s: device-tree property 'linux,gpio-base' is deprecated!", __func__);
638 if (val) {
639 if (size != sizeof(*val))
640 dev_warn(&client->dev, "%s: wrong linux,gpio-base\n",
641 node->full_name);
642 else
643 *gpio_base = be32_to_cpup(val);
644 }
645
646 val = of_get_property(node, "polarity", NULL);
647 WARN(val, "%s: device-tree property 'polarity' is deprecated!", __func__);
648 if (val)
649 *invert = *val;
650}
651#else
652static void
653pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
654{
655 *gpio_base = -1;
656}
657#endif
658
659static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
660{
661 int ret;
662 u8 val[MAX_BANK];
663
664 ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
665 if (ret)
666 goto out;
667
668 ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
669 chip->reg_direction);
670 if (ret)
671 goto out;
672
673 /* set platform specific polarity inversion */
674 if (invert)
675 memset(val, 0xFF, NBANK(chip));
676 else
677 memset(val, 0, NBANK(chip));
678
679 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
680out:
681 return ret;
682}
683
684static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
685{
686 int ret;
687 u8 val[MAX_BANK];
688
689 ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
690 if (ret)
691 goto out;
692 ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
693 if (ret)
694 goto out;
695
696 /* set platform specific polarity inversion */
697 if (invert)
698 memset(val, 0xFF, NBANK(chip));
699 else
700 memset(val, 0, NBANK(chip));
701 pca953x_write_regs(chip, PCA957X_INVRT, val);
702
703 /* To enable register 6, 7 to controll pull up and pull down */
704 memset(val, 0x02, NBANK(chip));
705 pca953x_write_regs(chip, PCA957X_BKEN, val);
706
707 return 0;
708out:
709 return ret;
710}
711
712static int pca953x_probe(struct i2c_client *client,
713 const struct i2c_device_id *id)
714{
715 struct pca953x_platform_data *pdata;
716 struct pca953x_chip *chip;
717 int irq_base = 0;
718 int ret;
719 u32 invert = 0;
720
721 chip = devm_kzalloc(&client->dev,
722 sizeof(struct pca953x_chip), GFP_KERNEL);
723 if (chip == NULL)
724 return -ENOMEM;
725
726 pdata = dev_get_platdata(&client->dev);
727 if (pdata) {
728 irq_base = pdata->irq_base;
729 chip->gpio_start = pdata->gpio_base;
730 invert = pdata->invert;
731 chip->names = pdata->names;
732 } else {
733 pca953x_get_alt_pdata(client, &chip->gpio_start, &invert);
734#ifdef CONFIG_OF_GPIO
735 /* If I2C node has no interrupts property, disable GPIO interrupts */
736 if (of_find_property(client->dev.of_node, "interrupts", NULL) == NULL)
737 irq_base = -1;
738#endif
739 }
740
741 chip->client = client;
742
743 chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
744
745 mutex_init(&chip->i2c_lock);
746
747 /* initialize cached registers from their original values.
748 * we can't share this chip with another i2c master.
749 */
750 pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
751
752 if (chip->chip_type == PCA953X_TYPE)
753 ret = device_pca953x_init(chip, invert);
754 else
755 ret = device_pca957x_init(chip, invert);
756 if (ret)
757 return ret;
758
759 ret = pca953x_irq_setup(chip, id, irq_base);
760 if (ret)
761 return ret;
762
763 ret = gpiochip_add(&chip->gpio_chip);
764 if (ret)
765 return ret;
766
767 if (pdata && pdata->setup) {
768 ret = pdata->setup(client, chip->gpio_chip.base,
769 chip->gpio_chip.ngpio, pdata->context);
770 if (ret < 0)
771 dev_warn(&client->dev, "setup failed, %d\n", ret);
772 }
773
774 i2c_set_clientdata(client, chip);
775 return 0;
776}
777
778static int pca953x_remove(struct i2c_client *client)
779{
780 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
781 struct pca953x_chip *chip = i2c_get_clientdata(client);
782 int ret = 0;
783
784 if (pdata && pdata->teardown) {
785 ret = pdata->teardown(client, chip->gpio_chip.base,
786 chip->gpio_chip.ngpio, pdata->context);
787 if (ret < 0) {
788 dev_err(&client->dev, "%s failed, %d\n",
789 "teardown", ret);
790 return ret;
791 }
792 }
793
794 ret = gpiochip_remove(&chip->gpio_chip);
795 if (ret) {
796 dev_err(&client->dev, "%s failed, %d\n",
797 "gpiochip_remove()", ret);
798 return ret;
799 }
800
801 return 0;
802}
803
804static const struct of_device_id pca953x_dt_ids[] = {
805 { .compatible = "nxp,pca9505", },
806 { .compatible = "nxp,pca9534", },
807 { .compatible = "nxp,pca9535", },
808 { .compatible = "nxp,pca9536", },
809 { .compatible = "nxp,pca9537", },
810 { .compatible = "nxp,pca9538", },
811 { .compatible = "nxp,pca9539", },
812 { .compatible = "nxp,pca9554", },
813 { .compatible = "nxp,pca9555", },
814 { .compatible = "nxp,pca9556", },
815 { .compatible = "nxp,pca9557", },
816 { .compatible = "nxp,pca9574", },
817 { .compatible = "nxp,pca9575", },
818 { .compatible = "nxp,pca9698", },
819
820 { .compatible = "maxim,max7310", },
821 { .compatible = "maxim,max7312", },
822 { .compatible = "maxim,max7313", },
823 { .compatible = "maxim,max7315", },
824
825 { .compatible = "ti,pca6107", },
826 { .compatible = "ti,tca6408", },
827 { .compatible = "ti,tca6416", },
828 { .compatible = "ti,tca6424", },
829
830 { .compatible = "exar,xra1202", },
831 { }
832};
833
834MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
835
836static struct i2c_driver pca953x_driver = {
837 .driver = {
838 .name = "pca953x",
839 .of_match_table = pca953x_dt_ids,
840 },
841 .probe = pca953x_probe,
842 .remove = pca953x_remove,
843 .id_table = pca953x_id,
844};
845
846static int __init pca953x_init(void)
847{
848 return i2c_add_driver(&pca953x_driver);
849}
850/* register after i2c postcore initcall and before
851 * subsys initcalls that may rely on these GPIOs
852 */
853subsys_initcall(pca953x_init);
854
855static void __exit pca953x_exit(void)
856{
857 i2c_del_driver(&pca953x_driver);
858}
859module_exit(pca953x_exit);
860
861MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
862MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
863MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * PCA953x 4/8/16/24/40 bit I/O ports
4 *
5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * Derived from drivers/i2c/chips/pca9539.c
9 */
10
11#include <linux/acpi.h>
12#include <linux/bits.h>
13#include <linux/gpio/driver.h>
14#include <linux/gpio/consumer.h>
15#include <linux/i2c.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/of_platform.h>
20#include <linux/platform_data/pca953x.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24
25#include <asm/unaligned.h>
26
27#define PCA953X_INPUT 0x00
28#define PCA953X_OUTPUT 0x01
29#define PCA953X_INVERT 0x02
30#define PCA953X_DIRECTION 0x03
31
32#define REG_ADDR_MASK GENMASK(5, 0)
33#define REG_ADDR_EXT BIT(6)
34#define REG_ADDR_AI BIT(7)
35
36#define PCA957X_IN 0x00
37#define PCA957X_INVRT 0x01
38#define PCA957X_BKEN 0x02
39#define PCA957X_PUPD 0x03
40#define PCA957X_CFG 0x04
41#define PCA957X_OUT 0x05
42#define PCA957X_MSK 0x06
43#define PCA957X_INTS 0x07
44
45#define PCAL953X_OUT_STRENGTH 0x20
46#define PCAL953X_IN_LATCH 0x22
47#define PCAL953X_PULL_EN 0x23
48#define PCAL953X_PULL_SEL 0x24
49#define PCAL953X_INT_MASK 0x25
50#define PCAL953X_INT_STAT 0x26
51#define PCAL953X_OUT_CONF 0x27
52
53#define PCAL6524_INT_EDGE 0x28
54#define PCAL6524_INT_CLR 0x2a
55#define PCAL6524_IN_STATUS 0x2b
56#define PCAL6524_OUT_INDCONF 0x2c
57#define PCAL6524_DEBOUNCE 0x2d
58
59#define PCA_GPIO_MASK GENMASK(7, 0)
60
61#define PCAL_GPIO_MASK GENMASK(4, 0)
62#define PCAL_PINCTRL_MASK GENMASK(6, 5)
63
64#define PCA_INT BIT(8)
65#define PCA_PCAL BIT(9)
66#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
67#define PCA953X_TYPE BIT(12)
68#define PCA957X_TYPE BIT(13)
69#define PCA_TYPE_MASK GENMASK(15, 12)
70
71#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
72
73static const struct i2c_device_id pca953x_id[] = {
74 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
75 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
76 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
77 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
78 { "pca9536", 4 | PCA953X_TYPE, },
79 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
80 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
81 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
82 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
83 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
84 { "pca9556", 8 | PCA953X_TYPE, },
85 { "pca9557", 8 | PCA953X_TYPE, },
86 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
87 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
88 { "pca9698", 40 | PCA953X_TYPE, },
89
90 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
91 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
92 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
93
94 { "max7310", 8 | PCA953X_TYPE, },
95 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
96 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
97 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
98 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
99 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
100 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
101 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
102 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
103 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
104 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
105 { "xra1202", 8 | PCA953X_TYPE },
106 { }
107};
108MODULE_DEVICE_TABLE(i2c, pca953x_id);
109
110static const struct acpi_device_id pca953x_acpi_ids[] = {
111 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
112 { }
113};
114MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
115
116#define MAX_BANK 5
117#define BANK_SZ 8
118
119#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
120
121struct pca953x_reg_config {
122 int direction;
123 int output;
124 int input;
125 int invert;
126};
127
128static const struct pca953x_reg_config pca953x_regs = {
129 .direction = PCA953X_DIRECTION,
130 .output = PCA953X_OUTPUT,
131 .input = PCA953X_INPUT,
132 .invert = PCA953X_INVERT,
133};
134
135static const struct pca953x_reg_config pca957x_regs = {
136 .direction = PCA957X_CFG,
137 .output = PCA957X_OUT,
138 .input = PCA957X_IN,
139 .invert = PCA957X_INVRT,
140};
141
142struct pca953x_chip {
143 unsigned gpio_start;
144 struct mutex i2c_lock;
145 struct regmap *regmap;
146
147#ifdef CONFIG_GPIO_PCA953X_IRQ
148 struct mutex irq_lock;
149 u8 irq_mask[MAX_BANK];
150 u8 irq_stat[MAX_BANK];
151 u8 irq_trig_raise[MAX_BANK];
152 u8 irq_trig_fall[MAX_BANK];
153 struct irq_chip irq_chip;
154#endif
155 atomic_t wakeup_path;
156
157 struct i2c_client *client;
158 struct gpio_chip gpio_chip;
159 const char *const *names;
160 unsigned long driver_data;
161 struct regulator *regulator;
162
163 const struct pca953x_reg_config *regs;
164};
165
166static int pca953x_bank_shift(struct pca953x_chip *chip)
167{
168 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
169}
170
171#define PCA953x_BANK_INPUT BIT(0)
172#define PCA953x_BANK_OUTPUT BIT(1)
173#define PCA953x_BANK_POLARITY BIT(2)
174#define PCA953x_BANK_CONFIG BIT(3)
175
176#define PCA957x_BANK_INPUT BIT(0)
177#define PCA957x_BANK_POLARITY BIT(1)
178#define PCA957x_BANK_BUSHOLD BIT(2)
179#define PCA957x_BANK_CONFIG BIT(4)
180#define PCA957x_BANK_OUTPUT BIT(5)
181
182#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
183#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
184#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
185#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
186#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
187
188/*
189 * We care about the following registers:
190 * - Standard set, below 0x40, each port can be replicated up to 8 times
191 * - PCA953x standard
192 * Input port 0x00 + 0 * bank_size R
193 * Output port 0x00 + 1 * bank_size RW
194 * Polarity Inversion port 0x00 + 2 * bank_size RW
195 * Configuration port 0x00 + 3 * bank_size RW
196 * - PCA957x with mixed up registers
197 * Input port 0x00 + 0 * bank_size R
198 * Polarity Inversion port 0x00 + 1 * bank_size RW
199 * Bus hold port 0x00 + 2 * bank_size RW
200 * Configuration port 0x00 + 4 * bank_size RW
201 * Output port 0x00 + 5 * bank_size RW
202 *
203 * - Extended set, above 0x40, often chip specific.
204 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
205 * Input latch register 0x40 + 2 * bank_size RW
206 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
207 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
208 * Interrupt mask register 0x40 + 5 * bank_size RW
209 * Interrupt status register 0x40 + 6 * bank_size R
210 *
211 * - Registers with bit 0x80 set, the AI bit
212 * The bit is cleared and the registers fall into one of the
213 * categories above.
214 */
215
216static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
217 u32 checkbank)
218{
219 int bank_shift = pca953x_bank_shift(chip);
220 int bank = (reg & REG_ADDR_MASK) >> bank_shift;
221 int offset = reg & (BIT(bank_shift) - 1);
222
223 /* Special PCAL extended register check. */
224 if (reg & REG_ADDR_EXT) {
225 if (!(chip->driver_data & PCA_PCAL))
226 return false;
227 bank += 8;
228 }
229
230 /* Register is not in the matching bank. */
231 if (!(BIT(bank) & checkbank))
232 return false;
233
234 /* Register is not within allowed range of bank. */
235 if (offset >= NBANK(chip))
236 return false;
237
238 return true;
239}
240
241static bool pca953x_readable_register(struct device *dev, unsigned int reg)
242{
243 struct pca953x_chip *chip = dev_get_drvdata(dev);
244 u32 bank;
245
246 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
247 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
248 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
249 } else {
250 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
251 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
252 PCA957x_BANK_BUSHOLD;
253 }
254
255 if (chip->driver_data & PCA_PCAL) {
256 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
257 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
258 PCAL9xxx_BANK_IRQ_STAT;
259 }
260
261 return pca953x_check_register(chip, reg, bank);
262}
263
264static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
265{
266 struct pca953x_chip *chip = dev_get_drvdata(dev);
267 u32 bank;
268
269 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
270 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
271 PCA953x_BANK_CONFIG;
272 } else {
273 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
274 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
275 }
276
277 if (chip->driver_data & PCA_PCAL)
278 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
279 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
280
281 return pca953x_check_register(chip, reg, bank);
282}
283
284static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
285{
286 struct pca953x_chip *chip = dev_get_drvdata(dev);
287 u32 bank;
288
289 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
290 bank = PCA953x_BANK_INPUT;
291 else
292 bank = PCA957x_BANK_INPUT;
293
294 if (chip->driver_data & PCA_PCAL)
295 bank |= PCAL9xxx_BANK_IRQ_STAT;
296
297 return pca953x_check_register(chip, reg, bank);
298}
299
300static const struct regmap_config pca953x_i2c_regmap = {
301 .reg_bits = 8,
302 .val_bits = 8,
303
304 .readable_reg = pca953x_readable_register,
305 .writeable_reg = pca953x_writeable_register,
306 .volatile_reg = pca953x_volatile_register,
307
308 .cache_type = REGCACHE_RBTREE,
309 /* REVISIT: should be 0x7f but some 24 bit chips use REG_ADDR_AI */
310 .max_register = 0xff,
311};
312
313static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off,
314 bool write, bool addrinc)
315{
316 int bank_shift = pca953x_bank_shift(chip);
317 int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
318 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
319 u8 regaddr = pinctrl | addr | (off / BANK_SZ);
320
321 /* Single byte read doesn't need AI bit set. */
322 if (!addrinc)
323 return regaddr;
324
325 /* Chips with 24 and more GPIOs always support Auto Increment */
326 if (write && NBANK(chip) > 2)
327 regaddr |= REG_ADDR_AI;
328
329 /* PCA9575 needs address-increment on multi-byte writes */
330 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
331 regaddr |= REG_ADDR_AI;
332
333 return regaddr;
334}
335
336static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
337{
338 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true);
339 int ret;
340
341 ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip));
342 if (ret < 0) {
343 dev_err(&chip->client->dev, "failed writing register\n");
344 return ret;
345 }
346
347 return 0;
348}
349
350static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
351{
352 u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true);
353 int ret;
354
355 ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip));
356 if (ret < 0) {
357 dev_err(&chip->client->dev, "failed reading register\n");
358 return ret;
359 }
360
361 return 0;
362}
363
364static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
365{
366 struct pca953x_chip *chip = gpiochip_get_data(gc);
367 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
368 true, false);
369 u8 bit = BIT(off % BANK_SZ);
370 int ret;
371
372 mutex_lock(&chip->i2c_lock);
373 ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
374 mutex_unlock(&chip->i2c_lock);
375 return ret;
376}
377
378static int pca953x_gpio_direction_output(struct gpio_chip *gc,
379 unsigned off, int val)
380{
381 struct pca953x_chip *chip = gpiochip_get_data(gc);
382 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
383 true, false);
384 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off,
385 true, false);
386 u8 bit = BIT(off % BANK_SZ);
387 int ret;
388
389 mutex_lock(&chip->i2c_lock);
390 /* set output level */
391 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
392 if (ret)
393 goto exit;
394
395 /* then direction */
396 ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
397exit:
398 mutex_unlock(&chip->i2c_lock);
399 return ret;
400}
401
402static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
403{
404 struct pca953x_chip *chip = gpiochip_get_data(gc);
405 u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off,
406 true, false);
407 u8 bit = BIT(off % BANK_SZ);
408 u32 reg_val;
409 int ret;
410
411 mutex_lock(&chip->i2c_lock);
412 ret = regmap_read(chip->regmap, inreg, ®_val);
413 mutex_unlock(&chip->i2c_lock);
414 if (ret < 0) {
415 /* NOTE: diagnostic already emitted; that's all we should
416 * do unless gpio_*_value_cansleep() calls become different
417 * from their nonsleeping siblings (and report faults).
418 */
419 return 0;
420 }
421
422 return !!(reg_val & bit);
423}
424
425static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
426{
427 struct pca953x_chip *chip = gpiochip_get_data(gc);
428 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off,
429 true, false);
430 u8 bit = BIT(off % BANK_SZ);
431
432 mutex_lock(&chip->i2c_lock);
433 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
434 mutex_unlock(&chip->i2c_lock);
435}
436
437static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
438{
439 struct pca953x_chip *chip = gpiochip_get_data(gc);
440 u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
441 true, false);
442 u8 bit = BIT(off % BANK_SZ);
443 u32 reg_val;
444 int ret;
445
446 mutex_lock(&chip->i2c_lock);
447 ret = regmap_read(chip->regmap, dirreg, ®_val);
448 mutex_unlock(&chip->i2c_lock);
449 if (ret < 0)
450 return ret;
451
452 return !!(reg_val & bit);
453}
454
455static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
456 unsigned long *mask, unsigned long *bits)
457{
458 struct pca953x_chip *chip = gpiochip_get_data(gc);
459 unsigned int bank_mask, bank_val;
460 int bank;
461 u8 reg_val[MAX_BANK];
462 int ret;
463
464 mutex_lock(&chip->i2c_lock);
465 ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
466 if (ret)
467 goto exit;
468
469 for (bank = 0; bank < NBANK(chip); bank++) {
470 bank_mask = mask[bank / sizeof(*mask)] >>
471 ((bank % sizeof(*mask)) * 8);
472 if (bank_mask) {
473 bank_val = bits[bank / sizeof(*bits)] >>
474 ((bank % sizeof(*bits)) * 8);
475 bank_val &= bank_mask;
476 reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val;
477 }
478 }
479
480 pca953x_write_regs(chip, chip->regs->output, reg_val);
481exit:
482 mutex_unlock(&chip->i2c_lock);
483}
484
485static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
486 unsigned int offset,
487 unsigned long config)
488{
489 u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset,
490 true, false);
491 u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset,
492 true, false);
493 u8 bit = BIT(offset % BANK_SZ);
494 int ret;
495
496 /*
497 * pull-up/pull-down configuration requires PCAL extended
498 * registers
499 */
500 if (!(chip->driver_data & PCA_PCAL))
501 return -ENOTSUPP;
502
503 mutex_lock(&chip->i2c_lock);
504
505 /* Disable pull-up/pull-down */
506 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
507 if (ret)
508 goto exit;
509
510 /* Configure pull-up/pull-down */
511 if (config == PIN_CONFIG_BIAS_PULL_UP)
512 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
513 else if (config == PIN_CONFIG_BIAS_PULL_DOWN)
514 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
515 if (ret)
516 goto exit;
517
518 /* Enable pull-up/pull-down */
519 ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
520
521exit:
522 mutex_unlock(&chip->i2c_lock);
523 return ret;
524}
525
526static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
527 unsigned long config)
528{
529 struct pca953x_chip *chip = gpiochip_get_data(gc);
530
531 switch (config) {
532 case PIN_CONFIG_BIAS_PULL_UP:
533 case PIN_CONFIG_BIAS_PULL_DOWN:
534 return pca953x_gpio_set_pull_up_down(chip, offset, config);
535 default:
536 return -ENOTSUPP;
537 }
538}
539
540static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
541{
542 struct gpio_chip *gc;
543
544 gc = &chip->gpio_chip;
545
546 gc->direction_input = pca953x_gpio_direction_input;
547 gc->direction_output = pca953x_gpio_direction_output;
548 gc->get = pca953x_gpio_get_value;
549 gc->set = pca953x_gpio_set_value;
550 gc->get_direction = pca953x_gpio_get_direction;
551 gc->set_multiple = pca953x_gpio_set_multiple;
552 gc->set_config = pca953x_gpio_set_config;
553 gc->can_sleep = true;
554
555 gc->base = chip->gpio_start;
556 gc->ngpio = gpios;
557 gc->label = dev_name(&chip->client->dev);
558 gc->parent = &chip->client->dev;
559 gc->owner = THIS_MODULE;
560 gc->names = chip->names;
561}
562
563#ifdef CONFIG_GPIO_PCA953X_IRQ
564static void pca953x_irq_mask(struct irq_data *d)
565{
566 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
567 struct pca953x_chip *chip = gpiochip_get_data(gc);
568
569 chip->irq_mask[d->hwirq / BANK_SZ] &= ~BIT(d->hwirq % BANK_SZ);
570}
571
572static void pca953x_irq_unmask(struct irq_data *d)
573{
574 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
575 struct pca953x_chip *chip = gpiochip_get_data(gc);
576
577 chip->irq_mask[d->hwirq / BANK_SZ] |= BIT(d->hwirq % BANK_SZ);
578}
579
580static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
581{
582 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
583 struct pca953x_chip *chip = gpiochip_get_data(gc);
584
585 if (on)
586 atomic_inc(&chip->wakeup_path);
587 else
588 atomic_dec(&chip->wakeup_path);
589
590 return irq_set_irq_wake(chip->client->irq, on);
591}
592
593static void pca953x_irq_bus_lock(struct irq_data *d)
594{
595 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
596 struct pca953x_chip *chip = gpiochip_get_data(gc);
597
598 mutex_lock(&chip->irq_lock);
599}
600
601static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
602{
603 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
604 struct pca953x_chip *chip = gpiochip_get_data(gc);
605 u8 new_irqs;
606 int level, i;
607 u8 invert_irq_mask[MAX_BANK];
608 u8 reg_direction[MAX_BANK];
609
610 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
611
612 if (chip->driver_data & PCA_PCAL) {
613 /* Enable latch on interrupt-enabled inputs */
614 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
615
616 for (i = 0; i < NBANK(chip); i++)
617 invert_irq_mask[i] = ~chip->irq_mask[i];
618
619 /* Unmask enabled interrupts */
620 pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
621 }
622
623 /* Look for any newly setup interrupt */
624 for (i = 0; i < NBANK(chip); i++) {
625 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
626 new_irqs &= reg_direction[i];
627
628 while (new_irqs) {
629 level = __ffs(new_irqs);
630 pca953x_gpio_direction_input(&chip->gpio_chip,
631 level + (BANK_SZ * i));
632 new_irqs &= ~(1 << level);
633 }
634 }
635
636 mutex_unlock(&chip->irq_lock);
637}
638
639static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
640{
641 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
642 struct pca953x_chip *chip = gpiochip_get_data(gc);
643 int bank_nb = d->hwirq / BANK_SZ;
644 u8 mask = BIT(d->hwirq % BANK_SZ);
645
646 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
647 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
648 d->irq, type);
649 return -EINVAL;
650 }
651
652 if (type & IRQ_TYPE_EDGE_FALLING)
653 chip->irq_trig_fall[bank_nb] |= mask;
654 else
655 chip->irq_trig_fall[bank_nb] &= ~mask;
656
657 if (type & IRQ_TYPE_EDGE_RISING)
658 chip->irq_trig_raise[bank_nb] |= mask;
659 else
660 chip->irq_trig_raise[bank_nb] &= ~mask;
661
662 return 0;
663}
664
665static void pca953x_irq_shutdown(struct irq_data *d)
666{
667 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
668 struct pca953x_chip *chip = gpiochip_get_data(gc);
669 u8 mask = BIT(d->hwirq % BANK_SZ);
670
671 chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask;
672 chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask;
673}
674
675static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
676{
677 u8 cur_stat[MAX_BANK];
678 u8 old_stat[MAX_BANK];
679 bool pending_seen = false;
680 bool trigger_seen = false;
681 u8 trigger[MAX_BANK];
682 u8 reg_direction[MAX_BANK];
683 int ret, i;
684
685 if (chip->driver_data & PCA_PCAL) {
686 /* Read the current interrupt status from the device */
687 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
688 if (ret)
689 return false;
690
691 /* Check latched inputs and clear interrupt status */
692 ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
693 if (ret)
694 return false;
695
696 for (i = 0; i < NBANK(chip); i++) {
697 /* Apply filter for rising/falling edge selection */
698 pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
699 (cur_stat[i] & chip->irq_trig_raise[i]);
700 pending[i] &= trigger[i];
701 if (pending[i])
702 pending_seen = true;
703 }
704
705 return pending_seen;
706 }
707
708 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
709 if (ret)
710 return false;
711
712 /* Remove output pins from the equation */
713 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
714 for (i = 0; i < NBANK(chip); i++)
715 cur_stat[i] &= reg_direction[i];
716
717 memcpy(old_stat, chip->irq_stat, NBANK(chip));
718
719 for (i = 0; i < NBANK(chip); i++) {
720 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
721 if (trigger[i])
722 trigger_seen = true;
723 }
724
725 if (!trigger_seen)
726 return false;
727
728 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
729
730 for (i = 0; i < NBANK(chip); i++) {
731 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
732 (cur_stat[i] & chip->irq_trig_raise[i]);
733 pending[i] &= trigger[i];
734 if (pending[i])
735 pending_seen = true;
736 }
737
738 return pending_seen;
739}
740
741static irqreturn_t pca953x_irq_handler(int irq, void *devid)
742{
743 struct pca953x_chip *chip = devid;
744 u8 pending[MAX_BANK];
745 u8 level;
746 unsigned nhandled = 0;
747 int i;
748
749 if (!pca953x_irq_pending(chip, pending))
750 return IRQ_NONE;
751
752 for (i = 0; i < NBANK(chip); i++) {
753 while (pending[i]) {
754 level = __ffs(pending[i]);
755 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
756 level + (BANK_SZ * i)));
757 pending[i] &= ~(1 << level);
758 nhandled++;
759 }
760 }
761
762 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
763}
764
765static int pca953x_irq_setup(struct pca953x_chip *chip,
766 int irq_base)
767{
768 struct i2c_client *client = chip->client;
769 struct irq_chip *irq_chip = &chip->irq_chip;
770 u8 reg_direction[MAX_BANK];
771 int ret, i;
772
773 if (!client->irq)
774 return 0;
775
776 if (irq_base == -1)
777 return 0;
778
779 if (!(chip->driver_data & PCA_INT))
780 return 0;
781
782 ret = pca953x_read_regs(chip, chip->regs->input, chip->irq_stat);
783 if (ret)
784 return ret;
785
786 /*
787 * There is no way to know which GPIO line generated the
788 * interrupt. We have to rely on the previous read for
789 * this purpose.
790 */
791 pca953x_read_regs(chip, chip->regs->direction, reg_direction);
792 for (i = 0; i < NBANK(chip); i++)
793 chip->irq_stat[i] &= reg_direction[i];
794 mutex_init(&chip->irq_lock);
795
796 ret = devm_request_threaded_irq(&client->dev, client->irq,
797 NULL, pca953x_irq_handler,
798 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
799 IRQF_SHARED,
800 dev_name(&client->dev), chip);
801 if (ret) {
802 dev_err(&client->dev, "failed to request irq %d\n",
803 client->irq);
804 return ret;
805 }
806
807 irq_chip->name = dev_name(&chip->client->dev);
808 irq_chip->irq_mask = pca953x_irq_mask;
809 irq_chip->irq_unmask = pca953x_irq_unmask;
810 irq_chip->irq_set_wake = pca953x_irq_set_wake;
811 irq_chip->irq_bus_lock = pca953x_irq_bus_lock;
812 irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock;
813 irq_chip->irq_set_type = pca953x_irq_set_type;
814 irq_chip->irq_shutdown = pca953x_irq_shutdown;
815
816 ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip,
817 irq_base, handle_simple_irq,
818 IRQ_TYPE_NONE);
819 if (ret) {
820 dev_err(&client->dev,
821 "could not connect irqchip to gpiochip\n");
822 return ret;
823 }
824
825 gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq);
826
827 return 0;
828}
829
830#else /* CONFIG_GPIO_PCA953X_IRQ */
831static int pca953x_irq_setup(struct pca953x_chip *chip,
832 int irq_base)
833{
834 struct i2c_client *client = chip->client;
835
836 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
837 dev_warn(&client->dev, "interrupt support not compiled in\n");
838
839 return 0;
840}
841#endif
842
843static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
844{
845 int ret;
846 u8 val[MAX_BANK];
847
848 ret = regcache_sync_region(chip->regmap, chip->regs->output,
849 chip->regs->output + NBANK(chip));
850 if (ret)
851 goto out;
852
853 ret = regcache_sync_region(chip->regmap, chip->regs->direction,
854 chip->regs->direction + NBANK(chip));
855 if (ret)
856 goto out;
857
858 /* set platform specific polarity inversion */
859 if (invert)
860 memset(val, 0xFF, NBANK(chip));
861 else
862 memset(val, 0, NBANK(chip));
863
864 ret = pca953x_write_regs(chip, chip->regs->invert, val);
865out:
866 return ret;
867}
868
869static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
870{
871 int ret;
872 u8 val[MAX_BANK];
873
874 ret = device_pca95xx_init(chip, invert);
875 if (ret)
876 goto out;
877
878 /* To enable register 6, 7 to control pull up and pull down */
879 memset(val, 0x02, NBANK(chip));
880 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
881 if (ret)
882 goto out;
883
884 return 0;
885out:
886 return ret;
887}
888
889static const struct of_device_id pca953x_dt_ids[];
890
891static int pca953x_probe(struct i2c_client *client,
892 const struct i2c_device_id *i2c_id)
893{
894 struct pca953x_platform_data *pdata;
895 struct pca953x_chip *chip;
896 int irq_base = 0;
897 int ret;
898 u32 invert = 0;
899 struct regulator *reg;
900
901 chip = devm_kzalloc(&client->dev,
902 sizeof(struct pca953x_chip), GFP_KERNEL);
903 if (chip == NULL)
904 return -ENOMEM;
905
906 pdata = dev_get_platdata(&client->dev);
907 if (pdata) {
908 irq_base = pdata->irq_base;
909 chip->gpio_start = pdata->gpio_base;
910 invert = pdata->invert;
911 chip->names = pdata->names;
912 } else {
913 struct gpio_desc *reset_gpio;
914
915 chip->gpio_start = -1;
916 irq_base = 0;
917
918 /*
919 * See if we need to de-assert a reset pin.
920 *
921 * There is no known ACPI-enabled platforms that are
922 * using "reset" GPIO. Otherwise any of those platform
923 * must use _DSD method with corresponding property.
924 */
925 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
926 GPIOD_OUT_LOW);
927 if (IS_ERR(reset_gpio))
928 return PTR_ERR(reset_gpio);
929 }
930
931 chip->client = client;
932
933 reg = devm_regulator_get(&client->dev, "vcc");
934 if (IS_ERR(reg)) {
935 ret = PTR_ERR(reg);
936 if (ret != -EPROBE_DEFER)
937 dev_err(&client->dev, "reg get err: %d\n", ret);
938 return ret;
939 }
940 ret = regulator_enable(reg);
941 if (ret) {
942 dev_err(&client->dev, "reg en err: %d\n", ret);
943 return ret;
944 }
945 chip->regulator = reg;
946
947 if (i2c_id) {
948 chip->driver_data = i2c_id->driver_data;
949 } else {
950 const void *match;
951
952 match = device_get_match_data(&client->dev);
953 if (!match) {
954 ret = -ENODEV;
955 goto err_exit;
956 }
957
958 chip->driver_data = (uintptr_t)match;
959 }
960
961 i2c_set_clientdata(client, chip);
962
963 chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap);
964 if (IS_ERR(chip->regmap)) {
965 ret = PTR_ERR(chip->regmap);
966 goto err_exit;
967 }
968
969 regcache_mark_dirty(chip->regmap);
970
971 mutex_init(&chip->i2c_lock);
972 /*
973 * In case we have an i2c-mux controlled by a GPIO provided by an
974 * expander using the same driver higher on the device tree, read the
975 * i2c adapter nesting depth and use the retrieved value as lockdep
976 * subclass for chip->i2c_lock.
977 *
978 * REVISIT: This solution is not complete. It protects us from lockdep
979 * false positives when the expander controlling the i2c-mux is on
980 * a different level on the device tree, but not when it's on the same
981 * level on a different branch (in which case the subclass number
982 * would be the same).
983 *
984 * TODO: Once a correct solution is developed, a similar fix should be
985 * applied to all other i2c-controlled GPIO expanders (and potentially
986 * regmap-i2c).
987 */
988 lockdep_set_subclass(&chip->i2c_lock,
989 i2c_adapter_depth(client->adapter));
990
991 /* initialize cached registers from their original values.
992 * we can't share this chip with another i2c master.
993 */
994 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
995
996 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
997 chip->regs = &pca953x_regs;
998 ret = device_pca95xx_init(chip, invert);
999 } else {
1000 chip->regs = &pca957x_regs;
1001 ret = device_pca957x_init(chip, invert);
1002 }
1003 if (ret)
1004 goto err_exit;
1005
1006 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
1007 if (ret)
1008 goto err_exit;
1009
1010 ret = pca953x_irq_setup(chip, irq_base);
1011 if (ret)
1012 goto err_exit;
1013
1014 if (pdata && pdata->setup) {
1015 ret = pdata->setup(client, chip->gpio_chip.base,
1016 chip->gpio_chip.ngpio, pdata->context);
1017 if (ret < 0)
1018 dev_warn(&client->dev, "setup failed, %d\n", ret);
1019 }
1020
1021 return 0;
1022
1023err_exit:
1024 regulator_disable(chip->regulator);
1025 return ret;
1026}
1027
1028static int pca953x_remove(struct i2c_client *client)
1029{
1030 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
1031 struct pca953x_chip *chip = i2c_get_clientdata(client);
1032 int ret;
1033
1034 if (pdata && pdata->teardown) {
1035 ret = pdata->teardown(client, chip->gpio_chip.base,
1036 chip->gpio_chip.ngpio, pdata->context);
1037 if (ret < 0)
1038 dev_err(&client->dev, "teardown failed, %d\n", ret);
1039 } else {
1040 ret = 0;
1041 }
1042
1043 regulator_disable(chip->regulator);
1044
1045 return ret;
1046}
1047
1048#ifdef CONFIG_PM_SLEEP
1049static int pca953x_regcache_sync(struct device *dev)
1050{
1051 struct pca953x_chip *chip = dev_get_drvdata(dev);
1052 int ret;
1053
1054 /*
1055 * The ordering between direction and output is important,
1056 * sync these registers first and only then sync the rest.
1057 */
1058 ret = regcache_sync_region(chip->regmap, chip->regs->direction,
1059 chip->regs->direction + NBANK(chip));
1060 if (ret) {
1061 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
1062 return ret;
1063 }
1064
1065 ret = regcache_sync_region(chip->regmap, chip->regs->output,
1066 chip->regs->output + NBANK(chip));
1067 if (ret) {
1068 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
1069 return ret;
1070 }
1071
1072#ifdef CONFIG_GPIO_PCA953X_IRQ
1073 if (chip->driver_data & PCA_PCAL) {
1074 ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH,
1075 PCAL953X_IN_LATCH + NBANK(chip));
1076 if (ret) {
1077 dev_err(dev, "Failed to sync INT latch registers: %d\n",
1078 ret);
1079 return ret;
1080 }
1081
1082 ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK,
1083 PCAL953X_INT_MASK + NBANK(chip));
1084 if (ret) {
1085 dev_err(dev, "Failed to sync INT mask registers: %d\n",
1086 ret);
1087 return ret;
1088 }
1089 }
1090#endif
1091
1092 return 0;
1093}
1094
1095static int pca953x_suspend(struct device *dev)
1096{
1097 struct pca953x_chip *chip = dev_get_drvdata(dev);
1098
1099 regcache_cache_only(chip->regmap, true);
1100
1101 if (atomic_read(&chip->wakeup_path))
1102 device_set_wakeup_path(dev);
1103 else
1104 regulator_disable(chip->regulator);
1105
1106 return 0;
1107}
1108
1109static int pca953x_resume(struct device *dev)
1110{
1111 struct pca953x_chip *chip = dev_get_drvdata(dev);
1112 int ret;
1113
1114 if (!atomic_read(&chip->wakeup_path)) {
1115 ret = regulator_enable(chip->regulator);
1116 if (ret) {
1117 dev_err(dev, "Failed to enable regulator: %d\n", ret);
1118 return 0;
1119 }
1120 }
1121
1122 regcache_cache_only(chip->regmap, false);
1123 regcache_mark_dirty(chip->regmap);
1124 ret = pca953x_regcache_sync(dev);
1125 if (ret)
1126 return ret;
1127
1128 ret = regcache_sync(chip->regmap);
1129 if (ret) {
1130 dev_err(dev, "Failed to restore register map: %d\n", ret);
1131 return ret;
1132 }
1133
1134 return 0;
1135}
1136#endif
1137
1138/* convenience to stop overlong match-table lines */
1139#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
1140#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
1141
1142static const struct of_device_id pca953x_dt_ids[] = {
1143 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
1144 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
1145 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
1146 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
1147 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
1148 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
1149 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
1150 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
1151 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
1152 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
1153 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
1154 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
1155 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
1156 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
1157 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
1158
1159 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1160 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1161 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1162
1163 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
1164 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
1165 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
1166 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1167 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
1168
1169 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
1170 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1171 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1172 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1173 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1174 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
1175
1176 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
1177 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
1178
1179 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
1180 { }
1181};
1182
1183MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
1184
1185static SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
1186
1187static struct i2c_driver pca953x_driver = {
1188 .driver = {
1189 .name = "pca953x",
1190 .pm = &pca953x_pm_ops,
1191 .of_match_table = pca953x_dt_ids,
1192 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
1193 },
1194 .probe = pca953x_probe,
1195 .remove = pca953x_remove,
1196 .id_table = pca953x_id,
1197};
1198
1199static int __init pca953x_init(void)
1200{
1201 return i2c_add_driver(&pca953x_driver);
1202}
1203/* register after i2c postcore initcall and before
1204 * subsys initcalls that may rely on these GPIOs
1205 */
1206subsys_initcall(pca953x_init);
1207
1208static void __exit pca953x_exit(void)
1209{
1210 i2c_del_driver(&pca953x_driver);
1211}
1212module_exit(pca953x_exit);
1213
1214MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
1215MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
1216MODULE_LICENSE("GPL");