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1/*
2 * Renesas R-Car GPIO Support
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/pinctrl/consumer.h>
27#include <linux/platform_data/gpio-rcar.h>
28#include <linux/platform_device.h>
29#include <linux/spinlock.h>
30#include <linux/slab.h>
31
32struct gpio_rcar_priv {
33 void __iomem *base;
34 spinlock_t lock;
35 struct gpio_rcar_config config;
36 struct platform_device *pdev;
37 struct gpio_chip gpio_chip;
38 struct irq_chip irq_chip;
39 struct irq_domain *irq_domain;
40};
41
42#define IOINTSEL 0x00
43#define INOUTSEL 0x04
44#define OUTDT 0x08
45#define INDT 0x0c
46#define INTDT 0x10
47#define INTCLR 0x14
48#define INTMSK 0x18
49#define MSKCLR 0x1c
50#define POSNEG 0x20
51#define EDGLEVEL 0x24
52#define FILONOFF 0x28
53#define BOTHEDGE 0x4c
54
55#define RCAR_MAX_GPIO_PER_BANK 32
56
57static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
58{
59 return ioread32(p->base + offs);
60}
61
62static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
63 u32 value)
64{
65 iowrite32(value, p->base + offs);
66}
67
68static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
69 int bit, bool value)
70{
71 u32 tmp = gpio_rcar_read(p, offs);
72
73 if (value)
74 tmp |= BIT(bit);
75 else
76 tmp &= ~BIT(bit);
77
78 gpio_rcar_write(p, offs, tmp);
79}
80
81static void gpio_rcar_irq_disable(struct irq_data *d)
82{
83 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
84
85 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
86}
87
88static void gpio_rcar_irq_enable(struct irq_data *d)
89{
90 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
91
92 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
93}
94
95static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
96 unsigned int hwirq,
97 bool active_high_rising_edge,
98 bool level_trigger,
99 bool both)
100{
101 unsigned long flags;
102
103 /* follow steps in the GPIO documentation for
104 * "Setting Edge-Sensitive Interrupt Input Mode" and
105 * "Setting Level-Sensitive Interrupt Input Mode"
106 */
107
108 spin_lock_irqsave(&p->lock, flags);
109
110 /* Configure postive or negative logic in POSNEG */
111 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
112
113 /* Configure edge or level trigger in EDGLEVEL */
114 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
115
116 /* Select one edge or both edges in BOTHEDGE */
117 if (p->config.has_both_edge_trigger)
118 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
119
120 /* Select "Interrupt Input Mode" in IOINTSEL */
121 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
122
123 /* Write INTCLR in case of edge trigger */
124 if (!level_trigger)
125 gpio_rcar_write(p, INTCLR, BIT(hwirq));
126
127 spin_unlock_irqrestore(&p->lock, flags);
128}
129
130static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
131{
132 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
133 unsigned int hwirq = irqd_to_hwirq(d);
134
135 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
136
137 switch (type & IRQ_TYPE_SENSE_MASK) {
138 case IRQ_TYPE_LEVEL_HIGH:
139 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
140 false);
141 break;
142 case IRQ_TYPE_LEVEL_LOW:
143 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
144 false);
145 break;
146 case IRQ_TYPE_EDGE_RISING:
147 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
148 false);
149 break;
150 case IRQ_TYPE_EDGE_FALLING:
151 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
152 false);
153 break;
154 case IRQ_TYPE_EDGE_BOTH:
155 if (!p->config.has_both_edge_trigger)
156 return -EINVAL;
157 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
158 true);
159 break;
160 default:
161 return -EINVAL;
162 }
163 return 0;
164}
165
166static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
167{
168 struct gpio_rcar_priv *p = dev_id;
169 u32 pending;
170 unsigned int offset, irqs_handled = 0;
171
172 while ((pending = gpio_rcar_read(p, INTDT) &
173 gpio_rcar_read(p, INTMSK))) {
174 offset = __ffs(pending);
175 gpio_rcar_write(p, INTCLR, BIT(offset));
176 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
177 irqs_handled++;
178 }
179
180 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
181}
182
183static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
184{
185 return container_of(chip, struct gpio_rcar_priv, gpio_chip);
186}
187
188static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
189 unsigned int gpio,
190 bool output)
191{
192 struct gpio_rcar_priv *p = gpio_to_priv(chip);
193 unsigned long flags;
194
195 /* follow steps in the GPIO documentation for
196 * "Setting General Output Mode" and
197 * "Setting General Input Mode"
198 */
199
200 spin_lock_irqsave(&p->lock, flags);
201
202 /* Configure postive logic in POSNEG */
203 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
204
205 /* Select "General Input/Output Mode" in IOINTSEL */
206 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
207
208 /* Select Input Mode or Output Mode in INOUTSEL */
209 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
210
211 spin_unlock_irqrestore(&p->lock, flags);
212}
213
214static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
215{
216 return pinctrl_request_gpio(chip->base + offset);
217}
218
219static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
220{
221 pinctrl_free_gpio(chip->base + offset);
222
223 /* Set the GPIO as an input to ensure that the next GPIO request won't
224 * drive the GPIO pin as an output.
225 */
226 gpio_rcar_config_general_input_output_mode(chip, offset, false);
227}
228
229static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
230{
231 gpio_rcar_config_general_input_output_mode(chip, offset, false);
232 return 0;
233}
234
235static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
236{
237 u32 bit = BIT(offset);
238
239 /* testing on r8a7790 shows that INDT does not show correct pin state
240 * when configured as output, so use OUTDT in case of output pins */
241 if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
242 return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
243 else
244 return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
245}
246
247static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
248{
249 struct gpio_rcar_priv *p = gpio_to_priv(chip);
250 unsigned long flags;
251
252 spin_lock_irqsave(&p->lock, flags);
253 gpio_rcar_modify_bit(p, OUTDT, offset, value);
254 spin_unlock_irqrestore(&p->lock, flags);
255}
256
257static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
258 int value)
259{
260 /* write GPIO value to output before selecting output mode of pin */
261 gpio_rcar_set(chip, offset, value);
262 gpio_rcar_config_general_input_output_mode(chip, offset, true);
263 return 0;
264}
265
266static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
267{
268 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
269}
270
271static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int irq,
272 irq_hw_number_t hwirq)
273{
274 struct gpio_rcar_priv *p = h->host_data;
275
276 dev_dbg(&p->pdev->dev, "map hw irq = %d, irq = %d\n", (int)hwirq, irq);
277
278 irq_set_chip_data(irq, h->host_data);
279 irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
280 set_irq_flags(irq, IRQF_VALID); /* kill me now */
281 return 0;
282}
283
284static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
285 .map = gpio_rcar_irq_domain_map,
286};
287
288struct gpio_rcar_info {
289 bool has_both_edge_trigger;
290};
291
292static const struct of_device_id gpio_rcar_of_table[] = {
293 {
294 .compatible = "renesas,gpio-r8a7790",
295 .data = (void *)&(const struct gpio_rcar_info) {
296 .has_both_edge_trigger = true,
297 },
298 }, {
299 .compatible = "renesas,gpio-r8a7791",
300 .data = (void *)&(const struct gpio_rcar_info) {
301 .has_both_edge_trigger = true,
302 },
303 }, {
304 .compatible = "renesas,gpio-rcar",
305 .data = (void *)&(const struct gpio_rcar_info) {
306 .has_both_edge_trigger = false,
307 },
308 }, {
309 /* Terminator */
310 },
311};
312
313MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
314
315static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
316{
317 struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
318 struct device_node *np = p->pdev->dev.of_node;
319 struct of_phandle_args args;
320 int ret;
321
322 if (pdata) {
323 p->config = *pdata;
324 } else if (IS_ENABLED(CONFIG_OF) && np) {
325 const struct of_device_id *match;
326 const struct gpio_rcar_info *info;
327
328 match = of_match_node(gpio_rcar_of_table, np);
329 if (!match)
330 return -EINVAL;
331
332 info = match->data;
333
334 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
335 &args);
336 p->config.number_of_pins = ret == 0 ? args.args[2]
337 : RCAR_MAX_GPIO_PER_BANK;
338 p->config.gpio_base = -1;
339 p->config.has_both_edge_trigger = info->has_both_edge_trigger;
340 }
341
342 if (p->config.number_of_pins == 0 ||
343 p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
344 dev_warn(&p->pdev->dev,
345 "Invalid number of gpio lines %u, using %u\n",
346 p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
347 p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
348 }
349
350 return 0;
351}
352
353static int gpio_rcar_probe(struct platform_device *pdev)
354{
355 struct gpio_rcar_priv *p;
356 struct resource *io, *irq;
357 struct gpio_chip *gpio_chip;
358 struct irq_chip *irq_chip;
359 struct device *dev = &pdev->dev;
360 const char *name = dev_name(dev);
361 int ret;
362
363 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
364 if (!p) {
365 dev_err(dev, "failed to allocate driver data\n");
366 ret = -ENOMEM;
367 goto err0;
368 }
369
370 p->pdev = pdev;
371 spin_lock_init(&p->lock);
372
373 /* Get device configuration from DT node or platform data. */
374 ret = gpio_rcar_parse_pdata(p);
375 if (ret < 0)
376 return ret;
377
378 platform_set_drvdata(pdev, p);
379
380 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
381 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
382
383 if (!io || !irq) {
384 dev_err(dev, "missing IRQ or IOMEM\n");
385 ret = -EINVAL;
386 goto err0;
387 }
388
389 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
390 if (!p->base) {
391 dev_err(dev, "failed to remap I/O memory\n");
392 ret = -ENXIO;
393 goto err0;
394 }
395
396 gpio_chip = &p->gpio_chip;
397 gpio_chip->request = gpio_rcar_request;
398 gpio_chip->free = gpio_rcar_free;
399 gpio_chip->direction_input = gpio_rcar_direction_input;
400 gpio_chip->get = gpio_rcar_get;
401 gpio_chip->direction_output = gpio_rcar_direction_output;
402 gpio_chip->set = gpio_rcar_set;
403 gpio_chip->to_irq = gpio_rcar_to_irq;
404 gpio_chip->label = name;
405 gpio_chip->dev = dev;
406 gpio_chip->owner = THIS_MODULE;
407 gpio_chip->base = p->config.gpio_base;
408 gpio_chip->ngpio = p->config.number_of_pins;
409
410 irq_chip = &p->irq_chip;
411 irq_chip->name = name;
412 irq_chip->irq_mask = gpio_rcar_irq_disable;
413 irq_chip->irq_unmask = gpio_rcar_irq_enable;
414 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
415 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED
416 | IRQCHIP_MASK_ON_SUSPEND;
417
418 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
419 p->config.number_of_pins,
420 p->config.irq_base,
421 &gpio_rcar_irq_domain_ops, p);
422 if (!p->irq_domain) {
423 ret = -ENXIO;
424 dev_err(dev, "cannot initialize irq domain\n");
425 goto err0;
426 }
427
428 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
429 IRQF_SHARED, name, p)) {
430 dev_err(dev, "failed to request IRQ\n");
431 ret = -ENOENT;
432 goto err1;
433 }
434
435 ret = gpiochip_add(gpio_chip);
436 if (ret) {
437 dev_err(dev, "failed to add GPIO controller\n");
438 goto err1;
439 }
440
441 dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins);
442
443 /* warn in case of mismatch if irq base is specified */
444 if (p->config.irq_base) {
445 ret = irq_find_mapping(p->irq_domain, 0);
446 if (p->config.irq_base != ret)
447 dev_warn(dev, "irq base mismatch (%u/%u)\n",
448 p->config.irq_base, ret);
449 }
450
451 if (p->config.pctl_name) {
452 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
453 gpio_chip->base, gpio_chip->ngpio);
454 if (ret < 0)
455 dev_warn(dev, "failed to add pin range\n");
456 }
457
458 return 0;
459
460err1:
461 irq_domain_remove(p->irq_domain);
462err0:
463 return ret;
464}
465
466static int gpio_rcar_remove(struct platform_device *pdev)
467{
468 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
469 int ret;
470
471 ret = gpiochip_remove(&p->gpio_chip);
472 if (ret)
473 return ret;
474
475 irq_domain_remove(p->irq_domain);
476 return 0;
477}
478
479static struct platform_driver gpio_rcar_device_driver = {
480 .probe = gpio_rcar_probe,
481 .remove = gpio_rcar_remove,
482 .driver = {
483 .name = "gpio_rcar",
484 .of_match_table = of_match_ptr(gpio_rcar_of_table),
485 }
486};
487
488module_platform_driver(gpio_rcar_device_driver);
489
490MODULE_AUTHOR("Magnus Damm");
491MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
492MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas R-Car GPIO Support
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
7 */
8
9#include <linux/err.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/spinlock.h>
23#include <linux/slab.h>
24
25struct gpio_rcar_bank_info {
26 u32 iointsel;
27 u32 inoutsel;
28 u32 outdt;
29 u32 posneg;
30 u32 edglevel;
31 u32 bothedge;
32 u32 intmsk;
33};
34
35struct gpio_rcar_info {
36 bool has_outdtsel;
37 bool has_both_edge_trigger;
38 bool has_always_in;
39 bool has_inen;
40};
41
42struct gpio_rcar_priv {
43 void __iomem *base;
44 spinlock_t lock;
45 struct device *dev;
46 struct gpio_chip gpio_chip;
47 struct irq_chip irq_chip;
48 unsigned int irq_parent;
49 atomic_t wakeup_path;
50 struct gpio_rcar_info info;
51 struct gpio_rcar_bank_info bank_info;
52};
53
54#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
55#define INOUTSEL 0x04 /* General Input/Output Switching Register */
56#define OUTDT 0x08 /* General Output Register */
57#define INDT 0x0c /* General Input Register */
58#define INTDT 0x10 /* Interrupt Display Register */
59#define INTCLR 0x14 /* Interrupt Clear Register */
60#define INTMSK 0x18 /* Interrupt Mask Register */
61#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
62#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
63#define EDGLEVEL 0x24 /* Edge/level Select Register */
64#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
65#define OUTDTSEL 0x40 /* Output Data Select Register */
66#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
67#define INEN 0x50 /* General Input Enable Register */
68
69#define RCAR_MAX_GPIO_PER_BANK 32
70
71static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
72{
73 return ioread32(p->base + offs);
74}
75
76static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
77 u32 value)
78{
79 iowrite32(value, p->base + offs);
80}
81
82static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
83 int bit, bool value)
84{
85 u32 tmp = gpio_rcar_read(p, offs);
86
87 if (value)
88 tmp |= BIT(bit);
89 else
90 tmp &= ~BIT(bit);
91
92 gpio_rcar_write(p, offs, tmp);
93}
94
95static void gpio_rcar_irq_disable(struct irq_data *d)
96{
97 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
98 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
99
100 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
101}
102
103static void gpio_rcar_irq_enable(struct irq_data *d)
104{
105 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
106 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
107
108 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
109}
110
111static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
112 unsigned int hwirq,
113 bool active_high_rising_edge,
114 bool level_trigger,
115 bool both)
116{
117 unsigned long flags;
118
119 /* follow steps in the GPIO documentation for
120 * "Setting Edge-Sensitive Interrupt Input Mode" and
121 * "Setting Level-Sensitive Interrupt Input Mode"
122 */
123
124 spin_lock_irqsave(&p->lock, flags);
125
126 /* Configure positive or negative logic in POSNEG */
127 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
128
129 /* Configure edge or level trigger in EDGLEVEL */
130 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
131
132 /* Select one edge or both edges in BOTHEDGE */
133 if (p->info.has_both_edge_trigger)
134 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
135
136 /* Select "Interrupt Input Mode" in IOINTSEL */
137 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
138
139 /* Write INTCLR in case of edge trigger */
140 if (!level_trigger)
141 gpio_rcar_write(p, INTCLR, BIT(hwirq));
142
143 spin_unlock_irqrestore(&p->lock, flags);
144}
145
146static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
147{
148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
149 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
150 unsigned int hwirq = irqd_to_hwirq(d);
151
152 dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
153
154 switch (type & IRQ_TYPE_SENSE_MASK) {
155 case IRQ_TYPE_LEVEL_HIGH:
156 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
157 false);
158 break;
159 case IRQ_TYPE_LEVEL_LOW:
160 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
161 false);
162 break;
163 case IRQ_TYPE_EDGE_RISING:
164 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
165 false);
166 break;
167 case IRQ_TYPE_EDGE_FALLING:
168 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
169 false);
170 break;
171 case IRQ_TYPE_EDGE_BOTH:
172 if (!p->info.has_both_edge_trigger)
173 return -EINVAL;
174 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
175 true);
176 break;
177 default:
178 return -EINVAL;
179 }
180 return 0;
181}
182
183static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
184{
185 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
186 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
187 int error;
188
189 if (p->irq_parent) {
190 error = irq_set_irq_wake(p->irq_parent, on);
191 if (error) {
192 dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
193 p->irq_parent);
194 p->irq_parent = 0;
195 }
196 }
197
198 if (on)
199 atomic_inc(&p->wakeup_path);
200 else
201 atomic_dec(&p->wakeup_path);
202
203 return 0;
204}
205
206static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
207{
208 struct gpio_rcar_priv *p = dev_id;
209 u32 pending;
210 unsigned int offset, irqs_handled = 0;
211
212 while ((pending = gpio_rcar_read(p, INTDT) &
213 gpio_rcar_read(p, INTMSK))) {
214 offset = __ffs(pending);
215 gpio_rcar_write(p, INTCLR, BIT(offset));
216 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
217 offset));
218 irqs_handled++;
219 }
220
221 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
222}
223
224static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
225 unsigned int gpio,
226 bool output)
227{
228 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
229 unsigned long flags;
230
231 /* follow steps in the GPIO documentation for
232 * "Setting General Output Mode" and
233 * "Setting General Input Mode"
234 */
235
236 spin_lock_irqsave(&p->lock, flags);
237
238 /* Configure positive logic in POSNEG */
239 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
240
241 /* Select "General Input/Output Mode" in IOINTSEL */
242 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
243
244 /* Select Input Mode or Output Mode in INOUTSEL */
245 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
246
247 /* Select General Output Register to output data in OUTDTSEL */
248 if (p->info.has_outdtsel && output)
249 gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
250
251 spin_unlock_irqrestore(&p->lock, flags);
252}
253
254static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
255{
256 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
257 int error;
258
259 error = pm_runtime_get_sync(p->dev);
260 if (error < 0) {
261 pm_runtime_put(p->dev);
262 return error;
263 }
264
265 error = pinctrl_gpio_request(chip->base + offset);
266 if (error)
267 pm_runtime_put(p->dev);
268
269 return error;
270}
271
272static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
273{
274 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
275
276 pinctrl_gpio_free(chip->base + offset);
277
278 /*
279 * Set the GPIO as an input to ensure that the next GPIO request won't
280 * drive the GPIO pin as an output.
281 */
282 gpio_rcar_config_general_input_output_mode(chip, offset, false);
283
284 pm_runtime_put(p->dev);
285}
286
287static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
288{
289 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
290
291 if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
292 return GPIO_LINE_DIRECTION_OUT;
293
294 return GPIO_LINE_DIRECTION_IN;
295}
296
297static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
298{
299 gpio_rcar_config_general_input_output_mode(chip, offset, false);
300 return 0;
301}
302
303static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
304{
305 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
306 u32 bit = BIT(offset);
307
308 /*
309 * Before R-Car Gen3, INDT does not show correct pin state when
310 * configured as output, so use OUTDT in case of output pins
311 */
312 if (!p->info.has_always_in && (gpio_rcar_read(p, INOUTSEL) & bit))
313 return !!(gpio_rcar_read(p, OUTDT) & bit);
314 else
315 return !!(gpio_rcar_read(p, INDT) & bit);
316}
317
318static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask,
319 unsigned long *bits)
320{
321 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
322 u32 bankmask, outputs, m, val = 0;
323 unsigned long flags;
324
325 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
326 if (chip->valid_mask)
327 bankmask &= chip->valid_mask[0];
328
329 if (!bankmask)
330 return 0;
331
332 if (p->info.has_always_in) {
333 bits[0] = gpio_rcar_read(p, INDT) & bankmask;
334 return 0;
335 }
336
337 spin_lock_irqsave(&p->lock, flags);
338 outputs = gpio_rcar_read(p, INOUTSEL);
339 m = outputs & bankmask;
340 if (m)
341 val |= gpio_rcar_read(p, OUTDT) & m;
342
343 m = ~outputs & bankmask;
344 if (m)
345 val |= gpio_rcar_read(p, INDT) & m;
346 spin_unlock_irqrestore(&p->lock, flags);
347
348 bits[0] = val;
349 return 0;
350}
351
352static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
353{
354 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
355 unsigned long flags;
356
357 spin_lock_irqsave(&p->lock, flags);
358 gpio_rcar_modify_bit(p, OUTDT, offset, value);
359 spin_unlock_irqrestore(&p->lock, flags);
360}
361
362static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
363 unsigned long *bits)
364{
365 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
366 unsigned long flags;
367 u32 val, bankmask;
368
369 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
370 if (chip->valid_mask)
371 bankmask &= chip->valid_mask[0];
372
373 if (!bankmask)
374 return;
375
376 spin_lock_irqsave(&p->lock, flags);
377 val = gpio_rcar_read(p, OUTDT);
378 val &= ~bankmask;
379 val |= (bankmask & bits[0]);
380 gpio_rcar_write(p, OUTDT, val);
381 spin_unlock_irqrestore(&p->lock, flags);
382}
383
384static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
385 int value)
386{
387 /* write GPIO value to output before selecting output mode of pin */
388 gpio_rcar_set(chip, offset, value);
389 gpio_rcar_config_general_input_output_mode(chip, offset, true);
390 return 0;
391}
392
393static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
394 .has_outdtsel = false,
395 .has_both_edge_trigger = false,
396 .has_always_in = false,
397 .has_inen = false,
398};
399
400static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
401 .has_outdtsel = true,
402 .has_both_edge_trigger = true,
403 .has_always_in = false,
404 .has_inen = false,
405};
406
407static const struct gpio_rcar_info gpio_rcar_info_gen3 = {
408 .has_outdtsel = true,
409 .has_both_edge_trigger = true,
410 .has_always_in = true,
411 .has_inen = false,
412};
413
414static const struct gpio_rcar_info gpio_rcar_info_v3u = {
415 .has_outdtsel = true,
416 .has_both_edge_trigger = true,
417 .has_always_in = true,
418 .has_inen = true,
419};
420
421static const struct of_device_id gpio_rcar_of_table[] = {
422 {
423 .compatible = "renesas,gpio-r8a779a0",
424 .data = &gpio_rcar_info_v3u,
425 }, {
426 .compatible = "renesas,rcar-gen1-gpio",
427 .data = &gpio_rcar_info_gen1,
428 }, {
429 .compatible = "renesas,rcar-gen2-gpio",
430 .data = &gpio_rcar_info_gen2,
431 }, {
432 .compatible = "renesas,rcar-gen3-gpio",
433 .data = &gpio_rcar_info_gen3,
434 }, {
435 .compatible = "renesas,gpio-rcar",
436 .data = &gpio_rcar_info_gen1,
437 }, {
438 /* Terminator */
439 },
440};
441
442MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
443
444static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
445{
446 struct device_node *np = p->dev->of_node;
447 const struct gpio_rcar_info *info;
448 struct of_phandle_args args;
449 int ret;
450
451 info = of_device_get_match_data(p->dev);
452 p->info = *info;
453
454 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
455 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
456
457 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
458 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
459 *npins, RCAR_MAX_GPIO_PER_BANK);
460 *npins = RCAR_MAX_GPIO_PER_BANK;
461 }
462
463 return 0;
464}
465
466static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p)
467{
468 u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0);
469
470 /* Select "Input Enable" in INEN */
471 if (p->gpio_chip.valid_mask)
472 mask &= p->gpio_chip.valid_mask[0];
473 if (mask)
474 gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask);
475}
476
477static int gpio_rcar_probe(struct platform_device *pdev)
478{
479 struct gpio_rcar_priv *p;
480 struct resource *irq;
481 struct gpio_chip *gpio_chip;
482 struct irq_chip *irq_chip;
483 struct gpio_irq_chip *girq;
484 struct device *dev = &pdev->dev;
485 const char *name = dev_name(dev);
486 unsigned int npins;
487 int ret;
488
489 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
490 if (!p)
491 return -ENOMEM;
492
493 p->dev = dev;
494 spin_lock_init(&p->lock);
495
496 /* Get device configuration from DT node */
497 ret = gpio_rcar_parse_dt(p, &npins);
498 if (ret < 0)
499 return ret;
500
501 platform_set_drvdata(pdev, p);
502
503 pm_runtime_enable(dev);
504
505 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
506 if (!irq) {
507 dev_err(dev, "missing IRQ\n");
508 ret = -EINVAL;
509 goto err0;
510 }
511
512 p->base = devm_platform_ioremap_resource(pdev, 0);
513 if (IS_ERR(p->base)) {
514 ret = PTR_ERR(p->base);
515 goto err0;
516 }
517
518 gpio_chip = &p->gpio_chip;
519 gpio_chip->request = gpio_rcar_request;
520 gpio_chip->free = gpio_rcar_free;
521 gpio_chip->get_direction = gpio_rcar_get_direction;
522 gpio_chip->direction_input = gpio_rcar_direction_input;
523 gpio_chip->get = gpio_rcar_get;
524 gpio_chip->get_multiple = gpio_rcar_get_multiple;
525 gpio_chip->direction_output = gpio_rcar_direction_output;
526 gpio_chip->set = gpio_rcar_set;
527 gpio_chip->set_multiple = gpio_rcar_set_multiple;
528 gpio_chip->label = name;
529 gpio_chip->parent = dev;
530 gpio_chip->owner = THIS_MODULE;
531 gpio_chip->base = -1;
532 gpio_chip->ngpio = npins;
533
534 irq_chip = &p->irq_chip;
535 irq_chip->name = "gpio-rcar";
536 irq_chip->parent_device = dev;
537 irq_chip->irq_mask = gpio_rcar_irq_disable;
538 irq_chip->irq_unmask = gpio_rcar_irq_enable;
539 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
540 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
541 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
542
543 girq = &gpio_chip->irq;
544 girq->chip = irq_chip;
545 /* This will let us handle the parent IRQ in the driver */
546 girq->parent_handler = NULL;
547 girq->num_parents = 0;
548 girq->parents = NULL;
549 girq->default_type = IRQ_TYPE_NONE;
550 girq->handler = handle_level_irq;
551
552 ret = gpiochip_add_data(gpio_chip, p);
553 if (ret) {
554 dev_err(dev, "failed to add GPIO controller\n");
555 goto err0;
556 }
557
558 p->irq_parent = irq->start;
559 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
560 IRQF_SHARED, name, p)) {
561 dev_err(dev, "failed to request IRQ\n");
562 ret = -ENOENT;
563 goto err1;
564 }
565
566 if (p->info.has_inen) {
567 pm_runtime_get_sync(p->dev);
568 gpio_rcar_enable_inputs(p);
569 pm_runtime_put(p->dev);
570 }
571
572 dev_info(dev, "driving %d GPIOs\n", npins);
573
574 return 0;
575
576err1:
577 gpiochip_remove(gpio_chip);
578err0:
579 pm_runtime_disable(dev);
580 return ret;
581}
582
583static int gpio_rcar_remove(struct platform_device *pdev)
584{
585 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
586
587 gpiochip_remove(&p->gpio_chip);
588
589 pm_runtime_disable(&pdev->dev);
590 return 0;
591}
592
593#ifdef CONFIG_PM_SLEEP
594static int gpio_rcar_suspend(struct device *dev)
595{
596 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
597
598 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
599 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
600 p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
601 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
602 p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
603 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
604 if (p->info.has_both_edge_trigger)
605 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
606
607 if (atomic_read(&p->wakeup_path))
608 device_set_wakeup_path(dev);
609
610 return 0;
611}
612
613static int gpio_rcar_resume(struct device *dev)
614{
615 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
616 unsigned int offset;
617 u32 mask;
618
619 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
620 if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
621 continue;
622
623 mask = BIT(offset);
624 /* I/O pin */
625 if (!(p->bank_info.iointsel & mask)) {
626 if (p->bank_info.inoutsel & mask)
627 gpio_rcar_direction_output(
628 &p->gpio_chip, offset,
629 !!(p->bank_info.outdt & mask));
630 else
631 gpio_rcar_direction_input(&p->gpio_chip,
632 offset);
633 } else {
634 /* Interrupt pin */
635 gpio_rcar_config_interrupt_input_mode(
636 p,
637 offset,
638 !(p->bank_info.posneg & mask),
639 !(p->bank_info.edglevel & mask),
640 !!(p->bank_info.bothedge & mask));
641
642 if (p->bank_info.intmsk & mask)
643 gpio_rcar_write(p, MSKCLR, mask);
644 }
645 }
646
647 if (p->info.has_inen)
648 gpio_rcar_enable_inputs(p);
649
650 return 0;
651}
652#endif /* CONFIG_PM_SLEEP*/
653
654static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
655
656static struct platform_driver gpio_rcar_device_driver = {
657 .probe = gpio_rcar_probe,
658 .remove = gpio_rcar_remove,
659 .driver = {
660 .name = "gpio_rcar",
661 .pm = &gpio_rcar_pm_ops,
662 .of_match_table = of_match_ptr(gpio_rcar_of_table),
663 }
664};
665
666module_platform_driver(gpio_rcar_device_driver);
667
668MODULE_AUTHOR("Magnus Damm");
669MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
670MODULE_LICENSE("GPL v2");